SM5841H NIPPON PRECISION CIRCUITS INC. OVERVIEW The SM5841H is an 8-times oversampling (interpolation) digital filter for digital audio reproduction equipment. It accepts 16 or 18-bit input data, and outputs data in 16, 18 or 20-bit format, making a wide range of interfaces possible. It also features digital deemphasis for 3 sampling frequencies, a noise shaper to reduce quantization noise, a DC offset output and other circuits. Audio Multi-function Digital Filter ORDERING INFOMATION Device Package SM5841HP 18pin DIP SM5841HS 22pin SOP FEATURES Functions ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ 2-channel processing 8-times (8fs) oversampling (interpolation) Digital deemphasis (fs = 48/44.1/32 kHz) Serial input data 2s complement, MSB first, 16/18-bit Serial output data 2s complement, MSB first, 16/18/20-bit 1st-order noise shaper (for 16/18-bit output only) 256fs/384fs system clock selectable Output data DC offset (approximately 0.8%) ON/OFF control TTL-compatible input/outputs 5 V (standard) supply 3.2 V operating voltage Molybdenum-gate CMOS Filter Characteristics ■ ■ ■ 3-stage DC FIR interpolation filter 1st stage (fs → 2fs), 69-tap 2nd stage (2fs → 4fs), 13-tap 3rd stage (4fs → 8fs), 9-tap IIR deemphasis filter for gain and phase characteristics close to those of analog filters Overflow limiter built-in APPLICATIONS ■ ■ ■ ■ ■ Digital amplifiers CD players DAT players DBS systems PCM systems NIPPON PRECISION CIRCUITS—1 SM5841H PINOUT PACKAGE DIMENSIONS 18-pin DIP 18-pin DIP (Unit: mm) 17 BCKI CKSL 3 16 LRCI CKO 4 15 OFST VSS 5 14 VDD WSL2 6 13 WCKO DSF1 7 12 DOL DSF2 8 11 DOR RST 9 10 BCKO 22-pin SOP 0 15 + 0.20 0.25 0. 05 2 7.62TYP CKI 22.05 − 0.30 + 0.30 1.20− 0 1.27MAX + 0.14 0.45 − 0.05 2.54TYP 3.00MIN 5.00MAX DIN 6.20 0.25 18 0.51MIN 1 SM5841HP WSL1 22-pin SOP (Unit: mm) BCKI CKSL 3 20 LRCI CKO 4 19 OFST VSS 5 18 (NC) (NC) 6 17 (NC) 16 VDD (NC) 7 WSL2 8 15 WCKO DSF1 9 14 DOL DSF2 10 13 DOR 11 12 BCKO RST + 0.1 0.15 − 0.05 0.4 ± 0.1 1.27 0 to 10˚ 21 0.5 ± 0.2 2 1.8 ± 0.1 CKI 13.9 ± 0.3 5.4 ± 0.2 DIN 7.8 ± 0.3 22 0.05 ± 0.05 1 SM5841HS WSL1 NIPPON PRECISION CIRCUITS—2 SM5841H BLOCK DIAGRAM LRCI CKSL CKI DIN BCKI System Clock Input data Interface CKO Timing Controller RST DSF1 Filter and Attenuation Airthmetic block OFST Deemphasis Controler DSF2 Input/output word length selector WSL1 WSL2 VSS WCKO DOL DOR BCKO Interface Output date VDD PIN DESCRIPTION SOP DIP Name I/O1 Description Input/output data select pins 1 8 1 6 WSL1 WSL2 Ip Ip WSL1 WSL2 Noise shaper Input bit length Output bit length HIGH HIGH Off 18 bits 20 bits HIGH LOW On 18 bits 18 bits LOW HIGH On 16 bits 18 bits LOW LOW On 16 bits 16 bits 2 2 CKI Ip System clock input 3 3 CKSL Ip System clock select input. 384fs when HIGH, and 256fs when LOW. 4 4 CKO O System clock output. The CKI is first buffered before output on CKO. 5 5 VSS – Ground 6 – NC – No connection 7 – NC – No connection Deemphasis select inputs 9 10 7 8 DSF1 DSF2 Ip Ip DSF1 DSF2 Deemphasis Sampling frequency LOW LOW On 44.1 kHz LOW HIGH On 48.0 kHz HIGH LOW Off – HIGH HIGH On 32.0 kHz 11 9 RST Ip System reset. Reset and initialization when RST is LOW. 12 10 BCKO O Output bit clock NIPPON PRECISION CIRCUITS—3 SM5841H SOP DIP Name I/O1 13 11 DOR O Right-channel 8fs data output 14 12 DOL O Left-channel 8fs data output 15 13 WCKO O Output word clock 16 14 VDD – 5 V supply 17 – NC – No connection 18 – NC – No connection 19 15 OFST Ip Output data DC offset select input. Summing ON when HIGH, and OFF when LOW. 20 16 LRCI Ip Input data sample rate (fs) clock 21 17 BCKI Ip Input bit clock 22 18 DIN Ip Input data Description 1. Ip = Input with pull-up resistor SPECIFICATIONS Absolute Maximum Ratings VSS = 0 V Parameter Symbol Rating Unit Supply voltage range V DD −0.3 to 7.0 V Input voltage range V IN −0.3 to V DD + 0.3 V Storage temperature range Tstg −40 to 125 °C Power dissipation PD 250 mW Soldering temperature Tsld 255 °C Soldering time tsld 10 s Symbol Rating Unit Supply voltage range V DD 3.2 to 5.5 V Operating temperature range Topr −20 to 80 °C Recommended Operating Conditions VSS = 0 V Parameter NIPPON PRECISION CIRCUITS—4 SM5841H DC Electrical Characteristics Standard voltage: VDD = 4.5 to 5.5 V, VSS = 0 V, Ta = −20 to 80 °C Rating Parameter Symbol Condition V DD = 5.0 V 1 Unit min typ max – – 40 mA Current consumption IDD HIGH-level input voltage2 V IH1 0.7VDD – – V LOW-level input voltage2 V IL1 – – 0.3VDD V 0.3VDD – – V p-p CKI AC-coupled input voltage V INAC HIGH-level input voltage3 V IH2 2.4 – – V LOW-level input voltage3 V IL2 – – 0.5 V HIGH-level output voltage4 VOH IOH = −0.4 mA 2.5 – – V LOW-level output voltage4 VOL IOL = 1.6 mA – – 0.4 V CKI HIGH-level input current IIH1 V IN = V DD – 10 20 µA CKI LOW-level input current IIL1 V IN = 0 V – 10 20 µA LOW-level input current3 IIL2 V IN = 0 V – 10 20 µA Input leakage current2, 3 ILH V IN = V DD – – 1.0 µA Input leakage current2 ILL V IN = 0 V – – 1.0 µA 1. 2. 3. 4. Sine wave input fSYS = 384fs = 20 MHz, no output load Pins CKSL, OFST Pins LRCI, DIN, BCKI, DSF1, DSF2, WSL1, WSL2, RST Pins CKO, DOL, DOR, BCKO, WCKO Low voltage: VDD = 3.2 to 4.5 V, VSS = 0 V, Ta = −20 to 80 °C Rating Parameter Symbol Condition V DD = 3.4 V 1 Unit min typ max – – 20 mA Current consumption IDD HIGH-level input voltage2 V IH1 0.7VDD – – V LOW-level input voltage2 V IL1 – – 0.3VDD V 0.3VDD – – V p-p CKI AC-coupled input voltage V INAC HIGH-level input voltage3 V IH2 2.4 – – V LOW-level input voltage3 V IL2 – – 0.5 V HIGH-level output voltage4 VOH IOH = −0.2 mA 2.5 – – V LOW-level output voltage4 VOL IOL = 0.8 mA – – 0.4 V CKI HIGH-level input current IIH1 V IN = V DD – – 12 µA CKI LOW-level input current IIL1 V IN = 0 V – – 12 µA LOW-level input current3 IIL2 V IN = 0 V – – 12 µA Input leakage current2, 3 ILH V IN = V DD – – 1.0 µA Input leakage current2 ILL V IN = 0 V – – 1.0 µA 1. 2. 3. 4. Sine wave input fSYS = 384fs = 18.5 MHz, no output load Pins CKSL, OFST Pins LRCI, DIN, BCKI, DSF1, DSF2, WSL1, WSL2, RST Pins CKO, DOL, DOR, BCKO, WCKO NIPPON PRECISION CIRCUITS—5 SM5841H AC Electrical Characteristics Clock (CKI) Standard voltage: VDD = 4.5 to 5.5 V, VSS = 0 V, Ta = −20 to 80 °C Condition Parameter Symbol HIGH-level clock pulsewidth tCWH LOW-level clock pulsewidth tCWL Clock pulse cycle tCI Rating Unit CKSL System clock min typ max HIGH 384fs 23 – 250 LOW 256fs 35 – 500 HIGH 384fs 23 – 250 LOW 256fs 35 – 500 HIGH 384fs 50 – 500 LOW 256fs 76 – 1000 ns ns ns Low voltage: VDD = 3.2 to 4.5 V, VSS = 0 V, Ta = −20 to 80 °C Condition Parameter Symbol HIGH-level clock pulsewidth tCWH LOW-level clock pulsewidth tCWL Clock pulse cycle tCI Rating Unit CKSL System clock min typ max HIGH 384fs 25 – 250 LOW 256fs 50 – 500 HIGH 384fs 25 – 250 LOW 256fs 50 – 500 HIGH 384fs 54 – 500 LOW 256fs 108 – 1000 ns ns ns over 0.7×VDD 0.5×VDD CKI tCWL tCWH under 0.3×VDD tCI NIPPON PRECISION CIRCUITS—6 SM5841H Serial input timing (BCKI, DI, LRCI) VDD = 3.2 to 5.5 V, VSS = 0 V, Ta = −20 to 80 °C Rating Parameter Symbol Unit min typ max BCKI HIGH-level pulsewidth tBCWH 50 – – ns BCKI LOW-level pulsewidth tBCWL 50 – – ns BCKI pulse cycle tBCY 100 – – ns DIN setup time tDS 50 – – ns DIN hold time tDH 50 – – ns Last BCKI rising edge to LRCI edge tBL 50 – – ns LRCI edge to first BCKI rising edge tLB 50 – – ns tBCY tBCWH tBCWL 1.5V BCKI tDS tDH DIN 1.5V tLB tBL LRCI 1.5V Reset timing (RST) VDD = 3.2 to 5.5 V, VSS = 0 V, Ta = −20 to 80 °C Rating Parameter RST LOW-level reset pulsewidth Symbol tRST Condition Unit min typ max At power-ON 1 – – µs At all other times 50 – – ns Control inputs (DSF1, DSF2) VDD = 3.2 to 5.5 V, VSS = 0 V, Ta = −20 to 80 °C Rating Parameter Symbol Condition Unit min typ max Rise time tr 10 to 90% level – – 100 ns Fall time tf 90 to 10% level – – 100 ns NIPPON PRECISION CIRCUITS—7 SM5841H Output timing Standard voltage: VDD = 4.5 to 5.5 V, VSS = 0 V, Ta = −20 to 80 °C, CL = 15 pF Rating Parameter CKI to CKO delay CKI to BCKO delay BCKO to DOL, DOR, WCKO delay RST to DOL, DOR delay Symbol Condition Unit min typ max tCKO CKI fall to CKO fall – – 30 tsbH CKI fall to BCKO rise 10 – 60 tsbL CKI fall to BCKO fall 10 – 60 tbdH BCKO fall to output rise 0 – 20 tbdL BCKO fall to output fall 0 – 20 trdH RST fall to output fall – – 40 trdL RST rise to output rise – – 40 ns ns ns ns Low voltage: VDD = 3.2 to 4.5 V, VSS = 0 V, Ta = −20 to 80 °C, CL = 15 pF Rating Parameter CKI to CKO delay CKI to BCKO delay BCKO to DOL, DOR, WCKO delay RST to DOL, DOR delay Symbol Condition Unit min typ max tCKO CKI fall to CKO fall – – 45 tsbH CKI fall to BCKO rise 10 – 100 tsbL CKI fall to BCKO fall 10 – 100 tbdH BCKO fall to output rise 0 – 30 tbdL BCKO fall to output fall 0 – 30 trdH RST fall to output fall – – 60 trdL RST rise to output rise – – 60 ns ns ns ns CKI (CKSL = L) Tsys CKI (CKSL = H) 0.5VDD tsbH tsbL 1.5V BCKO tbdL 1.5V DOL DOR WCKO tbdH 1.5V NIPPON PRECISION CIRCUITS—8 SM5841H Filter Characteristics 8-times interpolation filter Frequency Rating (dB) Parameter f @ fs = 44.1 kHz 0 to 0.4535fs 0 to 20 kHz Passband attenuation Passband ripple Stopband attenuation min typ max – 0.20 – −0.03 – +0.03 0.5465fs to 3.4535fs 24.1 to 152 kHz 53 – – 3.4535fs to 4.5465fs 152 to 201 kHz 50 – – 4.5465fs to 7.4535fs 201 to 328 kHz 53 – – 8fs filter response with deemphasis OFF Attenuation (dB) 0 20 40 60 80 100 120 0.0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 Frequency (fs) 8fs filter passband response with deemphasis OFF Attenuation (dB) -0.0001 -0.00005 0.00000 0.00005 0.0001 0.000 0.125 0.250 0.375 0.500 Frequency (fs) 8fs filter band transition response with deemphasis OFF 0 Attenuation (dB) 10 20 30 40 50 60 70 0.440 0.465 0.490 0.515 0.540 0.565 0.590 0.615 0.640 Frequency (fs) NIPPON PRECISION CIRCUITS—9 SM5841H Deemphasis filter Sampling frequency Parameter 32 kHz 44.1 kHz 48 kHz 0 to 14.5 0 to 20.0 0 to 21.7 −0.40 to +0.40 −0.05 to +0.15 −0.30 to +0.05 −2 to 19 −1 to 15 −1 to 14 Passband bandwidth (kHz) Deviation from ideal characteristic1 Attenuation (dB) Phase, θ (°) 1. The maximum deviation from an ideal filter with 0 dB attenuation and 0° phase characteristics for a 1 kHz input signal. Passband response with deemphasis ON (fs = 44.1 kHz) 0 Attenuation (dB) 2 4 6 8 10 10 20 50 100 200 500 1k 2k 5k 10k 20k Frequency (Hz) Passband response with deemphasis ON (fs = 32/48 kHz) Attenuation (dB) 0 2 48kHz 32kHz 4 6 8 10 10 20 50 100 200 500 1k 2k 5k 10k 20k Frequency (Hz) NIPPON PRECISION CIRCUITS—10 SM5841H FUNCTIONAL DESCRIPTION The basic arithmetic block is shown in figure 1, and the function of each block is described in the following sections. Input fs Deemphasis IIR filter fs fs Attenuator fs 1st FIR 69th - order 2 × interpolator 2fs 2nd FIR 13th - order 2 × interpolator 4fs 3rd FIR 9th - order 2 × interpolator 8fs Output Figure 1. Arithmetic block diagram 8-times Oversampling (Interpolation) Digital Deemphasis (DSF1, DSF2) The interpolation arithmetic block is comprised of 3 cascaded, 2-times FIR interpolation filters, as shown in figure 1. The digital deemphasis filter has the same construction as analog filters. It is implemented as an IIR filter to faithfully reproduce the gain and phase characteristics of standard analog deemphasis filters. The filter coefficients for fs = 32.0/44.1/48.0 kHz sampling frequency are selected by DSF1 and DSF2 when the sampling frequency is specified, as shown in the following table. The input signal is sampled at rate fs, and then 8times oversampling data is output. Sampling noise in the 0.5465fs to 7.4535fs stopband is removed by the interpolation filter. DSF1 DSF2 Deemphasis Sampling frequency LOW LOW On 44.1 kHz LOW HIGH On 48.0 kHz HIGH LOW Off – HIGH HIGH On 32.0 kHz NIPPON PRECISION CIRCUITS—11 SM5841H System Clock (CKI, CKO, CKSL) Two system clock frequencies, 384fs and 256fs, can be used. The clock is input on CKI. The CKI input inverter has a feedback resistor to allow AC-coupled input clocks. The system clock is also buffered and then output on CKO. The system clock frequency selection and the internal clock frequency are shown in the following table. CKSL Parameter HIGH LOW CKI input system clock frequency (fSYS ) 384fs 256fs CKO clock frequency 384fs 256fs Internal clock frequency 128fs 128fs Serial output clock frequency 192fs 256fs to timing controller CKSL CKSL = H Internal system clock (128fs) 1/3 CKI 1/2 CKSL = L CKO to timing controller Figure 2. Clock generator circuit Noise Shaper and I/O Data Length (WSL1, WSL2) The SM5841H has functions that can be used to suppress the level of requantization noise due to the inherent arithmetic rounding-off that occurs in digital signal processing. ■ ■ 16/18-bit input The input interface accepts 16 and 18-bit input source data. That means that if 16-bit source data is digitally processed, for example in a sound field control or other DSP, the output can be input to the SM5841H without the same need for roundingoff, thereby avoiding the requantization noise that would otherwise occur. 16/18/20-bit output The output interface can support 18 and 20-bit output data, making connection to 18 or 20-bit D/A converters possible. As a result, the requantization noise generated after digital processing can be greatly reduced. ■ Noise shaper function The 1st-order noise shaper processing occurs on the digital filter output. It reduces the requantization noise for 16 and 18-bit input signals to levels inherent in 18 and 20-bit output modes, respectively. The noise shaper does no processing on 20bit output data. There are 4 input data and output data length combinations possible, selected by the state of WSL1 and WSL2 as shown in the following table. WSL1 WSL2 Noise shaper Input bit length Output bit length HIGH HIGH Off 18 bits 20 bits HIGH LOW On 18 bits 18 bits LOW HIGH On 16 bits 18 bits LOW LOW On 16 bits 16 bits NIPPON PRECISION CIRCUITS—12 SM5841H Audio Data Input (DIN, BCKI, LRCI) The input data is in 16/18-bit serial, 2s complement, MSB first format. Serial input data on DIN is clocked into an SIPO (serial in, parallel out) register on the rising edge of the BCKI bit clock, and then converted to parallel data. SIPO output data is transferred into the left and right-channel input registers on the falling edge and rising edge, respectively, of the LRCI clock. The internal arithmetic operation and output circuit timing is independent of the input timing. Accordingly, phase differences between LRCI, BCKI and CKI do not affect device operation, and any jitter in the data input clock does not cause jitter in the output clock. Note that the device should be reset if either or both of the LRCI and CKI clocks stop. If the device is not reset, even though the clocks are low frequency, incorrect circuit operation may occur, generating unwanted output noise. 1/fs Lch MSB 16 / 18bit LSB Rch MSB 16 / 18bit LSB DIN BCKI LRCI Figure 3. Audio data input timing NIPPON PRECISION CIRCUITS—13 SM5841H Audio Data Output (DOL, DOR, BCKO, WCKO, OFST) The output data is in 16/18/20-bit serial, 8fs, simultaneous left and right-channel, 2s complement, MSB first format. A DC offset can be added to arithmetic data before the data is output to reduce the D/A converter zerocrossing distortion for very small input signals. The offset added is approximately 0.8% of full-scale for the corresponding output bit length, as shown below. ■ ■ ■ 512 LSB for 16-bit output 2048 LSB for 18-bit output 8192 LSB for 20-bit output 8fs serial data is output on independent DOL and DOR channels, in sync with the falling edge of the internal system clock and BCKO clock. The number of BCKO bit clock pulses per word changes depending on the output bit length selected (16/18/20 bits). Consequently, output data is latched into the D/A converter internal register on the falling of the edge of an output word clock WCKO, which has timing independent of the number of output bits as specified in the following table. Parameter The DC offset is added to the output when OFST is HIGH. DC offset is OFF when OFST is LOW. Bit clock rate Data word length Symbol CKSL = HIGH CKSL = LOW TB tSYS (1/192fs) tSYS (1/256fs) TDW 24TB 32TB System Clock BCKO TB DOL or DOR 1 2 3 4 5 11 12 13 14 15 16 17 18 19 20 1 2 3 4 WCKO 18TB 6TB TDW = 24TB The number of output bits is determined by the output bit length selected. Figure 4. 8fs data output timing (CKSL = HIGH) System Clock BCKO DOL or DOR TB 1 2 3 4 5 11 12 13 14 15 16 17 18 19 20 1 2 3 4 WCKO 26TB 6TB TDW = 32TB The number of output bits is determined by the output bit length selected. Figure 5. 8fs data output timing (CKSL = LOW) NIPPON PRECISION CIRCUITS—14 SM5841H System Reset and Output Muting (RST) System reset If the system clock is interrupted or is corrupted by jitter, after power-ON reset and all internal timing is synchronized, such that a timing error greater than ±3/8 × fLRCI occurs, the internal timing is automatically reset on the next LRCI start edge. This resynchronization affects the internal operation and can generate a momentary click noise output. The SM5841H must be reset at power-ON by applying a LOW-level pulse on RST. At system reset, the arithmetic and output timing counters are reset on the next LRCI start edge, as long as the CKI clock has already stabilized. The power-ON reset pulse can be applied by a microcontroller or, for systems where CKI and LRCI are stable at power-ON, by connecting a 300 pF capacitor between RST and VSS. For systems that do not use a microcontroller, the capacitor must be chosen such that the CKI and LRCI clocks fully stabilize before RST goes from LOW to HIGH. RST Output muting When RST goes LOW, the DOL and DOR outputs go LOW, immediately muting the output signal, and they remain LOW for intervals in word units. Muting is released and timing is synchronized on the 3rd rising edge of LRCI after RST goes HIGH. Note that during muted output, the BCKO and WCKO clocks do not stop. (L) 1 2 3 4 LRCI Internal reset DOL DOR (L) Figure 6. System reset timing and output muting NIPPON PRECISION CIRCUITS—15 SM5841H TIMING DIAGRAMS Input Timing Examples (DIN, BCKI, LRCI) Audio ICs 18bit Lch (MSB) (LSB) 18bit Rch (MSB) (LSB) DIN BCKI LRCI 1 / fs Figure 7. 18-bit input timing (MSB) 16bit Lch (LSB) (MSB) 16bit Rch (LSB) DIN BCKI LRCI 1 / fs Figure 8. 16-bit input timing NIPPON PRECISION CIRCUITS—16 SM5841H Output Timing Examples (DOL, DOR, BCKO, WCKO) System Clock BCKO TB DOL or DOR 1 2 3 4 5 11 12 13 14 15 16 17 18 19 20 1 2 3 4 WCKO 18TB 6TB TDW = 24TB The number of output bits is determined by the output bit length selected. Figure 9. 8fs data output timing (CKSL = HIGH) System Clock BCKO DOL or DOR TB 1 2 3 4 5 11 12 13 14 15 16 17 18 19 20 1 2 3 4 WCKO 26TB 6TB TDW = 32TB The number of output bits is determined by the output bit length selected. Figure 10. 8fs data output timing (CKSL = LOW) NIPPON PRECISION CIRCUITS—17 SM5841H APPLICATION CIRCUITS Input Interface Circuits C16M SONY LRDK CXD2500 44.1kHz DA16 DA15 PSSL XCK MATSUSHITA MN6617 16.9344MHz 2.1168MHz 16.9344MHz IPSEL OA YAMAHA YM3623 L/R 2.1168MHz 16.9344MHz 44.1kHz 17MO TOSHIBA TC9200F CHCK 2.1168MHz 16.9344MHz 44.1kHz LRCI BCKI CKI LRCI BCKI CKI LRCI DIN DOUT BCK CKI DIN DO BCO BCKI DIN SRDATA SEL LRCI DIN R / L 44.1kHz SRCK CKI 2.1168MHz BCKI CKSL SM5841H WSL1 CKSL SM5841H WSL1 CKSL SM5841H WSL1 CKSL SM5841H WSL1 NIPPON PRECISION CIRCUITS—18 SM5841H Output Interface Circuits 18-bit, 2-DAC (8fs L+R output mode) WCKO DOL SM5841H (16bit Input) DOR BCKO WSL1 CLOCK BURR - BROWN L. E. PCM58P DATA Lch OutPut CLOCK BURR - BROWN L. E. PCM58P DATA Rch OutPut This example is for 16-bit input mode, so WSL1 is tied HIGH. For 18-bit mode, WSL1 is tied LOW. 16-bit, 1-DAC (8fs L+R output mode) SM5841H (16bit Input) WSL1 WSL2 WCKO DOL DOR BCKO WCKO LSI NEC µPD6376 RSI CLK Lch Output Rch Output 4/8fs SEL NIPPON PRECISION CIRCUITS—19 SM5841H NIPPON PRECISION CIRCUITS INC. reserves the right to make changes to the products described in this data sheet in order to improve the design or performance and to supply the best possible products. Nippon Precision Circuits Inc. assumes no responsibility for the use of any circuits shown in this data sheet, conveys no license under any patent or other rights, and makes no claim that the circuits are free from patent infringement. Applications for any devices shown in this data sheet are for illustration only and Nippon Precision Circuits Inc. makes no claim or warranty that such applications will be suitable for the use specified without further testing or modification. The products described in this data sheet are not intended to use for the apparatus which influence human lives due to the failure or malfunction of the products. Customers are requested to comply with applicable laws and regulations in effect now and hereinafter, including compliance with export controls on the distribution or dissemination of the products. Customers shall not export, directly or indirectly, any products without first obtaining required licenses and approvals from appropriate government agencies. NIPPON PRECISION CIRCUITS INC. NIPPON PRECISION CIRCUITS INC. 4-3, Fukuzumi 2-chome Koto-ku, Tokyo 135-8430, Japan Telephone: 03-3642-6661 Facsimile: 03-3642-6698 NC9625AE 1998.06 NIPPON PRECISION CIRCUITS—20