E2F0007-18-11
Pr
¡ Semiconductor
MSM9405
¡ Semiconductor
el
im
This version: Jan.
1998
MSM9405 ina
ry
IrDA Communication Controller
GENERAL DESCRIPTION
The MSM9405 is a communication controller conforming to IrDA, the international standard for
infrared data communication. The device covers the IrDA physical specifications Ver.1.0 and
1.1.
Since the device performs some of the functions concerning communication protocol control,
the load on the software (firmware) for protocol control can be reduced. By combining the
device with another microcontroller and an infrared transceiver module, a device provided
with IrDA-compliant communication function can be configured.
FEATURES
• Data transfer rates
IrDA 1.0
IrDA 1.1
: 2400, 9600 bps; 19.2, 38.4, 57.6, 115.2 kbps
: 0.576, 1.152, 4 Mbps
• Detection/removal for beginning of frame and end of frame (IrDA 1.0, 1.1)
Insertion for beginning of frame and end of frame (IrDA 1.0, 1.1)
• Generation/check for CRC (IrDA 1.0, 1.1)
• Host interface
8-bit data bus
DMA transfer
Interrupt
Address
Control signal
:
:
:
:
:
D0-D7
DREQ, DACK, TC
INTR
A0-A3
CS, RD, WR
• Infrared module control signal : SD
• Built-in 32-byte transmit-receive FIFOs
• Power down mode
• Built-in oscillator circuit
• Crystal oscillation frequency : 18.432 MHz (other than 4 Mbps data rate)
: 48 MHz (when 4 Mbps data rate used)
• Operating voltage (VDD)
: 2.7 to 3.6 V
• Package:
30-pin plastic SSOP (SSOP30-P-56-0.65-K) (Product name : MSM9405MB)
1/30
TEST
XOUT
XIN
DACK
8
OSC
I/F
DMA
Microcontroller I/F
DREQ
TC
PWDN
RESET
INTR
WR
RD
CS
A0-3
D0-7
GND
VDD
8
8
Generator
Baud Rate
(TSR)
Transmit Shift Register
8
(32¥8bit)
Transmit-Receive FIFO
8
Register (RSR)
Receive Shift
TCC/RCC
Control Circuit
DMA
Register
Control/Status
CRC
TX_
CRC
RX_
ENC
4 PPM-
ENC
HDLC-
Circuit
Flag Insertion
DEC
4 PPM-
Insertion Circuit
Preamble/Flag/
Flag Insertion Circuit
ENC
UART
Removal Circuit
Preamble/Flag Detection/
Flag Detection/
Removal Circuit
DEC
DEC
HDLC-
UART
Flag Detection/
Removal Circuit
Modulator
IrDA
Demodulator
IrDA
IROUT
IRIN-B
IRIN-A
SD
¡ Semiconductor
MSM9405
BLOCK DIAGRAM
2/30
¡ Semiconductor
MSM9405
PIN CONFIGURATION (TOP VIEW)
VDD
1
30
XIN
D7
2
29
XOUT
D6
3
28
TEST
D5
4
27
IRIN-A
D4
5
26
IRIN-B
D3
6
25
IROUT
D2
7
24
SD
D1
8
23
TC
D0
9
22
DREQ
A3
10
21
DACK
A2
11
20
PWDN
A1
12
19
RESET
A0
13
18
INTR
CS
14
17
WR
RD
15
16
GND
30-Pin Plastic SSOP
3/30
¡ Semiconductor
MSM9405
PIN DESCRIPTIONS
Pin
Symbol
Type
Transceiver
27
IRIN-A
I
Receive signal input A. (2.4 kbps to 4 Mbps)*1
Module Interface
26
IRIN-B
I
Receive signal input B. (0.576 to 4 Mbps)
Function
Description
When connecting this device to a transceiver module,
tie this pin high or low if the number of the receive signal
output pins that the module has is only one.*1
25
IROUT
O
Transmit signal output. Active high.
24
SD
O
Transceiver module control signal output.
Becomes active when PWDN is set low.*1
This pin must be left open if connecting this device to a
transceiver module having no shutdown pins.
Microcontroller
Interface
9-2
D0-D7
I/O
13-10
A0-A3
I
Register address inputs.
14
CS
I
Chip select input. Active low.
Data input-output.
When low, read and write signals are enabled.
15
RD
I
Read signal input. Active low.
17
WR
I
18
INTR
O
Write signal input. Active low.
Interrupt request signal output. Active low.
DMA Controller
22
DREQ
O
DMA Request signal output. *1
Interface
21
DACK
I
DMA acknowledge signal input. *1
23
TC
I
DMA transfer end signal input. Active low.
20
PWDN
I
Power down control. Active low.
Others
When set low, oscillation stops and the device enters power
down (low supply current) mode.
19
RESET
I
System reset input. Active low.
When set low, the internal registers are initialized.
28
TEST
O
Test. Must be left open.
30
XIN
I
Crystal connect.
29
XOUT
O
Crystal connect.
1
VDD
—
Power supply.
16
GND
—
Ground.
*1 Either active high or active low can be selected depending on the register setting.
4/30
¡ Semiconductor
MSM9405
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Condition
Rating
Unit
VDD
—
–0.5 to +4.0
V
Input Voltage
VI
—
–0.5 to +6.0
V
Power Dissipation
PD
—
230
mW
TSTG
—
–55 to +150
°C
Supply Voltage
Storage Temperature
RECOMMENDED OPERATING CONDITIONS
Symbol
Condition
Range
Unit
Supply Voltage
Parameter
VDD
—
2.7 to 3.6
V
Operating Temperature
Top
—
–20 to +70
°C
fOSC
—
18.432 MHz ±200 ppm or 48 MHz ±100 ppm
—
Crystal Oscillation
Frequency
ELECTRICAL CHARACTERISTICS
DC Characteristics
(VDD = 2.7 to 3.6 V, Ta = –20 to +70°C)
Symbol
Condition
"H" Input Voltage
Parameter
VIH
—
Min. Typ. Max. Unit
2.2
—
5.5
"L" Input Voltage
VIL
—
0
—
0.8*1
Input Leakage Current
ILI
VI = VDD/0 V
—
—
±1
"H" Input Voltage
VIH
—
2.2
—
5.5
"L" Input Voltage
VIL
—
0
—
0.8*1
Input Leakage Current
ILI
VI = VDD/0 V
—
—
±10
"H" Output Voltage
VOH
IO = –4 mA
2.4
—
—
"L" Output Voltage
VOL
IO = 4 mA
—
—
0.4
"H" Output Voltage
VOH
IO = –4 mA
2.4
—
—
"L" Output Voltage
VOL
IO = 4 mA
—
—
0.4
Supply Current
IDD
—
—
—
IDPN
When PWDN = "L"
—
—
Supply Current
(during Power Down)
V
mA
Applicable Pin
IRIN-A, IRIN-B, PWDN
A0-A3, CS, RD, WR,
TC, RESET, DACK
V
mA
D0-D7
V
V
IROUT, INTR, DREQ
20
mA
VDD
—
mA
VDD
*1 1.0 V when VDD = 3.0 to 3.6 V
5/30
¡ Semiconductor
MSM9405
AC Characteristics
(VDD = 2.7 to 3.6 V, Ta = –20 to +70°C)
Parameter
Read Pulse Width
Symbol
Condition
Min.
Typ.
Max.
Unit
Note
trpw
—
120/70
—
—
ns
*1
Read Data Delay Time
trdd
—
—
—
60
ns
*2
Read Data Hold Time
trdh
—
0
—
20
ns
*3
Read/Write Recovery Time
trcv
—
60
—
—
ns
CS Setup Time
tcss
—
60
—
—
ns
CS Hold Time
tcsh
—
0
—
—
ns
Write Address Hold Time
twah
—
0
—
—
ns
Write Pulse Width
twpw
—
120/70
—
—
ns
Write Data Setup Time
twds
—
60
—
—
ns
Write Data Hold Time
twdh
—
–10
—
—
ns
Write Address Setup Time
twas
—
–10
—
—
ns
Interrupt Clear Time
tintr
—
—
—
120/70
ns
DACK Pulse Width
tdak
—
60
—
—
ns
DACK Setup Time
tacs
—
10
—
—
ns
DREQ Clear Time
tdrqr
—
—
—
120/70
ns
DACK Hold Time (during Read)
tachr
—
–5
—
—
ns
DACK Hold Time (during Write)
tachw
—
10
—
—
ns
TC Pulse Width
ttcw
—
50
—
—
ns
TC Setup Time
ttcs
—
0
—
—
ns
TC Hold Time
ttch
SIR Pulse Width
SIR Data Rate Tolerance
MIR Pulse width
MIR Data Rate Tolerance
tspw
SDRT
tmpw
MDRT
FIR Single Pulse Width
tfpw
FIR Data Rate Tolerance
FDRT
FIR Double Pulse Width
tfdpw
Reset Pulse Width
trstw
—
0
—
—
ns
Transmitter
—
1.63
—
ms
Receiver
0.9
—
—
ms
Transmitter
—
—
±0.87
%
Receiver
—
—
±2.0
%
Transmitter
—
218
—
ns
Receiver
100
—
—
ns
Transmitter
—
—
±0.1
%
Receiver
—
—
±0.2
%
Transmitter
—
125
—
ns
Receiver
70
—
165
ns
Transmitter
—
—
±0.01
%
Receiver
—
—
±0.1
%
Transmitter
—
250
—
ns
Receiver
195
—
285
ns
—
70
—
—
ns
*1
*1
*1
*1 120 ns when crystal oscillation frequency = 18.432 MHz,
70 ns when crystal oscillation frequency = 48 MHz
*2 That which occurs latest of the following is to be used for the data delay time (trdd) :
the change of the state of A0-A3, the change from CS high to low, and the change from
RD high to low.
*3 That which occurs first of the following is to be used for the read data hold time (trdh) :
the change of the state of A0-A3, the change from CS low to high, and the change from
RD low to high.
6/30
¡ Semiconductor
MSM9405
• Read timing
trdd
trpw
trdh
CS
trdd
trpw
trdh
trpw
trcv
A0-A3
RD
trdd
trdh
D0-D7
tintr
INTR
7/30
¡ Semiconductor
MSM9405
• Write timing
tcsh
tcss
CS
twas
twah
A0-A3
twpw
trcv
WR
twds
twdh
D0-D7
tintr
INTR
8/30
¡ Semiconductor
MSM9405
• DMAC access timing 1
DMA_EN = "1", DMA_SL1 = "0", DMA_SL0 = "0"
MemoryÆM9405
CS
tdrqr
DREQ
(Active low)
tdak
trcv
trpw
trcv
DACK
RD
twds
twdh
D0-D7
M9405ÆMemory
CS
tdrqr
DREQ
(Active low)
trcv
tdak
trdh
DACK
twpw
trcv
WR
trdd
trdh
D0-D7
9/30
¡ Semiconductor
MSM9405
• DMAC access timing 2
DMA_EN = "1", DMA_SL1 = "0", DMA_SL0 = "1"
M9405ÆMemory
DREQ
(Active high)
tdrqr
DACK
tacs
trpw
tachr
RD
trcv
trdd
trdh
D0-D7
MemoryÆM9405
DREQ
(Active high)
tdrqr
DACK
tacs
twpw
tachw
WR
trcv
twds
twdh
D0-D7
WR
ttcs
ttcw
ttch
TC
10/30
¡ Semiconductor
MSM9405
• DMAC access timing 3
DMA_EN = "1", DMA_SL1 = "1", DMA_SL0 = "1" or "0"
M9405ÆMemory
tdrqr
DREQ
trdd
trpw
trdh
CS
trdd
trpw
trdh
A0-A3
trpw
RD
trdh
trdd
D0-D7
MemoryÆM9405
tdrqr
DREQ
tcsh
tcss
CS
twas
twah
A0-A3
twpw
WR
twds
twdh
D0-D7
11/30
¡ Semiconductor
MSM9405
• Infrared interface timing
tspw
SIR
tmpw
MIR
tfpw
tfdpw
FIR
• Reset timing
trstw
RESET
12/30
¡ Semiconductor
MSM9405
FUNCTIONAL DESCRIPTION
Modes
There are four modes provided by the MSM9405 for IrDA communication. Communication
with IrDA1.0 is in SIR mode or Extended-SIR mode, while communication with IrDA1.1 is in
MIR mode or FIR mode. In SIR mode, the MSM9405 has the necessary UART feature for IrDA
communication. The Extended-SIR mode is an original feature of the MSM9405. In this mode,
BOF/EOF insertion and CRC calculation/check are performed by the MSM9405. Therefore, the
burden to the CPU can be reduced compared with IrDA1.0 communication using ordinary
UART. Moreover, the Extended-SIR mode allows DMA transfer even in IrDA1.0 communication.
In MIR mode, IrDA1.1 communication at up to 1.152 Mbps is possible. The FIR mode supports
4 Mbps transfer for IrDA1.1. Features of each mode are as follows:
MSM9405 Modes Comparison
CE insertion/ "0" insertion/
Preamble
mode
Transfer rate
BOF
CRC
EOF
removal
removal
insertion/removal
SIR
2.4 to 115.2 kbps
SW
SW
SW
SW
—
—
Extended-SIR
2.4 to 115.2 kbps
HW
HW
HW
HW
—
—
MIR
0.576, 1.152 Mbps
HW
HW
HW
—
HW
—
FIR
4 Mbps
HW
HW
HW
—
—
HW
Sending/Receiving Switching Method
CE : Control Escape Byte
SW : Software
HW : Hardware
Mode switching between sending and receiving is made using the TX_EN and RX_EN bits in
the ICR1 (Infrared Control Register 1). For sending, writing "1" in TX_EN puts the MSM9405
in the sending mode. Writing "1" in RX_EN puts the MSM9405 in the receiving mode. If "0" is
written to both TX_EN and RX_EN bits, the MSM9405 does not perform sending/receiving but
enters the idle state. Each register can be set even during the idle state. Data to be sent can be
written in advance to the FIFO during the idle state.
If "1" is written to both TX_EN and RX_EN, the MSM9405 is put in the receiving mode.
DMA Transfer
The MSM9405 allows DMA transfer. The DMA transfer mode covers the single transfer mode
and demand transfer mode, but not the block transfer mode. When a DMA controller with TC
output is used for sending, the DMA controller and MSM9405 automatically perform highspeed transfer if the maximum frame length is specified for TFL and the transfer data length for
the TC counter of the DMA controller.
The timing when the DREQ signal is asserted is as follows:
During receiving, DREQ is asserted when data in the FIFO is at or above the receiving threshold
level or time-out occurs.
If all of the received data in the FIFO is read, DREQ is deasserted.
During sending, DREQ is asserted when data in the FIFO is lower than the sending threshold
level. Sent data is written and DREQ is deasserted when the FIFO becomes full or TXE_EV
occurs.
13/30
¡ Semiconductor
MSM9405
Time-out
The MSM9405 outputs an interrupt request or DMA request depending on the register setting
when the following time-out occurs even if the received data is below the receiving threshold
level:
The condition causing time-out in MIR or FIR mode is:
At least 1-byte data is in the receiving FIFO and 69.5 ms has passed after data is written from
the receiving shift register to the FIFO. During this period, the CPU or DMA controller does
not read the FIFO data.
The condition causing time-out in SIR or Extended SIR mode is:
At least 1-byte data is in the receiving FIFO and time (Tout) has passed after data is written
from the receiving shift register to the FIFO. During this period, the CPU or DMA controller
does not read the FIFO data.
Tout = 4 ¥ 8 ¥ 1/baud rate
baud rate: Transfer rate (2.4 to 115.2 kbps)
Register Map
The MSM9405 contains 14 registers, of which 13 are available. Each register can be selected with
the register address assigned from 0h through Ch. Various setting options are provided for each
register to allow optimum communication.
The registers are listed below. The register table is given on the next page.
A3-A0
0h
R/W Register Name
Description
R
RDR
Receive data register
W
TDR
Transmit data register
1h
R/W
ENR
Interrupt enable register
2h
R
EIR
Interrupt event and status indication register
3h
R
LSR
Status register
4h
R/W
ICR1
Transmit-receive control register
5h
R/W
ICR2
BOF count setting register
6h
R/W
MSR
Register for setting a transfer mode and a data rate and selecting a
7h
R/W
DSR
8h
R/W
FCR
9h
R/W
TFL (L)
*1
Transmit frame-length setting register (low-order byte)
Ah
R/W
TFL (H)
*1
Transmit frame-length setting register (high-order byte)
9h
R
TCC (L)
*1
Transmitter current-count register (low-order byte)
Ah
R
TCC (H)
*1
Transmitter current-count register (high-order byte)
Bh
R/W
MDS (L)
*2
Maximum data size setting register (low-order byte)
0h
R/W
MDS (H)
*2
Maximum data size setting register (high-order byte)
Bh
R
RST (L)
*2
Receiver frame length stack register (low-order byte)
Ch
R
RST (H)
*2
Receiver frame length stack register (high-order byte)
Fh
R/W
crystal to be used
TEST
DMA mode setting register
FIFO threshold setting register
Used for test.
*1 Whether TFL or TCC is read depends on the setting of the CTEST bit in the MSR
register.
*2 Whether MDS or RST is read depends on the setting of the CTEST bit in the MSR
register.
14/30
¡ Semiconductor
MSM9405
Register Table
Add
0
Register
name
TDR/RDR
Mode R/W
all
R/W
Function of each bit
Bit7
Bit6
Bit5
ENR
Ex-SIR
MIR
Bit3
Bit1
TDR6
TDR5
TDR4
TDR3
TDR2
TDR1
TDR0
/RDR6
/RDR5
/RDR4
/RDR3
/RDR2
/RDR1
/RDR0
TXE_IE TXL_IE
RXH/T
_IE
EOF_IE
*
MLE_IE
CE_IE
FE_IE
OE_IE
FIR
EIR
Ex-SIR
MIR
AS_IE
ECE_IE
SIR
2
Bit0
TDR7
*
R/W
Bit2
/RDR7
SIR
1
Bit4
*
R
TXE_EV TXL_EV
RXH/T
_EV
EOF_EV
*
MLE_EV
CE_EV
FE_EV
OE_EV
FIR
AS_EV
ECE_EV
SIR
3
LSR
Ex-SIR
MIR
R
FLV5
FLV4
FLV3
FLV2
FLV1
FLV0
IR_DET
TOUT
RX_EN
TX_EN
FIR
*
SIR
4
ICR1
Ex-SIR
MIR
R/W
MS_EN TCC_EN
FIR
CRC_
*
FCLR
5
ICR2
MIR
R/W
CTEST
SD_INV
IR_PLS
*
*
*
*
IRIN
SBF3
SBF2
SBF1
SBF0
MBF3
MBF2
MBF1
MBF0
*
*
*
*
_SL
RXINV
FIR
6
MSR
all
R/W
DRS2
DRS1
S_EOT
INV
SIR
Ex-SIR
*
DRS0
XT_SL
*
*
IRSL1
IRSL0
DMA_
DMA_
DMA_
7
DSR
all
R/W
*
*
*
*
*
SL1
SL0
EN
8
FCR
all
R/W
RXTH3
RXTH2
RXTH1
RXTH0
TXTH3
TXTH2
TXTH1
TXTH0
TFL (L)
all
R/W
TFL7
TFL6
TFL5
TFL4
TFL3
TFL2
TFL1
TFL0
9
A
B
C
F
TCC (L)
all
R
TCC7
TCC6
TCC5
TCC4
TCC3
TCC2
TCC1
TCC0
TFL (H)
all
R/W
*
*
*
*
TFL11
TFL10
TFL9
TFL8
TCC (H)
all
R
*
*
*
*
TCC11
TCC10
TCC9
TCC8
MDS (L)
all
R/W
MDS7
MDS6
MDS5
MDS4
MDS3
MDS2
MDS1
MDS0
RST (L)
all
R
RST7
RST6
RST5
RST4
RST3
RST2
RST1
RST0
MDS (H)
all
R/W
*
*
*
*
MDS11
MDS10
MDS9
MDS8
RST (H)
all
R
*
*
*
*
RST11
RST10
RST9
RST8
TEST
all
R/W
TEST7
TEST6
TEST5
TEST4
TEST3
TEST2
TEST1
TEST0
15/30
¡ Semiconductor
MSM9405
Registers
• TDR: Transmit Data Register (Write Only)
RDR: Receive Data Register (Read Only) (Address = 0h)
The TDR (Transmit Data Register) and RDR (Receive Data Register) are used to read/write data
directly upon receiving/sending the data. The TDR and RDR share the same address. When
data is written in the sending mode or during the idle state, the TDR works as the top of the FIFO
and 1-byte data can be written to the FIFO. When data is read in the receiving mode, the RDR
works as the bottom of the FIFO and 1-byte data in the FIFO can be read. Serial-to-parallel
conversion is performed by the RSR. Parallel-to-serial conversion is performed by the TSR.
Reading from the TDR or writing to the RDR is invalid. The contents of the FIFO and TDR/RDR
are cleard by writing "1" to FCLR in the ICR1 register. The TSR and RSR cannot be cleared.
• ENR: Enable Register (Address = 1h)
The ENR (Enable Register) is used to control enabling/disabling various interrupts on the
MSM9405. Each of eight bits corresponds to each of eight interrupts provided on the MSM9405.
Each of eight interrupts can be independently controlled by each bit. When the system is reset,
all bits are reset to "0". By writing "1" to the bit corresponding to the desired interrupt, the
specified interrupt is enabled.
ENR
ENR
ENR
ENR
ENR
ENR
ENR
ENR
7
6
5
4
3
2
1
0
FE_IE (Enable = "1")
AS_IE (Enable = "1")
ECE_IE (Enable = "1")
OE_IE (Enable = "1")
CE_IE (Enable = "1")
MLE_IE (Enable = "1")
EOF_IE (Enable = "1")
RXH/T_IE (Enable = "1")
TXL_IE (Enable = "1")
TXE_IE (Enable = "1")
16/30
¡ Semiconductor
MSM9405
Table bit
ENR bit
This bit works as FE_IE in SIR or Extended-SIR mode, as AS_IE in MIR mode, and as ECE_IE in FIR
mode.
- FE_IE (Framing Error Interrupt Enable) (SIR mode/Extended-SIR mode): This bit enables/disables
ENR[0]
interrupt when an FE (Framing Error : Stop bit not detected) has occurred.
- AS_IE (Abort Sequence Interrupt Enable) (MIR mode): This bit enables/disables interrupt when
an abort sequence has been received.
- ECE_IE (Encode Error Interrupt Enable) (FIR mode): This bit enables/disables interrupt when an
encode error has occurred.
OE_IE (Overrun Error Interrupt Enable) : This bit enables/disables interrupt when an OE (Overrun
ENR[1]
error : Error that occurs when the FIFO is full upon receiving and the next character is completely
received by the RSR) has occurred.
CE_IE (CRC Error Interrupt Enable) : This bit enables/disables interrupt when a CE (CRC Error) has
ENR[2]
occurred. This bit is valid in either Extended-SIR, MIR, or FIR mode. In SIR mode, this bit must
be set to "0" (disable).
MLE_IE (Maximum Length Error Interrupt Enable) : This bit enables/disables interrupt when an MLE
ENR[3]
(Maximum Length Error: Error that occurs when a frame exceeding the maximum data size set by
the MDS is received) has occurred.
EOF_IE (End Of Frame Interrupt Enable) : This bit enables/disables interrupt when the last byte in
ENR[4]
the frame's data field has been detected in either Extended-SIR, MIR, or FIR mode. In SIR mode,
this bit must be set to "0" (disable).
ENR[5]
ENR[6]
ENR[7]
RXH/T_IE (Receiver High-Data-Level/Timeout Interrupt Enable) : This bit enables/disables interrupt
when the received data is at or above the receiving threshold level or time-out has occurred.
TXL_IE (Transmitter Low-Data-Level Interrupt Enable) : This bit enables/disables interrupt when the
sent data is below the sending threshold level.
TXE_IE (Transmitter Empty Interrupt Enable) : This bit enables/disables interrupt when both the
FIFO and the TSR have become empty upon sending.
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¡ Semiconductor
MSM9405
• EIR: Event Identification Register (Read Only) (Address = 2h)
The EIR (Event Identification Register) indicates factors of various interrupts on the MSM9405.
Each of eight bits corresponds to each interrupt bit assignment set on the ENR. The EIR works
as the status register even if the interrupt is disabled. When an event occurs, each corresponding
bit is set to "1". When the system is reset, all bits are reset to "0".
EIR
EIR
EIR
EIR
EIR
EIR
EIR
EIR
7
6
5
4
3
2
1
0
FE_EV (Framing Error = "1")
AS_EV (Abort Sequence = "1")
ECE_EV (Encode Error = "1")
OE_EV (Overrun Error = "1")
CE_EV (CRC Error = "1")
MLE_EV (Maximum Length = "1")
EOF_EV (EOF = "1")
RXH/T_EV (RX High-Data-Level/Timeout = "1")
TXL_EV (TX Low-Data-Level = "1")
TXE_EV (TX Empty = "1")
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¡ Semiconductor
EIR bit
MSM9405
Description
This bit works as FE_EV in SIR or Extended-SIR mode, as AS_EV in MIR mode, and as ECE_EV in
FIR mode. When the CPU reads the EIR contents, this bit is set to "0".
EIR[0]
- FE_EV (Framing Error Event) (SIR mode/Extended-SIR mode): The bit is set to "1" when FE occurs.
- AS_EV (Abort Sequence Event) (MIR mode): The bit is set to "1" when an abort sequence is received.
- ECE_EV (Encode Error Event) (FIR mode): The bit is set to "1" when ECE occurs.
EIR[1]
OE_EV (Overrun Error Event): When OE occurs, this bit is set to "1". When the CPU reads the EIR
contents, OE_EV is set to "0". The RSR characters are not transferred to the FIFO but overwritten.
CE_EV (CRC Error Event): When a CRC error occurs, this bit is set to "1". When the CPU reads the
EIR[2]
EIR, this bit is set to "0". This bit is valid in either Extended-SIR, MIR, or FIR mode.
This bit is not used in SIR mode.
EIR[3]
MLE_EV (Maximum Length Error Event): When MLE occurs, this bit is set to "1". When the CPU
reads the EIR, this bit is set to "0".
EOF_EV (End Of Frame Event): This bit is valid in either Extended-SIR, MIR, or FIR mode. When the
EIR[4]
last byte in the frame's data field reaches the bottom of the FIFO in receiving mode, EOF_EV
is set to "1". When the CPU reads the EIR, this bit is set to "0". In SIR mode, this bit is not used.
RXH/T_EV (Receiver High-Data-Level/Timeout Event): When received data in the FIFO is at or above
the receiving threshold level or time-out occurs, RXH/T_EV is set to "1".
The condition for setting RXH/T_EV to "0" depends on the following two cases :
EIR[5]
If received data in the FIFO is at or above the receiving threshold level : Received data is read.
When received data in the FIFO is below the threshold level, this bit is set to "0".
If time-out occurs :
After received data in the FIFO is read, this bit is set to "0".
TXL_EV (Transmitter Low-Data-Level Event): When sent data in the FIFO is below the sending
EIR[6]
threshold level, this bit is set to "1". When sent data is written and sent data in the FIFO is at or
above the threshold level, this bit is set to "0".
EIR[7]
TXE_EV (Transmitter Empty Event): When both FIFO and TSR are empty in sending mode, this bit
is set to "1". When the CPU reads the EIR, this bit is set to "0".
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¡ Semiconductor
MSM9405
• LSR: Line Status Register (Read Only) (Address = 3h)
The LSR (Line Status Register) indicates various statuses of the MSM9405 that is running. When
the system is reset, all bits of the LSR are set to "0". This register is for read only and cannot be
written.
LSR
LSR
LSR
LSR
LSR
LSR
LSR
LSR
7
6
5
4
3
2
1
0
TOUT (Timeout = "1")
IR_DET (SIR Pulse detect = "1")
FLV (Byte number in FIFO)
LSR bit
LSR[0]
LSR[1]
LSR[2-7]
Description
TOUT (FIFO Timeout): When time-out occurs in the FIFO during receiving, this bit is set to "1".
When received data is read from the FIFO, TOUT is set to "0".
IR_DET (SIR Pulse detect) : This bit is set to "1" when a pulse having a width of tspw (SIR pulse width
upon receiving). It is set to "0" when the CPU reads the LSR.
FLV (FIFO Level): These bits indicate the number of data items in the FIFO with a value of 0 to 32.
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¡ Semiconductor
MSM9405
• ICR1: Infrared Control Register 1 (Address = 4h)
The ICR1 (Infrared Control Register 1) is used to set various environment so that the MSM9405
can perform IrDA communication under proper conditions. When the system is reset, all bits
of ICR1 are set to "0".
ICR1
ICR1
ICR1
ICR1
ICR1
ICR1
ICR1
ICR1
7
6
5
4
3
2
1
0
TX_EN ("1": Transmit Enable)
RX_EN ("1": Receive Enable)
S_EOT ("1": Set End Of Transmission)
IR_PLS ("1": Send Interaction Pulse)
FCLR ("1": FIFO Clear)
CRC_INV ("1": Send Inverted CRC Enable)
TCC_EN ("0": TCC off, "1": TCC on)
MS_EN ("1": Automatic mode Select)
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¡ Semiconductor
ICR1 bit
MSM9405
Description
TX_EN (Transmit Enable): When "1" is written to this bit, the sending mode is selected. When "0" is
ICR1[0]
written to this bit, sending terminates when data remaining in the FIFO has all been sent. In this
case, the TXE interrupt does not occur.
ICR1[1]
RX_EN (Receive Enable): When "1" is written to this bit, the receiving mode is selected. When "0" is
written to this bit, the device enters receive end mode.
S_EOT (Set End Of Transmission): This bit is valid in Extended-SIR, MIR, or FIR mode. When "1" is
written to this bit, the data written to the FIFO next time is recognized as the end of frame, and
ICR1[2]
immediately after it, the data added with CRC and EOF is sent as a frame. After a frame is sent,
this bit is automatically set to "0". To use S_EOT, TFL must be set to the maximum value or TCC
must be unused with TCC_EN = "0". This bit is not used in SIR mode.
IR_PLS (Send Interaction Pulse): This bit is valid in MIR or FIR mode. When "1" is written to
ICR1[3]
this bit, an approximately 2-ms serial infrared interaction pulse is sent immediately after the frame
being sent. After a frame is sent, this bit is automatically set to "0". This bit is not used in SIR
mode and Extended-SIR mode.
FCLR (FIFO Clear): When "1" is written to this bit, the FIFO (including the TDR and RDR) is made
ICR1[4]
empty. The FIFO threshold level does not change. The TSR and RSR are not cleared. When the
FIFO is made empty, this bit is automatically set to "0".
CRC_INV (Invert Transmitter CRC): This bit is valid in Extended-SIR, MIR, or FIR mode and is not
ICR1[5]
used in SIR mode. When "1" is written to this bit, transmission is interrupted if TXE (Transmitter
Empty) occurs. The inverted CRC and EOF are automatically added to the frame that caused TXE,
then the frame is sent. Writing "0" to this bit disables this function.
TCC_EN (TCC Enable): This bit is valid in Extended-SIR, MIR, or FIR mode. When this bit is set to
ICR1[6]
"1", the TCC is enabled. When TCC_EN is set to "0", the TCC is disabled. To use S_EOT, the TFL
must be set to the maximum value or the TCC must be disabled with TCC_EN = "0".
MS_EN (Mode Select Enable): When "1" is written to this bit, the MSM9405 performs the following
operation depending on the mode. After the operation is completed, this bit is automatically set to
"0".
If the MSM9405 is in FIR mode:
1. The SD pin is set to "H", and the Tx pin to "H".
ICR1[7]
2. Approximately 300 ns later, the SD pin is set to "L".
3. Approximately 300 ns later, the Tx pin is set to "L".
If the MSM9405 is in SIR, Extended-SIR, or MIR mode:
1. The SD pin is set to "H", and the Tx pin to "L".
2. Approximately 300 ns later, the SD pin is set to "L".
3. The Tx pin is held in the "L" level for approximately 300 ns.
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¡ Semiconductor
MSM9405
• ICR2: Infrared Control Register 2 (Address = 5h)
The ICR2 (Infrared Control Register 2) is used to set various environment so that the MSM9405
can perform IrDA communication under proper conditions. When the system is reset, all bits
of ICR2 are set to "0".
ICR2
ICR2
ICR2
ICR2
ICR2
ICR2
ICR2
ICR2
7
6
5
4
3
2
1
0
SBF (SIR Beginning Flags)
MBF (MIR Beginning Flags)
RXINV ("1": Signal Invert)
IRIN_SL ("0": Single Input "1": Double Input)
SD_INV ("0": SD Active High "1": SD Active Low)
CTEST ("0": TCC/RST "1": TFL/MDS)
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¡ Semiconductor
MSM9405
IRC2 bit
Description
These bits work as the SBF when Extended-SIR mode is selected, and as the MBF when the MIR
mode is selected. This function is disabled in SIR mode and FIR mode.
SBF (SIR beginning Flags): These bits determine the number of BOFs to be added during
sending in Extended-SIR mode as shown below.
MBF (MIR Beginning Flags): These bits determine the number of BOFs to be added during
sending in MIR mode as shown below.
ICR2[0-3]
Encoding
SIR BOFs
MIR BOFs
0000
1
2
0001
2
3
0010
3
4
0011
4
5
0100
5
8
0101
7
12
0110
9
16
0111
13
24
1000
17
24
1001
25
24
1010
49
24
1011
49
24
1100
49
24
1101
49
24
1110
49
24
1111
49
24
RXINV (IRIN Signal Invert): This bit is used to select active low or active high of the receive signal.
ICR2[4]
RXINV = "0": Active low
RXINV = "1": Active high
IRIN_SL (IRIN Select): This bit determines how the receive signal input pin is used.
ICR2[5]
IRIN_SL = "0": Only the input from the IRIN-A pin (2.4 kbps to 4 Mbps) is accepted.
IRIN_SL = "1": An input from IRIN-A or IRIN-B is automatically selected depending on the transfer
rate. (A: 2.4 to 115.2 kbps, B: 0.576 to 4 Mbps)
SD_INV (SD Signal Invert): This bit changes the polarity (active high/low) of the SD pin output on
ICR2[6]
the MSM9405.
SD_INV = "0": Active high ("H" output during shutdown)
SD_INV = "1": Active low ("L" output during shutdown)
ICR2[7]
CTEST (Counter Test): Normally this bit is set to "0". When TFL/TCC and MDS/RCC are read after
"1" is written to this bit, the TFL and MDS values can be obtained.
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¡ Semiconductor
MSM9405
• MSR: Mode Select Register (Address = 6h)
The MSR is used to select various modes of the MSM9405. When the system is reset, each bit
is set to the initial value.
MSR
MSR
MSR
MSR
MSR
MSR
MSR
MSR
7
6
5
4
3
2
1
0
IRSL0 (IrDA mode Select 0)
IRSL1 (IrDA mode Select 1)
Not Used
XT_SL ("0": 48 MHz "1": 18.432 MHz)
DRS (Data Rate Select)
MSR Bit
Description
IRSL (Infrared Mode Select): These bits are used to select the transfer mode as shown below.
The initial value is set to "00".
MSR[0-1]
MSR[2-3]
IRSL1
IRSL0
mode
0
0
SIR
0
1
Extended-SIR
1
0
MIR
1
1
FIR
These bits are not used.
XT_SL (Crystal Select): This bit determines the crystal to be used.
MSR[4]
The initial value is set to "0".
XT_SL = "0": 48 MHz crystal is used
XT_SL = "1": 18.432 MHz crystal is used
DRS (Data Rate Select): These bits determine the transfer rate as shown below. The initial value
is set to "001".
Encoding
MSR[5-7]
SIR Data Rate
MIR Data Rate
FIR Data Rate
000
2400 bps
0.576 Mbps
reserved
001
9600 bps
1.152 Mbps
4 Mbps
010
19.2 kbps
reserved
reserved
011
38.4 kbps
reserved
reserved
100
57.6 kbps
reserved
reserved
101
115.2 kbps
reserved
reserved
110
reserved
reserved
reserved
111
reserved
reserved
reserved
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¡ Semiconductor
MSM9405
• DSR: DMA Mode Select Register (Address = 7h)
The DSR (DMA Mode Select Register) is used to select the DMA mode for the MSM9405. When
the system is reset, all bits of DSR are set to "0".
DSR
DSR
DSR
DSR
DSR
DSR
DSR
DSR
7
6
5
4
3
2
1
0
DMA_EN ("1": DMA mode)
DMA_SL0 (DMA Select 0)
DMA_SL1 (DMA Select 1)
Not Used
Description
DSR Bit
DMA_EN (DMA Mode Enable): This bit determines whether the DMA is to be used. The initial value
is set to "0".
When "1" is written to this bit, DSR[1-2] (DMA_SL0, DMA_SL1) setting is enabled and the
DSR[0]
MSM9405 enters the DMA transfer standby mode. (DREQ is asserted when the DREQ assert
condition is met.)
If DMA_EN = "0", DSR[1-2] (DMA_SL0, DMA_SL1) setting is disabled and DMA transfer is not
performed. (DREQ is not asserted even if the DREQ assert condition is met.)
DMA_SL (DMA Select): These bits are used to select the method of interfacing with DMAC.
DMA_SL1
DMA_SL0
0
0
Function
DREQ becomes active low and DACK becomes active high.
When the RD signal becomes active while DACK is active,
the DMA read cycle (MemoryÆM9405) is selected. When
the WR signal becomes active while DACK is active, the
DMA write cycle (M9405ÆMemory) is selected. While
DACK is being asserted, address "0" (TDR/RDR) is
accessed regardless of the status of A0 to A3.
DSR[1-2]
0
1
DREQ becomes active high and DACK becomes active low.
When the WR signal becomes active while DACK is active,
the DMA read cycle (MemoryÆM9405) is selected. When
the RD signal becomes active while DACK is active, the
DMA write cycle (M9405ÆMemory) is selected. While
DACK is being asserted, address "0" (TDR/RDR) is
accessed regardless of the status of A0 to A3.
1
0
1
1
DREQ becomes active low and DACK becomes active high.
DACK is disabled.
DREQ becomes active high and DACK becomes active low.
DACK is disabled.
DSR[3-7]
These bits are not used.
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¡ Semiconductor
MSM9405
FCR : FIFO Control Register (Address = 8h)
The FCR (FIFO Control Register) is used to set the threshold level of the FIFO to be used by the
MSM9405 upon sending/receiving. The FCR setting is applied to both interrupt and DMA.
When the system is reset, the FCR is set to the initial value.
FCR
FCR
FCR
FCR
FCR
FCR
FCR
FCR
7
6
5
4
3
2
1
0
TXTH (TX Threshold Select)
RXTH (RX Threshold Select)
FCR bit
Description
TXTH (Transmit Threshold Select): These four bits set the following 16 sending threshold levels.
The initial value is set to "0111".
FCR[0-3]
FCR (0-3)
TX Threshold Level (Byte)
0000
01
0001
02
0010
04
0011
06
0100
08
0101
10
0110
12
0111
14
1000
16
1001
18
1010
20
1011
22
1100
24
1101
26
1110
28
1111
30
RXTH (Receive Threshold Select): These four bits set the following 16 receiving threshold levels.
FCR[4-7]
The relationship between the FCR (4-7) value and receiveing threshold level is the same as the
relationship between the FCR (0-3) and sending threshold level. The initial value is set to "0111".
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¡ Semiconductor
MSM9405
TFL : (Transmitter Frame Length Register
TCC : Transmitter Current-Count Register (Address = 9, Ah)
The TFL (Transmitter Frame Length) and TCC (Transmitter Current-Count Register) are used
to specify the length of the frame to be transferred for sending. The TFL and TCC shares the
same address. Bits 0 to 7 of address 9h and bits 0 to 3 of address Ah (totally 12 bits) are used.
Bit 0 of address 9h is the LSB.
When the TFL/TCC value is read, the CTEST setting is reflected. If CTEST = "0", the TCC
contents can be read. If CTEST = "1", the TFL contents can be read. When the TFL/TCC is
written, the TFL value is rewritten. The TCC cannot be written.
To use the TFL/TCC, write "1" to TCC_EN, and set the frame length in the TFL. The frame length
to be set does not include the CE, FCS, BOF, and EOF. When "1" is written to TX_EN, the TFL
value that has been set as the frame length is loaded to the TCC. When sending is started, the
TCC value is decremented by 1 each time 1 byte is sent. When the TCC value becomes "0", the
end of frame is assumed and the frame is automatically added with the CRC and EOF and sent.
After one frame is sent, the TFL value is loaded again into the TCC when the BOF of the second
frame is sent.
The TFL/TCC initial value is set to 800h.
MDS : Maximum Data Size Register
RST : Receiver Frame Length Stack Register (Address = B, Ch)
The MDS (Maximum Data Size Register) is used to set the maximum data size. The RST
(Receiver Frame Length Stack Register) is used to stack the received frame length. The MDS and
RST share the same address. Bits 0 to 7 of address Bh and bits 0 to 3 of address Ch (totally 12
bits) are used. Bit 0 of address Bh is the LSB.
When the MDS/RST value is read, the CTEST setting is reflected. If CTEST = "0", the RST
contents can be read. If CTEST = "1", the MDS contents can be read. When the MDS/RST is
written, the MDS value is rewritten. The RST cannot be written.
To use the MDS, set the maximum data size in the MDS in advance. The frame length to be set
does not include the CE, FCS, BOF, and EOF in the Extended-SIR, MIR, and FIR modes.
(However, it does include them in the SIR mode.) When receiving is started, the internal counter
value is incremented by 1 each time one byte is received. If the internal counter value exceeds
the MDS value during receiving, MLE occurs. The MDS initial value is set to 800h.
When a frame is fully received and all the data in the received frame is taken out of the FIFO,
the received frame length counted by the internal counter is stacked in the RST. This value is
stored untill the next frame is fully received. The value stacked in the RST is maintained even
if MSM9405 sending/receiving is switched. The RST initial value is set to 0h.
TEST : Test Register (Address = Fh)
This register is used for testing.
28/30
¡ Semiconductor
MSM9405
APPLICATION CIRCUIT
D0-D7
A0-A3
IRIN-A
RXD-A
IRIN-B
(RXD-B)
IROUT
TXD
Infrared
Transceiver
Module
Microcontroller
CS
RD
WR
TC
SD
MSM9405
SD
INTR
DREQ
DACK
XIN
XOUT
RESET
PWDN
29/30
¡ Semiconductor
MSM9405
PACKAGE OUTLINES AND DIMENSIONS
(Unit : mm)
Mirror finish
30-Pin Plastic SSOP
30/30