PERICOM PI6C2310

PI6C2310
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PCI-X Clock Buffers
Product Features
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Product Description
Four synchronous outputs
Selectable divider/multiplier
Output Enable control
Low phase error < 150 ps
Allows clock input to have spread spectrum modulation for
EMI reduction
Low output skew < 200 ps
Low cycle jitter < 200 ps
Industrial temperature (–40° C to 85° C)
3.3V V supply
Packages: 24-pin QSOP (Q) and 24-pin TSSOP (L)
PI6C2310 is a low skew, low jitter, PLL clock buffer with divider or
multiplier designed for PCI-X application in servers and workstations. There are two selectable input ranges using HF# input: 10-40
MHz and 40-80 MHz. All outputs are synchronized to the input and
to the other outputs. Each output can be independently turned off
to reduce EMI and power consumption.
Block Diagram
Pin Configuration
OUT0
OUT1
OUT2
OE[0:3]
HF#
OUT3
CLKIN
PLL
FBIN
FBOUT
DIV
DIV[0:1]
AGND
1
24
CLKIN
VCC
2
23
AVCC
HF#
3
22
VCC
DIV0
4
21
OUT0
DIV1
5
20
OUT1
GND
6
24-Pin
Q, L 19
GND
7
18
GND
FBIN
8
17
OUT2
FBOUT
9
16
OUT3
VCC
10
15
VCC
OE0
11
14
OE3
OE1
12
13
OE2
GND
Clock Select Table
HF#
DIV1
DIV0
OUTx
1
1
1
CLKIN
1
1
0
2xCLKIN
CLKIN
OUTx
33MHz
66MHz
33MHz
1
0
1
3xCLKIN
100MHz
1
0
0
4xCLKIN
133MHz
0
1
1
CLKIN/2
33MHz
0
1
0
CLKIN
66MHz
66MHz
0
0
1
1.5xCLKIN
100MHz
0
0
0
2xCLKIN
133MHz
1
PS8502
10/10/00
PI6C2310
PCI-X
Clock
Buffers
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Pin Description
Pin
Type
Qty
Symbol
De s cription
16,17,20,21
O
4
OUT[0:3]
Clock outputs. To achieve zero input to output delay, all outputs must have the
same loading.
11- 14
I
4
OE[0:3]
Active high Output Enable, pulled up. When OE is low, OUT [0:3] outputs are
disabled at low state.
9
O
1
FBOUT
Feedback output. To achieve zero input to output delay, FBOUT must have the
same loading as OUT[0:3].
8
I
1
FBIN
Feedback input. 7pF must be added to the output driving this pin (FBOUT) in
addition to the other load.
24
I
1
CLKIN
3
I
1
HF#
4,5
I
2
DIV[0,1]
2,10,15,22
P
4
VCC
3.3V power
6 , 7 , 18 , 19
P
4
GND
Ground
23
P
1
AVCC
3.3V analog power
1
P
1
AGND
Analog ground
Input Clock.
High Frequency range, pulled up.
"1" = Low, "0" = High.
Divider/Multiplier Select, pulled up.
Absolute Maximum Ratings
Supply Voltage (VCC, AVCC) ................................................ 0.5V to +7.0V
Input Voltage ................................................................ –0.5V to Vcc+0.5V
Industrial Operating Temperature ....................................... -40°C to +85°C
Storage Temperature ........................................................ –65°C to +150°C
Junction Temperature ....................................................................... 150°C
Input ESD MIL-883, Method 3015, human body model ....................... 2kV
Operating Condition
Symbol
VCC, AVCC
Ta
De s cription
M in.
M ax.
Units
I/O Supply, Analog Core Supply
3.0
3.6
V
Industrial Ambient Temperature
–40
+85
°C
2
PS8502
10/10/00
PI6C2310
PCI-X
Clock
Buffers
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DC Electrical Characteristics Over Operating Conditions
Symbol
Parame te r
Conditions
M in.
Typ.
M ax.
Vil
Low Input Voltage
Vih
High Input Voltage
Iil
Low Input Current
VIN = 0V
50
Iih
High Input Current
VIN = VCC
200
Vol
Low Output Voltage
VCC = 3.0V, Iol = 12mA
0.4
Voh
High Output Voltage
VCC = 3.0V, Ioh = –12mA
Idd_33
Supply Current
Cl = 15pF, FOUT = 33MHz
25
Idd_66
Supply Current
Cl = 15pF, FOUT = 66MHz
35
Idd_100
Supply Current
Cl = 15pF, FOUT = 100MHz
45
Idd_133
Supply Current
Cl = 15pF, FOUT = 133MHz
60
Units
0.8
V
2.0
uA
V
2.4
tbd
Co
Output Capacitance
6
Ci
Input Capacitance
5
Cl
Load Capacitance
15
Pin Inductance
7
Lpin
mA
pF
nH
Switching Characteristics (TA = 25°C, VCC = 3.3V ±0.3V, Cl = 15pF, FOUT = 66.67 MHz)
Symbol
Fin
Parame te r
Te s t Conditions
M in.
Typ.
M ax.
Low Freq., HF# = "1"
10
33
40
High Freq., HF# = "0"
40
66
80
Input frequency
Units
MHz
Tpd
Propagation delay
CLKIN to FBIN rising edges @VDD/2
–150
15 0
Tsk
Output skew
@1.4V, rising edges
200
Tskpp
Pkg to pkg skew
@VDD/2, rising edges, same CLKIN
400
Tjc
Cycle jitter
Tdc
Duty cycle
@1.4V
Tr/Tf
Rise/Fall time
0.8V~2.0V
ps
200
45
50
55
%
1.5
ns
Note: Tjc = Tp(n+1) –Tp(n)
Tdc = Th/Tp
Tp(n) = Period of the nth cycle
Tp = Period cycle time
Tp(n+1) = Period of nth+1 cycle Th = High time @1.4V
3
PS8502
10/10/00
PI6C2310
PCI-X
Clock
Buffers
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2.0V
T1
2.0V
0.8V
0.8V
Tr
1.4V
Tf
Tp
Figure 1. Rise/Fall time
Figure 2. Duty cycle
1.4V
Tp(n)
OUTx
1.65V
Tsk
OUTy
1.65V
1.4V
Tp(n+1)
Figure 4. Cycle jitter
Figure 3. Output skew
Device1
OUTx
1.65V
CLKIN
Tpd
Tskp2p
Device2
OUTy
1.65V
1.65V
FBIN
1.65V
Figure 6. Propagation Delay
Figure 5. Pkg.-to-Pkg. skew
DUT
OUTx
15pF
Figure 7. Test load
4
PS8502
10/10/00
PI6C2310
PCI-X
Clock
Buffers
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Packaging Mechanical: 24-pin QSOP (Q)
24
.150
.157
3.81
3.99
.015 x 45˚
0.38
1
.337
.344
8.56
8.74
.053
.069
1.35
1.75
.004
.008
0.09
0.20
.228
.244
5.79
6.20
SEATING
PLANE
.025
typical
0.635
0.178
0.254
0.406
1.27
.016
.050
.033
0.84
.007
.010
.004 0.101
.010 0.254
.008 0.203
.012 0.305
X.XX DENOTES DIMENSIONS
X.XX IN MILLIMETERS
Packaging Mechanical: 24-Pin TSSOP (L)
24
.169
.177
1
4.3
4.5
.303
.311
7.7
7.9
.047
1.20
Max
.0256
BSC
0.65
.007
.012
0.19
0.30
.002
.006
0.45
0.75
SEATING
PLANE
.018
.030
.252
BSC
6.4
0.05
0.15
X.XX DENOTES CONTROLLING
X.XX DIMENSIONS IN MILLIMETERS
Ordering Information
Orde ring Code
Package Name
Package Type
PI6C2310Q
Q 24
24- pin, 150- mil QSOP
PI6C2310L
L24
24- pin, 4.4- mil TSSOP
Ope rating Te mp
Industrial
Pericom Semiconductor Corporation
2380 Bering Drive • San Jose, CA 95131 • 1-800-435-2336 • Fax (408) 435-1100 • http://www.pericom.com
5
PS8502
10/10/00