IDT 2305M-1LF

DATASHEET
ICS2305
3.3 VOLT ZERO DELAY LOW SKEW BUFFER
Description
Features
The ICS2305 is a low phase noise, high-speed PLL
based, low-skew zero delay buffer. Based on IDT’s
proprietary low jitter Phase Locked Loop (PLL)
techniques, the device provides four low skew outputs
at speeds up to 133 MHz at 3.3 V. The outputs can be
generated from the PLL (for zero delay), or directly from
the input (for testing), and can be set to tri-state mode
or to stop at a low level. The PLL feedback is on-chip
and is obtained from the CLKOUT pad.
•
•
•
•
•
Clock outputs from 10 to 133 MHz
•
•
•
•
•
•
5 V tolerant CLKIN
The ICS2305 is available in two different versions. The
ICS2305-1 is the base part. The ICS2305-1H is a high
drive version with faster rise and fall times.
Zero input-output delay
Four low skew (<250 ps) outputs
Device-to-device skew <700 ps
Full CMOS outputs with 25 mA output drive
capability at TTL levels
Tri-state mode for board-level testing
Advanced, low power, sub-micron CMOS process
Operating voltage of 3.3 V
Industrial temperature range available
Packaged in 8-pin SOIC
Block Diagram
VDD
CLKIN
PLL
CLKOUT
CLK1
CLK2
CLK3
CLK4
GND
IDT™ / ICS™ 3.3 VOLT ZERO DELAY LOW SKEW BUFFER
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Pin Assignment
CLKIN
1
8
CLKOUT
CLK2
2
7
CLK4
CLK1
3
6
VDD
GND
4
5
CLK3
8 pin ( 150 mil ) SOIC
Pin Descriptions
Pin
Number
Pin
Name
Pin Type
1
CLKIN
Input
Clock input (5 V tolerant).
2
CLK2
Output
Buffered Clock output 2.
3
CLK1
Power
Buffered Clock output 1
4
GND
Power
Connect to ground.
5
CLK3
Output
Buffered Clock output 3
6
VDD
Power
Power supply. Connect to 3.3 V.
7
CLK4
Output
Buffered Clock output 4.
8
CLKOUT
Output
Buffered output. Internall feedback on this pin.
IDT™ / ICS™ 3.3 VOLT ZERO DELAY LOW SKEW BUFFER
Pin Description
2
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External Components
The ICS2305 requires a minimum number of external components for proper operation. Decoupling
capacitors of 0.01 mF should be connected between VDD and GND on pins 4 and 5, and VDD and GND
on pins 13 and 12, as close to the device as possible. A series termination resistor of 33Ω may be used to
each clock output pin to reduce reflections.
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the ICS2305. These ratings,
which are standard values for IDT commercially rated parts, are stress ratings only. Functional operation of
the device at these or any other conditions above those indicated in the operational sections of the
specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can
affect product reliability. Electrical parameters are guaranteed only over the recommended operating
temperature range.
Item
Rating
Supply Voltage, VDD
7V
All Inputs and Outputs
-0.5 V to VDD+0.5 V
CLKIN and FBIN inputs
-0.5 V to 5.5 V
Electrostatic Discharge (HBM)
2000 V
Ambient Operating Temperature (Commercial)
0 to +70° C
Ambient Operating Temperature (Industrial)
-40 to +85° C
Storage Temperature
-65 to +150° C
Junction Temperature
150° C
Soldering Temperature
260° C
Recommended Operation Conditions
Parameter
Min.
Ambient Operating Temperature (Industrial)
Ambient Operating Temperature (Commercial)
Power Supply Voltage (measured in respect to GND)
IDT™ / ICS™ 3.3 VOLT ZERO DELAY LOW SKEW BUFFER
3
Typ.
Max.
Units
-40
+85
°C
0
+70
°C
+3.0
+3.6
V
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DC Electrical Characteristics
ICS2305M-XX, VDD = 3.3 V ±10%, Ambient Temperature -40 to +85° C(Industrial), (0-70° C Commercial)
Parameter
Symbol
Conditions
Min.
Operating Voltage
VDD
3.0
Input High Voltage
VIH
2
Input Low Voltage
VIL
Input Low Current
IIL
Input High Current
IIH
Typ.
Max.
Units
3.6
V
V
0.8
V
VIN = 0V
50
µA
VIN = VDD
100
µA
Output High Voltage
VOH
IOH = -12 mA
Output Low Voltage
VOL
IOL = 12 mA
0.4
V
Operating Supply Current
IDD
No Load
32
mA
CLKIN = 0, Note 1
12
µA
Power Down Supply
Current
Short Circuit Current
IOS
Each output
Input Capacitance
CIN
CLKIN
2.4
V
±50
mA
5
pF
Note 1: When there is no clock signal present at CLKIN, the ICS2305 will enter power down mode. The
PLL is stopped and the outputs are tri-state.
AC Electrical Characteristics
ICS2305M-1, VDD=3.3 V ±10%, Ambient temperature -40 to +85° C(Industrial), (0-70° C Commercial)
Parameter
Symbol
Output Clock Frequency
fIN
Output Clock Frequency
Conditions
Min.
Typ.
Max. Units
10 pF load
10
133
MHz
30 pF load
10
100
MHz
Output Rise Time
tOR
0.8 to 2.0 V, outputs loaded
2.5
ns
Output Fall Time
tOF
2.0 to 0.8 V, outputs loaded
2.5
ns
Output Clock Duty Cycle
tDC
measured at 1.4V, Fout=66.67
MHz
40
50
60
%
Output Clock Duty Cycle
tDC
measured at 1.4V, Fout=50 MHz
45
50
55
%
Device to Device Skew
rising edges at VDD/2
700
ps
Output to Output Skew
rising edges at VDD/2
250
ps
Input to Output Skew
rising edges at VDD/2
±350
ps
Cycle to Cycle Jitter
measured at 66.67M, outputs
loaded
200
ps
PLL Lock Time
Note 2
1.0
ms
Note 2: With VDD at a steady rate and valid input at CLKIN.
IDT™ / ICS™ 3.3 VOLT ZERO DELAY LOW SKEW BUFFER
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ICS2305M-1H, VDD=3.3 V ±10%, Ambient temperature -40 to +85° C(Industrial), (0-70° C Commercial),
Parameter
Symbol
Output Clock Frequency
fIN
Output Clock Frequency
Conditions
Min.
Typ.
Max. Units
10 pF load
10
133
MHz
30 pF load
10
100
MHz
Output Rise Time
tOR
0.8 to 2.0 V, outputs loaded
1.5
ns
Output Fall Time
tOF
2.0 to 0.8 V, outputs loaded
1.5
ns
Output Clock Duty Cycle
tDC
measured at 1.4V, Fout=66.67
MHz
40
50
60
%
Output Clock Duty Cycle
tDC
measured at 1.4V, Fout=50 MHz
45
50
55
%
Device to Device Skew
rising edges at VDD/2
700
ps
Output to Output Skew
rising edges at VDD/2
250
ps
Input to Output Skew
rising edges at VDD/2
±350
ps
Cycle to Cycle Jitter
measured at 66.67M, outputs
loaded
200
ps
PLL Lock Time
Note 3
1.0
ms
Note 3: With VDD at a steady rate and valid input at CLKIN
Thermal Characteristics
Parameter
Thermal Resistance Junction to
Ambient
Thermal Resistance Junction to Case
IDT™ / ICS™ 3.3 VOLT ZERO DELAY LOW SKEW BUFFER
Symbol
Conditions
Min.
Typ.
Max. Units
θJA
Still air
120
° C/W
θJA
1 m/s air flow
115
° C/W
θJA
3 m/s air flow
105
° C/W
58
° C/W
θJC
5
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Package Outline and Package Dimensions (8-pin SOIC, 150 Mil. Narrow Body)
Package dimensions are kept current with JEDEC Publication No. 95
8
Millimeters
Symbol
E
Min
A
A1
B
C
D
E
e
H
h
L
α
H
INDEX
AREA
1 2
D
A
Inches
Max
Min
1.35
1.75
0.10
0.25
0.33
0.51
0.19
0.25
4.80
5.00
3.80
4.00
1.27 BASIC
5.80
6.20
0.25
0.50
0.40
1.27
0°
8°
Max
.0532
.0688
.0040
.0098
.013
.020
.0075
.0098
.1890
.1968
.1497
.1574
0.050 BASIC
.2284
.2440
.010
.020
.016
.050
0°
8°
h x 45
A1
C
-Ce
B
SEATING
PLANE
L
.10 (.004)
IDT™ / ICS™ 3.3 VOLT ZERO DELAY LOW SKEW BUFFER
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Ordering Information
Part / Order Number
Marking
Shipping Packaging
Package
Temperature
2305MI-1LF
2305MI-1LFT
2305MI-1HLF
2305MI-1HLFT
2305M-1LF
2305M-1LFT
2305M-1HLF
2305M-1HLFT
2305MI1L
2305MI1L
2305I1HL
2305I1HL
2305M1LF
2305M1LF
2305M1HL
2305M1HL
Tubes
Tape and Reel
Tubes
Tape and Reel
Tubes
Tape and Reel
Tubes
Tape and Reel
8-pin SOIC
8-pin SOIC
8-pin SOIC
8-pin SOIC
8-pin SOIC
8-pin SOIC
8-pin SOIC
8-pin SOIC
-40 to +85° C
-40 to +85° C
-40 to +85° C
-40 to +85° C
0 to +70° C
0 to +70° C
0 to +70° C
0 to +70° C
“LF” denotes Pb (lead free) package.
While the information presented herein has been checked for both accuracy and reliability, IDT assumes no responsibility for either its use or for
the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied.
This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range,
high reliability, or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the
right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or
critical medical instruments.
IDT™ / ICS™ 3.3 VOLT ZERO DELAY LOW SKEW BUFFER
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Revision History
Rev.
Originator
Date
Description of Change
A
P. Griffith
12/01/04
New device/datasheet; Preliminary.
B
P. Griffith
12/27/04
Made corrections to IDD, IDDP, input capacitance, duty cycle and jitter specs/test
conditions. Removed reference to table 2 in output clock frequency test conditions.
Removed abslolute and cycle-to-cycle jitter specs for 15 pF load. Added duty cycle spec
for Fout=50 MHz. Release from Preliminary to Final.
C
P. Griffith
1/25/05
Made corrections to test conditions of output rise time, fall-time, duty cycle and
cycle-to-cycle jitter.
D
J. Sarma
2/25/05
Added LF packing info.
E
08/17/09
Added EOL note per PDN U-09-01.
F
05/13/10
Removed EOL note and non-green orderable parts.
IDT™ / ICS™ 3.3 VOLT ZERO DELAY LOW SKEW BUFFER
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