Data sheet acquired from Cypress Semiconductor Corporation. Data sheet modified to remove devices not offered. CY74FCT163373 16-Bit Latch SCCS053 - March 1997 - Revised March 2000 Features Functional Description • Low power, pin-compatible replacement for LCX and LPT families • 5V tolerant inputs and outputs • 24 mA balanced drive outputs • Power-off disable outputs permits live insertion • Edge-rate control circuitry for reduced noise • FCT-C speed at 4.2 ns • Latch-up performance exceeds JEDEC standard no. 17 • Typical output skew < 250 ps • Industrial temperature range of –40˚C to +85˚C • TSSOP (19.6-mil pitch) or SSOP (25-mil pitch) • Typical Volp (ground bounce) performance exceeds Mil Std 883D • VCC = 2.7V to 3.6V • ESD (HBM) > 2000V This device is a 16-bit, D-type latch, designed for use in bus applications requiring high speed and low power. It can either be used as two independent 8-bit latches, or as a single 16-bit latch by connecting the Output Enable (OE) and Latch (LE) inputs. The outputs are 24-mA balanced output drivers with current limiting resistors to reduce the need for external terminating resistors and provide for minimal undershoot and reduced ground bounce. Flow-through pinout and small shrink packaging aid in simplifying board layout. The CY74FCT163373 is designed with inputs and outputs capable of being driven by 5.0V buses, allowing its use in mixed voltage systems as a translator. The outputs are also designed with a power off disable feature enabling its use in applications requiring live insertion. Pin Configuration Logic Block Diagrams CY74FCT163373 SSOP/TSSOP Top View 1OE 1LE 1D1 D 1O1 C TO 7 OTHER CHANNELS 2OE 2LE 2D1 D 2O1 C TO 7 OTHER CHANNELS 1OE 1 48 1O1 2 47 1D1 1O2 3 46 1D2 GND 4 45 GND 1O3 5 44 1D3 1O4 6 43 1D4 VCC 1O5 7 42 8 41 VCC 1D5 1O6 1LE 9 40 1D6 GND 10 39 GND 1O7 11 38 1D7 1O8 37 36 1D8 2O1 12 13 2O2 14 35 2D2 GND 15 34 GND 2O3 16 33 2D3 2O4 17 32 2D4 VCC 2O5 18 31 19 30 VCC 2D5 2D1 2O6 20 29 2D6 GND 21 28 GND 2O7 22 27 2D7 2O8 23 26 2D8 2OE 24 25 2LE Copyright © 2000, Texas Instruments Incorporated CY74FCT163373 Maximum Ratings[2, 3] Pin Description Name (Above which the useful life may be impaired. For user guidelines, not tested.) Description D Data Inputs LE Latch Enable Inputs (Active HIGH) OE Output Enable Inputs (Active LOW) Ambient Temperature with Power Applied .................................................. −55°C to +125°C O Three-State Outputs Supply Voltage Range ..................................... 0.5V to +4.6V Storage Temperature ...................................... −55°C to +125°C DC Input Voltage .................................................−0.5V to +7.0V Function Table[1] DC Output Voltage ..............................................−0.5V to +7.0V Inputs DC Output Current (Maximum Sink Current/Pin) ...........................−60 to +120 mA Outputs D LE OE O H H L H L H L L X L L Q0 X X H Z Power Dissipation .......................................................... 1.0W Operating Range Range Industrial Ambient Temperature VCC −40°C to +85°C 2.7V to 3.6V Electrical Characteristics for Non Bus Hold Devices Over the Operating Range VCC=2.7V to 3.6V Parameter Description Test Conditions VIH Input HIGH Voltage All Inputs VIL Input LOW Voltage VH Input Hysteresis[5] VIK Input Clamp Diode Voltage VCC=Min., IIN=–18 mA IIH Input HIGH Current IIL Min. Typ.[4] 2.0 Max. Unit 5.5 V 0.8 100 –0.7 V mV –1.2 V VCC=Max., VI=5.5 ±1 µA Input LOW Current VCC=Max., VI=GND ±1 µA IOZH High Impedance Output Current (Three-State Output pins) VCC=Max., VOUT=5.5V ±1 µA IOZL High Impedance Output Current (Three-State Output pins) VCC=Max., VOUT=GND ±1 µA IOS Short Circuit Current[6] VCC=Max., VOUT=GND –240 mA IOFF Power-Off Disable VCC=0V, VOUT≤4.5V ±100 µA ICC Quiescent Power Supply Current VIN≤0.2V, VIN>VCC–0.2V VCC=Max. 0.1 10 µA ∆ICC Quiescent Power Supply Current (TTL inputs HIGH) VIN=VCC–0.6V[7] VCC=Max. 2.0 30 µA –60 –135 Note: 1. H = HIGH Voltage Level. L = LOW Voltage Level. X = Don’t Care. Z = High Impedance. Q0=Previous state of flip-flop. 2. Operation beyond the limits set forth may impair the useful life of the device. Unless otherwise noted, these limits are over the operating free-air temperature range. 3. With the exception of inputs with bus hold, unused inputs must always be connected to an appropriate logic voltage level, preferably either VCC or ground. 4. Typical values are at VCC=3.3V, TA = +25˚C ambient. 5. This parameter is specified but not tested. 6. Not more than one output should be shorted at a time. Duration of short should not exceed one second. The use of high-speed test apparatus and/or sample and hold techniques are preferable in order to minimize internal chip heating and more accurately reflect operational values. Otherwise prolonged shorting of a high output may raise the chip temperature well above normal and thereby cause invalid readings in other parametric tests. In any sequence of parameter tests, IOS tests should be performed last. 7. Per TTL driven input; all other inputs at VCC or GND. 2 CY74FCT163373 Electrical Characteristics For Balanced Drive Devices Over the Operating Range VCC=2.7V to 3.6V Parameter Description Test Conditions [6] Min. IODL Output LOW Dynamic Current VCC=3.3V, VIN=VIH or VIL, VOUT=1.5V 45 IODH Output HIGH Dynamic Current[6] VCC=3.3V, VIN=VIH or VIL, VOUT=1.5V –45 VOH Output HIGH Voltage VCC=Min., IOH= –0.1 mA VOL Output LOW Voltage Typ.[4] Max. Unit 180 mA – –180 mA VCC–0.2 V VCC=Min., IOH= –8 mA 2.4[8] 3.0 V VCC=3.0V, IOH= –24 mA 2.0 3.0 V VCC=Min., IOL= 0.1mA 0.2 VCC=Min., IOL= 24 mA 0.3 V 0.55 Note: 8. VOH=VCC–0.6 V at rated current. Capacitance[5](TA = +25˚C, f = 1.0 MHz) Parameter Description Test Conditions Typ.[4] Max. Unit CIN Input Capacitance VIN = 0V 4.5 6.0 pF COUT Output Capacitance VOUT = 0V 5.5 8.0 pF Typ.[4] Max. Unit 50 75 µA/MHz Power Supply Characteristics Parameter Description Test Conditions ICCD Dynamic Power Supply Current[9] VCC=Max., One Input Toggling, 50% Duty Cycle, Outputs Open, OE=GND IC Total Power Supply Current[10] VCC=Max., f1=10 MHz, 50% Duty VIN=VCC or Cycle, Outputs Open, VIN=GND One Bit Toggling, OE=GND VIN=VCC–0.6V or VIN=GND 0.5 0.8 mA 0.5 0.8 mA VCC=Max., f1=2.5 MHz, 50% Duty VIN=VCC or Cycle, Outputs Open, Sixteen Bits VIN=GND Toggling, OE=GND VIN=VCC–0.6V or VIN=GND 2.0 3.0[11] mA 2.0 3.3[11] mA 3 VIN=VCC or VIN=GND CY74FCT163373 Switching Characteristics Over the Operating Range VCC=3.0V to 3.6V[12,13] CY74FCT163373C Parameter Description Min. Max. Unit Fig. No.[14] tPLH tPHL Propagation Delay D to Q Output 1.5 4.1 ns 1, 3 tPLH tPHL Propagation Delay LE to Q Output 2.0 5.5 ns 1, 5 tPZH tPZL Output Enable Time 1.5 5.8 ns 1, 7, 8 tPHZ tPLZ Output Disable Time 1.5 5.2 ns 1, 7, 8 tSU Input Setup time 2.0 - ns 1, 4 tH Input Hold time 1.5 - ns 1, 4 0.5 ns — tSK(O) Output Skew[15] Notes: 9. This parameter is not directly testable, but is derived for use in Total Power Supply calculations. 10. IC = IQUIESCENT + IINPUTS + IDYNAMIC IC = ICC+∆ICCDHNT+ICCD(f0/2 + f1N1) ICC = Quiescent Current with CMOS input levels ∆ICC = Power Supply Current for a TTL HIGH input (VIN=3.4V) DH = Duty Cycle for TTL inputs HIGH NT = Number of TTL inputs at DH ICCD = Dynamic Current caused by an input transition pair (HLH or LHL) = Clock frequency for registered devices, otherwise zero f0 = Input signal frequency f1 N1 = Number of inputs changing at f1 All currents are in milliamps and all frequencies are in megahertz. 11. Values for these conditions are examples of the ICC formula. These limits are specified but not tested. 12. Minimum limits are specified but not tested on Propagation Delays. 13. For VCC =2.7, propagation delay, output enable and output disable times should be degraded by 20%. 14. See “Parameter Measurement Information” in the General Information section. 15. Skew between any two outputs of the same package switching in the same direction. This parameter is ensured by design. Ordering Information CY74FCT163373 Speed (ns) 4.2 Ordering Code Package Name Package Type CY74FCT163373CPACT Z48 48-Lead (240-Mil) TSSOP CY74FCT163373CPVC/PVCT O48 48-Lead (300-Mil) SSOP 4 Operating Range Industrial CY74FCT163373 Package Diagrams 48-Lead Shrunk Small Outline Package O48 48-Lead Thin Shrunk Small Outline Package Z48 5 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. 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