PMC PM37LV512

PMC
Pm37LV512
512 Kbit (64K X 8) Dual-Voltage Multiple-Cycle-Programmable ROM
FEATURES
• Low Power Consumption
- Typical 5 mA active read current
- Typical 18 µA CMOS standby current
• Low Voltage Operation
- Dual read VCC ranges: 2.7 V to 3.6 V or 4.5 V to
5.5 V
- Program/Erase voltage: VCC - 2.7 V to 3.6 V and
VPP - 11.5 V to 12.5 V
• Excellent Product Reliablity
- Guarantee minimum 1,000 program/erase cycles
- Minimum 20 years data retention
• High Performance Read
- 70 ns access time
• JEDEC Standard Byte-wide Flash Memory
Pin-out
• Electrical Chip Erase and Byte Program
Using EPROM Programmer
- Maximum 20 µs/byte programming
- Maximum 100 ms chip erase
- Do not require UV erase
• Industrial Standard Packaging
- 32-pin PLCC
- 32-pin PDIP
- 32-pin VSOP
GENERAL DESCRIPTION
The Pm37LV512 is a 512 Kbit, Multiple-Cycle-Programmable Read-Only-Memory (MCP ROM) organized as 65,563
bytes of 8 bits each. The program and erase operation of device can be done on EPROM programmers by applying
3.0 Volt VCC and 12.0 Volt VPP to A9 and/or OE# pin. This eliminates the need of a UV-Source for erase operation
such as EPROM device. The read operation of device can be in 2.7 Volt to 3.6 Volt or 4.5 Volt - 5.5 Volt range
compatible to either 3.0 Volt or 5.0 Volt systems. The dual read operation ranges can greatly increase application
flexibility for users.
The device has a standard microprocessor interface as well as JEDEC single-power-supply Flash compatible pinout. For applications that do not require in-system-programming (ISP) function for firmwire upgrade, the Pm37LV512
offers a direct cost reduction path for Flash memory, i.e. Pm39LV512, without modifying the schematic and board
layout of system.
The Pm37LV512 is manufactured on PMC’s advanced nonvolatile CMOS technology, P-FLASH™. The device is
offered in 32-pin PLCC, VSOP and PDIP packages with access time of 70 ns.
Programmable Microelectronics Corp.
1
Issue Date: Dec, 2002 Rev:1.3
Pm37LV512
PMC
4
3
2
1
32
31
NC
WE#
V CC
NC
NC
A15
A12
CONNECTION DIAGRAMS
30
A7
5
29
A14
A6
6
28
A13
A5
7
27
A8
A4
8
26
A9
A3
9
25
A11
A2
10
24
OE#
A1
11
23
A10
A0
12
22
CE#
I/O0
13
21
I/O7
20
1
2
3
4
5
6
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
7
8
9
10
11
12
13
14
15
16
I/O6
19
I/O5
18
I/O4
17
I/O3
16
GND
15
I/O2
I/O1
14
NC
NC
A15
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
GND
V CC
WE#
NC
A14
A13
A8
A9
A11
OE#
A10
CE#
I/O7
I/O6
I/O5
I/O4
I/O3
17
32-Pin PDIP
32-Pin PLCC
LOGIC SYMBOL
A11
A9
A8
A13
A14
NC
WE#
V CC
NC
NC
A15
A12
A7
A6
A5
A4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
OE#
A10
CE#
I/O7
I/O6
I/O5
I/O4
I/O3
GND
I/O2
I/O1
I/O0
A0
A1
A2
A3
16
A0-A15
8
I/O0-I/O7
CE#
OE#
WE#
32-Pin VSOP
Programmable Microelectronics Corp.
2
Issue Date: Dec, 2002 Rev: 1.3
Pm37LV512
PMC
PRODUCT ORDERING INFORMATION
Pm37LV512
-70
J
C
Temperature Range
C = Commercial (0°C to +70°C)
Package Type
J = 32-pin Plastic J-Leaded Chip Carrier (32J)
P = 32-pin Plastic DIP (32P)
V = 32-pin Thin Small Outline Package (32V)
Speed Option
PMC Device Number
Part Number
tACC (ns)
Pm37LV512-70JC
Pm37LV512-70PC
Pm37LV512-70VC
Programmable Microelectronics Corp.
70
P ackag e
Temperature Range
32J
Commercial
(0°C to + 70°C)
32P
Commercial
(0°C to + 70°C)
32V
Commercial
(0°C to + 70°C)
3
Issue Date: Dec, 2002 Rev: 1.3
Pm37LV512
PMC
PIN DESCRIPTIONS
SYMBOL
TYPE
DESCRIPTION
A 0 - A 15
INPUT
Address Inputs: For memory addresses input. Addresses are internally
latched on the falling edge of WE# during a write cycle.
C E#
INPUT
Chip Enable: CE# goes low activates the device's internal circuitries for
device operation. CE# goes high deselects the device and switches into
standby mode to reduce the power consumption.
WE#
INPUT
Write Enable: Activate the device for write operation. WE# is active low.
OE#
INPUT
Output Enable: Control the device's output buffers during a read cycle. OE#
is active low.
INPUT/
OUTPUT
Data Inputs/Outputs: Input command/data during a write cycle or output data
during a read cycle. The I/O pins float to tri-state when OE# are disabled.
I/O0 - I/O7
V CC
Device Power Supply
GND
Ground
NC
No Connection
Programmable Microelectronics Corp.
4
Issue Date: Dec, 2002 Rev: 1.3
Pm37LV512
PMC
BLOCK DIAGRAM
I/O0-I/O7
I/O BUFFERS
WE#
COMMAND
REGISTER
CE,OE LOGIC
DATA
LATCH
SENSE
AMP
A0-A15
ADDRESS
LATCH
CE#
OE#
Y-DECODER
X-DECODER
Y-GATING
MEMORY
ARRAY
DEVICE OPERATION
READ OPERATION
CHIP ERASE
The access of Pm37LV512 is similar as that of EPROM
or Flash Memory. To obtain data at the outputs, three
control functions must be satisfied:
• CE# is the chip enable and should be pulled low
( VIL ).
• OE# is the output enable and should be pulled
low ( VIL).
• WE# is the write enable and should remains high
( VIH ).
The entire memory array can be erased through a chip
erase operation on an external EPROM programmer.
Pre-program the “1”s cells in the device is not required
prior to chip erase operation. The chip erase operation
is activated by applying 12.0 Volt to OE# and A9 pins
while CE# pin is low. All other address and data pins
are “don’t care”. Chip erase is completed by asserting
WE# pin to low for 100 ms. The falling edge of WE# will
start the chip erase operation. The device will return back
to standby mode after the completion of chip erase. Refer
to Chart 2. Chip Erase Flowchart and Chip Erase
Operations AC Waveforms.
BYTE PROGRAMMING
The Pm37LV512 is programmed by using an external
EPROM programmer. The programming mode is activated by applying 12.0 Volt on OE# pin and VIL on CE#
pin. The byte program operation is completed by asserting WE# to low for 20 µs. A chip erase operation is
required prior to program due to a data “0” can not be
programmed back to a “1” and only erase operation can
convert “0”s to “1”s. The entire chip can be programmed
byte-by-byte by using the byte program algorithmm. Refer to Chart 1. Byte Programming Flowchart and Byte
Program Operations AC Waveforms.
Programmable Microelectronics Corp.
PRODUCT IDENTIFICATION
The hardware product identification mode can be used
by an EPROM programmer to identify the device and
manufacturer for selecting the right programming algorithm for the device. The product identification mode is
activated by applying 12.0 Volt on A9 pin. For details,
please see Bus Operation Modes in Table 1.
5
Issue Date: Dec, 2002 Rev: 1.3
Pm37LV512
PMC
OPERATING MODES
Table 1. Bus Operation Modes
Mode
C E#
OE#
WE#
A9
ADDRESS
I/O
Read
VIL
VIL
VIH
AIN
AIN
DOUT
Chip-Erase
VIL
V H(1)
V IL
VH
X
Byte-Program
VIL
VH
VIL
AIN
AIN
DIN
X
X
VIH
X
X
High Z
X
VIL or VIH
X
X
X
High Z/ DOUT
Program/Erase Inhibit
(2)
High Z
Standby
VIH
X
X
X
X
High Z
Output Disable
X
VIH
X
X
X
High Z
Product Identification
Hardware
VIL
VIL
VIH
VH
A 2 - A 15 = X ,
A1 = VIL, A0 = VIL
Manufacturer Code
A 2 - A 15 = X ,
A1 = VIL, A0 = VIH
Device Code
(3)
(3)
Notes:
1. VH = 12.0 V ± 0.5 V.
2. X can be VIL, VIH or addresses.
3. Manufacturer Code: 9Dh;
Device Code: 9Bh
Programmable Microelectronics Corp.
6
Issue Date: Dec, 2002 Rev: 1.3
Pm37LV512
PMC
DEVICE OPERATIONS FLOWCHARTS
BYTE PROGRAMMING
Start
OE# = V H
Address = First
Location; Load Data
CE# = V IL
Program 20 µs
pulse (WE# = V IL )
OE# = V IL
Increment Address
Last Address?
Yes
No
Wait T R T
Recovery Time
Read Device
No
Compare all bytes to
original data
Yes
Failed
Pass
Chart 1. Byte Programming Flowchart
Programmable Microelectronics Corp.
7
Issue Date: Dec, 2002 Rev: 1.3
Pm37LV512
PMC
DEVICE OPERATIONS FLOWCHARTS (CONTINUED)
CHIP ERASE
Start
A 9 = V H ; OE# = V H
CE# = V IL
Erase 100 ms pulse
( W E # = V IL )
W E # = V IH
O E # / A9 = V IL or V IH
Wait T R T
Recovery Time
Read Device
No
Compare all bytes to FF
Yes
Fail
Pass
Chart 2. Chip Erase Flowchart
Programmable Microelectronics Corp.
8
Issue Date: Dec, 2002 Rev: 1.3
Pm37LV512
PMC
ABSOLUTE MAXIMUM RATINGS (1)
Temperature Under Bias
-65°C to +125°C
Storage Temperature
-65°C to +125°C
Surface Mount Lead Soldering Temperature
240°C 3 Seconds
Input Voltage with Respect to Ground on All Pins except OE# and A9 pin (2)
-0.5 V to VCC + 0.5 V
Input Voltage with Respect to Ground on OE# and A9 pin (3)
-0.5 V to +13.0 V
All Output Voltage with Respect to Ground
-0.5 V to VCC + 0.5 V
VCC (2)
-0.5 V to +6.0 V
Notes:
1. Stresses under those listed in “Absolute Maximum Ratings” may cause permanent
damage to the device. This is a stress rating only. The functional operation of the device
or any other conditions under those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating condition for extended periods
may affected device reliability.
2. Maximum DC voltage on input or I/O pins are VCC + 0.5 V. During voltage transitioning
period, input or I/O pins may overshoot to VCC + 2.0 V for a period of time up to 20 ns.
Minimum DC voltage on input or I/O pins are -0.5 V. During voltage transitioning period,
input or I/O pins may undershoot GND to -2.0 V for a period of time up to 20 ns.
3. Maximum DC voltage on OE# and A9 pin is +13.0 V. During voltage transitioning period,
OE# and A9 pin may overshoot to +14.0 V for a period of time up to 20 ns. Minimum DC
voltage on OE# and A9 pin is -0.5 V. During voltage transitioning period, OE# and A9 pin
may undershoot GND to -2.0 V for a period of time up to 20 ns.
DC AND AC OPERATING RANGE
Part Number
Pm37LV512
Operating Temperature
0°C to 70°C
Program/Erase
Read
V CC
2.7 V - 3.6 V
V PP
11.5 V - 12.5 V
V CC
2.7 V - 3.6 V or 4.5 V - 5.5 V
Programmable Microelectronics Corp.
9
Issue Date: Dec, 2002 Rev: 1.3
Pm37LV512
PMC
DC CHARACTERISTICS
Symbol
Parameter
Condition
Min
Typ
Max
Units
ILI
Input Load Current
VIN = 0 V to VCC
1
µA
ILO
Output Leakage Current
VI/O = 0 V to VCC
1
µA
ISB1
VCC Standby Current CMOS
CE#, OE# = VCC ± 0.3 V
18
100
µA
ISB2
VCC Standby Current TTL
CE# = VIH to VCC
0.01
3
mA
ICC1
VCC Active Read Current
5
15
mA
VIL
Input Low Voltage
-0.5
0.8
V
VIH
Input High Voltage
0.7 VCC
VCC + 0.3
V
VOL
Output Low Voltage
IOL = 2.1 mA; VCC = VCC
min
0.45
V
VOH
Output High Voltage
IOH = -100 µA; VCC = VCC
min
f = 5 MHz; IOUT = 0 mA
VCC - 0.2
V
AC CHARACTERISTICS
READ OPERATIONS CHARACTERISTICS
Pm37LV512-70
Symbol
Parameter
Units
Min
Max
tRC
Read Cycle Time
tACC
Address to Output Delay
70
ns
tCE
CE# to Output Delay
70
ns
tOE
OE# to Output Delay
35
ns
tDF
CE# or OE# to Output High Z
0
20
ns
tOH
Output Hold from OE#, CE# or Address,
whichever occured first
0
ns
tVCS
VCC Set-up Time
50
µs
Programmable Microelectronics Corp.
70
10
ns
Issue Date: Dec, 2002 Rev: 1.3
Pm37LV512
PMC
AC CHARACTERISTICS (CONTINUED)
READ OPERATIONS AC WAVEFORMS
t RC
ADDRESS
ADDRESS VALID
t ACC
t CE
CE#
t OE
OE#
t DF
WE#
tO H
HIGH Z
OUTPUT
OUTPUT
VALID
t VCS
VCC
OUTPUT TEST LOAD
INPUT TEST WAVEFORMS
AND MEASUREMENT LEVEL
3.3 V
1.8 K
3.0 V
OUTPUT PIN
Input
1.5 V
AC
Measurement
Level
0.0 V
1.3 K
100 pF
PIN CAPACITANCE ( f = 1 MHz, T = 25°C )
Typ
Max
Units
Conditions
CIN
4
6
pF
VIN = 0 V
COUT
8
12
pF
VOUT = 0 V
Note: These parameters are characterized but not 100% tested.
Programmable Microelectronics Corp.
11
Issue Date: Dec, 2002 Rev: 1.3
Pm37LV512
PMC
AC CHARACTERISTICS (CONTINUED)
WRITE (PROGRAM/ERASE) OPERATIONS CHARACTERISTICS
Pm37LV512-70
Symbol
Parameter
Units
Min
Max
tAS
Address Set-up Time
0
ns
tAH
Address Hold Time
30
ns
tCES
CE# Set-up Time
0
ns
tCEH
CE# Hold Time
0
ns
tDS
Data Set-up Time
40
ns
tDH
Data Hold Time
0
ns
tORT
OE# Rise Time for Program and Erase
1
ns
tOES
OE# SetupTime for Program and Erase
1
ns
tOEH
OE# Hold Time for Program and Erase
1
ns
tPW
WE# Program Pulse Width
20
µs
tEW
WE# Erase Pulse Width
100
ms
tRT
OE#/A9 Recovery Time for Erase
1
ns
tART
A9 Rise Time to 12V during Erase
1
ns
tA9S
A9 Setup Time during Erase
1
ms
tA9H
A9 Hold Time during Erase
1
ms
Programmable Microelectronics Corp.
12
Issue Date: Dec, 2002 Rev: 1.3
Pm37LV512
PMC
AC CHARACTERISTICS (CONTINUED)
BYTE PROGRAM OPERATIONS AC WAVEFORMS
ADDRESS VALID
ADDRESS
DATA IN
DATA VALID
HIGH-Z
tA S
//
//
//
//
//
tD S
VH
tO E S
tA H
tD H
V CC
OE#
V SS
tO E H
tO R T
tP W
//
WE#
tC E S
tC E H
CE#
//
CHIP ERASE OPERATIONS AC WAVEFORMS
ADDRESS
(Except A9)
DATA IN
VH
OE#
V CC
V SS
tO E S
tO E H
tO R T
tR T
VH
A9
V CC
V SS
tA 9 S
tA R T
tA 9 H
WE#
tC E S
tC E H
tE W
CE#
Programmable Microelectronics Corp.
13
Issue Date: Dec, 2002 Rev: 1.3
Pm37LV512
PMC
AC CHARACTERISTICS (CONTINUED)
RELIABILITY CHARACTERISTICS
Parameter
Endurance
Data Retention
ESD - Human Body Model
ESD - Machine Model
Latch-Up
Min
Unit
Test Method
1,000
Cycles
JEDEC Standard A117
20
Years
JEDEC Standard A103
2,000
Volts
JEDEC Standard A114
200
Volts
JEDEC Standard A115
100 + ICC1
mA
JEDEC Standard 78
Note: These parameters are characterized but not 100% tested.
Programmable Microelectronics Corp.
14
Issue Date: Dec, 2002 Rev: 1.3
Pm37LV512
PMC
PACKAGE TYPE INFORMATION
32J
32-Pin Plastic Leaded Chip Carrier Dimensions in Inches (Millimeters)
.485(12.32)
.495(12.51)
.447(11.35)
.453(11.51)
.009
.015
025(.635)X30°
.585(14.86)
.595(15.11)
.123(3.12)
.140(3.56)
.076(1.93)
.095(2.41)
Pin 1 I.D.
.547(13.89)
.553(14.05)
SEATING
PLANE
.400
REF.
.510(12.95)
.530(13.46)
.013(.33)
.021(.53)
.050 REF.
.026(.66)
.032(.81)
32P
32-Pin Plastic DIP Dimensions in Inches (Millimeters)
1.640(41.7)
1.680(42.7)
32
.600(15.24)
.625(15.88)
17
.008(0.20)
.013(0.33)
.537(13.64)
.557(14.05)
.625(15.88)
.665(16.89)
Pin 1 I.D.
0°
10°
16
.005(.127)
MIN
.040(1.02)
.065(1.65)
.146(3.71)
.162(4.11)
SEATING PLANE
.120(3.05)
.160(4.07)
.090(2.29)
.110(2.79)
Programmable Microelectronics Corp.
.014(.36)
.022(.56)
.015(.38) MIN
15
Issue Date: Dec, 2002 Rev: 1.3
Pm37LV512
PMC
PACKAGE TYPE INFORMATION (CONTINUED)
32V
32-Pin Thin Small Outline Package (TSOP 8mm x 14mm)(Millimeters)
.037(.95)
.041(1.05
Pin 1 I.D.
.006(.16)
.011(,27)
.315(7.90)
.319(8.10)
.020(0.05)
BSC
.020(.05)
.006(.15)
.484(12.30)
.492(12.50)
.543(13.80)
.560(14.20)
.047(1.20)
MAX
.010(.25)
Programmable Microelectronics Corp.
.004(.10)
.008(.20)
0°
5°
.020(.50)
.028(.70)
16
Issue Date: Dec, 2002 Rev: 1.3
Pm37LV512
PMC
REVISION HISTORY
Date
March, 2002
Revision No. Description of Changes
1.0
New publication
All
Revised features and general description
May, 2002
1.1
D e c. 2 0 0 2
1
Removed 90 ns speed grade
3, 10, 12
Revised bus operation modes
6
Revised absolute maximum ratings
9
Revised ISB1 specification
10
Revised program/erase operation
characteristics and waveforms
June, 2002
P ag e N o .
12, 13
Corrected the typo in 32-Pin PDIP pin
connection
2
Corrected the typo of TRT recovery time in Byte
Programming Flowchart
7
1.2
1.3
Programmable Microelectronics Corp.
Added 32-Pin VSOP package spec.
1, 2, 3, 16
17
Issue Date: Dec, 2002 Rev: 1.3