512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit (x8) Many-Time Programmable Flash SST37VF512 / SST37VF010 / SST37VF020 / SST37VF040 Data Sheet FEATURES: • Organized as 64K x8 / 128K x8 / 256K x8 / 512K x8 • 2.7-3.6V Read Operation • Superior Reliability – Endurance: At least 1000 Cycles – Greater than 100 years Data Retention • Low Power Consumption – Active Current: 10 mA (typical) – Standby Current: 1 µA (typical) • Fast Read Access Time – 70 and 90 ns • Fast Byte-Program Operation – Byte-Program Time: 10 µs (typical) – Chip-Program Time: 0.6 seconds (typical) for SST37VF512 1.2 seconds (typical) for SST37VF010 2.4 seconds (typical) for SST37VF020 4.8 seconds (typical) for SST37VF040 • Electrical Erase Using Programmer – Does not require UV source – Chip-Erase Time: 100 ms (typical) • CMOS I/O Compatibility • JEDEC Standard Byte-wide Flash EEPROM Pinouts • Packages Available – 32-Pin PDIP – 32-Pin PLCC – 32-Pin TSOP (8mm x 14mm) PRODUCT DESCRIPTION The SST37VF512/010/020/040 devices are 64K x8 / 128K x8 / 256K x8 / 512K x8 CMOS, Many-Time Programmable (MTP), low cost flash, manufactured with SST’s proprietary, high performance CMOS SuperFlash technology. The split-gate cell design and thick oxide tunneling injector attain better reliability and manufacturability compared with alternate approaches. The SST37VF512/010/020/040 can be electrically erased and programmed at least 1000 times using an external programmer, e.g., to change the contents of devices in inventory. The SST37VF512/010/020/040 have to be erased prior to programming. These devices conform to JEDEC standard pinouts for byte-wide flash memories. Featuring high performance Byte-Program, the SST37VF512/010/020/040 provide a typical Byte-Program time of 10 µs. Designed, manufactured, and tested for a wide spectrum of applications, these devices are offered with an endurance of at least 1000 cycles. Data retention is rated at greater than 100 years. The SST37VF512/010/020/040 are suited for applications that require infrequent writes and low power nonvolatile storage. These devices will improve flexibility, efficiency, and performance while matching the low cost in nonvolatile applications that currently use UV-EPROMs, OTPs, and mask ROMs. To meet surface mount and conventional through hole requirements, the SST37VF512/010/020/040 are offered in 32-pin PLCC, PDIP and TSOP packages. See Figures 1, 2 and 3 for pinouts. Device Operation The SST37VF512/010/020/040 devices are nonvolatile memory solutions that can be used instead of standard flash devices if in-system programmability is not required. It is functionally (Read) and pin compatible with industry standard flash products.The device supports electrical Erase operation via an external programmer. Read The Read operation of the SST37VF512/010/020/040 is controlled by CE# and OE#. Both CE# and OE# have to be low for the system to obtain data from the outputs. Once the address is stable, the address access time is equal to the delay from CE# to output (TCE). Data is available at the output after a delay of TOE from the falling edge of OE#, assuming the CE# pin has been low and the addresses have been stable for at least TCE - TOE. When the CE# pin is high, the chip is deselected and a standby current of only 10 µA (typical) is consumed. OE# is the output control and is used to gate data from the output pins. The data bus is in high impedance state when either CE# or OE# is VIH. Refer to Figure 4 for the timing diagram. Byte-Program Operation The SST37VF512/010/020/040 are programmed by using an external programmer. The programming mode is activated by asserting 12V (±5%) on OE# pin and VIL on CE# pin. The device is programmed using a single pulse (WE# pin low) of 10 µs per byte. Using the MTP programming algorithm, the Byte-Program process continues byte-by-byte until the entire chip has been programmed. Refer to Figure 10 for the flowchart and Figure 6 for the timing diagram. © 2000 Silicon Storage Technology, Inc.The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc. MTP is a trademark of Silicon Storage Technology, Inc. 1 397-03 2/00 These specifications are subject to change without notice. Powered by ICminer.com Electronic-Library Service CopyRight 2003 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Many-Time Programmable Flash SST37VF512 / SST37VF010 / SST37VF020 / SST37VF040 Data Sheet Chip-Erase Operation The only way to change a data from a “0” to “1” is by electrical erase that changes every bit in the device to “1”. The SST37VF512/010/020/040 use an electrical ChipErase operation. The entire chip can be erased in 100 ms (WE# pin low). In order to activate erase mode, the 12V (±5%) is applied to OE# and A9 pins while CE# is low. All other address and data pins are “don’t care”. The falling edge of WE# will start the Chip-Erase operation. Once the chip has been erased, all bytes must be verified for FF. Refer to Figure 9 for the flowchart and Figure 5 for the timing diagram. TABLE 1: PRODUCT IDENTIFICATION TABLE Byte Manufacturer’s Code 0000 H Device Code SST37VF512 0001 H SST37VF010 0001 H SST37VF020 0001 H SST37VF040 0001 H Data BF H C4 H C5 H C6 H C2 H 397 PGM T1.1 Design Considerations The SST37VF512/010/020/040 should have a 0.1µF ceramic high frequency, low inductance capacitor connected between VDD and GND. This capacitor should be placed as close to the package terminals as possible. Product Identification Mode The Product Identification mode identifies the devices as SST37VF512, SST37VF010, SST37VF020, and SST37VF040 and manufacturer as SST. This mode may be accessed by the hardware method. To activate this mode, the programming equipment must force VH (12V±5%) on address A9. Two identifier bytes may then be sequenced from the device outputs by toggling address line A0. For details, see Table 3 for hardware operation. OE# and A9 must remain stable at VH for the entire duration of an Erase operation. OE# must remain stable at VH for the entire duration of the Program operation. FUNCTIONAL BLOCK DIAGRAM X-Decoder Memory Address EEPROM Cell Array Address Buffer Y-Decoder CE# OE# A9 WE# I/O Buffers Control Logic DQ7 - DQ0 397 ILL B1.0 © 2000 Silicon Storage Technology, Inc. Powered by ICminer.com Electronic-Library Service CopyRight 2003 2 397-03 2/00 512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Many-Time Programmable Flash SST37VF512 / SST37VF010 / SST37VF020 / SST37VF040 Data Sheet SST37VF040 SST37VF020 SST37VF010 SST37VF512 A11 A9 A8 A13 A14 A17 WE# VDD A18 A16 A15 A12 A7 A6 A5 A4 A11 A9 A8 A13 A14 A17 WE# VDD NC A16 A15 A12 A7 A6 A5 A4 A11 A9 A8 A13 A14 NC WE# VDD NC A16 A15 A12 A7 A6 A5 A4 A11 A9 A8 A13 A14 NC WE# VDD NC NC A15 A12 A7 A6 A5 A4 SST37VF512 SST37VF010 SST37VF020 SST37VF040 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 Standard Pinout Top View OE# A10 CE# DQ7 DQ6 DQ5 DQ4 DQ3 VSS DQ2 DQ1 DQ0 A0 A1 A2 A3 OE# A10 CE# DQ7 DQ6 DQ5 DQ4 DQ3 VSS DQ2 DQ1 DQ0 A0 A1 A2 A3 OE# A10 CE# DQ7 DQ6 DQ5 DQ4 DQ3 VSS DQ2 DQ1 DQ0 A0 A1 A2 A3 OE# A10 CE# DQ7 DQ6 DQ5 DQ4 DQ3 VSS DQ2 DQ1 DQ0 A0 A1 A2 A3 397 ILL F01.0 1 2 3 4 5 FIGURE 1: PIN ASSIGNMENTS FOR 32-PIN TSOP 6 SST37VF512 SST37VF010 SST37VF020 SST37VF040 SST37VF040 SST37VF020 SST37VF010 SST37VF512 A18 A16 A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 VSS NC A16 A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 VSS NC A16 A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 VSS NC NC A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 VSS 1 2 3 4 5 32-Pin 6 PDIP 7 8 Top View 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VDD WE# NC A14 A13 A8 A9 A11 OE# A10 CE# DQ7 DQ6 DQ5 DQ4 DQ3 VDD WE# NC A14 A13 A8 A9 A11 OE# A10 CE# DQ7 DQ6 DQ5 DQ4 DQ3 VDD WE# A17 A14 A13 A8 A9 A11 OE# A10 CE# DQ7 DQ6 DQ5 DQ4 DQ3 7 VDD WE# A17 A14 A13 A8 A9 A11 OE# A10 CE# DQ7 DQ6 DQ5 DQ4 DQ3 8 9 10 11 397 ILL F02b.0 12 FIGURE 2: PIN ASSIGNMENTS FOR 32-PIN PDIP 13 14 15 16 © 2000 Silicon Storage Technology, Inc. Powered by ICminer.com Electronic-Library Service CopyRight 2003 3 397-03 2/00 512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Many-Time Programmable Flash SST37VF512 / SST37VF010 / SST37VF020 / SST37VF040 A17 NC NC A17 WE# WE# WE# WE# VDD A18 VDD VDD VDD NC NC NC A16 A16 NC A16 A12 A15 A15 A15 A15 A12 A12 A12 SST37VF040 SST37VF020 SST37VF010 SST37VF512 SST37VF512 SST37VF010 SST37VF020 SST37VF040 Data Sheet 4 3 2 1 32 31 30 29 SST37VF512 SST37VF010 SST37VF020 SST37VF040 A7 A7 A7 5 A14 A14 A14 A14 A6 A6 A6 A6 6 28 A13 A13 A13 A13 A5 A5 A5 A5 7 27 A8 A8 A8 A8 A4 A4 A4 A4 8 26 A9 A9 A9 A9 A3 A3 A3 A3 9 25 A11 A11 A11 A11 A2 A2 A2 A2 10 24 OE# OE# OE# OE# A1 A1 A1 A1 11 23 A10 A10 A10 A10 A0 A0 A0 A0 12 22 CE# CE# CE# CE# DQ0 DQ0 DQ0 DQ0 13 21 14 15 16 17 18 19 20 DQ7 DQ7 DQ7 DQ7 DQ1 DQ2 VSS DQ3 DQ4 DQ5 DQ6 DQ1 DQ2 VSS DQ3 DQ4 DQ5 DQ6 DQ1 DQ2 VSS DQ3 DQ4 DQ5 DQ6 DQ2 VSS DQ3 DQ4 DQ5 DQ6 32-Pin PLCC Top View DQ1 SST37VF040 SST37VF020 SST37VF010 SST37VF512 A7 397 ILL F02a.1 FIGURE 3: PIN ASSIGNMENTS FOR 32-PIN PLCC TABLE 2: PIN DESCRIPTION Symbol Pin Name Address Inputs AMS-A0 DQ7-DQ0 Data Input/Output CE# WE# OE# VDD VSS NC Note: Chip Enable Write Enable Output Enable Power Supply Ground No Connection Functions To provide memory addresses To output data during Read cycles and receive input data during Program cycle, the outputs are in tri-state when OE# or CE# is high. To activate the device when CE# is low To program or erase (WE# = VIL pulse during Program or Erase) To gate the data output buffers during Read operation when low To provide 3-volt supply (2.7 to 3.6V) Unconnected pins AMS = Most significant address AMS = A15 for SST37VF512, A16 for SST37VF010, A17 for SST37VF020 and A18 for SST37VF040. © 2000 Silicon Storage Technology, Inc. Powered by ICminer.com Electronic-Library Service CopyRight 2003 4 397 PGM T2.0 397-03 2/00 512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Many-Time Programmable Flash SST37VF512 / SST37VF010 / SST37VF020 / SST37VF040 Data Sheet TABLE 3: OPERATION MODES SELECTION Mode CE# WE# A9 Read VIL VIH AIN Output Disable VIL X X Standby VIH X X VIL VH Chip-Erase VIL Byte-Program VIL VIL AIN Program/Erase X VIH X Inhibit X X X Product VIL VIH VH Identification OE# VIL VIH X VH VH X VIL or VIH VIL DQ DOUT High Z High Z High Z DIN High Z High Z/DOUT Manufacturer Code (BF) Device Code (1) Address AIN AIN X X AIN X X AMS(2)-A1 = VIL, A0 = VIL AMS(2)-A1 = VIL, A0 = VIH 1 2 3 4 397 PGM T3.0 Note: X = VIL or VIH (or VH in case of OE# and A9) VH = 12V±5% (1) Device code C4 for SST37VF512, C5 for SST37VF010, C6 for SST37VF020 and C2 for SST37VF040. (2) AMS = Most significant address AMS = A15 for SST37VF512, A16 for SST37VF010, A17 for SST37VF020 and A18 for SST37VF040. 5 6 Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “Absolute Maximum Stress Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these conditions or conditions greater than those defined in the operational sections of this data sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.) Temperature Under Bias ................................................................................................................. -55°C to +125°C Storage Temperature ...................................................................................................................... -65°C to +150°C D. C. Voltage on Any Pin to Ground Potential ............................................................................. -0.5V to VDD+ 0.5V Transient Voltage (<20 ns) on Any Pin to Ground Potential ......................................................... -1.0V to VDD+ 1.0V Voltage on A9 and OE# Pin to Ground Potential ................................................................................. -0.5V to 13.2V Package Power Dissipation Capability (TA = 25°C) ........................................................................................... 1.0W Through Hole Lead Soldering Temperature (10 Seconds) .............................................................................. 300°C Surface Mount Lead Soldering Temperature (3 Seconds) ............................................................................... 240°C Output Short Circuit Current(1) ................................................................................................................................................................. 50 mA Note: (1) Outputs shorted for no more than one second. No more than one output shorted at a time. 7 8 9 10 11 12 13 OPERATING RANGE Range Ambient Temp Commercial 0°C to +70°C Industrial -40°C to +85°C AC CONDITIONS OF TEST VDD 2.7 to 3.6V 2.7 to 3.6V 14 Input Rise/Fall Time ......... 5 ns Output Load ..................... CL = 100 pF 15 See Figures 7 and 8 16 © 2000 Silicon Storage Technology, Inc. Powered by ICminer.com Electronic-Library Service CopyRight 2003 5 397-03 2/00 512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Many-Time Programmable Flash SST37VF512 / SST37VF010 / SST37VF020 / SST37VF040 Data Sheet TABLE 4: READ MODE DC OPERATING CHARACTERISTICS VDD = 2.7 to 3.6V, TA = 0°C to 70°C (Commercial) Limits Symbol Parameter Min Max IDD VDD Read Current 12 ISB Standby VDD Current 15 µA ILI ILO VIL VIH VIHC Input Leakage Current Output Leakage Current Input Low Voltage Input High Voltage 0.7 VDD Input High Voltage VDD-0.3 (CMOS) Output Low Voltage Output High Voltage VDD-0.2 Supervoltage Current for A9 for Read-ID 1 1 0.8 µA µA V V V Test Conditions CE# = OE# = VIL, all I/Os open, Address Input = VIL/VIH, at f = 1/TRC Min, VDD = VDD Max CE# = VIHC VDD = VDD Max VIN = GND to VDD, VDD = VDD Max VOUT = GND to VDD, VDD = VDD Max VDD = VDD Min VDD = VDD Max VDD = VDD Max 0.2 V V µA IOL = 100µA, VDD = VDD Min IOH = -100 µA, VDD = VDD Min CE# = OE# = VIL, A9 = VH Max. VOL VOH IH Units mA 200 397 PGM T4.1 © 2000 Silicon Storage Technology, Inc. Powered by ICminer.com Electronic-Library Service CopyRight 2003 6 397-03 2/00 512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Many-Time Programmable Flash SST37VF512 / SST37VF010 / SST37VF020 / SST37VF040 Data Sheet TABLE 5: PROGRAM/ERASE DC OPERATING CHARACTERISTICS VDD = 2.7 to 3.6V, TA = 25°C ± 5°C Limits Symbol Parameter Min Max Units VDD Erase or Program 30 mA IDD Current ILI Input Leakage Current 1 µA ILO Output Leakage Current 1 µA Supervoltage for A9 11.4 12.6 V VH and OE# IH Supervoltage Current 200 µA for A9 and OE# 1 Test Conditions CE# = VIL, OE# = VH, VDD = VDD Max, WE# = VIL VIN = GND to VDD, VDD = VDD Max VOUT = GND to VDD, VDD = VDD Max 2 OE# = VH Max, A9 = VH Max, VDD = VDD Max, CE# = VIL 4 3 397 PGM T5.0 5 6 TABLE 6: RECOMMENDED SYSTEM POWER-UP TIMINGS Symbol Parameter TPU-READ Power-up to Read Operation TPU-WRITE Power-up to Write Operation Minimum 100 100 Units µs µs 7 397 PGM T6.0 TABLE 7: CAPACITANCE (TA = 25 °C, f=1 MHz, other pins open) Parameter Description Test Condition (1) CI/O I/O Pin Capacitance VI/O = 0V CIN(1) Input Capacitance VIN = 0V 8 9 Maximum 12 pF 6 pF 10 397 PGM T7.0 Note: (1)This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. 11 TABLE 8: RELIABILITY CHARACTERISTICS Symbol Parameter NEND Endurance TDR(1) Data Retention (1) VZAP_HBM ESD Susceptibility Human Body Model (1) VZAP_MM ESD Susceptibility Machine Model (1) ILTH Latch Up Minimum Specification 1000 100 2000 Units Cycles Years Volts Test Method JEDEC Standard A117 JEDEC Standard A103 JEDEC Standard A114 200 Volts JEDEC Standard A115 100 + IDD mA (1) 13 14 JEDEC Standard 78 397 PGM T8.1 Note: 12 This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. 15 16 © 2000 Silicon Storage Technology, Inc. Powered by ICminer.com Electronic-Library Service CopyRight 2003 7 397-03 2/00 512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Many-Time Programmable Flash SST37VF512 / SST37VF010 / SST37VF020 / SST37VF040 Data Sheet AC CHARACTERISTICS TABLE 9: READ CYCLE TIMING PARAMETERS VDD = 2.7 to 3.6V, TA = 0°C to 70°C (Commercial) SST37VF512-70 SST37VF010-70 SST37VF020-70 SST37VF040-70 Symbol Parameter Min Max Read Cycle Time 70 TRC TCE Chip Enable Access Time 70 TAA Address Access Time 70 Output Enable Access Time 35 TOE TCLZ CE# Low to Active Output 0 OE# Low to Active Output 0 TOLZ TCHZ CE# High to High-Z Output 30 TOHZ OE# High to High-Z Output 30 TOH Output Hold from Address 0 Change SST37VF512-90 SST37VF010-90 SST37VF020-90 SST37VF040-90 Min Max 90 90 90 45 0 0 30 30 0 Units ns ns ns ns ns ns ns ns ns 397 PGM T9.1 TABLE 10: PROGRAM/ERASE CYCLE TIMING PARAMETERS VDD = 2.7 to 3.6V, TA = 25°C ± 5°C Symbol Parameter TPC Program Cycle Time TCES CE# Setup Time TCEH CE# Hold Time TAS Address Setup Time TAH Address Hold Time TDS Data Setup Time TDH Data Hold Time TPRT OE# Rise Time for Program and Erase TVPS OE# Setup Time for Program and Erase TVPH OE# Hold Time for Program and Erase TPW WE# Program Pulse Width TEW WE# Erase Pulse Width TVR OE#/A9 Recovery Time for Erase TART A9 Rise Time to 12V during Erase TA9S A9 Setup Time during Erase TA9H A9 Hold Time during Erase Min 12 1 1 1 1 1 1 1 1 1 10 100 1 1 1 1 Max 15 500 Units µs µs µs µs µs µs µs µs µs µs µs ms µs µs µs µs 397 PGM T10.0 © 2000 Silicon Storage Technology, Inc. Powered by ICminer.com Electronic-Library Service CopyRight 2003 8 397-03 2/00 512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Many-Time Programmable Flash SST37VF512 / SST37VF010 / SST37VF020 / SST37VF040 Data Sheet 1 TAA TRC ADDRESS 2 TCE CE# 3 TOE OE# 4 TOHZ TOLZ VIH WE# DQ7-0 5 TCHZ TOH TCLZ HIGH-Z HIGH-Z DATA VALID DATA VALID 6 397 ILL F03.0 FIGURE 4: READ CYCLE TIMING DIAGRAM 7 8 9 ADDRESS (EXCEPT A9) CE# 10 TCEH 11 DQ7-0 VH OE# 12 TVPS VDD VSS TVPH TPRT VH 13 TVR TA9S A9 VIH VIL 14 TART TA9H 15 TEW WE# TCES 397 ILL F04.0 16 FIGURE 5: CHIP-ERASE TIMING DIAGRAM © 2000 Silicon Storage Technology, Inc. Powered by ICminer.com Electronic-Library Service CopyRight 2003 9 397-03 2/00 512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Many-Time Programmable Flash SST37VF512 / SST37VF010 / SST37VF020 / SST37VF040 Data Sheet TPC ADDRESS ADDRESS VALID TAH TAS CE# TCEH TDS TDH DQ7-0 DATA VALID HIGH-Z VH TVPS TPRT VDD OE# TPW VSS TVPH WE# TCES 397 ILL F05.0 FIGURE 6: BYTE-PROGRAM TIMING DIAGRAM VIHT INPUT VIT REFERENCE POINTS VOT OUTPUT VILT 397 ILL F06.1 « AC test inputs are driven at VIHT (0.9 VDD) for a logic “1” and VILT (0.1 VDD) for a logic “0”. Measurement reference points for inputs and outputs are VIT (0.5 VDD) and VOT (0.5 VDD). Inputs rise and fall times (10% 90%) are <5 ns. Note: VIT–VINPUT Test VOT–VOUTPUT Test VIHT–VINPUT HIGH Test VILT–VINPUT LOW Test FIGURE 7: AC INPUT/OUTPUT REFERENCE WAVEFORMS © 2000 Silicon Storage Technology, Inc. Powered by ICminer.com Electronic-Library Service CopyRight 2003 10 397-03 2/00 512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Many-Time Programmable Flash SST37VF512 / SST37VF010 / SST37VF020 / SST37VF040 Data Sheet 1 TO TESTER 2 TO DUT CL 3 397 ILL F07.1 4 FIGURE 8: A TEST LOAD EXAMPLE 5 6 7 8 9 10 11 12 13 14 15 16 © 2000 Silicon Storage Technology, Inc. Powered by ICminer.com Electronic-Library Service CopyRight 2003 11 397-03 2/00 512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Many-Time Programmable Flash SST37VF512 / SST37VF010 / SST37VF020 / SST37VF040 Data Sheet Start A9 = VH, OE# = VH CE# = VIL Erase 100ms pulse (WE# = VIL) WE# = VIH OE#/A9 = VIL or VIH Wait TVR Recovery Time Read Device No Compare all bytes to FF Yes Device Passed Device Failed 397 ILL F08.0 FIGURE 9: CHIP-ERASE ALGORITHM © 2000 Silicon Storage Technology, Inc. Powered by ICminer.com Electronic-Library Service CopyRight 2003 12 397-03 2/00 512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Many-Time Programmable Flash SST37VF512 / SST37VF010 / SST37VF020 / SST37VF040 Data Sheet Start 1 Erase See Figure 8 2 OE# = VH 3 Address = First Location; Load Data 4 CE# = VIL 5 Program 10µs pulse (WE# = VIL) Increment Address 6 Last Address? No 7 OE# = VIL Yes 8 Wait TVR 9 Read Device 10 Compare all bytes to original data No 11 Yes 12 Device Passed Device Failed 13 397 ILL F09.0 FIGURE 10: BYTE-PROGRAM ALGORITHM 14 15 16 © 2000 Silicon Storage Technology, Inc. Powered by ICminer.com Electronic-Library Service CopyRight 2003 13 397-03 2/00 512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Many-Time Programmable Flash SST37VF512 / SST37VF010 / SST37VF020 / SST37VF040 Data Sheet PRODUCT ORDERING INFORMATION Device SST37VFxxx Speed - XXX Suffix1 - XX Suffix2 - XX Package Modifier H = 32 pins Numeric = Die modifier Package Type P = PDIP N = PLCC W = TSOP 8mm x14mm Operating Temperature C = Commercial = 0° to 70°C I = Industrial = -40° to 85°C Minimum Endurance 3 = 1000 cycles Read Access Speed 70 = 70 ns, 90 = 90 ns Device Density 512 = 512 Kilobit 010 = 1 Megabit 020 = 2 Megabit 040 = 4 Megabit SST37VF512 Valid combinations SST37VF512-70-3C-WH SST37VF512-70-3C-NH SST37VF512-90-3C-WH SST37VF512-90-3C-NH SST37VF512-70-3I-WH SST37VF512-70-3I-NH SST37VF512-90-3I-WH SST37VF512-90-3I-NH SST37VF512-90-3C-PH SST37VF010 Valid combinations SST37VF010-70-3C-WH SST37VF010-70-3C-NH SST37VF010-90-3C-WH SST37VF010-90-3C-NH SST37VF010-70-3I-WH SST37VF010-70-3I-NH SST37VF010-90-3I-WH SST37VF010-90-3I-NH SST37VF010-90-3C-PH SST37VF020 Valid combinations SST37VF020-70-3C-WH SST37VF020-70-3C-NH SST37VF020-90-3C-WH SST37VF020-90-3C-NH SST37VF020-70-3I-WH SST37VF020-70-3I-NH SST37VF020-90-3I-WH SST37VF020-90-3I-NH SST37VF020-90-3C-PH SST37VF040 Valid combinations SST37VF040-70-3C-WH SST37VF040-70-3C-NH SST37VF040-90-3C-WH SST37VF040-90-3C-NH SST37VF040-70-3I-WH SST37VF040-70-3I-NH SST37VF040-90-3I-WH SST37VF040-90-3I-NH SST37VF040-90-3C-PH Example:Valid combinations are those products in mass production or will be in mass production. Consult your SST sales representative to confirm availability of valid combinations and to determine availability of new combinations. © 2000 Silicon Storage Technology, Inc. Powered by ICminer.com Electronic-Library Service CopyRight 2003 14 397-03 2/00 512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Many-Time Programmable Flash SST37VF512 / SST37VF010 / SST37VF020 / SST37VF040 Data Sheet PACKAGING DIAGRAMS 1.05 0.95 PIN # 1 IDENTIFIER 1 .50 BSC 2 .270 .170 8.10 7.90 3 4 0.15 0.05 12.50 12.30 6 0.70 0.50 Note: 5 14.20 13.80 1. Complies with JEDEC publication 95 MO-142 BA dimensions, although some dimensions may be more stringent. 2. All linear dimensions are in millimeters (min/max). 3. Coplanarity: 0.1 (±.05) mm. 7 32.TSOP-WH-ILL.3 8 32-PIN THIN SMALL OUTLINE PACKAGE (TSOP) SST PACKAGE CODE: WH 9 pin 1 index 1 10 CL 11 .600 .625 32 12 .530 .550 1.645 1.655 .065 .075 7˚ 4 PLCS. 13 .170 .200 Base Plane Seating Plane .015 .050 .070 .080 Note: .045 .065 .016 .022 .100 BSC .120 .150 14 0˚ 15˚ .008 .012 .600 BSC 15 1. Complies with JEDEC publication 95 MO-015 AP dimensions, although some dimensions may be more stringent. 2. All linear dimensions are in inches (min/max). 3. Dimensions do not include mold flash. Maximum allowable mold flash is .010 inches. 16 32.pdipPH-ILL.1 32-PIN PLASTIC DUAL-IN-LINE PACKAGE (PDIP) SST PACKAGE CODE: PH © 2000 Silicon Storage Technology, Inc. Powered by ICminer.com Electronic-Library Service CopyRight 2003 15 397-03 2/00 512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Many-Time Programmable Flash SST37VF512 / SST37VF010 / SST37VF020 / SST37VF040 Data Sheet TOP VIEW Optional Pin #1 Identifier SIDE VIEW .485 .495 .447 .453 .042 .048 2 1 .106 .112 32 .020 R. MAX. .023 x 30˚ .029 .030 R. .040 .042 .048 .585 .595 BOTTOM VIEW .547 .553 .013 .021 .400 BSC .026 .032 .490 .530 .050 BSC. .015 Min. .075 .095 .050 BSC. .125 .140 Note: 1. Complies with JEDEC publication 95 MS-016 AE dimensions, although some dimensions may be more stringent. 2. All linear dimensions are in inches (min/max). 3. Dimensions do not include mold flash. Maximum allowable mold flash is .008 inches. .026 .032 32.PLCC.NH-ILL.1 32-PIN PLASTIC LEAD CHIP CARRIER (PLCC) SST PACKAGE CODE: NH Silicon Storage Technology, Inc. • 1171 Sonora Court • Sunnyvale, CA 94086 • Telephone 408-735-9110 • Fax 408-735-9036 www.SuperFlash.com or www.ssti.com • Literature FaxBack 888-221-1178, International 732-544-2873 © 2000 Silicon Storage Technology, Inc. Powered by ICminer.com Electronic-Library Service CopyRight 2003 16 397-03 2/00