PM5349 S/UNI-155-QUAD PMC-Sierra,Inc. Quad 155 Mb/s ATM Physical Layer Device PACKAGING • Implemented in low power 3.3 V CMOS technology. • Packaged in a 304-pin Ball Grid Array (BGA) package. • Industrial temp. range (-40° to +85°C). APPLICATIONS • Enterprise and Edge ATM Switches • ATM Switches and Hubs • Multiprotocol Switches TDO TCLK TFPO BLOCK DIAGRAM TFPI • Recovers clock and data. • Frames to and descrambles recovered stream. • Filters and captures Automatic Protection Switch (APS) byes (K1, K2) and detects APS byte failure. • Detects signal degrade and signal failure threshold crossing alarms. • Captures and debounces synchronization status byte (S1). • Synthesizes the 155.52 MHz transmit clock from a 19.44 MHz reference. • Provides a single transmit frame pulse input to align the transport frames to a system reference. • Provides single transmit clock as timing reference for transmit outputs. • Inserts register programmable APS (K1 and K2) and synchronization status (S1) bytes. • Inserts PAIS, PRDI, LAIS, and LRDI. • Scrambles the transmit data stream. • Implements the ATM Forum User Network Interface Specification. • Inserts and extracts ATM cells into and from the SONET SPE. • Performs cell payload scrambling and descrambling. • Provides a UTOPIA Level 2-compliant system interface. • Provides synchronous 4-cell transmit and receive FIFO buffers. TRSTB SONET RECEIVER SONET TRANSMITTER ATM PROCESSOR TCK • Quad-channel ATM OC-3c (155 Mb/s) PHY. • Provides on-chip clock and data recovery and clock synthesis. • Exceeds Bellcore-GR-253 jitter requirements. • Provides a generic 8-bit microprocessor interface for device control and register access. • Provides standard IEEE 1149.1 JTAG test port for boundary scan. • Counts received section BIP-8 (B1), line BIP-24 (B2), and BIP-8 (B3) errors, and line and path FEBEs. • Detects LOS, OOF, LOF, LAIS, LRDI, LOP, PAIS, PRDI, and PERDI. • Provides individual divide by eight recovered clocks for each channel. • Provides individual 8 kHz receive frame pulses for each channel. TDI TMS FEATURES JTAG Test Access Port DTCA[4:1] TDAT[15:0] TPRTY TXD[4:1]- Transmit Line Interface TSOC Transmit Section Transmit Line O/H Processor O/H Processor Transmit Path O/H Processor Transmit ATM Cell Processor TCA TADR[4:0] UTOPIA Level 2 System Interface TXD[4:1]+ ATB[3:0] REFCLK RXD[4:1]+ RXD[4:1]SD[4:1] Receive Line Interface Receive Section Receive Line O/H Processor O/H Processor Receive Path O/H Processor Receive ATM Cell Processor TENB TFCLK PHY_OEN RFCLK RENB RADR[4:0] RCA RSOC RPRTY Receive APS, Sync, BERM RDAT[15:0] DRCA[4:1] PMC-980863 (R3) INTB RDB RSTB WRB ALE PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE CSB D[7:0] A[10:0] RCLK[4:1] RFPO[4:1] RALRM[4:1] Microprocessor Interface 1999 PMC-Sierra, Inc. PM5349 S/UNI-155-QUAD Quad 155 Mb/s ATM Physical Layer Device TYPICAL APPLICATION STS-3c (STM-1) ATM SWITCH PORT APPLICATION UTOPIA Level 2 Interface ATM Layer Device PM5349 681,48$' Quad 155 Mb/s ATM Physical Layer Device TxClk TFCLK TxEnb TENB RX1+/SD1 TxAddr[4:0] TXD1+/- TADR[4:0] TxClav TCA TxSOC TSOC TxPrty TPRTY RX2+/SD2 TxData[15:0] RFCLK RxEnb RENB TXD2+/- RX3+/SD3 RADR[4:0] RxClav RCA RxSOC RSOC RxPrty RPRTY Head Office: PMC-Sierra, Inc. #105 - 8555 Baxter Place Burnaby, B.C. V5A 4V7 Canada Tel: 604.415.6000 Fax: 604.415.6200 RDAT[15:0] To order documentation, send email to: [email protected] or contact the head office, Attn: Document Coordinator Optical Transceiver TXD3+/- RXD4+/SD4 RxData[15:0] Optical Transceiver TDAT[15:0] RxClk RxAddr[4:0] Optical Transceiver Optical Transceiver TXD4+/- All product documentation is available on our web site at: http://www.pmc-sierra.com For corporate information, send email to: [email protected] PMC-980863 (R3) 1999 PMC-Sierra, Inc. August, 1999 SATURN and S/UNI-155-QUAD are trademarks of PMC-Sierra, Inc. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE