PM73123 AAL1gator™-8 8 Link CES/DBCES AAL1 SAR TRANSMIT SECTION • Provides individually enabled per-VC data and signaling conditioning in the transmit cell direction and per DS0 data and signaling conditioning in the transmit line direction. Includes DS3 AIS conditioning support in both directions. • Provides per-VC configuration of time slots allocated, CAS support, partial cell size, data and signaling conditioning, ATM Cell header definition. • Generates AAL1 sequence numbers, pointers and SRTS values in accordance with ITU-T I.363.1. Multicast connections are supported. • Provides a patented frame based calendar queue service algorithm with anti-clumping add-queue mechanism that produces minimal CDV. In unstructured mode, uses non-frame based scheduling to optimize CDV. LINE INTERFACE • Supports the following flexible line interfaces: • Eight individual T1 or E1 lines. • Two H-MVIP lines at 8 MHz. • One unstructured DS3, E3 or STS1/STM-0 line. • Provides lineside loopback support on a per channel basis. UTOPIA INTERFACE CTL_CLK CRL_CLK NCLK SYSCLK BLOCK DIAGRAM RL_CLK[7:0] • Supports 52 MHz, 8/16-bit Level 2, Multi-Phy Mode (MPHY) with parity, 8/16-bit Level 1, SPHY and 8-bit Level 1, ATM Master modes. TL_CLK[7:0] • Supports eight structured/unstructured T1, E1 links or one unstructured DS3, E3 or STS-1/STM-0 link over an AAL1 CBR ATM network. • Compliant with ATM Forum's CES (AFVTOA-0078), and ITU-T I.363.1. • Supports up to 256 VCs. • Supports n x 64 (consecutive channels) and m x 64 (nonconsecutive channels) structured data format with channel associated signaling (CAS) support. • Internal E1/T1 clock synthesizers provided for each line which can be controlled via internal synchronous residual time stamp (SRTS) or an internal programmable weighted moving average adaptive clocking algorithm in unstructured mode. Clock synthesizers can also be controlled externally to provide customization of SRTS or adaptive clocking methods. • Provides transparent transmission of CCS and CAS and termination of CAS signaling. • Compliant with ATM Forum's Dynamic Bandwidth Circuit Emulation Service • Provides an optional 8/16-bit AnyPHY™ slave interface. • Provides a three cell FIFO for UTOPIA loopback support on a per VC basis or a global basis. (DBCES) AF-VTOA-0085. Supports idle channel detection via processor intervention, CAS signaling, or data pattern detection. Provides idle channel indication on a per channel basis. • Supports AAL0 mode, selectable on a per VC basis. • Provides transmit and receive buffers which can be used for OAM cells as well as any other user-generated cells such as AAL5 cells for ATM signaling. TL_CLK_OE FEATURES RSTB SCAN_ENB SCAN_MODEB Line Interface Clock MUX TATM_DATA[15:0] LINE_MODE TATM_PAR TATM_ENB TATM_SOC TATM_CLAV F0B 8 H-MVIP TATM_CLK 8 TL_DATA[7:0] RPHY_ADD[4:0] UTOPIA Interface RATM_DATA[15:0] TL_SYNC[7:0] TL_SIG[7:0] 8 RATM_PAR 8 A1SP 8 RATM_ENB RATM_SOC RL_DATA[7:0] RL_SYNC[7:0] 8 Direct Mode RL_SIG[7:0] RATM_CLAV RATM_CLK TPHY_ADD[4:0] CGC_SER_D SRTS_STB CGC_VALID ADAP_STB C_DOUT[3:0] INTB CSB ACKB RDB ALE WRB A[19:0] D[15:0] RAM_OEB PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE GC_LINE[3:0] External Clock Interface Processor Interface RAM_CSB AM_WEB[1:0] AM_PAR[1:0] RAM_A[16:0] RAM_ADSCB TCK TDI TMS TDO TRST PMC-1991272 (r2) RAM_D[15:0] RAM Interface JTAG Copyright PMC-Sierra, Inc. 2001 PM73123 AAL1gator™-8 8 Link CES/DBCES AAL1 SAR • Queues are added by making entries into an add queue FIFO to minimize queue activation overhead. RECEIVE SECTION • Provides per-VC configuration of time slots allocated, partial cell size, sequence number processing options, cell delay variation tolerance buffer depth, maximum buffer depth. • Supports Fast Sequence Number processing and Robust Sequence Number processing. GENERAL • Provides a microprocessor interface for configuration, management, and statistics gathering. • Provides single maskable, opencollector interrupt with master interrupt register to facilitate processing for AAL1, RAM and UTOPIA exceptions. • Provides multiple counters in the Cell Transmit and Receive directions as required by the ATM Forum's CES-IS 2.0 MIB. • Provides a seamless interface to an external 128K x 16 (18) (10 ns) Synchronous SRAM or ZBT RAM. • Low-power 2.5V CMOS with 3.3V, 5V tolerant I/O. • 324-pin plastic ball grid array (PBGA) package. • Pin compatible with PM73124 AAL1gator-4. APPLICATIONS • Integrated Access Device. • DACS with an ATM Interface. • ATM Multiservice Switch CES Port Cards. • ATM Optical Networking Unit (ONU), ATM Passive Optical Network (APON). TYPICAL APPLICATIONS INTEGRATED ACCESS DEVICE T1/E1 x 8 PM4354 COMET-QUAD PM4354 COMET-QUAD UTOPIA L2/ Any-PHY UTOPIA L2 PM7329 S/UNI-APEX1K800 PM73123 AAL1gator-8 PM7347 S/UNI-JET Ethernet Video T1/E1 x 8 PM4354 COMET-QUAD PM4354 COMET-QUAD PM7328 S/UNI-ATLAS1K800 ATM Interworking Function, AAL5 SAR ATM OPTICAL NETWORK UNIT (ONU) UTOPIA L2/ Any-PHY PM73123 AAL1gator-8 UTOPIA L2 PM7329 S/UNI-APEX1K800 Optical Module Ethernet Video Head Office: PMC-Sierra, Inc. 8555 Baxter Place Burnaby, B.C. V5A 4V7 Canada Tel: 604.415.6000 Fax: 604.415.6200 ATM Interworking Function, AAL5 SAR To order documentation, send email to: [email protected] or contact the head office, Attn: Document Coordinator DS3 LIU APON PM7328 S/UNI-ATLAS1K800 All product documentation is available on our web site at: http://www.pmc-sierra.com For corporate information, send email to: [email protected] PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE PMC-1991272 (r2) Copyright PMC-Sierra, Inc. 2001. All rights reserved. August 2001 S/UNI is a registered trademark and AAL1gator, Any-PHY, COMETQUAD, ALL1gator-8, and PMC-Sierra are trademarks of PMC-Sierra, Inc.