PMC PM5351-BI

PMC-Sierra, Inc.
PM5351 S/UNI-TETRA
S/UNI-TETRA
DATASHEET
PMC-1971240
ISSUE 7
SATURN USER NETWORK INTERFACE (155-TETRA)
PM5351
S/UNI- ®
155-TETRA
S/UNI-TETRA
SATURN
USER NETWORK INTERFACE
(155-TETRA)
DATA SHEET
ISSUE 7: FEBRUARY 2000
PMC-Sierra, Inc.
105 - 8555 Baxter Place Burnaby, BC Canada V5A 4V7 604 .415.6000
PMC-Sierra, Inc.
PM5351 S/UNI-TETRA
S/UNI-TETRA
DATASHEET
PMC-1971240
ISSUE 7
SATURN USER NETWORK INTERFACE (155-TETRA)
REVISION HISTORY
Issue
No.
Issue Date
Details of Change
7
February 2000
•
Converted Bit 0 of register 0x0E to “Reserved"
•
Added PERFCTRL register bit to register 0x0F
•
Changed AVGPER bit description in register 0xDD.
PMC-Sierra, Inc.
105 - 8555 Baxter Place Burnaby, BC Canada V5A 4V7 604 .415.6000
PMC-Sierra, Inc.
PM5351 S/UNI-TETRA
S/UNI-TETRA
DATASHEET
PMC-1971240
ISSUE 7
SATURN USER NETWORK INTERFACE (155-TETRA)
Issue
No.
Issue Date
Details of Change
6
December,
1999
General update including:
PMC-Sierra, Inc.
•
Page 17 – Signal Detect connection information
•
Page 18 – Power info when using 155.52 transmit clocks
•
Page 24,32 – Clarification on use of TENB and RENB
•
Page 37 – PHY_OEN operation when the TETRA is
shared with other PHY devices on the same bus
•
Page 38 – Device initialization information
•
Page 40 – 220nf X7R 10% ceramatic capacitor used to
meet jitter transfer specifications
•
Page 42 – Pull-up resistor on QAVD signals needed to
avoid latchup during power-up
•
Page 60, 214, 234 – Maximum packet length should be
set no greater than 0xFFFE
•
Page 66 – Packets are not aborted in overrun conditions
•
Page 72 – RPA assertion information
•
Page 86 – Revision ID bits incremented
•
Page 105 – LANB_WAN bit added to select between jitter
transfer and non jitter transfer mode of operations
•
Page 152 – Path far end receiver failure alarm persistence
bit info updated
•
Page 161 – Info on setting Path Signal Label for POS
mode
•
Page 176 – FIFO reset should be performed after FIFO
overrrun
•
Page 210 – Register bit added to select between abort
sequence or flag insertion under a drop path AIS condition
•
Page 216 – Maximum Receive Packet Available High
Water Mark is 0xF0
105 - 8555 Baxter Place Burnaby, BC Canada V5A 4V7 604 .415.6000
PMC-Sierra, Inc.
PM5351 S/UNI-TETRA
S/UNI-TETRA
DATASHEET
PMC-1971240
ISSUE 7
SATURN USER NETWORK INTERFACE (155-TETRA)
Issue
No.
Issue Date
Details of Change
6
December
1999
•
Page 229 – Info on setting Transmit Initiation Levels
•
Page 232 – Setting of Transmit Packet Available High
Water Mark to avoid FIFO overrruns
•
Page 250 – S1 debouncing information
•
Page 268 – Updated boundary scan info
•
Page 296 – Analog Power Supply Filtering info
•
Page 298 – Updated Power Supply Sequencing info
•
Page 303 – Setting the TETRA for SDH or SONET mode
•
Page 308 – Updated POS Receive Synchronous FIFO
Timing Diagram
•
Page 313 – Updated DC characteristic
•
Page 336 – Updated air flow info
PMC-Sierra, Inc.
105 - 8555 Baxter Place Burnaby, BC Canada V5A 4V7 604 .415.6000
PMC-Sierra, Inc.
PM5351 S/UNI-TETRA
S/UNI-TETRA
DATASHEET
PMC-1971240
ISSUE 7
SATURN USER NETWORK INTERFACE (155-TETRA)
CONTENTS
1
FEATURES .............................................................................................................. 1
1.1
GENERAL.................................................................................................... 1
1.2
THE SONET RECEIVER............................................................................... 2
1.3
THE RECEIVE ATM PROCESSOR................................................................ 3
1.4
THE RECEIVE POS PROCESSOR ............................................................... 3
1.5
THE SONET TRANSMITTER ........................................................................ 4
1.6
THE TRANSMIT ATM PROCESSOR.............................................................. 4
1.7
THE TRANSMIT POS PROCESSOR ............................................................. 5
2
APPLICATIONS ........................................................................................................ 6
3
REFERENCES ......................................................................................................... 7
4
DEFINITIONS........................................................................................................... 9
5
APPLICATION EXAMPLES ..................................................................................... 12
6
BLOCK DIAGRAM .................................................................................................. 16
7
DESCRIPTION ....................................................................................................... 18
8
PIN DIAGRAM........................................................................................................ 21
9
PIN DESCRIPTION................................................................................................. 23
10
9.1
LINE SIDE INTERFACE SIGNALS............................................................... 23
9.2
SECTION AND LINE STATUS DCC SIGNALS .............................................. 27
9.3
ATM (UTOPIA) AND PACKET OVER SONET (POS-PHY) SYSTEM
INTERFACE ............................................................................................... 29
9.4
MICROPROCESSOR INTERFACE SIGNALS .............................................. 51
9.5
JTAG TEST ACCESS PORT (TAP) SIGNALS ............................................... 52
9.6
ANALOG SIGNALS..................................................................................... 53
9.7
POWER AND GROUND.............................................................................. 54
FUNCTIONAL DESCRIPTION................................................................................. 61
10.1
10.2
RECEIVE LINE INTERFACE (CRSI) ............................................................ 61
10.1.1
CLOCK RECOVERY................................................................. 61
10.1.2
SERIAL TO PARALLEL CONVERTER ....................................... 62
RECEIVE SECTION OVERHEAD PROCESSOR (RSOP)............................. 62
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
i
PMC-Sierra, Inc.
PM5351 S/UNI-TETRA
S/UNI-TETRA
DATASHEET
PMC-1971240
ISSUE 7
10.3
10.4
10.5
10.6
10.7
SATURN USER NETWORK INTERFACE (155-TETRA)
10.2.1
FRAMER.................................................................................. 63
10.2.2
DESCRAMBLE ......................................................................... 63
10.2.3
DATA LINK EXTRACT............................................................... 63
10.2.4
ERROR MONITOR................................................................... 63
10.2.5
LOSS OF SIGNAL .................................................................... 64
10.2.6
LOSS OF FRAME..................................................................... 64
RECEIVE LINE OVERHEAD PROCESSOR (RLOP)..................................... 64
10.3.1
LINE RDI DETECT.................................................................... 64
10.3.2
LINE AIS DETE CT.................................................................... 65
10.3.3
DATA LINK EXTRACT BLOCK................................................... 65
10.3.4
ERROR MONITOR BLOCK ....................................................... 65
THE RECEIVE APS, SYNCHRONIZATION EXTRACTOR AND BIT ERROR
MONITOR (RASE)...................................................................................... 66
10.4.1
AUTOMATIC PROTECTION SWITCH CONTROL ...................... 66
10.4.2
BIT ERROR RATE MONITOR.................................................... 67
10.4.3
SYNCHRONIZATION STATUS EXTRACTION............................ 67
RECEIVE PATH OVERHEAD PROCESSOR (RPOP)................................... 68
10.5.1
POINTER INTERPRETER......................................................... 68
10.5.2
SPE TIMING............................................................................. 72
10.5.3
ERROR MONITOR................................................................... 72
RECEIVE ATM CELL PROCESSOR (RXCP)................................................ 73
10.6.1
CELL DELINEATION................................................................. 73
10.6.2
DESCRAMBLER ...................................................................... 75
10.6.3
CELL FILTER AND HCS VERIFICATION.................................... 75
10.6.4
PERFORMANCE MONITOR ..................................................... 76
RECEIVE POS FRAME PROCESSOR (RXFP) ............................................ 77
10.7.1
OVERHEAD REMOVAL............................................................ 77
10.7.2
DESCRAMBLER ...................................................................... 77
10.7.3
POS FRAME DELINEATION ..................................................... 77
10.7.4
BYTE DESTUFFING................................................................. 78
10.7.5
FCS CHECK............................................................................. 78
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
ii
PMC-Sierra, Inc.
PM5351 S/UNI-TETRA
S/UNI-TETRA
DATASHEET
PMC-1971240
ISSUE 7
10.8
10.9
10.10
10.11
10.12
10.13
SATURN USER NETWORK INTERFACE (155-TETRA)
10.7.6
PERFORMANCE MONITOR ..................................................... 79
10.7.7
RECEIVE FIFO......................................................................... 80
TRANSMIT LINE INTERFACE (CSPI).......................................................... 80
10.8.1
CLOCK SYNTHESIS................................................................. 81
10.8.2
PARALLEL TO SERIAL CONVERTER....................................... 81
TRANSMIT SECTION OVERHEAD PROCESSOR (TSOP)........................... 81
10.9.1
LINE AIS INSERT..................................................................... 81
10.9.2
DATA LINK INSERT.................................................................. 81
10.9.3
BIP-8 INSERT.......................................................................... 82
10.9.4
FRAMING AND IDENTITY INSERT............................................ 82
10.9.5
SCRAMBLER........................................................................... 82
TRANSMIT LINE OVERHEAD PROCESSOR (TLOP)................................... 83
10.10.1
APS INSERT............................................................................ 83
10.10.2
DATA LINK INSERT.................................................................. 83
10.10.3
LINE BIP CALCULATE .............................................................. 83
10.10.4
LINE RDI INSERT..................................................................... 83
10.10.5
LINE FEBE INSERT.................................................................. 84
TRANSMIT PATH OVERHEAD PROCESSOR (TPOP)................................. 84
10.11.1
POINTER GENERATOR ........................................................... 84
10.11.2
BIP-8 CALCULATE ................................................................... 85
10.11.3
FEBE CALCULA TE................................................................... 85
TRANSMIT ATM CELL PROCESSOR (TXCP).............................................. 85
10.12.1
IDLE/UNASSIGNED CELL GENERATOR................................... 85
10.12.2
SCRAMBLER........................................................................... 85
10.12.3
HCS GENERATOR ................................................................... 86
TRANSMIT POS FRAME PROCESSOR (TXFP).......................................... 86
10.13.1
TRANSMIT FIFO ...................................................................... 86
10.13.2
POS FRAME GENERATOR ...................................................... 87
10.13.3
FCS GENERATO R ................................................................... 87
10.13.4
BYTE STUFFING...................................................................... 88
10.13.5
DATA SCRAMBLING................................................................. 88
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
iii
PMC-Sierra, Inc.
PM5351 S/UNI-TETRA
S/UNI-TETRA
DATASHEET
PMC-1971240
ISSUE 7
10.13.6
10.14
SONET/SDH FRAMER ............................................................. 89
SONET/SDH SECTION AND PATH TRACE BUFFERS (SSTB AND SPTB).... 89
10.14.1
10.14.2
10.15
RECEIVE TRACE BUFFER (RTB)............................................. 89
10.14.1.1
TRACE MESSAGE RECEIVER..................................... 89
10.14.1.2
OVERHEAD BYTE RECEIVER...................................... 90
TRANSMIT TRA CE BUFFER (TTB)........................................... 91
ATM UTOPIA AND PACKET OVER SONET/SDH POS-PHY SYSTEM
INTERFACES............................................................................................. 91
10.15.1
RECEIVE ATM INTERFACE ...................................................... 92
10.15.2
RECEIVE POS INTERFACE...................................................... 92
10.15.2.1
10.16
SATURN USER NETWORK INTERFACE (155-TETRA)
PREMATURE RPA ASSERTION.................................... 93
10.15.3
TRANSMIT ATM INTERFACE.................................................... 94
10.15.4
TRANSMIT POS INTERFACE ................................................... 95
WAN SYNCHRONIZATION CONTROLLER (WANS)..................................... 96
10.16.1
PHASE COMPARISON ............................................................. 96
10.16.1.1
10.16.2
PHASE REACQUISITION CONTROL ............................ 97
PHASE AVERAGER.................................................................. 98
10.17
JTAG TEST ACCESS PORT........................................................................ 99
10.18
MICROPROCESSOR INTERFACE .............................................................. 99
11
NORMAL MODE REGIS TER DESCRIPTION..........................................................108
12
TEST FEATURES DESCRIPTION ..........................................................................331
12.1
MASTER TEST REGISTER........................................................................331
12.2
TEST MODE 0 DETAILS ............................................................................333
12.3
JTAG TEST PORT.....................................................................................333
12.3.1
13
BOUNDARY SCAN CELLS ......................................................341
OPERATION .........................................................................................................344
13.1
13.2
SONET/SDH FRAME MAPPINGS AND OVERHEAD BYTE USAGE.............344
13.1.1
ATM MAPPING........................................................................344
13.1.2
PACKET OVER SONET/SDH MAPPING...................................346
13.1.3
TRANSPORT AND PATH OVERHEAD BYTES..........................348
ATM CELL DATA STRUCTURE ..................................................................356
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
iv
PMC-Sierra, Inc.
PM5351 S/UNI-TETRA
S/UNI-TETRA
DATASHEET
PMC-1971240
ISSUE 7
13.3
PACKET OVER SONET/SDH DATA STRUCTURE ......................................358
13.4
BIT ERROR RATE MONITOR.....................................................................358
13.5
CLOCKING OPTIONS ...............................................................................359
13.6
LOOPBACK OPERATION..........................................................................361
13.7
JTAG SUPPORT........................................................................................369
13.7.1
14
SATURN USER NETWORK INTERFACE (155-TETRA)
TAP CONTROLLE R.................................................................370
13.7.1.1
STATES ......................................................................372
13.7.1.2
INSTRUCTIONS ..........................................................373
13.8
BOARD DESIGN RECOMMENDATIONS ....................................................374
13.9
ANALOG POWER SUPPLY FILTERING......................................................375
13.10
POWER SUPPLIES SEQUENCING............................................................380
13.11
INTERFACING TO ECL OR PECL DEVICES...............................................382
13.12
CLOCK RECOVERY LOOP FILTER...........................................................385
13.13
SETTING THE S/UNI-TETRA IN ATM MODE ..............................................385
13.14
SETTING THE S/UNI-TETRA IN POS MODE ..............................................386
13.15
SETTING THE S/UNI-TETRA FOR SONET OR SDH APPLICATIONS ..........387
13.16
USING THE S/UNI-TETRA WITH A 5 VOLT ODL.........................................387
FUNCTIONAL TIMING ...........................................................................................388
14.1
ATM UTOPIA LEVEL 2 SYSTEM INTERFACE.............................................388
14.2
PACKET OVER SONET/SDH (POS) SYSTEM INTERFACE.........................390
14.3
SECTION AND LINE DATA COMMUNICATION CHANNELS ........................393
15
ABSOLUTE MAXIMUM RATINGS...........................................................................396
16
D.C. CHARACTERISTICS ......................................................................................397
17
MICROPROCESSOR INTERFACE TIMING CHARACTERISTICS ............................400
18
A.C. TIMING CHARACTERISTICS .........................................................................404
18.1
SYSTEM RESET TIMING...........................................................................404
18.2
REFERENCE TIMING................................................................................404
18.3
ATM SYSTEM INTERFACE TIMING ...........................................................405
18.4
POS SYSTEM INTERFACE TIMING ...........................................................409
18.5
LINE AND SECTION DCC TIMING.............................................................414
18.6
TRANSMIT AND RE CEIVE FRAME PULSES..............................................416
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
v
PMC-Sierra, Inc.
PM5351 S/UNI-TETRA
S/UNI-TETRA
DATASHEET
PMC-1971240
ISSUE 7
SATURN USER NETWORK INTERFACE (155-TETRA)
18.7
TRANSMIT LINE TIMING IN SINCLE ENDED TXD/TXC MODE ...................417
18.8
JTAG TEST PORT TIMING.........................................................................417
19
ORDERING AND THERMAL INFORMATION ..........................................................420
20
MECHANICAL INFORMATION...............................................................................422
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
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PMC-Sierra, Inc.
PM5351 S/UNI-TETRA
S/UNI-TETRA
DATASHEET
PMC-1971240
ISSUE 7
SATURN USER NETWORK INTERFACE (155-TETRA)
LIST OF REGISTERS
REGISTER 0X00: S/UNI-TETRA MASTER RESET AND IDENTITY ......................................109
REGISTER 0X01: S/UNI-TETRA MASTER CONFIGURATION ............................................. 110
REGISTER 0X02: S/UNI-TETRA MASTER SYSTEM INTERFACE CONTROL...................... 112
REGISTER 0X03: S/UNI-TETRA MASTER CLOCK MONITOR............................................. 114
REGISTER 0X04: S/UNI-TETRA MASTER INTERRUPT STATUS ........................................ 116
REGISTER 0X05: S/UNI-TETRA CHANNEL RESET AND MONITORING UPDATE ............... 118
REGISTER 0X06: S/UNI-TETRA CHANNEL CONFIGURATION........................................... 119
REGISTER 0X07: S/UNI-TETRA CHANNEL CONTROL.......................................................121
REGISTER 0X08: S/UNI-TETRA CHANNEL CONTROL EXTENSION ..................................123
REGISTER 0X0A: S/UNI-TETRA CHANNEL INTERRUPT STATUS #1.................................124
REGISTER 0X0B: S/UNI-TETRA CHANNEL INTERRUPT STATUS #2.................................126
REGISTER 0X0C: CSPI (CLOCK SYNTHESIS) CONTROL AND STATUS ............................128
REGISTER 0X0D: CSPI (CLOCK SYNTHESIS) RESERVED...............................................130
REGISTER 0X0E: CRSI (CLOCK RECOVERY) CONTROL AND STATUS ............................131
REGISTER 0X0F: CRSI (CLOCK RECOVERY) PLL MODE SELECT...................................133
REGISTER 0X10: RSOP CONTROL/INTERRUPT ENABLE.................................................135
REGISTER 0X11: RSOP STATUS/INTERRUPT STATUS .....................................................137
REGISTER 0X12: RSOP SECTION BIP-8 LSB....................................................................139
REGISTER 0X13: RSOP SECTION BIP-8 MSB...................................................................139
REGISTER 0X14: TSOP CONTROL ...................................................................................140
REGISTER 0X15: TSOP DIAGNOSTIC...............................................................................143
REGISTER 0X18: RLOP CONTROL/STATUS .....................................................................144
REGISTER 0X19: RLOP INTERRUPT ENABLE/INTERRUPT STATUS.................................147
REGISTER 0X1A: RLOP LINE BIP-24 LSB .........................................................................149
REGISTER 0X1B: RLOP LINE BIP-24 ................................................................................149
REGISTER 0X1C: RLOP LINE BIP-24 MSB........................................................................150
REGISTER 0X1D: RLOP LINE FEBE LSB ..........................................................................151
REGISTER 0X1E: RLOP LINE FEBE..................................................................................151
REGISTER 0X1F: RLOP LINE FEBE MSB..........................................................................152
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
vii
PMC-Sierra, Inc.
PM5351 S/UNI-TETRA
S/UNI-TETRA
DATASHEET
PMC-1971240
ISSUE 7
SATURN USER NETWORK INTERFACE (155-TETRA)
REGISTER 0X20: TLOP CONTROL ...................................................................................153
REGISTER 0X21: TLOP DIAGNOSTIC...............................................................................156
REGISTER 0X22: TLOP TRANSMIT K1..............................................................................157
REGISTER 0X23: TLOP TRANSMIT K2..............................................................................158
REGISTER 0X24: S/UNI-TETRA CHANNEL TRANSMIT SYNC. MESSAGE (S1) ..................159
REGISTER 0X25: S/UNI-TETRA CHANNEL TRANSMIT J0/Z0.............................................160
REGISTER 0X28: SSTB CONTROL ...................................................................................161
REGISTER 0X29: SSTB SECTION TRACE IDENTIFIER STATUS.......................................163
REGISTER 0X2A: SSTB INDIRECT ADDRESS REGISTER.................................................165
REGISTER 0X2B: SSTB INDIRECT DATA REGISTER........................................................166
REGISTER 0X30 (EXTD=0): RPOP STATUS/CONTROL.....................................................170
REGISTER 0X30 (EXTD=1): RPOP STATUS/CONTROL.....................................................172
REGISTER 0X31 (EXTD=0): RPOP INTERRUPT STATUS ..................................................174
REGISTER 0X31 (EXTD=1): RPOP INTERRUPT STATUS ..................................................176
REGISTER 0X32: RPOP POINTER INTERRUPT STATUS...................................................177
REGISTER 0X33 (EXTD=0): RPOP INTERRUPT ENABLE ..................................................179
REGISTER 0X33 (EXTD=1): RPOP INTERRUPT ENABLE .................................................181
REGISTER 0X34: RPOP POINTER INTERRUPT ENABLE ..................................................183
REGISTER 0X35: RPOP POINTER LSB.............................................................................185
REGISTER 0X36: RPOP POINTER MSB AND RDI FILTER CONTROL ................................186
REGISTER 0X37: RPOP PATH SIGNAL LABEL..................................................................188
REGISTER 0X38: RPOP PATH BIP-8 LSB..........................................................................189
REGISTER 0X39: RPOP PATH BIP-8 MSB .........................................................................189
REGISTER 0X3A: RPOP PATH FEBE LSB .........................................................................190
REGISTER 0X3B: RPOP PATH FEBE MSB ........................................................................190
REGISTER 0X3C: RPOP AUXILIARY RDI...........................................................................191
REGISTER 0X3D: RPOP ERROR EVENT CONTROL .........................................................193
REGISTER 0X40: TPOP CONTROL/DIAGNOSTIC .............................................................196
REGISTER 0X41: TPOP POINTER CONTROL ...................................................................199
REGISTER 0X43: TPOP CURRENT POINTER LSB ............................................................203
REGISTER 0X44: TPOP CURRENT POINTER MSB ...........................................................204
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
viii
PMC-Sierra, Inc.
PM5351 S/UNI-TETRA
S/UNI-TETRA
DATASHEET
PMC-1971240
ISSUE 7
SATURN USER NETWORK INTERFACE (155-TETRA)
REGISTER 0X45: TPOP ARBITRARY POINTER LSB..........................................................205
REGISTER 0X46: TPOP ARBITRARY POINTER MSB.........................................................206
REGISTER 0X47: TPOP PATH TRACE ...............................................................................207
REGISTER 0X48: TPOP PATH SIGNAL LABEL...................................................................208
REGISTER 0X49: TPOP PATH STATUS .............................................................................209
REGISTER 0X50: SPTB CONTROL ...................................................................................217
REGISTER 0X51: SPTB PATH TRACE IDENTIFIER STATUS ..............................................219
REGISTER 0X52: SPTB INDIRECT ADDRESS REGISTER.................................................221
REGISTER 0X53: SPTB INDIRECT DATA REGISTER.........................................................222
REGISTER 0X54: SPTB EXPECTED PATH SIGNAL LABEL................................................223
REGISTER 0X55: SPTB PATH SIGNAL LABEL STATUS .....................................................224
REGISTER 0X60: RXCP_50 CONFIGURATION 1..............................................................226
REGISTER 0X61: RXCP_50 CONFIGURATION 2..............................................................228
REGISTER 0X62: RXCP_50 FIFO/UTOPIA CONTROL & CONFIG......................................231
REGISTER 0X63: RXCP_50 INTERRUPT ENABLES AND COUNTER STATUS ..................233
REGISTER 0X64: RXCP_50 STATUS/INTERRUPT STATUS ..............................................235
REGISTER 0X65: RXCP_50 LCD COUNT THRESHOLD (MSB) .........................................237
REGISTER 0X66: RXCP_50 LCD COUNT THRESHOLD (LSB) ..........................................237
REGISTER 0X67: RXCP_50 IDLE CELL HEADER PATTERN.............................................239
REGISTER 0X68: RXCP_50 IDLE CELL HEADER MASK...................................................240
REGISTER 0X69: RXCP_50 CORRECTED HCS ERROR COUNT......................................241
REGISTER 0X6A: RXCP_50 UNCORRECTED HCS ERROR COUNT.................................242
REGISTER 0X6B: RXCP_50 RECEIVE CELL COUNTER (LSB)..........................................243
REGISTER 0X6C: RXCP_50 RECEIVE CELL COUNTER...................................................243
REGISTER 0X6D: RXCP_50 RECEIVE CELL COUNTER (MSB)........................................243
REGISTER 0X6E: RXCP_50 IDLE CELL COUNTER (LSB).................................................245
REGISTER 0X6F: RXCP_50 IDLE CELL COUNTER..........................................................245
REGISTER 0X70: RXCP_50 IDLE CELL COUNTER (MSB)................................................246
REGISTER 0X80: TXCP_50 CONFIGURATION 1..............................................................247
REGISTER 0X81: TXCP_50 CONFIGURATION 2..............................................................249
REGISTER 0X82: TXCP_50 CELL COUNT STATUS/CONFIGURATION OPTIONS ..............251
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
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PMC-Sierra, Inc.
PM5351 S/UNI-TETRA
S/UNI-TETRA
DATASHEET
PMC-1971240
ISSUE 7
SATURN USER NETWORK INTERFACE (155-TETRA)
REGISTER 0X83: TXCP_50 INTERRUPT ENABLE/STATUS ..............................................252
REGISTER 0X84: TXCP_50 IDLE CELL HEADER CONTROL ............................................254
REGISTER 0X85: TXCP_50 IDLE CELL PAYLOAD CONTROL ...........................................255
REGISTER 0X86: TXCP_50 TRANSMIT CELL COUNT (LSB).............................................256
REGISTER 0X87: TXCP_50 TRANSMIT CELL COUNT......................................................256
REGISTER 0X88: TXCP_50 TRANSMIT CELL COUNT (MSB)............................................256
REGISTER 0X90: S/UNI-TETRA CHANNEL AUTO LINE RDI CONTROL.............................258
REGISTER 0X91: S/UNI-TETRA CHANNEL AUTO PATH RDI CONTROL............................260
REGISTER 0X92: S/UNI-TETRA CHANNEL AUTO ENHANCED PATH RDI CONTROL .........262
REGISTER 0X93: S/UNI-TETRA CHANNEL RECEIVE RDI AND ENHANCED RDI CONTROL
EXTENSIONS .......................................................................................................265
REGISTER 0X94: S/UNI-TETRA CHANNEL RE CEIVE LINE AIS CONTROL.........................267
REGISTER 0X95: S/UNI-TETRA CHANNEL RECEIVE PATH AIS CONTROL........................269
REGISTER 0X96: S/UNI-TETRA CHANNEL RECEIVE ALARM CONTROL #1 ......................271
REGISTER 0X97: S/UNI-TETRA CHANNEL RECEIVE ALARM CONTROL #2 ......................271
REGISTER 0XA0: RXFP CONFIGURATION .......................................................................273
REGISTER 0XA1: RXFP CONFIGURATION/INTERRUPT ENABLES ...................................275
REGISTER 0XA2: RXFP INTERRUPT STATUS ..................................................................276
REGISTER 0XA3: RXFP MINIMUM PACKET LENGTH........................................................277
REGISTER 0XA4: RXFP MAXIMUM PACKET LENGTH (LSB).............................................278
REGISTER 0XA5: RXFP MAXIMUM PACKET LENGTH (MSB)............................................278
REGISTER 0XA6: RXFP RECEIVE INITIATION LEVEL.......................................................279
REGISTER 0XA7: RXFP RECEIVE PACKET AVAILABLE HIGH WATER MARK ....................281
REGISTER 0XA8: RXFP RECEIVE BYTE COUNTER (LSB)................................................282
REGISTER 0XA9: RXFP RECEIVE BYTE COUNTER.........................................................282
REGISTER 0XAA: RXFP RECEIVE BYTE COUNTER.........................................................282
REGISTER 0XAB: RXFP RECEIVE BYTE COUNTER (MSB)...............................................283
REGISTER 0XAC: RXFP RECEIVE FRAME COUNTER (LSB)............................................284
REGISTER 0XAD: RXFP RECEIVE FRAME COUNTER......................................................284
REGISTER 0XAE: RXFP RECEIVE FRAME COUNTER (MSB)............................................284
REGISTER 0XAF: RXFP RECEIVE ABORTED FRAME COUNTER (LSB)............................286
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SATURN USER NETWORK INTERFACE (155-TETRA)
REGISTER 0XB0: RXFP RECEIVE ABORTED FRAME COUNTER (MSB) ...........................286
REGISTER 0XB1: RXFP RECEIVE FCS ERROR FRAME COUNTER (LSB)........................287
REGISTER 0XB2: RXFP RECEIVE FCS ERROR FRAME COUNTER (MSB)........................287
REGISTER 0XB3: RXFP RECEIVE MINIMUM LENGTH ERROR FRAME COUNTER (LSB)..288
REGISTER 0XB4: RXFP RECEIVE MINIMUM LENGTH ERROR FRAME COUNTER (MSB).288
REGISTER 0XB5: RXFP RECEIVE MAXIMUM LENGTH ERROR FRAME COUNTER (LSB).289
REGISTER 0XB6: RXFP RECEIVE MAXIMUM LENGTH ERROR FRAME COUNTER (MSB)289
REGISTER 0XC0: TXFP INTERRUPT ENABLE/STATUS.....................................................290
REGISTER 0XC1: TXFP CONFIGURATION........................................................................292
REGISTER 0XC2: TXFP CONTROL ...................................................................................294
REGISTER 0XC3: TXFP TRANSMIT PACKET AVAILABLE LOW WATER MARK...................296
REGISTER 0XC4: TXFP TRANSMIT PACKET AVAILABLE HIGH WATER MARK ..................297
REGISTER 0XC5: TXFP TRANSMIT BYTE COUNTER (LSB)..............................................298
REGISTER 0XC6: TXFP TRANSMIT BYTE COUNTER.......................................................298
REGISTER 0XC7: TXFP TRANSMIT BYTE COUNTER.......................................................298
REGISTER 0XC8: TXFP TRANSMIT BYTE COUNTER (MSB).............................................299
REGISTER 0XC9: TXFP TRANSMIT FRAME COUNTER (LSB)...........................................300
REGISTER 0XCA: TXFP TRANSMIT FRAME COUNTER....................................................300
REGISTER 0XCB: TXFP TRANSMIT FRAME COUNTER (MSB)..........................................301
REGISTER 0XCC: TXFP TRANSMIT USER ABORTED FRAME COUNTER (LSB) ...............302
REGISTER 0XCD: TXFP TRANSMIT USER ABORTED FRAME COUNTER (MSB)...............302
REGISTER 0XCE: TXFP TRANSMIT FIFO ERROR ABORTED FRAME COUNTER (LSB) ....303
REGISTER 0XCF: TXFP TRANSMIT FIFO ERROR ABORTED FRAME COUNTER (MSB)....303
REGISTER 0XD0: WANS CONFIGURATION......................................................................305
REGISTER 0XD1: WANS INTERRUPT & STATUS .............................................................306
REGISTER 0XD2: WANS PHASE WORD [7:0]...................................................................307
REGISTER 0XD3: WANS PHASE WORD [15:8] .................................................................307
REGISTER 0XD4: WANS PHASE WORD [23:16] ...............................................................307
REGISTER 0XD5: WANS PHASE WORD [30:24] ...............................................................308
REGISTER 0XD9: WANS REFERENCE PERIOD [7:0] .......................................................309
REGISTER 0XDA: WANS REFERENCE PERIOD [15:8] .....................................................309
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SATURN USER NETWORK INTERFACE (155-TETRA)
REGISTER 0XDB: WANS PHASE COUNTER PERIOD[7:0]................................................310
REGISTER 0XDC: WANS PHASE COUNTER PERIOD[15:8]..............................................310
REGISTER 0XDD: WANS PHASE AVERAGE PERIOD [3:0] ............................................... 311
REGISTER 0XE0: RASE INTERRUPT ENABLE..................................................................312
REGISTER 0XE1: RASE INTERRUPT STATUS ..................................................................313
REGISTER 0XE2: RASE CONFIGURATION/CONTROL......................................................315
REGISTER 0XE3: RASE SF ACCUMULATION PERIOD......................................................318
REGISTER 0XE4: RASE SF ACCUMULATION PERIOD......................................................318
REGISTER 0XE5: RASE SF ACCUMULATION PERIOD......................................................319
REGISTER 0XE6: RASE SF SATURATION THRESHOLD ...................................................320
REGISTER 0XE7: RASE SF SATURATION THRESHOLD ...................................................320
REGISTER 0XE8: RASE SF DECLARING THRESHOLD.....................................................321
REGISTER 0XE9: RASE SF DECLARING THRESHOLD.....................................................321
REGISTER 0XEA: RASE SF CLEARING THRESHOLD.......................................................322
REGISTER 0XEB: RASE SF CLEARING THRESHOLD.......................................................322
REGISTER 0XEC: RASE SD ACCUMULATION PERIOD.....................................................323
REGISTER 0XED: RASE SD ACCUMULATION PERIOD.....................................................323
REGISTER 0XEE: RASE SD ACCUMULATION PERIOD.....................................................324
REGISTER 0XEF: RASE SD SATURATION THRESHOLD...................................................325
REGISTER 0XF0: RASE SD SATURATION THRESHOLD ...................................................325
REGISTER 0XF1: RASE SD DECLARING THRESHOLD.....................................................326
REGISTER 0XF2: RASE SD DECLARING THRESHOLD.....................................................326
REGISTER 0XF3: RASE SD CLEARING THRESHOLD .......................................................327
REGISTER 0XF4: RASE SD CLEARING THRESHOLD .......................................................327
REGISTER 0XF5: RASE RECEIVE K1 ...............................................................................328
REGISTER 0XF6: RASE RECEIVE K2 ...............................................................................329
REGISTER 0XF7: RASE RECEIVE Z1/S1...........................................................................330
REGISTER 0X400: MASTER TEST....................................................................................332
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SATURN USER NETWORK INTERFACE (155-TETRA)
LIST OF FIGURES
FIGURE 1: TYPICAL STS-3C (STM-1) ATM SWITCH PORT APPLICATION.......................... 13
FIGURE 2: TYPICAL STS-3C (STM-1) PACKER OVER SONET/SDH (PPP) APPLICATION... 15
FIGURE 3: TYPICAL STS-3C (STM-1) JITTER TOLERANCE............................................... 62
FIGURE 4: POINTER INTERPRETATION STATE DIAGRAM................................................ 69
FIGURE 5: CELL DELINEATION STATE DIAGRAM............................................................. 74
FIGURE 6: HCS VERIFICATION STATE DIAGRAM............................................................. 76
FIGURE 7: PACKET OVER SONET/SDH FRAME FORMAT................................................. 78
FIGURE 8: CRC DECODER............................................................................................... 79
FIGURE 9: PACKET OVER SONET/SDH FRAME FORMAT................................................. 87
FIGURE 10: CRC GENERATOR......................................................................................... 88
FIGURE 11 : PRE-MATURE RPA ASSERTION TIMING ........................................................ 94
FIGURE 12. PHASE COMPARATOR BLOCK DIAGRAM ...................................................... 97
FIGURE 13. PHASE AVERAGER BLOCK DIAGRAM............................................................ 98
FIGURE 14: INPUT OBSERVATION CELL (IN_CELL).........................................................342
FIGURE 15: OUTPUT CELL (OUT_CELL)..........................................................................342
FIGURE 16: BIDIRECTIONAL CELL (IO_CELL) .................................................................343
FIGURE 17: LAYOUT OF OUTPUT ENABLE AND BIDIRECTIONAL CELLS ........................343
FIGURE 18: ATM MAPPING INTO THE STS-3C (STM-1) SPE.............................................344
FIGURE 19: POS MAPPING INTO THE STS-3C (STM-1) SPE ............................................346
FIGURE 20: STS-3C (STM-1) OVERHEAD........................................................................348
FIGURE 21: 16-BIT WIDE, 27 WORD ATM CELL STRUCTURE ...........................................357
FIGURE 22: PACKET DATA STRUCTURE .........................................................................358
FIGURE 23: CONCEPTUAL CLOCKING STRUCTURE ......................................................360
FIGURE 24: LINE LOOPBACK MODE ...............................................................................363
FIGURE 25: SERIAL DIAGNOSTIC LOOPBACK MODE .....................................................365
FIGURE 26: PARALLEL DIAGNOSTIC LOOPBACK MODE ................................................367
FIGURE 27: BOUNDARY SCAN ARCHITECTURE .............................................................369
FIGURE 28: TAP CONTROLLER FINITE STATE MACHINE ................................................371
FIGURE 29: WAN MODE ANALOG POWER PIN PASSIVE-FILTERING WITH 3.3V SUPPLY 376
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FIGURE 30: WAN MODE ANALOG POWER FILTERS WITH 3.3V SUPPLY (1).....................379
FIGURE 31: LAN MODE ANALOG POWER FILTERS WITH 3.3V SUPPLY (2)......................380
FIGURE 32: POWER SEQUENCING CIRCUIT ..................................................................382
FIGURE 33: INTERFACING TO ECL OR PECL ...................................................................383
FIGURE 34: CLOCK RECOVERY EXTERNAL COMPONENTS............................................385
FIGURE 35: MULTI-PHY POLLING AND ADDRESSING TRANSMIT CELL INTERFACE.......388
FIGURE 36: MULTI-PHY POLLING AND ADDRESSING RECEIVE CELL INTERFACE .........389
FIGURE 37: TRANSMIT POS SYSTEM INTERFACE TIMING .............................................391
FIGURE 38: RECEIVE POS SYSTEM INTERFACE .............................................................393
FIGURE 39: TRANSPORT OVERHEAD DATA LINK CLOCK AND DATA EXTRACTION........394
FIGURE 40: TRANSPORT OVERHEAD DATA LINK CLOCK AND DATA INSERTION...........395
FIGURE 41: MICROPROCESSOR INTERFACE READ TIMING ..........................................401
FIGURE 42: MICROPROCESSOR INTERFACE WRITE TIMING.........................................403
FIGURE 43: RSTB TIMING DIAGRAM...............................................................................404
FIGURE 44: TRANSMIT ATM SYSTEM INTERFACE TIMING DIAGRAM .............................406
FIGURE 45: RECEIVE ATM SYSTEM INTERFACE TIMING DIAGRAM ...............................408
FIGURE 46: TRANSMIT POS SYSTEM INTERFACE TIMING .............................................410
FIGURE 47: RECEIVE POS SYSTEM INTERFACE TIMING ...............................................413
FIGURE 48: SECTION DCC TIMING DIAGRAM.................................................................414
FIGURE 49: LINE DCC TIMING DIAGRAM ........................................................................415
FIGURE 50: TRANSMIT AND RECEIVE FRAME PULSES..................................................416
FIGURE 51: LINE SIDE TRANSMIT TIMING DIAGRAM (TXC_OE=1)..................................417
FIGURE 52: JTAG PORT INTERFACE TIMING ..................................................................418
FIGURE 53:- MECHANICAL DRAWING 304 PIN SUPER BALL GRID ARRAY (SBGA)..........422
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SATURN USER NETWORK INTERFACE (155-TETRA)
LIST OF TABLES
TABLE 1: POINTER INTERPRETER EVENT (INDICATIONS) DESCRIPTION........................ 69
TABLE 2: POINTER INTERPRETER TRANSITION DESCRIPTION...................................... 71
TABLE 3: BYTE DESTUFFING ........................................................................................... 78
TABLE 4: BYTE STUFFING................................................................................................ 88
TABLE 5: OBR MISMATCH MECHANISM........................................................................... 91
TABLE 6: REGISTER MEMORY MAP.................................................................................. 99
TABLE 8: TFPO CHANNEL SELECTION............................................................................. 111
TABLE 9: RECEIVE INITIATION LEVEL VALUES ................................................................279
TABLE 10: TRANSMIT INITIATION LEVEL VALUES............................................................294
TABLE 11: INTER PACKET GAPING VALUES.....................................................................295
TABLE 12: TEST MODE REGISTER MEMORY MAP...........................................................331
TABLE 13: INSTRUCTION REGISTER (LENGTH - 3 BITS).................................................334
TABLE 14: IDENTIFICATION REGISTER (LENGTH – 32 BITS)..........................................334
TABLE 15: S/UNI-TETRA BOUNDARY SCAN REGISTER (LENGTH – 155 BITS) ................334
TABLE 16: S/UNI-QUAD BOUNDARY SCAN REGISTER (LENGTH – 114 BITS)...................338
TABLE 17: RECOMMENDED BERM SETTINGS ................................................................359
TABLE 18 – SETTINGS FOR SONET OR SDH APPLICATIONS...........................................387
TABLE 19: ABSOLUTE MAXIMUM RATINGS.....................................................................396
TABLE 20: D.C CHARACTERISTICS .................................................................................397
TABLE 21: MICROPROCESSOR INTERFACE READ ACCESS (FIGURE 41) ......................400
TABLE 22: MICROPROCESSOR INTERFACE WRITE ACCESS (FIGURE 42).....................402
TABLE 23: RSTB TIMING (FIGURE 43) .............................................................................404
TABLE 24: TRANSMIT ATM SYSTEM INTERFACE TIMING (FIGURE 44) ...........................405
TABLE 25: RECEIVE ATM SYSTEM INTERFACE TIMING (FIGURE 45)..............................407
TABLE 26: TRANSMIT POS SYSTEM INTERFACE TIMING (FIGURE 46) ...........................409
TABLE 27: RECEIVE POS SYSTEM INTERFACE TIMING (FIGURE 47) ............................. 411
TABLE 28: SECTION DCC TIMING (FIGURE 48)...............................................................414
TABLE 29: LINE DCC TIMING (FIGURE 49).......................................................................415
TABLE 30: TRANSMIT AND RECEIVE FRAME PULSE TIMING (FIGURE 50) .....................416
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TABLE 31: LINE SIDE TRANSMIT TIMIGN (TXC_OE=1 ONLY) (FIGURE 51) .....................417
TABLE 32: JTAG PORT INTERFACE (FIGURE 52).............................................................417
TABLE 33: ORDERING INFORMATION.............................................................................420
TABLE 34: THERMAL INFORMATION ................................................................................420
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1
1.1
ISSUE 7
SATURN USER NETWORK INTERFACE (155-TETRA)
FEATURES
General
•
Single chip QUAD ATM User-Network Interface operating at 155.52 Mbit/s.
•
Implements the ATM Forum User Network Interface Specification and the
ATM physical layer for Broadband ISDN according to CCITT
Recommendation I.432.
•
Implements the Point-to-Point Protocol (PPP) over SONET/SDH specification
according to RFC 1619/1662 of the PPP Working Group of the Internet
Engineering Task Force (IETF).
•
Processes duplex 155.52 Mbit/s STS-3c (STM-1) data streams with on-chip
clock and data recovery and clock synthesis.
•
Exceeds Bellcore GR-253-CORE jitter tolerance and intrinsic jitter criteria.
•
Exceeds Bellcore GR-253-CORE (1995 Issue) jitter transfer and phase
variation criteria.
•
Provides control circuitry required to exceed Bellcore GR-253-CORE WAN
clocking requirements related to wander transfer, holdover and long term
stability when using an external VCXO.
•
Fully implements the ATM Forum’s Utopia Level 2 Specification with MultiPHY addressing and parity support.
•
Implements the POS-PHY 16-bit System Interface for Packet over
SONET/SDH (POS) applications. This system interface is similar to Utopia
Level 2, but adapted to packet transfer. Both byte-level and packet-level
transfer modes are supported.
•
Provides a standard 5 signal IEEE 1149.1 JTAG test port for boundary scan
board test purposes.
•
Provides a generic 8-bit microprocessor bus interface for configuration,
control, and status monitoring.
•
Low power 3.3V CMOS with PECL and TTL compatible inputs and
CMOS/TTL outputs, with 5V tolerance inputs (system side interface is 3.3V
only).
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ISSUE 7
SATURN USER NETWORK INTERFACE (155-TETRA)
•
Industrial temperature range (-40°C to +85°C).
•
304 pin Super BGA package.
The SONET Receiver
•
Provides a serial interface at 155.52 Mbit/s.
•
Recovers the clock and data.
•
Frames to and de-scrambles the recovered stream.
•
Detects signal degrade (SD) and signal fail (SF) threshold crossing alarms
based on received B2 errors.
•
Captures and debounces the synchronization status (S1) byte in a readable
register.
•
Filters and captures the automatic protection switch channel (K1, K2) bytes in
readable registers and detects APS byte failure.
•
Counts received section BIP-8 (B1) errors, received line BIP-24 (B2) errors,
line far end block errors (FEBE), received path BIP-8 (B3) errors and path far
end block errors (FEBE).
•
Detects loss of signal (LOS), out of frame (OOF), loss of frame (LOF), line
alarm indication signal (AIS), line remote defect indication (LRDI), loss of
pointer (LOP), path alarm indication signal (AIS), path remote defect
indication (PRDI) and path extended remote defect indicator (PERDI).
•
Extracts the section and line data communication channels (D1-D3 and D412) as selected in internal register banks and serializes them at 192 Kbit/s
(D1-D3) and 576 Kbit/s (D4-D12) for optional external processing.
•
Extracts the 16 or 64 byte section trace (J0) sequence and the 16 or 64 byte
path trace (J1) sequence into internal register banks.
•
Interprets the received payload pointer (H1, H2) and extracts the STS-3c
(STM-1) synchronous payload envelope and path overhead.
•
Provides individual divide by 8 recovered clocks (19.44 MHz) for each
channel.
•
Provides individual 8KHz receive frame pulses for each channel.
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1.4
ISSUE 7
SATURN USER NETWORK INTERFACE (155-TETRA)
The Receive ATM Processor
•
Extracts ATM cells from the received STS-3c (STM-1) synchronous payload
envelope using ATM cell delineation.
•
Provides ATM cell payload de-scrambling.
•
Performs header check sequence (HCS) error detection and correction, and
idle/unassigned cell filtering.
•
Detects Out of Cell Delineation (OCD) and Loss of Cell Delineation (LCD).
•
Counts number of received cells, idle cells, errored cells and dropped cells.
•
Provides a synchronous 8-bit wide, four cell FIFO buffer.
The Receive POS Processor
•
Generic design that supports packet based link layer protocols, like PPP,
HDLC and Frame Relay.
•
Performs self synchronous POS data de-scrambling on SPE payload (x43+1
polynomial).
•
Performs flag sequence detection and terminates the received POS frames.
•
Performs frame check sequence (FCS) validation. The POS processor
supports the validation of both CRC-CCITT and CRC-32 frame check
sequences.
•
Performs Control Escape de-stuffing.
•
Checks for packet abort sequence.
•
Checks for octet aligned packet lengths and for minimum and maximum
packet lengths. Automatically deletes short packets (software configurable),
and marks those exceeding the maximum length as errored.
•
Provides a synchronous 256 byte FIFO buffer accessed through a 16-bit data
bus on the POS-PHY System Interface.
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1.6
ISSUE 7
SATURN USER NETWORK INTERFACE (155-TETRA)
The SONET Transmitter
•
Synthesizes the 155.52 MHz transmit clock from a 19.44 MHz reference.
•
Provides a differential TTL serial interface (can be adapted to PECL levels) at
155.52 Mbit/s with both line rate data (TXD+/-) and clock (TXC+/-).
•
Provides a single transmit frame pulse input across the four channels to align
the transport frames to a system reference.
•
Provides a single transmit byte clock (divide by eight of the synthesized line
rate clock) to provide a timing reference for the transmit outputs.
•
Optionally inserts register programmable APS (K1, K2) and synchronization
status (S1) bytes.
•
Optionally inserts path alarm indication signal (PAIS), path remote defect
indication (PRDI), line alarm indication signal (LAIS) and line remote defect
indication (LRDI).
•
Inserts path BIP-8 codes (B3), path far end block error (G1) indications, line
BIP-24 codes (B2), line far end block error (M1) indications, and section BIP-8
codes (B1) to allow performance monitoring at the far end.
•
Optionally inserts the section and line data communication channels (D1-D3
or D4-12) via a 192 kbit/s (D1-D3) and 576 kbit/s (D4-D12) serial stream.
•
Optionally inserts the 16 or 64 byte section trace (J0) sequence and the 16 or
64 byte path trace (J1) sequence from internal register banks.
•
Scrambles the transmitted STS-3c (STM-1) stream and inserts the framing
bytes (A1,A2).
•
Inserts ATM cells or POS frames into the transmitted STS-3c (STM-1)
synchronous payload envelope.
The Transmit ATM Processor
•
Provides idle/unassigned cell insertion.
•
Provides HCS generation/insertion, and ATM cell payload scrambling.
•
Counts number of transmitted and idle cells.
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•
1.7
ISSUE 7
SATURN USER NETWORK INTERFACE (155-TETRA)
Provides a synchronous 8-bit wide, four cell FIFO buffer.
The Transmit POS Processor
•
Generic design that supports any packet based link layer protocol, like PPP,
HDLC and Frame Relay.
•
Performs self synchronous POS data scrambling (X 43 + 1 polynomial).
•
Encapsulates packets within a POS frame.
•
Performs flag sequence insertion.
•
Performs byte stuffing for transparency processing.
•
Performs frame check sequence generation. The POS processor supports
the generation of both CRC-CCITT and CRC-32 frame check sequences.
•
Aborts packets under the direction of the host or when the FIFO underflows.
•
Provides a synchronous 256 byte FIFO buffer accessed through the16-bit
data bus on the POS-PHY System Interface.
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2
ISSUE 7
SATURN USER NETWORK INTERFACE (155-TETRA)
APPLICATIONS
•
WAN and edge ATM switches.
•
LAN switches and hubs.
•
Packet switches and hubs.
•
Layer 3 switches.
•
Multiservice switches (FR, ATM, IP, etc..).
•
Gigabit and Terabit routers.
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ISSUE 7
SATURN USER NETWORK INTERFACE (155-TETRA)
REFERENCES
•
Bell Communications Research - GR-253-CORE “SONET Transport Systems:
Common Generic Criteria”, Issue 2, December 1995.
•
Bell Communications Research - GR-436-CORE “Digital Network
Synchronization Plan”, Issue 1 Revision 1, June 1996..
•
ITU-T Recommendation G.703 - "Physical/Electrical Characteristics of
Hierarchical Digital Interfaces", 1991.
•
ITU-T Recommendation G.704 - "General Aspects of Digital Transmission
Systems; Terminal Equipment - Synchronous Frame Structures Used At 1544,
6312, 2048, 8488 and 44 736 kbit/s Hierarchical Levels", July, 1995.
•
ITU, Recommendation G.707 - "Network Node Interface For The
Synchronous Digital Hierarchy", 1996.
•
ITU Recommendation G781, “Structure of Recommendations on Equipment
for the Synchronous Design Hierarchy (SDH)”, January 1994.
•
ITU, Recommendation G.783 - "Characteristics of Synchronous Digital
Hierarchy (SDH) Equipment Functional Blocks", 1996.
•
ITU Recommendation I.432, “ISDN User Network Interfaces”, March 93.
•
ATM Forum - ATM User-Network Interface Specification, V3.1, October, 1995.
•
ATM Forum - “UTOPIA, An ATM PHY Interface Specification, Level 2, Version
1”, June, 1995.
•
IETF Network Working Group – RFC-1619 “Point to Point Protocol (PPP) over
SONET/SDH Specification”, May 1994.
•
IETF Network Working Group - RFC-1661 “The Point to Point Protocol
(PPP)”, July 1994.
•
IETF Network Working Group - RFC-1662 “PPP in HDLC like framing”, July
1994.
•
PMC-971147 “Saturn Compliant Interface for Packet over SONET Physical
Layer and Link Layer Devices, Level 2”, Issue 3, February 1998.
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•
ISSUE 7
SATURN USER NETWORK INTERFACE (155-TETRA)
PMC-950820 “SONET/SDH Bit Error Threshold Monitoring Application Note”,
Issue 2, September 1998.
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ISSUE 7
SATURN USER NETWORK INTERFACE (155-TETRA)
DEFINITIONS
The following table defines the abbreviations for the S/UNI-TETRA.
AIS
Alarm Indication Signal
APS
Automatic Protection Switching
ASSP
Application Specific Standard Product
ATM
Asynchronous Transfer Mode
BER
Bit Error Rate
BIP
Byte Interleaved Parity
CBI
Common Bus Interface
CMOS
Complementary Metal Oxide Semiconductor
CRC
Cyclic Redundancy Check
CRSI
CRU and Serial-In Parallel-Out
CRU
Clock Recovery Unit
CSPI
CSU and Parallel-In Serial-Out
CSU
Clock Synthesis Unit
DCC
Data Communication Channel
ECL
Emitter Controlled Logic
ERDI
Enhanced Remote Defect Indication
ESD
Electrostatic Discharge
FCS
Frame Check Sequence
FEBE
Far-End Block Error
FIFO
First-In First-Out
GFC
Generic Flow Control
HCS
Header Check Sequence
HDLC
High-level Data Link Layer
LAN
Local Area Network
LCD
Loss of Cell Delineation
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
9
PMC-Sierra, Inc.
PM5351 S/UNI-TETRA
S/UNI-TETRA
DATASHEET
PMC-1971240
ISSUE 7
SATURN USER NETWORK INTERFACE (155-TETRA)
LOF
Loss of Frame
LOH
Line Overhead
LOP
Loss of Pointer
LOS
Loss of Signal
NC
No Connect, indicates an unused pin
NDF
New Data Flag
NNI
Network-Network Interface
ODL
Optical Data Link
OOF
Out of Frame
PECL
Pseudo-ECL
PLL
Phase-Locked Loop
POS
Packet Over SONET
PPP
Point-to-Point Protocol
PSL
Path Signal Label
PSLM
Path Signal Label Mismatch
RASE
Receive APS, Synchronization Extractor and Bit
Error Monitor
RDI
Remote Defect Indication
RLOP
Receive Line Overhead Processor
RPOP
Receive Path Overhead Processor
RSOP
Receive Section Overhead Processor
RXCP
Receive ATM Cell Processor
RXFP
Receive POS Frame Processor
SBGA
Super Ball Grid Array
SD
Signal Degrade
SDH
Synchronous Digital Hierarchy
SF
Signal Fail
SOH
Section Overhead
SONET
Synchronous Optical Network
SPE
Synchronous Payload Envelope
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
10
PMC-Sierra, Inc.
PM5351 S/UNI-TETRA
S/UNI-TETRA
DATASHEET
PMC-1971240
ISSUE 7
SATURN USER NETWORK INTERFACE (155-TETRA)
SPTB
SONET/SDH Path Trace Buffer
SSTB
SONET/SDH Section Trace Buffer
TIM
Trace Identifier Mismatch
TIU
Trace Identifier Unstable
TLOP
Transmit Line Overhead Processor
TOH
Transport Overhead
TPOP
Transmit Path Overhead Processor
TSB
Telecom System Block
TSOP
Transmit Section Overhead Processor
TXCP
Transmit ATM Cell Processor
TXFP
Transmit POS Frame Processor
UI
Unit Interval
UNI
User-Network Interface
VCI
Virtual Connection Indicator
VCXO
Voltage Controlled Oscillator
VPI
Virtual Path Indicator
WAN
Wide Area Network
XOR
Exclusive OR logic operator
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
11
PMC-Sierra, Inc.
PM5351 S/UNI-TETRA
S/UNI-TETRA
DATASHEET
PMC-1971240
5
ISSUE 7
SATURN USER NETWORK INTERFACE (155-TETRA)
APPLICATION EXAMPLES
The PM5351 S/UNI-TETRA is intended for use in equipment implementing
Asynchronous Transfer Mode (ATM) User-Network Interfaces (UNI), ATM
Network-Network Interfaces (NNI), as well as Packet over SONET/SDH (POS)
interfaces. The POS interface can be used to support several packet based
protocols, including the Point-to-Point Protocol (PPP). The S/UNI-TETRA may
find application at either end of switch-to-switch links or switch-to-terminal links,
both in public network (WAN) and private network (LAN) situations. The S/UNITETRA provides a comprehensive feature set as well as provides circuitry to
enable full compliance to WAN synchronization requirements. The S/UNI-TETRA
performs the mapping of either ATM cells or POS frames into the SONET/SDH
STS-3c (STM-1) synchronous payload envelope (SPE) and processes applicable
SONET/SDH section, line and path overhead.
In a typical STS-3c (STM-1) ATM application, the S/UNI-TETRA performs clock
and data recovery for the receive direction and clock synthesis for the transmit
direction of the line interface. On the system side, the S/UNI-TETRA interfaces
directly with ATM layer processors and switching or adaptation functions using a
Utopia Level 2 compliant synchronous FIFO style interface. The initial
configuration and ongoing control and monitoring of the S/UNI-TETRA are
normally provided via a generic microprocessor interface. This application is
shown in Figure 1.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
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PMC-Sierra, Inc.
PM5351 S/UNI-TETRA
S/UNI-TETRA
DATASHEET
PMC-1971240
ISSUE 7
SATURN USER NETWORK INTERFACE (155-TETRA)
Figure 1: Typical STS-3c (STM-1) ATM Switch Port Application
ATM Layer Device
TxCl k
TxEnb
TxAddr<4 :0>
TxCla v
TxSOC
TxPrty
TxD ata<15:0>
RxClk
RxEnb
RxAddr<4:0>
RxClav
R xSOC
RxPrty
RxData<15:0>
Utopia Level 2
Interface
PM5351
S/UNI-155-TETRA
RX D1+/SD1
TXD1 +/-
Optical
Transceiver
TFCL K
TENB
TAD R[4 :0]
TC A
TSOC
TPRTY
TD AT[15:0]
RFCLK
RENB
RADR[4:0]
RC A
RSOC
RPRTY
RDAT[15:0 ]
RX D2+/SD2
TXD2 +/-
RX D3+/SD3
TXD3 +/-
RX D4+/SD4
TXD4 +/-
Optical
Transceiver
Optical
Transceiver
Optical
Transceiver
In a typical Packet over SONET/SDH application, using the PPP protocol, the
S/UNI-TETRA performs clock and data recovery for the receive direction and
clock synthesis for the transmit direction of the line interface. On the system side,
the S/UNI-TETRA interfaces directly with a PPP link layer processors using a 256
byte synchronous FIFO interface over which packets are transferred. The initial
configuration and ongoing control and monitoring of the S/UNI-TETRA are
normally provided via a generic microprocessor interface. This application is
shown in Figure 2.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
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PMC-Sierra, Inc.
PM5351 S/UNI-TETRA
S/UNI-TETRA
DATASHEET
PMC-1971240
ISSUE 7
SATURN USER NETWORK INTERFACE (155-TETRA)
Figure 2: Typical STS-3c (STM-1) Packer over SONET/SDH (PPP)
Application
Link Layer Device
TFCLK
TENB
TADR[4:0]
STPA
DTPA[4:1]
TSOP
TPRTY
TDAT[15:0]
TMOD
TEOP
TERR
RFCLK
RENB
RADR[4:0]
DRPA[4: 1]
RVAL
RSOP
RPRTY
RDAT[15:0]
RMOD
REOP
RERR
PM5351
S/UNI-155-TETRA
TFCLK
TENB
TADR[4:0]
STPA
DTPA[4: 1]
TSOP
TPRTY
TDAT[15:0]
TMOD
TEOP
TERR
RFCLK
RXD1+/SD1
TXD 1+/-
Optical
Transceiver
RXD2+/SD2
TXD 2+/-
Optical
Transceiver
RXD3+/SD3
TXD 3+/-
RXD4+/SD4
TXD 4+/-
Optical
Transceiver
Optical
Transceiver
RENB
RADR[4:0]
DRPA[4:1]
RVAL
RSOP
RPRTY
RDAT[15:0]
RMOD
REOP
RERR
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
14
Line
DCC
Extract
RLDCLK1-4
RLD1-4
Section
DCC
Extract
Rx
APS,
Sync,
BERM
Rx
Line O/H
Processor
Rx
Section O/H
Processor
Section
Trace
Buffer
Rx
Path O/H
Processor
Path
Trace
Buffer
Rx
ATM Cell
processor
Rx
POS F rame
Processor
Utopia / POS-PHY
System Inte rface
Microprocess or
I/F
STPA
TMOD
TERR
TEOP
DTCA[4:1]/DTPA[4:1]
TDAT[15 :0]
TPRTY
TSOC/TSOP
T C A/PTPA
TADR[4:0]
TENB
TFCLK
PHY_OEN
RFCLK
RENB
RADR[4:0]
RCA/PRPA
RSOC/RSOP
RPRTY
RDAT[15:0]
DRCA[4:1]/DRP[4:1]
REOP
RERR
RMOD
RVAL
ISSUE 7
CP1-4
CN1-4
Rx Line
I/F
TCLK
TFPO
TFPI
RXD1-4 +
RXD1-4 SD1-4
TSDCLK1-4
TSD1-4
Tx
POS F rame
Processor
TDI
REFCLK
Tx
Path O/H
Processor
TDO
Tx
Line O/H
Processor
TMS
Tx
Section O/H
Processor
Tx
ATM Cell
Processor
TCK
ATB0-3
Tx Line
I/F
Line
DCC
Insert
PMC-1971240
TXD1-4 +
TXD1-4 -
TXC1-4 +
TXC1-4 -
TLDCLK1-4
TLD1-4
Section
DCC
Insert
6
JTAG Test
Access Port
PMC-Sierra, Inc.
S/UNI-TETRA
PM5351 S/UNI-TETRA
DATASHEET
SATURN USER NETWORK INTERFACE (155-TETRA)
BLOCK DIAGRAM
TRSTB
INTB
RSTB
RDB
WRB
CSB
ALE
A[10:0]
D[7:0]
RSDCLK1-4
RSD1-4
RCLK1-4
RFPO1-4
RALRM1-4
WAN
Synchronization
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
15
PMC-Sierra, Inc.
PM5351 S/UNI-TETRA
S/UNI-TETRA
DATASHEET
PMC-1971240
7
ISSUE 7
SATURN USER NETWORK INTERFACE (155-TETRA)
DESCRIPTION
The PM5351 S/UNI-TETRA SATURN User Network Interface is a monolithic
integrated circuit that implements four channel SONET/SDH processing, ATM
mapping and Packet over SONET/SDH mapping functions at the STS-3c (STM1) 155.52 Mbit/s rate.
The S/UNI-TETRA receives SONET/SDH streams using a bit serial interface,
recovers the clock and data and processes section, line, and path overhead. It
performs framing (A1, A2), de-scrambling, detects alarm conditions, and monitors
section, line, and path bit interleaved parity (B1, B2, B3), accumulating error
counts at each level for performance monitoring purposes. Line and path far end
block error indications (M1, G1) are also accumulated. The S/UNI-TETRA
interprets the received payload pointers (H1, H2) and extracts the synchronous
payload envelope which carries the received ATM cell or POS packet payload.
When used to implement an ATM UNI or NNI, the S/UNI-TETRA frames to the
ATM payload using cell delineation. HCS error correction is provided.
Idle/unassigned cells may be dropped according to a programmable filter. Cells
are also dropped upon detection of an uncorrectable header check sequence
error. The ATM cell payloads are descrambled. The ATM cells that are passed
are written to a four cell FIFO buffer. The received cells are read from the FIFO
using a 16-bit wide Utopia level 2 compliant datapath interface. Counts of
received ATM cell headers that are errored and uncorrectable and also those that
are errored and correctable are accumulated independently for performance
monitoring purposes.
When used to implement packet transmission over a SONET/SDH link, the
S/UNI-TETRA extracts Packet over SONET/SDH (POS) frames from the
SONET/SDH synchronous payload envelope. Frames are verified for correct
construction and size. The Control Escape characters are removed. The error
check sequence is optionally verified for correctness and the extracted packets
are placed in a receive FIFO. The received packets are read from the FIFO
through the system side interface. Valid and errored packet counts are provided
for performance monitoring. The S/UNI-TETRA Packet over SONET/SDH
implementation is flexible enough to support several link layer protocols,
including HDLC, PPP and Frame Relay.
The S/UNI-TETRA transmits SONET/SDH streams using a bit serial interface
and formats section, line, and path overhead appropriately. It synthesizes the
transmit clock from a lower frequency reference and performs framing pattern
insertion (A1, A2), scrambling, alarm signal insertion, and creates section, line,
and path bit interleaved parity (B1, B2, B3) as required to allow performance
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
16
PMC-Sierra, Inc.
PM5351 S/UNI-TETRA
S/UNI-TETRA
DATASHEET
PMC-1971240
ISSUE 7
SATURN USER NETWORK INTERFACE (155-TETRA)
monitoring at the far end. Line and path far end block error indications (M1, G1)
are also inserted. The S/UNI-TETRA generates the payload pointer (H1, H2) and
inserts the synchronous payload envelope which carries the ATM cell or POS
frame payload. Line and Section DCC ports are available for direct insertion and
extraction of DCC data. The S/UNI-TETRA also supports the insertion of a large
variety of errors into the transmit stream, such as framing pattern errors, bit
interleaved parity errors, and illegal pointers, which are useful for system
diagnostics and tester applications.
When used to implement an ATM UNI or NNI, ATM cells are written to an internal
four cell FIFO using a 16-bit wide Utopia Level 2 datapath interface.
Idle/unassigned cells are automatically inserted when the internal FIFO contains
less than one cell. The S/UNI-TETRA provides generation of the header check
sequence and scrambles the payload of the ATM cells. Each of these transmit
ATM cell processing functions can be enabled or bypassed.
When used to implement a Packet over SONET/SDH link, the S/UNI-TETRA
inserts POS frames into the SONET/SDH synchronous payload envelope.
Packets to be transmitted are written into a 256-byte FIFO through the POS-PHY
System Interface. POS Frames are built by inserting the flags, Control Escape
characters and the FCS fields. Either the CRC-CCITT or CRC-32 can be
computed and added to the frame. Several counters are provided for
performance monitoring.
No line rate clocks are required directly by the S/UNI-TETRA as it synthesizes
the transmit clock and recovers the receive clock using a 19.44 MHz reference
clock. The S/UNI-TETRA outputs a differential TTL (externally coverted to PECL)
line data (TXD+/-). Optionally, the S/UNI-TETRA can also output a differential
TTL (externally converted to PECL) transmit line rate clock (TXC+/-). The S/UNITETRA also provides a WAN Synchronization controller that can be used to
control an external VCXO in order to fully meet Bellcore GR-253-CORE jitter,
wander, holdover and stability requirements.
The S/UNI-TETRA is configured, controlled and monitored via a generic 8-bit
microprocessor bus interface. The S/UNI-TETRA also provides a standard 5
signal IEEE 1149.1 JTAG test port for boundary scan board test purposes.
The S/UNI-TETRA is implemented in low power, +3.3 Volt, CMOS technology. It
has TTL and pseudo-ECL (PECL) compatible inputs and TTL/CMOS compatible
outputs and is packaged in a 304 pin SBGA package.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
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PMC-Sierra, Inc.
PM5351 S/UNI-TETRA
S/UNI-TETRA
DATASHEET
PMC-1971240
8
ISSUE 7
SATURN USER NETWORK INTERFACE (155-TETRA)
PIN DIAGRAM
The S/UNI-TETRA is available in a 304 pin SBGA package having a body size of
31 mm by 31 mm and a ball pitch of 1.27 mm.
23
22
21
A
VDD
VSS
TDAT[12]
B
VSS
VDD
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
TDAT[15] PHY_OEN
VSS
D[2]
VSS
A[0]
A[3]
A[7]
VSS
A[10]
WRB
TDO
VSS
N/C
VSS
N/C
VSS
TDAT[13]
STPA
N/C
D[1]
D[4]
D[6]
A[2]
A[6]
A[9]
CSB
RSTB
TMS
TCK
N/C
N/C
QAVS_5
C1+
3
RAVD1_B RAVS1_B
VSS
2
1
VSS
VDD
VDD
VSS
C
TDAT[7]
VSS
VDD
TDAT[10]
TDAT[14]
TEOP
BIAS
D[3]
D[5]
A[1]
A[5]
A[8]
ALE
INTB
TRSTB
N/C
N/C
QAVD_5
C1-
RAVD1_C
VDD
VSS
TXD1P
D
TDAT[4]
TDAT[6]
TDAT[9]
VDD
TDAT[11]
VDD
TERR
D[0]
VDD
D[7]
A[4]
VDD
RDB
TDI
VDD
N/C
N/C
VDD
RAVS1_C
VDD
TXC1P
TXD1N
RX1-
E
TDAT[0]
TDAT[3]
TDAT[5]
TDAT[8]
TXC1N
SD1
RX1+
TXD2P
F
VSS
TMOD
TDAT[2]
VDD
VDD
RAVS1_A
TXD2N
VSS
G
TADR[0]
TADR[2]
TADR[4]
TDAT[1]
RAVD1_A
TXC2P
RX2-
RX2+
H
VSS
TPRTY
TADR[1]
TADR[3]
TXC2N
J
TCA /
PTPA
TENB
TSOC /
TSOP
VDD
VDD
K
DTCA[3] /
DTPA[3]
DTCA[4] /
DTPA[4]
BIAS
TFCLK
L
REOP
RERR
DTCA[1] / DTCA[2] /
DTPA[1] DTPA[2]
M
VSS
RVAL
DRCA[4] /
DRPA[4]
N
DRCA[3] / DRCA[2] / DRCA[1] /
DRPA[3]
DRPA[2] DRPA[1]
RAVS2_A RAVD2_A
SD2
RAVS2_C RAVS2_B
VSS
N/C
RAVD2_C
C2+
C2-
RAVD2_B TAVD1_A TAVS1_A TAVD1_B
VDD
VDD
RCA /
PRPA
TAVS1_B RAVD3_B
RAVD3_C RAVS3_B
VSS
C3+
C3-
P
RSOC /
RSOP
RENB
RFCLK
RADR[3]
ATB2
ATB1
ATB0
RAVS3_C
R
RADR[4]
RADR[2]
RADR[1]
VDD
VDD
TXC3N
TXC3P
ATB3
T
VSS
RADR[0]
RPRTY
RDAT[13]
RAVS3_A
N/C
TXD3P
VSS
RDAT[9]
TXC4P
SD3
RAVD3_A
TXD3N
U
RDAT[15] RDAT[14] RDAT[12]
V
VSS
RDAT[11]
RDAT[8]
VDD
VDD
TXC4N
RX3-
VSS
W
RDAT[10]
RDAT[7]
RDAT[5]
RDAT[2]
RAVS4_A
SD4
TXD4P
RX3+
Y
RDAT[6]
RDAT[4]
RDAT[1]
VDD
AA
RDAT[3]
VSS
VDD
RDAT[0]
AB
VSS
VDD
VSS
AC
VDD
VSS
RMOD
VDD
RSDCLK2 RLDCLK3
RLDCLK2
RSD2
VDD
RALRM3
RCLK2
VDD
TLDCLK3
TSDCLK2
VDD
TSD3
TFPI
VDD
RAVS4_C
VDD
RAVD4_A
RX4-
TXD4N
RSD3
RLD4
RLD1
RALRM1
RCLK1
RFPO1
TLDCLK4
TSDCLK4
TLD4
TLD2
TSD2
QAVD_1
C4-
RAVD4_C
VDD
VSS
RX4+
C4+
VSS
VDD
VSS
VSS
VDD
RSDCLK3 RLDCLK4
RSD4
RSD1
RLD2
RALRM4
RCLK4
RFPO4
RFPO2
TFPO
TLDCLK1 TSDCLK1
TLD3
TSD4
TSD1
QAVS_1
RSDCLK4 RSDCLK1 RLDCLK1
VSS
RLD3
VSS
RALRM2
RCLK3
RFPO3
VSS
TCLK
TLDCLK2 TSDCLK3
VSS
TLD1
VSS
REFCLK RAVD4_B RAVS4_B
BOTTOM VIEW
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
18
PMC-Sierra, Inc.
PM5351 S/UNI-TETRA
S/UNI-TETRA
DATASHEET
PMC-1971240
9
9.1
ISSUE 7
SATURN USER NETWORK INTERFACE (155-TETRA)
PIN DESCRIPTION
Line Side Interface Signals
Pin Name
Type
REFCLK
Input
Pin
No.
AC5
Function
The reference clock input (REFCLK) must provide a
jitter-free 19.44 MHz reference clock. It is used as
the reference clock by both clock recovery and
clock synthesis circuits.
When the WAN Synchronization controller is used,
REFCLK is supplied using a VCXO. In this
application, the transmit direction can be looped
timed to any of the line receivers in order to meet
wander transfer and holdover requirements.
This pin is shared by all channels.
RXD1+
RXD1RXD2+
RXD2RXD3+
RXD3RXD4+
RXD4-
Differential E2
PECL
D1
inputs
G1
G2
W1
V2
AA1
Y2
The receive differential data inputs (RXD+, RXD-)
contain the NRZ bit serial receive stream. The
receive clock is recovered from the RXD+/- bit
stream. Please refer to the Operation section for a
discussion of PECL interfacing issues and for the
PECL voltage level selection through PECLV for 5V
ODL interface.
This pin is available independently for each
channel.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
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PMC-Sierra, Inc.
PM5351 S/UNI-TETRA
S/UNI-TETRA
DATASHEET
PMC-1971240
Pin Name
SD1
SD2
SD3
SD4
ISSUE 7
Type
SingleEnded
PECL
Input
Pin
No.
E3
J3
U3
W3
SATURN USER NETWORK INTERFACE (155-TETRA)
Function
The Signal Detect pin (SD) indicates the presence
of valid receive signal power from the Optical
Physical Medium Dependent Device. A PECL high
indicates the presence of valid data and a PECL low
indicates a loss of signal. It is mandatory that SD be
terminated into the equivalent network that RXD+/is terminated into.
SD input is compared to the common mode of the
receive data line (RXD+/-). It is also assumed SD
will be driven by a low impedance PECL voltage
source coming from the same source as the RXD+/signals
This pin is available independently for each
channel.
RCLK1
RCLK2
RCLK3
RCLK4
Output
AA13
Y13
AC14
AB14
The receive byte clock (RCLK) provides a timing
reference for the S/UNI-TETRA receive outputs.
RCLK is a divide by eight of the recovered line rate
clock (19.44 MHz).
This pin is available independently for each
channel.
RFPO1
RFPO2
RFPO3
RFPO4
Output
AA12
AB12
AC13
AB13
The Receive Frame Pulse Output (RFPO), when
the framing alignment is found (the OOF register bit
is logic zero), is an 8 kHz signal derived from the
receive line clock. RFPO pulses high for one RCLK
cycle every 2430 RCLK cycles (STS-3c (STM-1)).
RFPO is updated on the rising edge of RCLK.
This pin is available independently for each
channel.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
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PMC-Sierra, Inc.
PM5351 S/UNI-TETRA
S/UNI-TETRA
DATASHEET
PMC-1971240
ISSUE 7
Pin Name
Type
Pin
No.
RALRM1
RALRM2
RALRM3
RALRM4
Output
AA14
AC15
Y14
AB15
SATURN USER NETWORK INTERFACE (155-TETRA)
Function
The Receive Alarm (RALRM) output indicates the
state of the receive framing. RALRM is low if no
receive alarms are active. RALRM is high if line AIS
(LAIS), path AIS (PAIS), line RDI (LRDI), path RDI
(PRDI), enhanced path RDI (PERDI), loss of signal
(LOS), loss of frame (LOF), out of frame (OOF),
loss of pointer (LOP), loss of cell delineation (LCD),
signal fail BER (SFBER), signal degrade BER
(SDBER), path trace identification mismatch (TIM),
path signal label mismatch (PSLM) is detected in
the associated channel. Each alarm can be
individually enabled using bits in the S/UNI-TETRA
Channel Alarm Control registers #1 and #2.
RALRM is updated on the rising edge of RCLK.
This pin is available independently for each
channel.
TXD1+
TXD1TXD2+
TXD2TXD3+
TXD3TXD4+
TXD4-
Differential C1
TTL output D2
E1
(externally F2
converted T2
to PECL) U1
W2
Y1
The transmit differential data outputs (TXD+, TXD-)
contain the 155.52 Mbit/s transmit stream.
TXC1+
TXC1TXC2+
TXC2TXC3+
TXC3TXC4+
TXC4-
Differential D3
TTL output E4
G3
(externally H4
converted R2
to PECL) R3
U4
V3
The transmit differential clock outputs (TXC+, TXC-)
contain the 155.52 Mbit/s transmit clock.
This pin is available independently for each
channel.
TXC+/- must be enabled by setting the TXC_OE
register bit to logic one. Enabling the transmit line
clocks significantly increases the device power
consumption and will likely require airflow. Most
optic modules don’t require TXC+/-.
TXD+/- is updated on the falling edge of TXC+/-.
This pin is available independently for each
channel.
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ISSUE 7
Pin Name
Type
TFPI
Input
Pin
No.
Y7
SATURN USER NETWORK INTERFACE (155-TETRA)
Function
The active high framing position (TFPI) signal is an
8 kHz timing marker for the transmitter. TFPI is used
to align the SONET/SDH transport frame generated
by the S/UNI-TETRA device to a system reference.
TFPI is internally used to aligh a master frame pulse
counter. When TFPI is not used, this counter is freerunning.
TFPI should be brought high for a single TCLK
period every 2430 (STS-3c (STM-1)) TCLK cycles,
or a multiple thereof. TFPI shall be tied low if such
synchronization is not required. TFPI cannot be
used as an input to a loop-timed channel. For TFPI
to operate correctly it is required that the
TCLK/TFPO output be configured to output the
CSU byte clock.
The TFPI_EN register bits allow to individually
configure each channel to use the global framing
pulse counter and TFPI for framing alignment.
TFPI is sampled on the rising edge of TCLK, but
only when the TTSEL register bit is set to logic zero.
When TTSEL is set to logic one, TFPI is unused.
This pin is shared by all channels.
TCLK
Output
AC11
The transmit byte clock (TCLK) output provides a
timing reference for the S/UNI-TETRA self-timed
channels. TCLK always provide a divide by eight of
the synthesized line rate clock and thus has a
nominal frequency of 19.44 MHz. TFPI is sampled
on the rising edge of TCLK. TCLK does not apply to
internally loop-timed channels, in which case the
channel’s RCLK provides transmit timing
information.
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Pin Name
TFPO
9.2
ISSUE 7
Type
Pin
No.
Output
AB11
SATURN USER NETWORK INTERFACE (155-TETRA)
Function
The Transmit Frame Pulse Output (TFPO) pulses
high for one TCLK cycle every 2430 TCLK cycles
and provides an 8 KHz timing reference. TFPO can
be assigned to any of the four channels using
TFPO_CH[1:0] configuration register bits, with the
restriction that the selected channel must be selftimed (not in loop-timed or line-loopback modes).
TFPO is updated on the rising edge of TCLK.
Section and Line Status DCC Signals
Pin Name
RSD1
RSD2
RSD3
RSD4
RSDCLK1
RSDCLK2
RSDCLK3
RSDCLK4
Type
Output
Output
Pin
No.
Function
AB17
Y16
AA17
AB18
The receive section DCC (RSD) signal contains the
section data communications channel (D1-D3)
AC20
AA19
AB20
AC21
The receive section DCC clock (RSDCLK) is used
to clock out the section DCC.
This pin is available independently for each
channel.
RSDCLK is a 192 kHz clock used to update the
RSD output. RSDCLK is generated by gapping a
216 kHz clock.
This pin is available independently for each
channel.
TSD1
TSD2
TSD3
TSD4
Input
AB6
AA7
Y8
AB7
The transmit section DCC (TSD) signal contains the
section data communications channel (D1-D3).
TSD is sampled on the rising edge of TSDCLK.
This pin is available independently for each
channel.
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Pin Name
TSDCLK1
TSDCLK2
TSDCLK3
TSDCLK4
ISSUE 7
Type
Output
SATURN USER NETWORK INTERFACE (155-TETRA)
Pin
No.
Function
AB9
Y10
AC9
AA10
The transmit section DCC clock (TSDCLK) is used
to clock in the section DCC.
TSDCLK is a 192 kHz clock used to sample the
TSD input. TSDCLK is generated by gapping a 216
kHz clock.
This pin is available independently for each
channel.
RLD1
RLD2
RLD3
RLD4
RLDCLK1
RLDCLK2
RLDCLK3
RLDCLK4
Output
Output
AA15
AB16
AC17
AA16
The receive line DCC (RLD) signal contains the line
data communications channel (D4-D12).
AC19
Y17
AA18
AB19
The receive line DCC clock (RLDCLK) is used to
clock out the line DCC.
This pin is available independently for each
channel.
RLDCLK is a 576 kHz clock used to update the
RLD output. RLDCLK is generated by gapping a
2.16 MHz clock.
This pin is available independently for each
channel.
TLD1
TLD2
TLD3
TLD4
Input
AC7
AA8
AB8
AA9
The transmit line DCC (TLD) signal contains the line
data communications channel (D4-D12).
TLD is sampled on the rising edge of TLDCLK.
This pin is available independently for each
channel.
TLDCLK1
TLDCLK2
TLDCLK3
TLDCLK4
Output
AB10
AC10
Y11
AA11
The transmit line DCC clock (TLDCLK) is used to
clock in the line DCC.
TLDCLK is a 576 kHz clock used to sample the TLD
input. TLDCLK is generated by gapping a 2.16
MHz clock.
This pin is available independently for each
channel.
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PM5351 S/UNI-TETRA
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DATASHEET
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9.3
ISSUE 7
SATURN USER NETWORK INTERFACE (155-TETRA)
ATM (UTOPIA) and Packet over SONET (POS-PHY) System Interface
Pin Name
Type
Pin
No.
Function
TDAT[15]
TDAT[14]
TDAT[13]
TDAT[12]
TDAT[11]
TDAT[10]
TDAT[9]
TDAT[8]
TDAT[7]
TDAT[6]
TDAT[5]
TDAT[4]
TDAT[3]
TDAT[2]
TDAT[1]
TDAT[0]
Input
A20
C19
B20
A21
D19
C20
D21
E20
C23
D22
E21
D23
E22
F21
G20
E23
UTOPIA Transmit Cell Data Bus (TDAT[15:0]).
A20
C19
B20
A21
D19
C20
D21
E20
C23
D22
E21
D23
E22
F21
G20
E23
POS-PHY Transmit Packet Data Bus (TDAT[15:0]).
TDAT[15]
TDAT[14]
TDAT[13]
TDAT[12]
TDAT[11]
TDAT[10]
TDAT[9]
TDAT[8]
TDAT[7]
TDAT[6]
TDAT[5]
TDAT[4]
TDAT[3]
TDAT[2]
TDAT[1]
TDAT[0]
(ATM)
Input
(POS)
This data bus carries the ATM cell octets that are
written to the selected transmit FIFO. TDAT[15:0] is
considered valid only when TENB is simultaneously
asserted and the S/UNI-TETRA is selected via
TADR[4:0].
TDAT[15:0] is sampled on the rising edge of
TFCLK.
This data bus carries the POS packet octets that
are written to the selected transmit FIFO.
TDAT[15:0] is considered valid only when TENB is
simultaneously asserted and the S/UNI-TETRA is
selected via TADR[4:0].
TDAT[15:0] is sampled on the rising edge of
TFCLK.
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Pin Name
TPRTY
ISSUE 7
SATURN USER NETWORK INTERFACE (155-TETRA)
Type
Pin
No.
Function
Input
H22
UTOPIA Transmit bus parity (TPRTY) signal.
(ATM)
The transmit parity (TPRTY) signal indicates the
parity of the TDAT[15:0] bus. A parity error is
indicated by a status bit and a maskable interrupt.
Cells with parity errors are inserted in the transmit
stream, so the TPRTY input may be unused. Odd or
even parity selection is made independently for
each channel using the RXPTYP register bit.
TPRTY is considered valid only when TENB is
simultaneously asserted and the S/UNI-TETRA is
selected via TADR[4:0].
TPRTY is sampled on the rising edge of TFCLK.
TPRTY
Input
H22
(POS)
POS-PHY Transmit bus parity (TPRTY) signal.
The transmit parity (TPRTY) signal indicates the
parity of the TDAT[15:0] bus. A parity error is
indicated by a status bit and a maskable interrupt.
Packets with parity errors are inserted in the
transmit stream, so the TPRTY input may be
unused. Odd or even parity selection is made
independently for each channel using the RXPTYP
register bit. TPRTY is considered valid only when
TENB is simultaneously asserted and the
S/UNI-TETRA is selected via TADR[4:0].
TPRTY is sampled on the rising edge of TFCLK
TSOC
Input
(ATM)
J21
UTOPIA Transmit Start of Cell (TSOC) signal.
The transmit start of cell (TSOC) signal marks the
start of cell on the TDAT bus. When TSOC is high,
the first word of the cell structure is present on the
TDAT bus. It is not necessary for TSOC to be
present for each cell. An interrupt may be
generated if TSOC is high during any word other
than the first word of the cell structure.
TSOC is considered valid only when TENB is
simultaneously asserted and the S/UNI-TETRA is
selected via TADR[4:0].
TSOC is sampled on the rising edge of TFCLK.
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S/UNI-TETRA
DATASHEET
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Pin Name
TSOP
ISSUE 7
SATURN USER NETWORK INTERFACE (155-TETRA)
Type
Pin
No.
Function
Input
J21
POS-PHY Transmit Start of Packet (TSOP) signals.
(POS)
TSOP indicates the first word of a packet. TSOP is
required to be present at the beginning of every
packet for proper operation.
TSOP is considered valid only when TENB is
simultaneously asserted and the S/UNI-TETRA is
selected via TADR[4:0].
TSOP is sampled on the rising edge of TFCLK.
TENB
Input
(ATM)
J22
UTOPIA Transmit Multi-PHY Write Enable (TENB)
signal.
The TENB signal is an active low input which is
used along with the TADR[4:0] inputs to initiate
writes to the transmit FIFO’s.
TENB works as follows. When sampled high, no
write is performed, but the TADR[4:0] address is
latched to identify the transmit FIFO to be
accessed. When TENB is sampled low, the word on
the TDAT bus is written into the transmit FIFO that
is selected by the TADR[4:0] address bus. A
complete 53 octet cell must be written to the
transmit FIFO before it is inserted into the transmit
stream. Idle cells are inserted when a complete cell
is not available. While TENB is deasserted,
TADR[4:0] can be used for polling TCA.
TENB is sampled on the rising edge of TFCLK.
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Pin Name
TENB
ISSUE 7
SATURN USER NETWORK INTERFACE (155-TETRA)
Type
Pin
No.
Function
Input
J22
POS-PHY Transmit Multi-PHY Write Enable (TENB)
signal.
(POS)
The S/UNI-TETRA supports both byte-level and
packet-level transfer. Packet-level transfer operates
in a similar fashion to Utopia, with a selection phase
when TENB is deasserted and a transfer phase
when TENB is asserted. While TENB is asserted,
TADR[4:0] is exclusively used for polling PTPA and
the currently selected PHY status is provided on
STPA. While TENB is deasserted, TADR[4:0] can
be used for polling PTPA as well as selecting the
next PHY to transfer to. Byte level transfer works on
a cycle basis. When TENB is asserted, data is
transferred to the selected PHY. Nothing happens
when TENB is deasserted. Polling is not available
and packet availability is indicated by DTPA[4:1].
TENB is sampled on the rising edge of TFCLK.
TADR[4]
TADR[3]
TADR[2]
TADR[1]
TADR[0]
Input
(ATM)
G21
H20
G22
H21
G23
UTOPIA Transmit Write Address (TADR[4:0])
signals.
The TADR[4:0] bus is used to select the FIFO (and
hence port) that is written to using the TENB signal
and the FIFO's whose cell available signal is visible
on the TCA polling output.
Note that address 0x1F is the null-PHY address and
cannot be assigned to any port on the
S/UNI-TETRA.
TADR[4:0] is sampled on the rising edge of TFCLK.
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ISSUE 7
SATURN USER NETWORK INTERFACE (155-TETRA)
Pin Name
Type
Pin
No.
Function
TADR[4]
TADR[3]
TADR[2]
TADR[1]
TADR[0]
Input
G21
H20
G22
H21
G23
POS-PHY Transmit Write Address (TADR[4:0])
signals.
(POS)
The TADR[4:0] bus is used to select the FIFO (and
hence port) that is written to using the TENB signal.
In packet level transfer mode, TADR[4:0] is also
used for polling on PTPA.
Note that address 0x1F is the null-PHY address and
cannot be assigned to any port on the
S/UNI-TETRA.
TADR[4:0] is sampled on the rising edge of TFCLK.
TCA
Output
(ATM)
J23
UTOPIA Transmit multi-PHY Cell Available (TCA)
The TCA signal indicates when a cell is available in
the transmit FIFO for the port polled by TADR[4:0]
when TENB is asserted. When high, TCA indicates
that the corresponding transmit FIFO is not full and
a complete cell may be written. When TCA goes
low, it can be configured to indicate either that the
corresponding transmit FIFO is near full or that the
corresponding transmit FIFO is full. TCA will
transition low on the rising edge of TFCLK after the
Payload word 19 (TCALEVEL0=0) or 23
(TCALEVEL0=1) is sampled if the PHY being polled
is the same as the PHY in use. To reduce FIFO
latency, the FIFO depth at which TCA indicates "full"
can be set to one, two, three or four cells. Note that
regardless of what fill level TCA is set to indicate
"full" at, the transmit cell processor can store 4
complete cells.
TCA is tri-stated when either the null-PHY address
(0x1F) or an address not matching the address
space set by PHY_ADR[2:0] is latched from the
TADR[4:0] inputs when TENB is high.
TCA is updated on the rising edge of TFCLK.
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Pin Name
PTPA
ISSUE 7
Type
SATURN USER NETWORK INTERFACE (155-TETRA)
Pin
No.
Function
J23
POS-PHY Polled Transmit multi-PHY Packet
Available (PTPA).
PTPA transitions high when a programmable
minimum number of bytes is available in the polled
transmit FIFO (TPAHWM[7:0] register bits). Once
high, PTPA indicates that the transmit FIFO is not
full. When PTPA transitions low, it optionally
indicates that the transmit FIFO is full or near full
(TPALWM[7:0] register bits). PTPA allows to poll
the PHY address selected by TADR[4:0] when
TENB is asserted.
PTPA is tri-stated when either the null-PHY address
(0x1F) or an address not matching the address
space set by PHY_ADR[2:0] is latched from the
TADR[4:0] inputs when TENB is high.
PTPA is only available in POS-PHY packet-level
transfer mode, as selected by the POS_PLVL
register bit. PTPA is tristated in byte-level transfer
mode. PTPA is updated on the rising edge of
TFCLK.
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Pin Name
STPA
ISSUE 7
SATURN USER NETWORK INTERFACE (155-TETRA)
Type
Pin
No.
Function
Output
B19
POS-PHY Selected multi-PHY Transmit Packet
Available (STPA) signal.
(POS)
STPA transitions high when a predefined
(TPAHWM[7:0] register bits) minimum number of
bytes is available in the selected transmit FIFO (the
FIFO that data is written into). Once high, STPA
indicates that the transmit FIFO is not full. When
STPA transitions low, it optionally indicates that the
transmit FIFO is full or near full (TPALWM[7:0]
register bits). STPA always provide status
indication for the selected PHY in order to avoid
FIFO overflows while polling is performed.
The PHY Layer device shall tristate STPA when
TENB is deasserted. STPA shall also be tristated
when either the null-PHY address (0x1F) or an
address not matching the address space set by
PHY_ADR[2:0] is presented on the TADR[4:0]
signals when TENB is sampled high (deasserted
during the previous clock cycle).
STPA is only available in POS-PHY packet-level
transfer mode, as selected by the POS_PLVL
register bit. STPA is tristated in byte-level transfer
mode. STPA is updated on the rising edge of
TFCLK.
TFCLK
Input
K20
(ATM)
UTOPIA Transmit FIFO Write Clock (TFCLK).
This signal is used to write ATM cells to the four cell
transmit FIFOs.
TFCLK cycles at a 50 MHz or lower instantaneous
rate.
TFCLK
Input
(POS)
K20
POS-PHY Transmit FIFO Write Clock (TFCLK).
This signal is used to write packet octets into the
256 bytes packet FIFO’s.
TFCLK cycles at a 50 MHz or lower instantaneous
rate.
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Pin Name
DTCA[4]
DTCA[3]
DTCA[2]
DTCA[1]
ISSUE 7
SATURN USER NETWORK INTERFACE (155-TETRA)
Type
Pin
No.
Function
Output
K22
K23
L20
L21
UTOPIA Direct Transmit Cell Available (DTCA[4:1]).
(ATM)
These output signals provide direct status indication
of when a cell is available in the transmit FIFO for
the corresponding port. When high, DTCA indicates
that the corresponding transmit FIFO is not full and
a complete cell may be written. When DTCA goes
low, it can be configured to indicate either that the
corresponding transmit FIFO is near full or that the
corresponding transmit FIFO is full. DTCA will
transition low on the rising edge of TFCLK after the
Payload word 19 (TCALEVEL0=0) or 23
(TCALEVEL0=1) is sampled if the PHY being polled
is the same as the PHY in use. To reduce FIFO
latency, the FIFO depth at which DTCA indicates
"full" can be set to one, two, three or four cells.
Note that regardless of what fill level DTCA is set to
indicate "full" at, the transmit cell processor can
store 4 complete cells
DTCA[4:1] are updated on the rising edge of
TFCLK.
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S/UNI-TETRA
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Pin Name
DTPA[4]
DTPA[3]
DTPA[2]
DTPA[1]
ISSUE 7
Type
Output
(POS)
Pin
No.
K22
K23
L20
L21
SATURN USER NETWORK INTERFACE (155-TETRA)
Function
POS-PHY Direct Transmit Packet Available
(DTPA[4:1]).
These output signals provide direct status indication
of when some programmable number of bytes is
available in the transmit FIFO, for the corresponding
port. When transitioning high, DTPA indicates that
the transmit FIFO has enough room to store data.
The transition level is selected by the TXFP
Transmit Packet Available Low Water-mark
(TPALWM[7:0]) register. When DTPA transitions
low, it indicates that the transmit FIFO is either full
or near full as selected by the TXFP Transmit
Packet Available High Water-mark (TPAHWM[7:0])
register. This last option provides the Link Layer
system with some look ahead capability in order to
avoid FIFO overruns and smoothly transition
between PHY’s.
DTPA[4:1] are updated on the rising edge of
TFCLK.
TMOD
Input
(POS)
F22
POS-PHY Transmit Word Modulo (TMOD) signal.
TMOD indicates the size of the current word. TMOD
is only used during the last word transfer of a
packet, at the same time TEOP is asserted. During
a packet transfer every word must be complete
except the last word, which can be composed of 1
or 2 bytes. TMOD set high indicates a 1-byte word
(present on MSB’s, LSB’s are discarded) while
TMOD set low indicates a 2-byte word.
TMOD is considered valid only when TENB is
simultaneously asserted and the S/UNI-TETRA is
selected via TADR[4:0].
TMOD is sampled on the rising edge of TFCLK.
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Pin Name
TEOP
ISSUE 7
SATURN USER NETWORK INTERFACE (155-TETRA)
Type
Pin
No.
Function
Input
C18
POS-PHY Transmit End of Packet (TEOP).
(POS)
The active high TEOP signal marks the end of a
packet on the TDAT[15:0] bus. When TEOP is high,
the last word of the packet is present on the
TDAT[15:0] data bus and TMOD indicates how
many bytes this last word is composed of. It is legal
to set TSOP high at the same time TEOP is high.
This provides support for one or two byte packets,
as indicated by the value of TMOD.
TEOP is considered valid only when TENB is
simultaneously asserted and the S/UNI-TETRA is
selected via TADR[4:0].
TEOP is sampled on the rising edge of TFCLK.
TERR
Input
(POS)
D17
POS-PHY Transmit Error (TERR).
The transmit error indicator (TERR) is used to
indicate that the current packet must be aborted.
TERR should only be asserted during the last word
transfer of a packet. Packets marked with TERR will
be appended with the abort sequence (0x7D-0x7E)
when transmission.
TERR is considered valid only when TENB is
simultaneously asserted and the S/UNI-TETRA is
selected via TADR[4:0].
TERR is sampled on the rising edge of TFCLK.
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ISSUE 7
Pin Name
Type
RDAT[15]
RDAT[14]
RDAT[13]
RDAT[12]
RDAT[11]
RDAT[10]
RDAT[9]
RDAT[8]
RDAT[7]
RDAT[6]
RDAT[5]
RDAT[4]
RDAT[3]
RDAT[2]
RDAT[1]
RDAT[0]
Output
RDAT[15]
RDAT[14]
RDAT[13]
RDAT[12]
RDAT[11]
RDAT[10]
RDAT[9]
RDAT[8]
RDAT[7]
RDAT[6]
RDAT[5]
RDAT[4]
RDAT[3]
RDAT[2]
RDAT[1]
RDAT[0]
Output
(ATM)
(POS)
SATURN USER NETWORK INTERFACE (155-TETRA)
Pin
No.
Function
U23
U22
T20
U21
V22
W23
U20
V21
W22
Y23
W21
Y22
AA23
W20
Y21
AA20
UTOPIA Receive Cell Data Bus (RDAT[15:0]).
U23
U22
T20
U21
V22
W23
U20
V21
W22
Y23
W21
Y22
AA23
W20
Y21
AA20
POS-PHY Receive Packet Data Bus (RDAT[15:0]).
This data bus carries the ATM cells that are read
from the receive FIFO selected by RADR[4:0].
RDAT[15:0] is tri-stated when RENB is high.
RDAT[15:0] is tristated when RENB is high.
RDAT[15:0] is also tristated when either the nullPHY address (0x1F) or an address not matching
the address space is latched from the RADR[4:0]
inputs when RENB is high.
RDAT[15:0] is updated on the rising edge of
RFCLK.
This data bus carries the POS packet octets that
are read from the selected receive FIFO.
RDAT[15:0] is considered valid only when RVAL is
asserted.
RDAT[15:0] is tristated when RENB is high.
RDAT[15:0] is also tristated when either the nullPHY address (0x1F) or an address not matching
the address space is latched from the RADR[4:0]
inputs.
RDAT[15:0] is updated on the rising edge of
RFCLK.
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ISSUE 7
SATURN USER NETWORK INTERFACE (155-TETRA)
Pin Name
Type
Pin
No.
Function
RPRTY
Output
T21
UTOPIA Receive Parity (RPRTY).
(ATM)
The receive parity (RPRTY) signal indicates the
parity of the RDAT bus. RPRTY reflects the parity
of RDAT[15:0]. Odd or even parity selection is made
independently for every channel by using the
RXPTYP register bit (in ATM cell processors, the
four RXCP shall be programmed with the same
parity setting).RPRTY is tristated when RENB is
high. RPRTY is also tristated when either the nullPHY address (0x1F) or an address not matching
the address space is latched from the RADR[4:0]
inputs when RENB is high.
RPRTY is updated on the rising edge of RFCLK.
RPRTY
Output
T21
(POS)
POS-PHY Receive Parity (RPRTY).
The receive parity (RPRTY) signal indicates the
parity of the RDAT bus. Odd or even parity
selection is made independently for every channel
by using the RXPTYP register bit (in POS Frame
Processors; the four RXFP shall be programmed
with the same parity setting). RPRTY is tristated
when RENB is high. RPRTY is also tristated when
either the null-PHY address (0x1F) or an address
not matching the address space is latched from the
RADR[4:0] inputs.
RPRTY is updated on the rising edge of RFCLK.
RSOC
Output
(ATM)
P23
UTOPIA Receive Start of Cell (RSOC).
RSOC marks the start of cell on the RDAT bus.
RSOC is tristated when RENB is deasserted.
RSOC is also tristated when either the null-PHY
address (0x1F) or an address not matching the
address space is latched from the RADR[4:0] inputs
when RENB is high.
RSOC is sampled on the rising edge of RFCLK.
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Pin Name
RSOP
ISSUE 7
SATURN USER NETWORK INTERFACE (155-TETRA)
Type
Pin
No.
Function
Output
P23
POS-PHY Receive Start of Packet (RSOP).
(POS)
RSOP marks the first word of a packet transfer.
RSOP is tristated when RENB is deasserted. RSOP
is also tristated when either the null-PHY address
(0x1F) or an address not matching the address
space is latched from the RADR[4:0] inputs.
RSOP/RSOP is sampled on the rising edge of
RFCLK
RENB
Input
(ATM)
P22
UTOPIA Receive multi-PHY Read Enable (RENB).
The RENB signal is used to initiate reads from the
receive FIFO’s. RENB works as follows. When
RENB is sampled high, no read is performed and
RDAT[15:0], RPRTY and RSOC are tristated, and
the address on RADR[4:0] is latched to select the
device or port for the next FIFO access. When
RENB is sampled low, the word on the RDAT bus is
read from the selected receive FIFO.
RENB must operate in conjunction with RFCLK to
access the FIFO’s at a high enough rate to prevent
FIFO overflows. The system may de-assert RENB
at anytime it is unable to accept another byte.
RENB is sampled on the rising edge of RFCLK.
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Pin Name
RENB
ISSUE 7
SATURN USER NETWORK INTERFACE (155-TETRA)
Type
Pin
No.
Function
Input
P22
POS-PHY Receive multi-PHY Read Enable
(RENB).
(POS)
The S/UNI-TETRA supports both byte-level and
packet-level transfer. Packet-level transfer operates
as described above, with a selection phase when
RENB is deasserted and a transfer phase when
RENB is asserted. While RENB is asserted,
RADR[4:0] is exclusively used for polling RPA.
While RENB is deasserted, RADR[4:0] can be used
for polling RPA as well as selecting the next PHY to
transfer from. Byte level transfer works on a cycle
basis. When RENB is asserted data is transferred
from the selected PHY and RADR[4:0] is used to
select the PHY. Nothing happens when RENB is
deasserted. Polling is not possible; packet
availability is directly indicated by DRPA[4:1].
During a data transfer, RVAL shall be monitored
since it will indicate if the data is valid. Once RVAL
is deasserted, RENB or RADR[4:0] must be used to
select a new PHY for data transfer.
RENB must operate in conjunction with RFCLK to
access the FIFO’s at a high enough rate to prevent
FIFO overflows. The system may de-assert RENB
at anytime it is unable to accept another byte.
RENB is sampled on the rising edge of RFCLK.
RADR[4]
RADR[3]
RADR[2]
RADR[1]
RADR[0]
Input
(ATM)
R23
P20
R22
R21
T22
UTOPIA Receive Read Address (RADR[4:0]).
The RADR[4:] signal is used to select the FIFO (and
hence port) that is read from using the RENB signal
and the FIFO whose cell available signal is visible
on the RCA output.
Note that address 0x1F is the null-PHY address and
will not be identified to any port on the
S/UNI-TETRA.
RADR[4:0] is sampled on the rising edge of RFCLK.
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ISSUE 7
SATURN USER NETWORK INTERFACE (155-TETRA)
Pin Name
Type
Pin
No.
Function
RADR[4]
RADR[3]
RADR[2]
RADR[1]
RADR[0]
Input
R23
P20
R22
R21
T22
POS-PHY Receive Read Address (RADR[4:0]).
(POS)
The RADR[4:0] signal is used to select the FIFO
(and hence port) that is read from using the RENB
signal.
The RADR[4:0] bus is used to select the FIFO (and
hence port) that is written to using the TENB signal
and the FIFO's whose packet available signal is
visible on the PRPA polling output.
Note that address 0x1F is the null-PHY address and
will not be identified to any port on the
S/UNI-TETRA.
RADR[4:0] is sampled on the rising edge of RFCLK.
RCA
Output
(ATM)
N20
UTOPIA Receive multi-PHY Cell Available (RCA).
RCA indicates when a cell is available in the receive
FIFO for the port selected by RADR[4:0]. RCA can
be configured to be de-asserted when either zero or
four bytes remain in the selected/addressed FIFO.
RCA will thus transition low on the rising edge of
RFCLK after Payload word 24 (RCALEVEL0=1) or
19 (RCALEVEL0=0) is output if the PHY being
polled is the same as the PHY in use.
RCA is tristated when either the null-PHY address
(0x1F) or an address not matching the address
space is latched from the RADR[4:0] inputs when
RENB is high.
RCA is updated on the rising edge of RFCLK.
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Pin Name
PRPA
ISSUE 7
SATURN USER NETWORK INTERFACE (155-TETRA)
Type
Pin
No.
Function
Output
N20
POS-PHY Polled multi-PHY Receive Packet
Available (PRPA) signal.
(POS)
PRPA indicates when data is available in the polled
receive FIFO. When PRPA is high, the receive
FIFO has at least one end of packet or a predefined
number of bytes to be read (the number of bytes
might be user programmable). PRPA is low when
the receive FIFO fill level is below the assertion
threshold and the FIFO contains no end of packet.
PRPA allows to poll every PHY while transferring
data from the selected PHY.
PRPA is driven by a PHY layer device when its
address is polled on RADR[4:0]. A PHY layer device
shall tristate PRPA when either the null-PHY
address (0x1F) or an address not matching the
address range set by the PHY_ADR[2:0] register
bits is provided on RADR[4:0].
PRPA is only available in POS-PHY packet-level
transfer mode, as selected by the POS_PLVL
register bit. PRPA is tristated in byte-level transfer
mode. PRPA is updated on the rising edge of
RFCLK.
Note: In some conditions RPA can assert
prematurely. Refer to section 10.15.2.1.
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Pin Name
RVAL
ISSUE 7
SATURN USER NETWORK INTERFACE (155-TETRA)
Type
Pin
No.
Function
Output
M22
POS-PHY Receive Data Valid (RVAL).
(POS)
RVAL indicates the validity of the receive data
signals. When RVAL is high, the Receive signals
(RDAT, RSOP, REOP, RMOD, RPRTY and RERR)
are valid. When RVAL is low, all Receive signals are
invalid and must be disregarded. RVAL will
transition low on a FIFO empty condition or on an
end of packet. . No data will be removed from the
receive FIFO while RVAL is deasserted. Once
deasserted, RVAL will remain deasserted until the
current PHY is deselected.
RVAL allows to monitor the selected PHY during a
data transfer, while monitoring other PHY’s is done
using DRPA[4:1].
RVAL is tristated when RENB is deasserted. RVAL
is also tristated when either the null-PHY address
(0x1F) or an address not matching the PHY layer
device address is presented on the RADR[4:0]
signals.
RVAL is updated on the rising edge of RFCLK.
RFCLK
Input
P21
(ATM)
RFCLK
Input
(ATM)
UTOPIA Receive FIFO Read Clock (RFCLK).
RFCLK is used to read ATM cells from the receive
FIFO’s. RFCLK must cycle at a 50 MHz or lower
instantaneous rate, but at a high enough rate to
avoid FIFO overflows.
P21
POS-PHY Receive FIFO Read Clock (RFCLK).
This signal is used to read packets from the receive
FIFO’s. RFCLK must cycle at a 50 MHz or lower
instantaneous rate, but at a high enough rate to
avoid FIFO overflows.
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ISSUE 7
SATURN USER NETWORK INTERFACE (155-TETRA)
Pin Name
Type
Pin
No.
Function
DRCA[4]
DRCA[3]
DRCA[2]
DRCA[1]
Output
M21
N23
N22
N21
UTOPIA Direct Receive Cell Available (DRCA[4:1]).
(ATM)
These output signals provides direct status
indication of when a cell is available in the receive
FIFO for the corresponding port. DRCA can be
configured to be de-asserted when either zero or
four bytes remain in the selected/addressed FIFO.
DRCA will thus transition low on the rising edge of
RFCLK after Payload word 24 (RCALEVEL0=1) or
19 (RCALEVEL0=0) is output if the PHY being
polled is the same as the PHY in use.
DRCA[x] is updated on the rising edge of RFCLK.
DRPA[4]
DRPA[3]
DRPA[2]
DRPA[1]
Output
(POS)
M21
N23
N22
N21
POS-PHY Direct Receive Packet Available
(DRPA[4:1]).
DRPA[x] provides a direct status indication. DRPA
indicates when data is available in the receive
FIFO. When DRPA is high, the receive FIFO has at
least one end of packet or a programmable
minimum number of bytes to be read. DRPA is
otherwise low. The polarity of DRPA can be inverted
with the RPAINV register bit.
DRPA[x] is updated on the rising edge of RFCLK.
Note: In some conditions RPA can assert
prematurely. Refer to section 10.15.2.1.
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Pin Name
RMOD
ISSUE 7
SATURN USER NETWORK INTERFACE (155-TETRA)
Type
Pin
No.
Function
Output
Y19
POS-PHY Receive Modulo (RMOD).
(POS)
The RMOD signal indicates the number of bytes
carried by the RDAT[15:0] bus during the last word
of a packet transfer. During a packet transfer every
word must be complete except the last word which
can be composed of 1 or 2 bytes. RMOD set high
indicate a single byte word (present on MSB’s,
LSB’s are discarded) while RMOD set low indicates
a two byte word. RMOD is only used in POS mode.
RMOD is tristated when RENB is deasserted.
RMOD is also tristated when either the null-PHY
address (0x1F) or an address not matching the
address space set by PHY_ADR[2:0] is latched
from the RADR[4:0] inputs when RENB is high.
RMOD is updated on the rising edge of RFCLK.
REOP
Output
(POS)
L23
POS-PHY Receive End Of Packet (REOP).
The REOP signal marks the end of packet on the
RDAT[15:0] bus. When the RXFP-50 is selected,
REOP is set high to mark the last word of the
packet presented on the RDAT[15:0] bus. During
this same cycle RMOD is used to indicate if the last
word has 1 or 2 bytes. It is legal to set RSOP high
at the same time REOP is high. This provides
support for one or two bytes packets, as indicated
by the value of RMOD. REOP is only used in POS
mode.
REOP is tristated when RENB is deasserted. REOP
is also tristated when either the null-PHY address
(0x1F) or an address not matching the address
space is latched from the RADR[4:0] inputs when
RENB is high.
REOP is updated on the rising edge of RFCLK.
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Pin Name
RERR
ISSUE 7
SATURN USER NETWORK INTERFACE (155-TETRA)
Type
Pin
No.
Function
Output
L22
POS-PHY Receive Error (RERR).
(POS)
The RERR signal indicates that the current packet
is aborted. RERR can only be asserted during the
last word transfer, at the same time REOP is
asserted. RERR is only used in POS mode.
RERR is tristated when RENB is deasserted. RERR
is also tristated when either the null-PHY address
(0x1F) or an address not matching the address
space is latched from the RADR[4:0] inputs when
RENB is high.
RERR is updated on the rising edge of RFCLK.
PHY_OEN
Input
(ATM/
POS)
A19
The PHY Output Enable (PHY_OEN) signal
controls the operation of the system interface.
When set to logic zero, all System Interface outputs
are held tristate. When PHY_OEN is set to logic
one, the interface is enabled. PHY_OEN can be
overwritten by the PHY_EN Master System
Interface Configuration register bit. PHY_OEN and
PHY_EN are OR’ed together to enable the
interface.
When the S/UNI-TETRA is the only PHY layer
device on the bus, PHY_OEN can safely be tied to
logic one. When the S/UNI-TETRA shares the bus
with other devices, then PHY_OEN must be tied to
logic zero, and the PHY_EN register bit used to
enable the bus once its PHY_ADR[2:0] is
programmed in order to avoid conflicts.
The PHY Output Enable does not tristate the DTCA,
DTPA, DRCA, DRPA pins.
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9.4
ISSUE 7
SATURN USER NETWORK INTERFACE (155-TETRA)
Microprocessor Interface Signals
Pin Name
Type
Pin
No.
Function
CSB
Input
B11
The active-low chip select (CSB) signal is low
during S/UNI-TETRA register accesses.
If CSB is used, it must be held high while RSTB is
low to properly initialize the device. If CSB is not
required (i.e. register accesses are controlled using
the RDB and WRB signals only), CSB must be
connected to an inverted version of the RSTB input
to ensure proper device initialization.
RDB
Input
D11
The active-low read enable (RDB) signal is low
during S/UNI-TETRA register read accesses. The
S/UNI-TETRA drives the D[7:0] bus with the
contents of the addressed register while RDB and
CSB are low.
WRB
Input
A10
The active-low write strobe (WRB) signal is low
during a S/UNI-TETRA register write accesses. The
D[7:0] bus contents are clocked into the addressed
register on the rising WRB edge while CSB is low.
D[0]
D[1]
D[2]
D[3]
D[4]
D[5]
D[6]
D[7]
I/O
D16
B17
A17
C16
B16
C15
B15
D14
The bi-directional data bus D[7:0] is used during
S/UNI-TETRA register read and write accesses.
A[0]
A[1]
A[2]
A[3]
A[4]
A[5]
A[6]
A[7]
A[8]
A[9]
Input
A15
C14
B14
A14
D13
C13
B13
A13
C12
B12
The address bus A[9:0] selects specific registers
during S/UNI-TETRA register accesses.
Except for S/UNI-TETRA global registers, the A[9:8]
bits allow to select which channel is being
accessed. The A[7:0] bits allow to select which
register is being access within a given channel
address space.
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ISSUE 7
SATURN USER NETWORK INTERFACE (155-TETRA)
Pin Name
Type
Pin
No.
Function
A[10]/TRS
Input
A11
The test register select (TRS) signal selects
between normal and test mode register accesses.
TRS is high during test mode register accesses,
and is low during normal mode register accesses.
RSTB
Input
pull-up
B10
The active-low reset (RSTB) signal provides an
asynchronous S/UNI-TETRA reset. RSTB is a
Schmitt triggered input with an integral pull-up
resistor.
ALE
Input
pull-up
C11
The address latch enable (ALE) is active-high and
latches the address bus A[7:0] when low. When
ALE is high, the internal address latches are
transparent. It allows the S/UNI-TETRA to interface
to a multiplexed address/data bus. ALE has an
integral pull-up resistor.
INTB
Output
Opendrain
C10
The active-low interrupt (INTB) signal goes low
when a S/UNI-TETRA interrupt source is active and
that source is unmasked. The S/UNI-TETRA may
be enabled to report many alarms or events via
interrupts.
Examples of interrupt sources are loss of signal
(LOS), loss of frame (LOF), line AIS, line remote
defect indication (LRDI) detect, loss of pointer
(LOP), path AIS, path remote defect indication
detect and others.
INTB is tristated when the interrupt is acknowledged
via an appropriate register access. INTB is an open
drain output.
9.5
JTAG Test Access Port (TAP) Signals
Pin Name
Type
Pin
No.
Function
TCK
Input
B8
The test clock (TCK) signal provides timing for test
operations that are carried out using the IEEE
P1149.1 test access port.
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Pin Name
ISSUE 7
SATURN USER NETWORK INTERFACE (155-TETRA)
Type
Pin
No.
Function
TMS
Input
pull-up
B9
The test mode select (TMS) signal controls the test
operations that are carried out using the IEEE
P1149.1 test access port. TMS is sampled on the
rising edge of TCK. TMS has an integral pull-up
resistor.
TDI
Input
pull-up
D10
The test data input (TDI) signal carries test data into
the S/UNI-TETRA via the IEEE P1149.1 test access
port. TDI is sampled on the rising edge of TCK.
TDI has an integral pull-up resistor.
TDO
Tristate
A9
The test data output (TDO) signal carries test data
out of the S/UNI-TETRA via the IEEE P1149.1 test
access port. TDO is updated on the falling edge of
TCK. TDO is a tristate output which is inactive
except when scanning of data is in progress.
TRSTB
Input
pull-up
C9
The active-low test reset (TRSTB) signal provides
an asynchronous S/UNI-TETRA test access port
reset via the IEEE P1149.1 test access port.
TRSTB is a Schmitt triggered input with an integral
pull-up resistor.
Note that when not being used, TRSTB must be
connected to the RSTB input.
9.6
Analog Signals
Pin Name
CP1
CN1
CP2
CN2
CP3
CN3
CP4
CN4
Type
Pin
No.
Function
Analog
B4
C5
K2
K1
N2
N1
AB4
AA5
The analog CP and CN pins are provided for
applications that must meet SONET/SDH jitter
transfer specifications. A 220 nF X7R 10% ceramic
capacitor can be attached across CP and CN.
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Pin Name
ATB0
ATB1
ATB2
ATB3
9.7
ISSUE 7
Type
Pin
No.
Analog I/O P2
P3
P4
R1
SATURN USER NETWORK INTERFACE (155-TETRA)
Function
The Analog Test Bus (ATB). These pins are used for
manufacturing testing only and should be
connected ground.
Power and Ground
Pin Name
BIAS
Type
Pin
No.
Function
Bias
Voltage
K21
C17
I/O Bias (BIAS). When tied to +5V via a 1 KΩ
resistor, the BIAS input is used to bias the wells in
the input and I/O pads so that the pads can tolerate
5V on their inputs without forward biasing internal
ESD protection devices. When BIAS is tied to
+3.3V, the inputs and bi-directional inputs will only
tolerate 3.3V level inputs.
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ISSUE 7
SATURN USER NETWORK INTERFACE (155-TETRA)
Pin Name
Type
Pin
No.
Function
VDD
Power
A1
A23
B2
B22
C3
C21
D4
D6
D9
D12
D15
D18
D20
F4
F20
J4
J20
M4
M20
R4
R20
V4
V20
Y4
Y6
Y9
Y12
Y15
Y18
Y20
AA3
AA21
AB2
AB22
AC1
AC23
The digital power (VDD) pins should be connected
to a well-decoupled +3.3 V DC supply.
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Pin Name
VSS
ISSUE 7
Type
Ground
SATURN USER NETWORK INTERFACE (155-TETRA)
Pin
No.
Function
A2
A6
A8
A12
A16
A18
A22
B1
B3
B21
B23
C2
C22
F1
F23
H1
H23
M1
M23
T1
T23
V1
V23
AA2
AA22
AB1
AB3
AB21
AB23
AC2
AC6
AC8
AC12
AC16
AC18
AC22
The digital ground (VSS) pins should be connected
to ground.
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Pin Name
QAVD
ISSUE 7
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Type
Pin
No.
Function
Analog
Power
AA6
C6
QAVD1
QAVD2
The quiet analog power (QAVD) pins for the analog
core. QAVD should be connected to analog +3.3V
through a 100Ω resistor to avoid latchup during
power-up.
QAVS
Analog
Ground
AB5
B5
QAVS1
QAVS2
The quiet analog ground (QAVS) pins for the analog
core. QAVS should be connected to analog GND.
AVD
Analog
Power
G4
A4
C4
H2
L4
J1
U2
M2
N4
Y3
AC4
AA4
L3
L1
RAVD1_A - Channel #1 PECL Input Buffer
RAVD1_B - Channel #1 CRU
RAVD1_C - Channel #1 CRU
RAVD2_A - Channel #2 PECL Input Buffer
RAVD2_B - Channel #2 CRU
RAVD2_C - Channel #2 CRU
RAVD3_A - Channel #3 PECL Input Buffer
RAVD3_B - Channel #3 CRU
RAVD3_C - Channel #3 CRU
RAVD4_A - Channel #4 PECL Input Buffer
RAVD4_B - Channel #4 CRU
RAVD4_C - Channel #4 CRU
TAVD1_A - CSU
TAVD1_B - CSU
The analog power (AVD) pins for the analog core.
AVD should be connected to analog +3.3V.
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Pin Name
AVS
ISSUE 7
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Type
Pin
No.
Function
Analog
Ground
F3
A3
D5
H3
K3
K4
T4
N3
P1
W4
AC3
Y5
L2
M3
RAVS1_A - Channel #1 PECL Input Buffer
RAVS1_B - Channel #1 CRU
RAVS1_C - Channel #1 CRU
RAVS2_A - Channel #2 PECL Input Buffer
RAVS2_B - Channel #2 CRU
RAVS2_C - Channel #2 CRU
RAVS3_A - Channel #3 PECL Input Buffer
RAVS3_B - Channel #3 CRU
RAVS3_C - Channel #3 CRU
RAVS4_A - Channel #4 PECL Input Buffer
RAVS4_B - Channel #4 CRU
RAVS4_C - Channel #4 CRU
TAVS1_A - CSU
TAVS1_B - CSU
The analog ground (AVS) pins for the analog core.
AVS should be connected to analog GND.
Notes on Pin Description:
1. All S/UNI-TETRA inputs and bi-directionals present minimum capacitive
loading and operate at TTL logic levels except: the SD, RXD+ and RXDinputs which operate at pseudo-ECL (PECL) logic levels
2. The RDAT[15:0], RPRTY, RSOC, REOP, RMOD, RERR, RVAL, DRCA4-1,
RCA/PRPA, DTCA4-1, TCA/PRPA, STPA, TCLK and RCLK1-4 outputs have
a 4 mA DC drive capability. The TDO and INTB outputs have a 1 mA drive
capability. All the other outputs have a 2 mA DC drive capability. The TXD+
and TXD- outputs should be terminated in a passive network and interface at
PECL levels.
3. It is mandatory that every ground pin (VSS) be connected to the printed
circuit board ground plane to ensure a reliable device operation.
4. It is mandatory that every power pin (VDD) be connected to the printed circuit
board power plane to ensure a reliable device operation.
5. All analog power and ground can be sensitive to noise. They must be
isolated from the digital power and ground. Care must be taken to decouple
these pins from each other and all other analog power and ground pins.
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Power supply filtering recommendations are provided in the
OPERATION section of this document.
6. Due to ESD protection structures in the pads it is necessary to exercise
caution when powering a device up or down. ESD protection devices behave
as diodes between power supply pins and from I/O pins to power supply pins.
Under extreme conditions it is possible to blow these ESD protection devices
or trigger latch up. Please adhere to the recommended power supply
sequencing as described in the OPERATION section of this document.
7. If it is intended to substitute a S/UNI-TETRA in a S/UNI-QUAD socket,
special attention must be given to the NC pins. The requirement is that no
S/UNI-TETRA input pin is left floating when used in a S/UNI-QUAD socket.
Please refer to the relevant PMC-Sierra, Inc. application note.
8. Some device pins can be made 5V tolerant by connecting the BIAS pins to a
5V power supply, while some other pins are 3.3V only. In summary, the
system interface (ATM or POS) is 3.3V only while the microprocessor
interface, SONET and line interfaces are 5V tolerant.
3.3V only I/O’s:
RDAT[15:0], RSOC/RSOP, RPRTY, RENB, REOP, RMOD, RERR, RVAL,
TDAT[15:0], TSOC/TSOP, TPRTY, TENB, TEOP, TMOD, TERR,
RCA/RPA, DRCA4-1/DRPA4-1, TCA/PTPA, STPA, DTCA4-1/DTPA4-1,
RADR[5:0], TADR[5:0], PHY_OEN
5V tolerant I/O’s:
REFCLK, RXD
RCLK4-1, RFPO4-1, RALRM4-1,
TCLK, TFPO, TFPI,
RSD, RSDCLK, TSD, TSDCLK. RLD, RLDCLK, TLD, TLDCLK.,
D[7:0], A[10:0], WRB, RDB, CSB, RSTB, INTB, ALE,
TRSTB, TCK, TMS, TDI, TDO,
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10 FUNCTIONAL DESCRIPTION
10.1 Receive Line Interface (CRSI)
The Receive Line Interface allows to directly interface the S/UNI-TETRA with
optical modules (ODLs) or other medium interfaces. This block performs clock
and data recovery and performs serial to parallel conversion on the incoming
155.52 Mbit/s data stream.
10.1.1 Clock Recovery
The clock recovery unit recovers the clock from the incoming bit serial data
stream. The clock recovery unit is fully compliant with SONET and SDH jitter
tolerance requirements. The clock recovery unit utilizes a low frequency
reference clock to train and monitor its clock recovery PLL. Under loss of signal
conditions, the clock recovery unit continues to output a line rate clock that is
locked to this reference for keep alive purposes. The clock recovery unit utilizes
a reference clocks at 19.44 MHz. The clock recovery unit provides status bits
that indicate whether it is locked to data or the reference. The clock recovery unit
also supports diagnostic loopback and a loss of signal input that squelches
normal input data.
Initially, the PLL locks to the reference clock, REFCLK. When the frequency of
the recovered clock is within 488 ppm of the reference clock, the PLL attempts to
lock to the data. Once in data lock, the PLL reverts to the reference clock if no
data transitions occur in 80 bit periods or if the recovered clock drifts beyond 488
ppm of the reference clock.
When the transmit clock is derived from the recovered clock (loop timing), the
accuracy of the transmit clock is directly related to the REFCLK reference
accuracy in the case of a loss of signal condition. To meet the Bellcore GR-253CORE SONET Network Element free-run accuracy specification, the reference
must be within +/-20ppm. When used in LAN applications, the REFCLK
accuracy may be relaxed to +/-50ppm.
The loop filter transfer function is optimized to enable the PLL to track the jitter,
yet tolerate the minimum transition density expected in a received SONET/SDH
data signal. The total loop dynamics of the clock recovery PLL yield a jitter
tolerance that exceeds the minimum tolerance proposed for SONET equipment
by GR-253-CORE (Figure 3).
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Figure 3: Typical STS-3c (STM-1) Jitter Tolerance
100
10
GR-253-CORE
1
0.1
100
1000
10000
100000
Jitter Freq. (Hz)
1000000
10000000
Note that for frequencies below 300 Hz, the jitter tolerance is greater than 15
UIpp; 15 UIpp is the maximum jitter tolerance of the test equipment. Also note
that the dip in the tolerance curve between 300 Hz and 10 kHz is due to the
S/UNI-TETRA's internal clock difference detector: if the recovered clock d rifts
beyond 488 ppm of the reference, the PLL locks to the reference clock.
10.1.2 Serial to Parallel Converter
The Serial to Parallel Converter (SIPO) converts the received bit serial stream to
a byte serial stream. The SIPO searches for the SONET/SDH framing pattern
(A1, A2) in the receive stream, and performs serial to parallel conversion on octet
boundaries.
10.2 Receive Section Overhead Processor (RSOP)
The Receive Section Overhead Processor (RSOP) provides frame
synchronization, de-scrambling, section level alarm and performance monitoring.
In addition, it extracts the section data communication channel from the section
overhead and, if selected, provides it serially on output RSD.
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10.2.1 Framer
The Framer Block determines the in-frame/out-of-frame status of the receive
stream.
While in-frame, the framing bytes (A1, A2) in each frame are compared against
the expected pattern. Out-of-frame is declared when four consecutive frames
containing one or more framing pattern errors have been received.
While out-of-frame, the SIPO block monitors the receive stream for an
occurrence of the framing pattern. When a framing pattern is recognized, the
Framer block verifies that an error free framing pattern is present in the next
frame before declaring in-frame.
10.2.2 Descramble
The Descramble Block utilizes a frame synchronous descrambler to process the
receive stream. The generating polynomial is x7 + x6 + 1 and the sequence
length is 127. Details of the de-scrambling operation are provided in the
references. Note that the framing bytes (A1 and A2) and the trace/growth bytes
(J0/Z0) are not descrambled. A register bit is provided to disable the descrambling operation.
10.2.3 Data Link Extract
The Data Link Extract Block extracts the section data communication channel
(bytes D1, D2, and D3) from the STS-3c (STM-1) stream. The extracted bytes
are serialized and output on signal RSD at a nominal 192 kbit/s rate. Timing for
downstream processing of the data communication channel is provided by the
RSDCLK signal that is also output by the Data Link Extract Block. RSDCLK is
derived from a 216 kHz clock that is gapped to yield an average frequency of 192
kHz. RSD is updated with timing aligned to RSDCLK.
10.2.4 Error Monitor
The Error Monitor Block calculates the received section BIP-8 error detection
code (B1) based on the scrambled data of the complete STS-3c (STM-1) frame.
The section BIP -8 code is based on a bit interleaved parity calculation using even
parity. Details are provided in the references. The calculated BIP-8 code is
compared with the BIP -8 code extracted from the B1 byte of the following frame.
Differences indicate that a section level bit error has occurred. Up to 64000 (8 x
8000) bit errors can be detected per second. The Error Monitor Block
accumulates these section level bit errors in a 16-bit saturating counter that can
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be read via the microprocessor interface. Circuitry is provided to latch this
counter so that its value can be read while simultaneously resetting the internal
counter to 0 or 1, if appropriate, so that a new period of accumulation can begin
without loss of any events. It is intended that this counter be polled at least once
per second so as not to miss bit error events.
10.2.5 Loss of Signal
The Loss of Signal Block monitors the scrambled data of the receive stream for
the absence of 1's. When 20 ± 3 µs of all zeros patterns is detected, a loss of
signal (LOS) is declared. Loss of signal is cleared when two valid framing words
are detected and during the intervening time, no loss of signal condition is
detected. The LOS signal is optionally reported on the RALRM output pin when
enabled by the LOSEN Receive Alarm Control Register bit.
10.2.6 Loss of Frame
The Loss of Frame Block monitors the in-frame / out-of-frame status of the
Framer Block. A loss of frame (LOF) is declared when an out-of-frame (OOF)
condition persists for 3 ms. The LOF is cleared when an in-frame condition
persists for a period of 3 ms. To provide for intermittent out-of-frame (or in-frame)
conditions, the 3 ms timer is not reset to zero until an in-frame (or out-of-frame)
condition persists for 3 ms. The LOF and OOF signals are optionally reported
on the RALRM output pin when enabled by the LOFEB and OOFEN Receive
Alarm Control Register bits.
10.3 Receive Line Overhead Processor (RLOP)
The Receive Line Overhead Processor (RLOP) provides line level alarm and
performance monitoring. In addition, it extracts the line data communication
channel from the line overhead and, if selected, provides it serially on output
RLD.
10.3.1 Line RDI Detect
The Line RDI Detect Block detects the presence of Line Remote Defect
Indication (LRDI) in the receive stream. Line RDI is declared when a 110 binary
pattern is detected in bits 6, 7, and 8 of the K2 byte, for three or five consecutive
frames. Line RDI is removed when any pattern other than 110 is detected in bits
6, 7, and 8 of the K2 byte for three or five consecutive frames. The LRDI signal is
optionally reported on the RALRM output pin when enabled by the LRDIEN
Receive Alarm Control Register bit.
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10.3.2 Line AIS Detect
The Line AIS Block detects the presence of a Line Alarm Indication Signal (LAIS)
in the receive stream. Line AIS is declared when a 111 binary pattern is detected
in bits 6, 7, and 8 of the K2 byte, for three or five consecutive frames. Line AIS is
removed when any pattern other than 111 is detected in bits 6, 7, and 8 of the K2
byte for three or five consecutive frames. The LAIS signal is optionally reported
on the RALRM output pin when enabled by the LAISEN Receive Alarm Control
Register bit.
10.3.3 Data Link Extract Block
The Data Link Extract Block extracts the line data communication channel (bytes
D4 to D12) from the STS-3c (STM-1) stream. The extracted bytes are serialized
and output on the RLD output at a nominal 576 kbit/s rate. Timing for
downstream processing of the data communication channel is provided by the
RLDCLK output. RLDCLK is derived from a 2.16 MHz clock that is gapped to
yield an average frequency of 576 kHz.
10.3.4 Error Monitor Block
The Error Monitor Block calculates the received line BIP-8 error detection codes
based on the Line Overhead bytes and synchronous payload envelopes of the
STS-3c (STM-1) stream. The line BIP-8 code is a bit interleaved parity calculation
using even parity. Details are provided in the references. The calculated BIP-8
codes are compared with the BIP-8 codes extracted from the following frame.
Any differences indicate that a line layer bit error has occurred. Optionally the
RLOP can be configured to count a maximum of only one BIP error per frame.
This block also extracts the line FEBE code from the M1 byte . The FEBE code is
contained in bits 2 to 8 of the M1 byte, and represents the number of line BIP-8
errors that were detected in the last frame by the far end. The FEBE code value
has 25 legal values (0 to 24) for an STS-3c (STM-1) stream. Illegal values are
interpreted as zero errors.
The Error Monitor Block accumulates B2 error events and FEBE events in two 20
bit saturating counter that can be read via the microprocessor interface. The
contents of these counters may be transferred to internal holding registers by
writing to any one of the counter addresses, or by using the TIP register bit
feature. During a transfer, the counter value is latched and the counter is reset to
0 (or 1, if there is an outstanding event). Note, these counters should be polled at
least once per second to avoid saturation.
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The B2 error events counters optionally can be configured to accumulate only
"word" errors. A B2 word error is defined as the occurrence of one or more B2 bit
error events during a frame. The B2 error counter is incremented by one for each
frame in which a B2 word error occurs.
In addition the FEBE events counters optionally can be configured to accumulate
only "word" events. In STS-3c (STM-1) framing a FEBE word event is defined as
the occurrence of one or more FEBE bit events during a frame. The FEBE event
counter is incremented by one for each frame in which a FEBE event occurs.
10.4 The Receive APS, Synchronization Extractor and Bit Error Monitor (RASE)
10.4.1 Automatic Protection Switch Control
The Automatic Protection Switch (APS) control block filters and captures the
receive automatic protection switch channel bytes (K1 and K2) allowing them to
be read via the RASE APS K1 Register and the RASE APS K2 Register. The
bytes are filtered for three frames before being written to these registers. A
protection switching byte failure alarm is declared when twelve successive
frames have been received, where no three consecutive frames contain identical
K1 bytes. The protection switching byte failure alarm is removed upon detection
of three consecutive frames containing identical K1 bytes. The detection of
invalid APS codes is done in software by polling the RASE APS K1 Register and
the RASE APS K2 Register.
10.4.2 Bit Error Rate Monitor
The Bit Error Monitor Block (BERM) calculates the received line BIP-24 error
detection code (B2) based on the line overhead and synchronous payload
envelope of the receive data stream. The line BIP-24 code is a bit interleaved
parity calculation using even parity. Details are provided in the references. The
calculated BIP code is compared with the BIP-24 code extracted from the B2
byte(s) of the following frame. Any differences indicate that a line layer bit error
has occurred. Up to 192000 (24 BIP/frame x 8000 frames/second) bit errors can
be detected per second for STS-3c (STM-1) rate.
The BERM accumulates these line layer bit errors in a 20 bit saturating counter
that can be read via the microprocessor interface. During a read, the counter
value is latched and the counter is reset to 0 (or 1, if there is an outstanding
event). Note, this counter should be polled at least once per second to avoid
saturation which in turn may result in missed bit error events.
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The BERM block is able to simultaneously monitor for signal fail (SF) or signal
degrade (SD) threshold crossing and provide alarms through software interrupts.
The bit error rates associated with the SF or SD alarms are programmable over a
range of 10-3 to 10-9. Details are provided in the Operations section.
In both declaring and clearing detection states, the accumulated BIP count is
continuously compared against the threshold. This allows to rapidly declare in the
presence of error bursts or error rates that significantly exceed the monitored
BER. This behavior allows meeting the ITU-T G.783 detection requirements at
various error rates (where the detection time is a function of the actual BER, for a
given monitored BER.
10.4.3 Synchronization Status Extraction
The Synchronization Status Extraction (SSE) Block extracts the synchronization
status (S1) byte from the line overhead. The SSE block can be configured to
capture the S1 nibble after three or after eight frames with the same value
(filtering turned on) or after any change in the value (filtering turned off). The S1
nibble can be read via the microprocessor interface. Optionally, the SSE can be
configured to perform filtering based on the whole S1 byte. Although this mode of
operation is not standard, it might become useful in the future.
10.5 Receive Path Overhead Processor (RPOP)
The Receive Path Overhead Processor (RPOP) provides pointer interpretation,
extraction of path overhead, extraction of the synchronous payload envelope,
and path level alarm indication and performance monitoring.
10.5.1 Pointer Interpreter
The Pointer Interpreter interprets the incoming pointer (H1, H2) as specified in
the references. The pointer value is used to determine the location of the path
overhead (the J1 byte) in the incoming STS-3c (STM-1) stream. The algorithm
can be modeled by a finite state machine. Within the pointer interpretation
algorithm three states are defined as shown below:
NORM_state (NORM)
AIS_state (AIS)
LOP_state (LOP)
The transition between states will be consecutive events (indications), e.g., three
consecutive AIS indications to go from the NORM_state to the AIS_state. The
kind and number of consecutive indications activating a transition is chosen such
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that the behavior is stable and insensitive to low BER. The only transition on a
single event is the one from the AIS_state to the NORM_state after receiving a
NDF enabled with a valid pointer value. It should be noted that, since the
algorithm only contains transitions based on consecutive indications, this implies
that, for example, non-consecutively received invalid indications do not activate
the transitions to the LOP_state.
Figure 4: Pointer Interpretation State Diagram
3 x eq_new_point
inc_ind /
dec_ind
NDF_enable
NORM
3x
eq_new_point
8x
inv_point
8x
NDF_enable
3x
eq_new_point
3x
AIS_ind
NDF_enable
3 x AIS_ind
LOP
AIS
8 x inv_point
The following table defines the events (indications) shown in the state diagram.
Table 1: Pointer Interpreter Event (Indications) Description
Event (Indication) Description
norm_point
disabled NDF + ss + offset value equal to active offset
NDF_enable
enabled NDF + ss + offset value in range of 0 to 782 or
enabled NDF + ss, if NDFPOR bit is set (Note that the
current pointer is not updated by an enabled NDF if the
pointer is out of range).
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AIS_ind
H1 = 'hFF, H2 = 'hFF
inc_ind
disabled NDF + ss + majority of I bits inverted + no
majority of D bits inverted + previous NDF_enable, inc_ind
or dec_ind more than 3 frames ago
dec_ind
disabled NDF + ss + majority of D bits inverted + no
majority of I bits inverted + previous NDF_enable, inc_ind
or dec_ind more than 3 frames ago
inv_point
not any of above (i.e., not norm_point, and not
NDF_enable, and not AIS_ind, and not inc_ind and not
dec_ind)
new_point
disabled_NDF + ss + offset value in range of 0 to 782 but
not equal to active offset
inc_req
majority of I bits inverted + no majority of D bits inverted
dec_req
majority of D bits inverted + no majority of I bits inverted
Note 1.-
active offset is defined as the accepted current phase o f the SPE
(VC) in the NORM_state and is undefined in the other states.
Note 2 -
enabled NDF is defined as the following bit patterns: 1001, 0001,
1101, 1011, 1000.
Note 3 -
disabled NDF is defined as the following bit patterns: 0110, 1110,
0010, 0100, 0111.
Note 4 -
the remaining six NDF codes (0000, 0011, 0101, 1010, 1100, 1111)
result in an inv_point indication.
Note 5 -
ss bits are unspecified in SONET and has bit pattern 10 in SDH
Note 6 -
the use of ss bits in definition of indications may be optionally
disabled.
Note 7 -
the requirement for previous NDF_enable, inc_ind or dec_ind be
more than 3 frames ago may be optionally disabled.
Note 8 -
new_point is also an inv_point.
Note 9 -
LOP is not declared if all the following conditions exist:
• the received pointer is out of range (>782),
• the received pointer is static,
• the received pointer can be interpreted, according
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to majority voting on the I and D bits, as a
positive or negative justification indication,
• after making the requested justification, the received
pointer continues to be interpretable as a
pointer justification.
When the received pointer returns to an in-range value, the
S/UNI/TETRA will interpret it correctly.
Note 10 -
LOP will exit at the third frame of a three frame sequence consisting
of one frame with NDF enabled followed by two frames with NDF
disabled, if all three pointers have the same legal value.
The transitions indicated in the state diagram are defined in the following table.
Table 2: Pointer Interpreter Transition Description
Transition
Description
inc_ind/dec_ind
offset adjustment (increment or decrement indication)
3 x eq_new_point
three consecutive equal new_point indications
NDF_enable
single NDF_enable indication
3 x AIS_ind
three consecutive AIS indications
8 x inv_point
eight consecutive inv_point indications
8 x NDF_enable
eight consecutive NDF_enable indications
Note 1 -
the transitions from NORM_state to NORM_state do not represent
state changes but imply offset changes.
Note 2 -
3 x new_point takes precedence over other events and if the
IINVCNT bit is set resets the inv_point count.
Note 3 -
all three offset values received in 3 x eq_new_point must be
identical.
Note 4 -
"consecutive event counters" are reset to zero on a change of state
except for consecutive NDF count.
The Pointer Interpreter detects loss of pointer (LOP) in the incoming STS-3c
(STM-1) stream. LOP is declared on entry to the LOP_state as a result of eight
consecutive invalid pointers or eight consecutive NDF enabled indications. The
alarm condition is reported in the receive alarm port and is optionally returned to
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the source node by signaling the corresponding Transmit Path Overhead
Processor in the local S/UNI-TETRA to insert a path RDI indication.
The Pointer Interpreter detects path AIS in the incoming STS-3c (STM-1)
stream. PAIS is declared on entry to the AIS_state after three consecutive AIS
indications. The alarm condition reported in the receive alarm port and is
optionally returned to the source node by signaling the corresponding Transmit
Path Overhead Processor in the local SONET/SDH equipment to insert a path
RDI indication.
Invalid pointer indications (inv_point), invalid NDF codes, new pointer indications
(new_point), discontinuous change of pointer alignment, and illegal pointer
changes are also detected and reported by the Pointer Interpreter block via
register bits. An invalid NDF code is any NDF code that does not match the NDF
enabled or NDF disabled definitions. The third occurrence of equal new_point
indications (3 x eq_new_point) is reported as a discontinuous change of pointer
alignment event (DISCOPA) instead of a new pointer event and the active offset
is updated with the receive pointer value. An illegal pointer change is defined as
a inc_ind or dec_ind indication that occurs within three frames of the previous
inc_ind, dec_ind or NDF_enable indications. Illegal pointer changes may be
optionally disabled via register bits.
The active offset value is used to extract the path overhead from the incoming
stream and can be read from an internal register.
10.5.2 SPE Timing
The SPE Timing Block provides SPE timing information to the Error Monitor and
the Extract blocks. The block contains a free running timeslot counter that is
initialized by a J1 byte identifier (which identifies the first byte of the SPE).
Control signals are provided to the Error Monitor and the Extract blocks to
identify the Path Overhead bytes and to downstream circuitry to extract the ATM
cell or POS payload.
10.5.3 Error Monitor
The Error Monitor Block contains two 16-bit counters that are used to accumulate
path BIP-8 errors (B3), and far end block errors (FEBEs). The contents of the two
counters may be transferred to holding registers, and the counters reset under
microprocessor control.
Path BIP-8 errors are detected by comparing the path BIP-8 byte (B3) extracted
from the current frame, to the path BIP-8 computed for the previous frame.
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FEBEs are detected by extracting the 4-bit FEBE field from the path status byte
(G1). The legal range for the 4-bit field is between 0000 and 1000, representing
zero to eight errors. Any other value is interpreted as zero errors.
Path RDI alarm is detected by extracting bit 5 of the path status byte. The PRDI
signal is set high when bit 5 is set high for five/ten consecutive frames. PRDI is
set low when bit 5 is low for five/ten consecutive frames. Auxiliary RDI alarm is
detected by extracting bit 6 of the path status byte. The Auxiliary RDI alarm is
indicated when bit 6 is set high for five/ten consecutive frames. The Auxiliary RDI
alarm is removed when bit 6 is low for five/ten consecutive frames. The
Enhanced RDI alarm is detected when the enhanced RDI code in bits 5,6,7 of
the path status byte indicates the same error codepoint for five/ten consecutive
frames. The Enhanced RDI alarm is removed when the enhanced RDI code in
bits 5,6,7 of the path status byte indicates the same non error codepoint for
five/ten consecutive frames. The ERDII maskable interrupt is set high when bits
5, 6 & 7 of the path status byte (G1) byte are set to a new codepoint for five or
ten consecutive frames. The ERDIV[2:0] signal reflects the state of the filtered
ERDI value (G1 byte bits 5, 6, & 7).
10.6 Receive ATM Cell Processor (RXCP)
The Receive ATM Cell Processor (RXCP) performs ATM cell delineation,
provides cell filtering based on idle/unassigned cell detection and HCS error
detection, and performs ATM cell payload de-scrambling. The RXCP also
provides a four cell deep receive FIFO. This FIFO is used to separate the
STS-3c (STM-1) line timing from the higher layer ATM system timing.
10.6.1 Cell Delineation
Cell Delineation is the process of framing to ATM cell boundaries using the
header check sequence (HCS) field found in the cell header. The HCS is a
CRC-8 calculation over the first 4 octets of the ATM cell header. When
performing delineation, correct HCS calculations are assumed to indicate cell
boundaries. Cells are assumed to be byte-aligned to the synchronous payload
envelope. The cell delineation algorithm searches the 53 possible cell boundary
candidates individually to determine the valid cell boundary location. While
searching for the cell boundary location, the cell delineation circuit is in the HUNT
state. When a correct HCS is found, the cell delineation state machine locks on
the particular cell boundary, corresponding to the correct HCS, and enters the
PRESYNC state. The PRESYNC state validates the cell boundary location. If
the cell boundary is invalid, an incorrect HCS will be received within the next
DELTA cells, at which time a transition back to the HUNT state is executed. If no
HCS errors are detected in this PRESYNC period, the SYNC state is entered.
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While in the SYNC state, synchronization is maintained until ALPHA consecutive
incorrect HCS patterns are detected. In such an event a transition is made back
to the HUNT state. The state diagram of the delineation process is shown in
Figure 5.
Figure 5: Cell Delineation State Diagram
correct HCS
(byte by byte)
HUNT
Incorrect HCS
(cell by cell)
PRESYNC
ALPHA
consecutive
incorrect HCS's
(cell by cell)
SYNC
DELTA
consecutive
correct HCS's
(cell by cell)
The values of ALPHA and DELTA determine the robustness of the delineation
process. ALPHA determines the robustness against false misalignments due to
bit errors. DELTA determines the robustness against false delineation in the
synchronization process. ALPHA is chosen to be 7 and DELTA is chosen to be 6.
These values result in an average time to delineation of 33.66 µs for the STS-3c
(STM-1) rate.
10.6.2 Descrambler
The self synchronous descrambler operates on the 48 byte cell payload only.
The circuitry descrambles the information field using the x43 + 1 polynomial. The
descrambler is disabled for the duration of the header and HCS fields and may
optionally be disabled for the payload.
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10.6.3 Cell Filter and HCS Verification
Cells are filtered (or dropped) based on HCS errors and/or a cell header pattern.
Cell filtering is optional and is enabled through the RXCP registers. Cells are
passed to the receive FIFO while the cell delineation state machine is in the
SYNC state as described above. When both filtering and HCS checking are
enabled, cells are dropped if uncorrectable HCS errors are detected, or if the
corrected header contents match the pattern contained in the RXCP Match
Header Pattern and RXCP Match Header Mask registers. Idle or unassigned cell
filtering is accomplished by writing the appropriate cell header pattern into the
RXCP Match Header Pattern and RXCP Match Header Mask registers.
Idle/Unassigned cells are assumed to contain the all zeros pattern in the VCI and
VPI fields. The RXCP Match Header Pattern and RXCP Match Header Mask
registers allow filtering control over the contents of the GFC, PTI, and CLP fields
of the header.
The HCS is a CRC-8 calculation over the first 4 octets of the ATM cell header.
The RXCP block verifies the received HCS using the polynomial, x8 + x2 + x + 1.
The coset polynomial, x6 + x4 + x2 + 1, is added (modulo 2) to the received HCS
octet before comparison with the calculated result. While the cell delineation
state machine (described above) is in the SYNC state, the HCS verification circuit
implements the state machine shown in Figure 6.
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Figure 6: HCS Verification State Diagram
ATM DELINEATION
SYNC STATE
ALPHA
consecutive
incorrect HCS's
(To HUNT state)
Apparent Multi-Bit Error
(Drop Cell)
No Errors
Detected
(Pass Cell)
CORRECTION
MODE
Single-Bit Error
(Correct Error
and Pass Cell)
Errors
Detected
(Drop Cell)
DETECTION
MODE
DELTA
consecutive
correct HCS's
(From PRESYNC
state)
No Errors Detected
In M Cells
(Pass M thCell)
No Errors Detected
(Pass Cell)
In normal operation, the HCS verification state machine remains in the
'Correction Mode' state. Incoming cells containing no HCS errors are passed to
the receive FIFO. Incoming single-bit errors are corrected, and the resulting cell
is passed to the FIFO. Upon detection of a single-bit error or a multi-bit error, the
state machine transitions to the 'Detection Mode' state. In this state,
programmable HCS error filtering is provided. The detection of any HCS error
causes the corresponding cell to be dropped. The state machine transitions back
to the 'Correction Mode' state when M (where M = 1, 2, 4, 8) cells are received
with correct HCSs. The Mth cell is not discarded.
10.6.4 Performance Monitor
The Performance Monitor consists of two 8-bit saturating HCS error event
counters and a 19-bit saturating receive cell counter. One of the counters
accumulates correctable HCS errors which are HCS single-bit errors detected
and corrected while the HCS Verification state machine is in the 'Correction
Mode' state. The second counter accumulates uncorrectable HCS errors which
are HCS bit errors detected while the HCS Verification state machine is in the
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'Detection Mode' state or HCS bit errors detected but not corrected while the
state machine is in the 'Correction Mode' state. The 19-bit receive cell counter
counts all cells written into the receive FIFO. Filtered cells are not counted.
Each counter may be read through the microprocessor interface. Circuitry is
provided to latch these counters so that their values can be read while
simultaneously resetting the internal counters to 0 or 1, if appropriate, so that a
new period of accumulation can begin without loss of any events. It is intended
that the counter be polled at least once per second so as not to miss HCS error
events.
10.7 Receive POS Frame Processor (RXFP)
The Receive POS Frame Processor (RXFP) performs packet extraction, provides
FCS error correction, performs packet payload de-scrambling, and provides
performance monitoring functions. The RXFP also provides a 256 byte deep
receive FIFO. This FIFO is used to separate the STS-3c (STM-1) line timing
from the link layer system timing, and to handle timing differences caused by the
removal of escape characters.
10.7.1 Overhead Removal
The overhead removal consist of striping SONET/SDH overhead bytes from the
data stream. Once overhead bytes are removed, the data stream consists of
POS frame octets which can be fed directly to the descrambler or the POS
Frame Delineation block.
10.7.2 Descrambler
When enabled, the self-synchronous descrambler operates on the POS Frame
data, de-scrambling the data with the polynomial x43 + 1. De-scrambling is
performed on the raw data stream, before any POS frame delineation or byte
destuffing is performed. Data scrambling can provide for a more robust system
preventing the injection of hostile patterns into the data stream.
10.7.3 POS Frame Delineation
This block accepts data one byte at a time and arranges it as POS framed octets.
Frame boundaries are found by searching for the Flag Character (0x7E). Flags
are also used to fill inter-packet spacing. This block removes the Flag Sequence
and passes the data onto the Byte Destuffing block.
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The POS Frame Delineation is performed on the descrambled data and consists
of arranging the POS framed octets. Frame boundaries are found by searching
for the Flag Character (0x7E). Flags are also used to fill inter-packet spacing.
This block removes the Flag Sequence and passes the data onto the Byte
Destuffing block. The POS Frame format is shown on Figure 7.
Figure 7: Packet Over SONET/SDH Frame Format
Flag
Information
FCS
Flag
Flag
Packet
(PPP or other)
POS F rame
In the event of a FIFO overflow caused by the FIFO being full while a packet is
being received, the packet is marked with an error so it can be discarded by the
system. Following bytes associated with this now aborted frame are discarded.
Reception of POS data resumes when a Start of Packet is encountered and the
FIFO level is below the programmable Reception Initialization Level (RIL[7:0]).
10.7.4 Byte Destuffing
The byte destuffing algorithm searches for the Control Escape character (0x7D).
These characters are added for transparency in the transmit direction, as shown
in Table 3, and must be removed to recover the user data. When the Control
Escape character is encountered, it is removed and the following data byte is
XORed with 0x20. Only the Flag Sequence (0x7E) and the Control Escape
character itself are expected to have been escaped in the transmit direction, but
this implementation does not preclude escaping other values as well.
Table 3: Byte Destuffing
Original
7E (Flag Sequence)
7D (Control Escape)
Aborted Packet
Escaped
7D-5E
7D-5D
7D-7E
10.7.5 FCS Check
The FCS Generator performs a CRC-CCITT or CRC-32 calculation on the whole
POS frame, after byte destuffing and data de-scrambling. A parallel
implementation of the CRC polynomial is used. The CRC algorithm for the frame
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checking sequence (FCS) field is either a CRC-CCITT or CRC-32 function. The
CRC-CCITT is two bytes in size and has a generating polynomial g(X) = 1 + X 5 +
X12 + X 16 . The CRC-32 is four bytes in size and has a generating polynomial
g(X) = 1 + X + X 2 + X 4 + X 5 + X 7 + X 8 + X 10 + X 11 + X 12 + X 16 + X 22 + X 23 + X 26
+ X 32 . The first FCS bit transmitted is the coefficient of the highest term. The
RXFP-50 implements a CRC decoder that uses a CRC encoder. The coder
registers are preset to ones. Then the packet data and CRC are feed in. The
result should be a constant number provided in the HDLC documentation. A
different value indicates an error. Packets with FCS errors are marked as such
and should be discarded by the system.
Figure 8: CRC Decoder
g1
Message
+
D0
+
g2
D1
+
gn-1
...
+
Dn-1
10.7.6 Performance Monitor
The Performance Monitor consists of four 16-bit saturating error event counters
and one 24-bit saturating received good packet counter. One of the error event
counters accumulates FCS errors. The second error event counter accumulates
minimum length violation packets. The third error event counter accumulates
maximum length violation packets. The fourth error event counter accumulates
aborted packets. The 24-bit receive good packet counter counts all error free
packets.
Each counter may be read through the microprocessor interface. Circuitry is
provided to latch these counters so that their values can be read while
simultaneously resetting the internal counters to 0 or 1, whichever is appropriate,
so that a new period of accumulation can begin without loss of any events. The
counters are intended to be polled at least once per second so error events will
not be missed.
The RXFP-50 monitors the packets for both minimum and maximum length
errors. When a packet size is smaller than MINPL[7:0], the packet is marked with
an error but still written into the FIFO. Misformed packets, that is packets that do
not at least contain the FCS field plus one byte, are treated differently. If a
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misformed packet is received and FCS stripping is enabled, the packet is
discarded, not written in the FIFO, and counted as a minimum packet size
violation. If a misformed packet is received and FCS stripping is disabled, it is
written into the FIFO since in this case the misformed packet criteria is reduced
to one byte, but will still count as a minimum packet size violation. When the
packet size exceeds MAXPL[15:0] the packet is marked with an error and the
exceeding bytes are discarded.
Packet greater than 64k bytes are not supported. When the MAXPL is set to
0xFFFF, a packet of length greater than 0xFFFF will generate an MINLI instead
of a MAXLI. When the MAXPL value is less than 0xFFFF, the behaviour will be
normal for any packet length less than, equal or greater than 0xFFFF. It is
recommended to only set MAXPL to a value smaller or equal to 0xFFFE.
10.7.7 Receive FIFO
The Receive FIFO block contains storage for 256 octets, along with management
circuitry for reading and writing the FIFO. The receive FIFO provides for the
separation of the physical layer timing from the system timing.
Receive FIFO management functions include filling the receive FIFO, indicating
when packets or bytes are available to be read from the receive FIFO,
maintaining the receive FIFO read and write pointers, and detecting FIFO
overrun and underrun conditions. Upon detection of an overrun, the FIFO aborts
the current packet and discards the current incoming bytes until there is room in
the FIFO. Once enough room is available, as defined by the RIL[7:0] register, the
RXFP-50 will wait for the next start of packet before writing any data into the
FIFO. FIFO overruns are indicated through a maskable interrupt and register bit
and are considered a system error. A FIFO underrun is caused when the System
Interface tries to read more data words while the FIFO is empty. This action will
be detected and reported through the FUDRI interrupt, but it is not considered a
system error. The system will continue to operate normally. In that situation,
RVAL can be used by the Link Layer device to find out if valid or invalid data is
provided on the System Interface.
10.8 Transmit Line Interface (CSPI)
The Transmit Line Interface allows to directly interface the S/UNI-TETRA with
optical modules (ODLs) or other medium interfaces. This block performs clock
synthesis and performs parallel to serial conversion of the incoming outgoing
155.52 Mbit/s data stream.
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10.8.1 Clock Synthesis
The transmit clock is synthesized from a 19.44 MHz reference. The transfer
function yields a typical low pass corner of 2.0 MHz above which reference jitter
is attenuated at 12 dB per octave. The design of the loop filter and PLL is
optimized for minimum intrinsic jitter. With a jitter free 19.44 MHz reference, the
intrinsic jitter is typically less than 0.01 UI RMS when measured using a high
pass filter with a 12 kHz cutoff frequency.
The REFCLK reference should be within ±20 ppm to meet the SONET free-run
accuracy requirements specified in GR-253-CORE.
10.8.2 Parallel to Serial Converter
The Parallel to Serial Converter (PISO) converts the transmit byte serial stream
to a bit serial stream. Every self-timed channel (a self-timed channel is one that
uses the CSU output clock) share a common line rate clock and byte clock,
which can be output as TCLK. Only self-timed channels can be synchronized
using the TFPI input. When a channel is loop-timed, TCLK, TFPI and TFPI are no
more available and the receive signals shall be used instead to extract timing
information.
10.9 Transmit Section Overhead Processor (TSOP)
The Transmit Section Overhead Processor (TSOP) provides frame pattern
insertion (A1, A2), scrambling, section level alarm signal insertion, and section
BIP-8 (B1) insertion.
10.9.1 Line AIS Insert
Line AIS insertion results in all bits of the SONET/SDH frame being set to 1
before scrambling except for the section overhead. The Line AIS Insert Block
substitutes all ones as described when enabled through an internal register
(Register 0x14 TSOP) accessed through the microprocessor interface. Activation
or deactivation of line AIS insertion is synchronized to frame boundaries.
10.9.2 Data Link Insert
The Data Link Insert Block inserts the section data communication channel
(bytes D1, D2, and D3) into the STS-3c (STM-1) stream when enabled by an
internal register accessed via the common bus interface. The bytes to be
inserted are serially input on signal TSD at a nominal 192 kbit/s rate. Timing for
upstream processing of the data communication channel is provided by the
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TSDCLK signal that is output by the Data Link Insert Block. TSDCLK is derived
from a 216 kHz clock that is gapped to yield an average frequency of 192 kHz.
TSD is sampled with timing aligned to TSDCLK
10.9.3 BIP-8 Insert
The BIP-8 Insert Block calculates and inserts the BIP-8 error detection code (B1)
into the transmit stream.
The BIP-8 calculation is based on the scrambled data of the complete STS-3c
(STM-1) frame. The section BIP-8 code is based on a bit interleaved parity
calculation using even parity. Details are provided in the references. The
calculated BIP-8 code is then inserted into the B1 byte of the following frame
before scrambling. BIP-8 errors may be continuously inserted under register
control for diagnostic purposes.
10.9.4 Framing and Identity Insert
The Framing and Identity Insert Block inserts the framing bytes (A1, A2) and
trace/growth bytes (J0/Z0) into the STS-3c (STM-1) frame. Framing bit errors
may be continuously inserted under register control for diagnostic purposes.
10.9.5 Scrambler
The Scrambler Block utilizes a frame synchronous scrambler to process the
transmit stream when enabled through an internal register accessed via the
microprocessor interface. The generating polynomial is x7 + x6 + 1. Precise
details of the scrambling operation are provided in the references. Note that the
framing bytes and the identity bytes are not scrambled. All zeros may be
continuously inserted (after scrambling) under register control for diagnostic
purposes.
10.10 Transmit Line Overhead Processor (TLOP)
The Transmit Line Overhead Processor (TLOP) provides line level alarm signal
insertion, and line BIP -24 insertion (B2).
10.10.1
APS Insert
The APS Insert Block inserts the two automatic protection switch (APS) channel
bytes in the Line Overhead (K1 and K2) into the transmit stream when enabled
by an internal register.
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Data Link Insert
The Data Link Insert Block inserts the line data communication channel (DCC)
(bytes D4 to D12) into the STS-3c (STM-1) stream when enabled by an internal
register. The D4 to D12 bytes are input serially using the TLD signal at a
nominal 576 kbit/s rate. Timing for processing of the line DCC is provided by the
TLDCLK output. TLDCLK is derived from a 2.16 MHz clock that is gapped to
yield an average frequency of 576 kHz.
10.10.3
Line BIP Calculate
The Line BIP Calculate Block calculates the line BIP -24 error detection code (B2)
based on the line overhead and synchronous payload envelope of the transmit
stream. The line BIP -24 code is a bit interleaved parity calculation using even
parity. Details are provided in the references. The calculated BIP -24 code is
inserted into the B2 byte positions of the following frame. BIP -24 errors may be
continuously inserted under register control for diagnostic purposes.
10.10.4
Line RDI Insert
The Line RDI Insert Block controls the insertion of line remote defect indication.
Line RDI insertion is enabled using the TLRDI input, or register control. Line RDI
is inserted by transmitting the code 110 (binary) in bit positions 6, 7, and 8 of the
K2 byte contained in the transmit stream.
10.10.5
Line FEBE Insert
The Line FEBE Insert Block accumulates line BIP -24 errors (B2) detected by the
Receive Line Overhead Processor and encodes far end block error indications in
the transmit M1 byte.
10.11 Transmit Path Overhead Processor (TPOP)
The Transmit Path Overhead Processor (TPOP) provides transport frame
alignment generation, pointer generation (H1, H2), path overhead insertion and
the insertion of path level alarm signals.
10.11.1
Pointer Generator
The Pointer Generator Block generates the outgoing payload pointer (H1, H2) as
specified in the references. The concatenation indication (the NDF field set to
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1001, I-bits and D-bits set to all ones, and unused bits set to all zeros) is inserted
in the second and third pointer byte locations in the transmit stream.
•
(1) A "normal pointer value" locates the start of the SPE. Note: 0 ≤ "normal
pointer value" ≤ 782, and the new data flag (NDF) field is set to 0110. Note
that values greater than 782 may be inserted, using internal registers, to
generate a loss of pointer alarm in downstream circuitry.
•
(2) Arbitrary "pointer values" may be generated using internal registers.
These new values may optionally be accompanied by a programmable new
data flag. New data flags may also be generated independently using internal
registers.
•
(3) Positive pointer movements may be generated using a bit in an internal
register. A positive pointer movement is generated by inverting the five I-bits
of the pointer word. The SPE is not inserted during the positive stuff
opportunity byte position, and the pointer value is incremented by one.
Positive pointer movements may be inserted once per frame for diagnostic
purposes.
•
(4) Negative pointer movements may be generated using a bit in an internal
register. A negative pointer movement is generated by inverting the five Dbits of the pointer word. The SPE is inserted during the negative stuff
opportunity byte position, the H3 byte, and the pointer value is decremented
by one. Negative pointer movements may be inserted once per frame for
diagnostic purposes.
The pointer value is used to insert the path overhead into the transmit stream.
The current pointer value may be read via internal registers.
10.11.2
BIP-8 Calculate
The BIP-8 Calculate Block performs a path bit interleaved parity calculation on
the SPE of the transmit stream. Details are provided in the references. The
resulting parity byte is inserted in the path BIP-8 (B3) byte position of the
subsequent frame. BIP-8 errors may be continuously inserted under register
control for diagnostic purposes.
10.11.3
FEBE Calculate
The FEBE Calculate Block accumulates far end block errors on a per frame
basis, and inserts the accumulated value (up to maximum value of eight) in the
FEBE bit positions of the path status (G1) byte. The FEBE information is derived
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from path BIP-8 errors detected by the receive path overhead processor, RPOP.
Far end block errors may be inserted under register control for diagnostic
purposes.
10.12 Transmit ATM Cell Processor (TXCP)
The Transmit ATM Cell Processor (TXCP) provides rate adaptation via
idle/unassigned cell insertion, provides HCS generation and insertion, and
performs ATM cell scrambling. The TXCP contains a four cell transmit FIFO. An
idle or unassigned cell is transmitted if a complete ATM cell has not been written
into the FIFO.
10.12.1
Idle/Unassigned Cell Generator
The Idle/Unassigned Cell Generator inserts idle or unassigned cells into the cell
stream when enabled. Registers are provided to program the GFC, PTI, and
CLP fields of the idle cell header and the idle cell payload. The idle cell HCS is
automatically calculated and inserted.
10.12.2
Scrambler
The Scrambler scrambles the 48 octet information field. Scrambling is performed
using a parallel implementation of the self synchronous scrambler (x43 + 1
polynomial) described in the references. The cell headers are transmitted
unscrambled, and the scrambler may optionally be disabled.
10.12.3
HCS Generator
The HCS Generator performs a CRC-8 calculation over the first four header
octets. A parallel implementation of the polynomial, x8+x2+x+1, is used. The
coset polynomial, x6+x4 +x2+1, is added (modulo 2) to the residue. The HCS
Generator optionally inserts the result into the fifth octet of the header.
10.13 Transmit POS Frame Processor (TXFP)
The Transmit POS Frame Processor (TXFP) provides rate adaptation by
transmitting flag sequences (0x7E) between packets, provides FCS generation
and insertion, performs packet data scrambling, and provides performance
monitoring functions. The TXFP contains a 256 byte transmit FIFO. This FIFO is
used to separate the STS-3c (STM-1) line timing from the link layer system
timing, and to handle timing differences caused by insertion of escape
characters.
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Transmit FIFO
The Transmit FIFO is responsible for holding packets provided through the Input
Interface until they are transmitted. The transmit FIFO can accommodate a
maximum of 256 bytes. There is no limit on the number of packets that can be
stored, other than the FIFO depth limitation. Octets are written in with a single 16
bit data bus running off TFCLK and are read out with a single 8-bit data bus
running off the SONET/SDH clock. Separate read and write clock domains
provide for separation of the physical layer line timing (PICLK) from the System
Link layer timing (TFCLK).
Internal read and write pointers track the insertion and removal of octets, and
indicate the fill status of the Transmit FIFO. These status indications are used to
detect underrun and overrun conditions, abort packets as appropriate on both
System and Line sides, control flag insertion and to generate the TPA outputs.
The TXFP does not abort packets under an overrun condition. The packet will be
sent and will appear as a good packet with a good FCS. Overruns should never
occur in normal system operating conditions, thus this limitation should not affect
the system performance. Overruns can be avoided by setting the high and low
watermarks. The optimal setup depends on the system design.
10.13.2
POS Frame Generator
The POS Frame Generator runs off of the SONET/SDH sequencer to create the
POS frames to be transmitted, whose format is shown in Figure 7. Flags are
inserted whenever the Transmit FIFO is empty and there is no data to transmit.
When there is enough data to be transmitted, the block operates normally; it
removes the packets from the Transmit FIFO and transmits them. In addition,
FCS generation, error insertion, byte stuffing, and scrambling can be optionally
enabled.
Figure 9: Packet Over SONET/SDH Frame Format
Flag
Information
FCS
Flag
Flag
Packet
(PPP or other)
POS F rame
In the event of a FIFO underflow caused by the FIFO being empty while a packet
is being transmitted, the packet is aborted by transmitting the Abort Sequence.
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The Abort Sequence consists of an Escape Control character (0x7D) followed by
the Flag Sequence (0x7E). Bytes associated with this aborted frame are still read
from the FIFO but are discarded and replaced with the Flag Sequence in the
outgoing data stream. Transmission of data resumes when a Start of Packet is
encountered in the FIFO data stream.
The POS Frame Generator also performs Inter Packet Gaping. This operation
consists of inserting a programmable number of Flag Sequence characters
between each POS Frame transmission. This feature allows to control the
system effective data transmission rate if required.
10.13.3
FCS Generator
The FCS Generator performs a CRC-CCITT or CRC-32 calculation on the whole
POS frame, before byte stuffing and data scrambling. A parallel implementation
of the CRC polynomial is used. The CRC algorithm for the frame checking
sequence (FCS) field is either a CRC-CCITT or CRC-32 function. The CRCCCITT is two bytes in size and has a generating polynomial g(X) = 1 + X 5 + X 12 +
X16. The CRC-32 is four bytes in size and has a generating polynomial g(X) = 1
+ X + X 2 + X 4 + X 5 + X 7 + X 8 + X 10 + X 11 + X 12 + X 16 + X 22 + X 23 + X 26 + X 32 .
The first FCS bit transmitted is the coefficient of the highest term. When
transmitting a packet from the Transmit FIFO, the FCS Generator appends the
result after the last data byte, before the closing flag. Note that the Frame Check
Sequence is the one's complement of the CRC register after calculation ends.
FCS calculation and insertion can be disabled.
Figure 10: CRC Generator
g1
D0
g2
D1
LSB
g n- 1
D2
Message
D n -1
Parity Che ck Digits
MSB
An error insertion mechanism is provided for system diagnosis purposes. Error
insertion is performed by inverting the resulting FCS value, before transmission.
This should cause an FCS Error at the far end.
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Byte Stuffing
The POS Frame generator provides transparency by performing byte stuffing.
This operation is done after the FCS calculation. Two characters need to be
escaped, the Flag Sequence (0x7E) and the Escape Character itself (0x7D).
When a character is being escaped, it is XORed with 0x20 before transmission
and preceded by the Control Escape (0x7D) character.
Table 4: Byte Stuffing
Original
7E (Flag Sequence)
7D (Control Escape)
Abort Sequence
10.13.5
Escaped
7D-5E
7D-5D
7D-7E
Data Scrambling
The Scrambler will optionally scramble the whole packet data, including the FCS
and the flags. Scrambling is performed after the POS frame is formed using a
parallel implementation of the self synchronous scrambler polynomial, x43+1.
On reset, the scrambler is set to all ones to ensure scrambling on start-up. The
scrambler may optionally be completely disabled. Data scrambling can provide
for a more robust system preventing the injection of hostile patterns into the data
stream.
10.13.6
SONET/SDH Framer
The SONET/SDH Framer gaps the POS frames in order to insert the
SONET/SDH framing and overhead bytes (Section/Line Overhead and Path
Overhead). The framer uses framing alignment information provided by the
RPOP to perform its function. The TXFP does not set any SONET/SDH overhead
byte.
10.14 SONET/SDH Section and Path Trace Buffers (SSTB and SPTB)
The SONET/SDH Section Trace Buffer (SSTB) block and the SONET/SDH Path
Trace Buffer (SPTB) block are identical. The blocks can handle both 64-byte
CLLI messages in SONET and 16-byte E.164 messages in SDH. The generic
SONET/SDH Trace Buffer (STB) block is described below.
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Receive Trace Buffer (RTB)
The RTB consists of two parts: the Trace Message Receiver and the Overhead
Byte Receiver.
10.14.1.1
Trace Message Receiver
The Trace Message Receiver (TMR) processes the trace message, and consists
of three sub-processes: Framer, Persistency, and Compare.
10.14.1.1.1
Framer
The TMR handles the incoming 16-byte message by synchronizing to the byte
with the most significant bit set high, and places that byte in the first location in
the capture page of the internal RAM. In the case of the 64-byte message, the
TMR synchronizes to the trailing carriage return (0x0D), line feed (0x0A)
sequence and places the next byte in the first location in the capture page of the
internal RAM. The Framer block maintains an internal representation of the
resulting 16-byte or 64-byte "frame" cycle. If the phase of the start of frame
shifts, the framer adjusts accordingly and resets the persistency counter and
increments the unstable counter.
Frame synchronization may be disabled, in which case the RAM acts as a
circular buffer.
10.14.1.1.2
Persistency
The Persistency process checks for repeated reception of the same 16-byte or
64-byte trace message. An unstable counter is incremented for each message
that differs from the previous received message. For example, a single corrupted
message in a field of constant messages causes the unstable count to increment
twice, once on receipt of the corrupted message, and again on the next
(uncorrupted) message. A section/path trace message unstable alarm is
declared when the count reaches eight.
The persistency counter is reset to zero, the unstable alarm is removed, and the
trace message is accepted when the same 16-byte or 64-byte message is
received three or five times consecutively (as determined by an internal register
bit). The accepted message is passed to the Compare process for comparison
with the expected message.
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Compare
A receive trace message mismatch alarm is declared if the accepted message
(i.e. the message that passed the persistency check) does not match the
expected message (previously downloaded to the receive expected page by the
microprocessor). The mismatch alarm is removed if the accepted message is allzero, or if the accepted message is identical to the expected message.
10.14.1.2
Overhead Byte Receiver
The Overhead Byte Receiver (OBR) processes the path signal label byte (C2).
The OBR consists of two sub-processes: Persistency and Compare.
10.14.1.2.1
Persistency
The Persistency process checks for the repeated reception of the same C2 byte.
An unstable counter is incremented for each received C2 byte that differs from
the byte received in the previous frame. For example, a single corrupted byte
value in a sequence of constant values causes the unstable count to increment
twice, once on receipt of the corrupted value, and again on the next
(uncorrupted) value. A path signal label unstable alarm or a synchronization
status unstable alarm is declared when either unstable counter reaches five.
The unstable counter is reset to zero, the unstable alarm is removed, and the
byte value is accepted when the same label is received in five consecutive
frames. The accepted value is passed to the Compare process for comparison
with the expected value.
10.14.1.2.2
Compare
A path signal label mismatch alarm or a synchronization status mismatch alarm is
declared if the accepted C2 byte (i.e. the byte value that has passed the
persistency check) does not match the expected C2 byte (previously downloaded
by the microprocessor).
The OBR mismatch mechanism follows the table below:
Table 5: OBR Mismatch Mechanism
Expect
00
00
00
Receive
00
01
XX
Action
Match
Mismatch
Mismatch
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01
01
01
XX
XX
XX
XX
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00
01
XX
00
01
XX
YY
Mismatch
Match
Match
Mismatch
Match
Match
Mismatch
Note: XX, YY = anything except 00H or 01H (XX not equal YY).
10.14.2
Transmit Trace Buffer (TTB)
The TTB sources the 16-byte or 64-byte trace identifier message. The TTB
contains one page of transmit trace identifier message memory. Identifier
message data bytes are written by the microprocessor into the message buffer
and inserted in the transmit stream. When the microprocessor is updating the
transmit page buffer, the TTB may be programmed to transmit null characters to
prevent transmission of partial messages.
10.15 ATM UTOPIA and Packet over SONET/SDH POS-PHY System Interfaces
The S/UNI-TETRA system interface can be configured for ATM or POS mode.
When configured for ATM applications, the system interface provides a Utopia
level 2 compliant bus to transfer ATM cells between the ATM layer device and the
S/UNI-TETRA. When configures for POS applications, the system interface is
POS-PHY Level 2 compliant and provides a packet or byte level transfer
interface that allows the transfer of data packets between the link layer device
and the S/UNI-TETRA. The link layer device can implement various protocols,
including PPP.
10.15.1
Receive ATM Interface
The Receive ATM FIFO (RXCP) provides FIFO management at the
S/UNI-TETRA receive cell interface. The receive FIFO contains four cells. The
FIFO provides the cell rate decoupling function between the transmission system
physical layer and the ATM layer.
In general, the management functions include filling the receive FIFO, indicating
when the receive FIFO contains cells, maintaining the receive FIFO read and
write pointers, and detecting FIFO overrun and underrun conditions.
The FIFO interface is “UTOPIA Level 2" compliant and accepts a read clock
(RFCLK) and read enable signal (RENB). The receive FIFO output bus
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(RDAT[15:0]) is tri-stated when RENB is logic one or if the PHY device address
(RADR[4:0]) selected does not match this device's address. The interface
indicates the start of a cell (RSOC) and the receive cell available status (RCA
and DRCA[4:1]) when data is read from the receive FIFO (using the rising edges
of RFCLK). The RCA (and DRCA[x]) status changes from available to
unavailable when the FIFO is either empty (RCALEVEL0=1) or near empty
(RCALEVEL0 is logic zero). This interface also indicates FIFO overruns via a
maskable interrupt and register bits. Read accesses while RCA (or DRCA[x]) is a
logic zero will output invalid data. The FIFO is reset on FIFO overrun, causing up
to 4 cells to be lost.
10.15.2
Receive POS Interface
The Receive POS FIFO (RXFP) provides FIFO management at the
S/UNI-TETRA receive packet interface. The receive FIFO contains 256 bytes.
The FIFO provides the system rate decoupling function between the transmission
system physical layer and the link layer, and to handle timing differences caused
by the removal of escape characters.
The interface is based on the POS-PHY Level 2 specification. The POS-PHY
Interface is an extension to the UTOPIA 2 interface defined for the transfer of
POS frames. Both the POS-PHY Byte-Level and Packet-Level transfer modes
are supported.
The RSOP signal is used to identify the start of a packet, the DRPA[x] signal
notifies the system side that data is in the receive FIFO (when a programmable
number of bytes in a single packet is received or when an end of packet is
available); the RDATA[15:0] bus transfer the data from the FIFO across the
system interface; the RADR[4:0] signals are used to select the desired PHY
device; the RPRTY signal determines the parity on the RDAT bus (selectable as
odd or even parity); the RFCLK is used to read words from the FIFO interface;
and the RENB is used to initiate reads from the receive FIFO. Signal REOP
(Receive End of Packet) is used to identify the end of a packet. Signal RMOD
(Receive Mod) is provided to indicate whether 1 or 2 bytes are valid on the final
word transfer (REOP is asserted). Signal RERR (Receive Error) is provided to
indicate that an error in the received packet has occurred (may have several
causes, including an abort sequence and an FCS error). The receive data valid
signal, RVAL, plays a special role in this interface. The data signals shall be
considered valid only when RVAL is asserted. RVAL is asserted when a data
transfer is initiated, conditional to RPA being also asserted. Once the transfer is
initiated, RVAL will remain asserted until either the FIFO is empty or an end of
packet is encountered. Once deasserted, RVAL will remain low until the current
PHY is deselected and another or the same PHY is reselected. RVAL allows the
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link layer device to align data transfers with packet boundaries, making it easier
to manage packet buffers.
10.15.2.1
Premature RPA Assertion
In normal operation, there are a few microseconds of delay between when a
SONET frame arrives (with packet data) and to when it is available on the system
side interface (the POS-PHY interface RDAT[15:0] ). This delay is the time that is
required to extract packets from the SONET/SDH frame.
When a packet with less than 22 bytes arrives (from the line side), the receive
packet available signal (DRPA[4..1] or PRPA) may assert prematurely. In this
condition, RPA will assert between 1 to 11 RFCLK clock cycles before the data is
available and will remain asserted for 1 to 11 RFCLK clock cycles. This is shown
in Figure 11.
Figure 11 : Pre-mature RPA assertion timing
RFCLK
00
RADR
Assertion of
RENB
RENB
Assertion of RENB
due to RPA assertion
RVAL
No data
RSOP
REOP
Pre-mature RPA
assertion
RERR
DRPA1
Previous
Packet EOP
Real RPA
assertion
Pre-mature RPA
assertion after
previous RPA
deassertion
Pre-mature
RPA Width
1 to 11 FIFO Cycles
This condition is created because the FIFO outputs and receives two EOP bytes
within four line side clock cycles. The EOP byte that generates the premature
RPA will then be available from the FIFO four line clock cycles after the RPA
assertion. Thus, packet larger than a minimum length will have sufficient data to
provide the POS-PHY interface while the EOP byte is being processed. This
minimum packet length is proportional to the ratio between the line side clock
and the POS-PHY interface clock. For a line side at OC-3 (19.44MHz) and a
POS-PHY interface at 50MHz, at least 22 bytes are required. For any packet
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greater than this minimum length, RVAL will stay asserted from the transfer
initialization to the transfer of the EOP byte that generated the premature RPA.
For any packet length smaller than the minimum length, the transfer may be
stopped for lack of available data from the FIFO. In either case, the data will not
be corrupted; however, the problem may reduce bandwidth on the receive POSPHY interface. This problem can not happen for packet larger than the FIFO size
since it would be impossible to get two EOP bytes in the FIFO within those four
clock cycles. Furthermore, if the packet size is larger than the RPAHWM, the
RPA will assert because of the FIFO level and the premature RPA issue will not
happen.
10.15.3
Transmit ATM Interface
The ATM Transmit FIFO (TXCP) provides FIFO management at the
S/UNI-TETRA transmit cell interface. The transmit FIFO contains four cells. The
FIFO depth may be programmed to four, three, two, or one cells. The FIFO
provides the cell rate decoupling function between the transmission system
physical layer and the ATM layer.
In general, the management functions include emptying cells from the transmit
FIFO, indicating when the transmit FIFO is full, maintaining the transmit FIFO
read and write pointers, and detecting a FIFO overrun condition.
The FIFO interface is “UTOPIA Level 2” compliant and accepts a write clock
(TFCLK), a write enable signal (TENB), the start of a cell (TSOC) indication, the
parity bit (TPRTY), and the ATM device address (TADR[4:0]) when data is written
to the transmit FIFO (using the rising edges of TFCLK). The interface provides
the transmit cell available status (TCA and DTCA[4:1]) which can transition from
"available" to "unavailable" when the transmit FIFO is near full (when
TCALEVEL0 is logic zero) or when the FIFO is full (when TCALEVEL0 is logic
one) and can accept no more writes. To reduce FIFO latency, the FIFO depth at
which TCA and DTCA[x] indicates "full" can be set to one, two, three or four cells
by the FIFODP[1:0] bits of TXCP Configuration 2 register. If the programmed
depth is less than four, more than one cell may be written after TCA or DTCA[x] is
asserted as the TXCP still allows four cells to be stored in its FIFO. This
interface also indicates FIFO overruns via a maskable interrupt and register bit,
but write accesses while TCA or DTCA[x] is logic zero are not processed. The
TXCP automatically transmits idle cells until a full cell is available to be
transmitted.
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Transmit POS Interface
The Transmit POS FIFO (TXFP) provides FIFO management at the
S/UNI-TETRA transmit packet interface. The transmit FIFO contains 256 bytes.
The FIFO provides the system rate decoupling function between the transmission
system physical layer and the link layer, and handles timing differences caused
by the insertion of escape characters.
The interface is based on the POS-PHY Level 2 specification. The POS-PHY
Interface is an extension to the UTOPIA 2 interface defined for the transfer of
POS frames. Both the POS-PHY Byte-Level and Packet-Level transfer modes
are supported.
The TSOP signal is used to identify the start of a packet; the DTPA[x] signals
notify the system side that the transmit FIFO is not full (the POS processor will
not start transmitting a packet until a programmable number of bytes for a single
packet or the entire packet is in the FIFO; the TDAT[15:0] bus transfers the data
to the FIFO from the system interface; the TADR[4:0] bus is used in polling to
select the desired PHY device; the TPRTY signal determines the parity on the
TDAT bus (selectable as odd or even parity); the TFCLK is used to write words to
the FIFO interface; and finally the TENB is used to initiate writes to the transmit.
The TEOP signal (Transmit End of Packet) is used to identify the end of a packet.
The TMOD signal (Transmit Mod) is provided to indicate whether 1 or 2 bytes are
valid of the final word transfer (TEOP is asserted). The TERR signal (Transmit
Error) is provided to error a packet that has begun transmission (the packet will
be aborted).
10.16 WAN Synchronization Controller (WANS)
The WANS provides hardware support to implement a local clock reference
compliant to SONET Stratum 3 clock specifications (GR-253-CORE & GR-1244CORE) in wander transfer, long term and holdover stability. The WANS is
intended to be used in conjunction with an external processor, DAC, analog
circuitry and VCXO. The software running on the external processor is
responsible for performing: digital loop filtering, temperature compensation,
VCXO linearity compensation; determining the validity of the timing reference;
and performing reference switchover if need be. A description of how to program
and use the WANS feature will be made available in the S/UNI-TETRA reference
design (PMC-980322). A description of the functionality supplied by the WANS
block is given below. The WANS block contains circuitry to implement a digital
phase comparison between the reference clock (RCLK) and the variable clock
(VCOCLK). It also performs an averaging process of the value obtained.
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Phase Comparison
The phase comparison between the reference clock (RCLK ) and the variable
clock (or VCXO clock, VCOCLK) is implemented by sampling at a fixed interval,
the Reference Period of Phase Counter output.
Figure 12. Phase Comparator Block Diagram
R C LK
R E FER E NC E
P E RIO D COU NT E R
PH ASE
C OU NTER
V CO CL K
RP H A LF LG
R
PH ASE
SAMPL E REG IST ER
EN
R E A CQ UISITION
C ON TR OL
SA MPLEN
RP H A LF LG
P H SAMP[1 5:0]
Successive reading of the value obtained, referred to as phase sample
(PHSAMP), can be used to calculate the phase relation between both clocks.
Both the Reference Counter and the Phase Counter are programmable counters
and are set to have equal cycle period. Therefore, if VCOCLK is locked to RCLK,
successive readings of the phase sample would be equal. The phase sample
value would increase or decrease depending if VOCLK is faster or slower that
RCLK.
The Reference Period is obtained by dividing RCLK. At each reference period, a
signal enabling the sampling (SAMPLEN) of the Phase Counter is produced. This
signal is resynchronized to VCOCLK to avoid any potential metastability problem
that could result from the asynchronous nature of both clocks.
10.16.1.1
Phase Reacquisition Control
The Phase Reacquisition Control circuit prevents using phase samples from both
sides of the counter wrap-around-point when performing the Phase Sample
averaging. The Phase Count is first divided into four quadrants, each equal to
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SATURN USER NETWORK INTERFACE (155-TETRA)
approximatively a quarter of the Phase Count. Comparators are used to
determine the quadrant that each phase sample is located. The Phase
Alignment Flag (RPHALFLG) is generated when a sample in the first quadrant is
followed successively by a sample in the last quadrant.
Upon reception of this signal, the Phase Counter is reset to align the phase count
sampling point towards its middle count. This signal is also sent to the Phase
Averager cicuit. The generation of this signal is user controllable by setting the
AUTOREAC bit of the WANS configuration register.
10.16.2
Phase Averager
To provide some noise immunity and improve the resolution of the phase
detector algorithm of the WANS, the phase samples are averaged over a
programmable number of samples.
Figure 13. Phase Averager Block Diagram
P H SAMP[1 5:0]
SAMPL E CO UN T ER
SAMPL EN
SAMPLEN
EN
EO C
SAMPL EN
EN
SAMPL E
A C CU MU LAT OR
R
P H ASE AVE R AGER
C ON TR OL
P H ASE W OR D
R E GISTE R
EN
R P HA L FLG
R P HA L GN
TIMFL G
P H AW OR D[3 0:0]
Although referred to as an averaging process, it is truly an accumulation process.
It retains full resolution, i.e. no division is performed on the accumulated value.
The Phase Word includes an integer and a fractional part. The number of
averaging samples sets the size of the fractional part.
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SATURN USER NETWORK INTERFACE (155-TETRA)
A programmable counter, the Sample Counter, is incremented at each SAMPLEN
signal. This Sample Counter defines the Phase Averaging Period, equal to the
Reference Period times the programmed number of phase samples. At the end
of this period, the accumulated phase sample value is transferred to the Phase
Word register. The Phase Word (PHAWORD) is then accessible for read
operations by an external processor. A timer flag (TIMFLG) is raised at the end of
the averaging period. The flag is used to generate an interrupt request to an
outside processor.
Because it indicates that the averaging process includes invalid sample values,
the reception of the RPHALFLG signal prevents the Phase Word register to be
updated at the end of the current Phase Averaging period. The RPHAFLG signal
will also send the Reference Phase Alignment condition signal (RPHALGN) to
the status register. The RPHALGN signal is reset at the end of the following valid
Phase Averaging period.
10.17 JTAG Test Access Port
The JTAG Test Access Port block provides JTAG support for boundary scan. The
standard JTAG EXTEST, SAMPLE, BYPASS, IDCODE and STCTEST
instructions are supported. The S/UNI-TETRA identification code is 053510CD
hexadecimal.
10.18 Microprocessor Interface
The microprocessor interface block provides normal and test mode registers, and
the logic required to connect to the microprocessor interface. The normal mode
registers are required for normal operation, and test mode registers are used to
enhance the testability of the S/UNI-TETRA. The register set is accessed as
shown in Table 6. In the following section every register is documented and
identified using the register number (REG #). The corresponding memory map
address for every channel (CH #1,2,3,4) is given in the table. Addresses that are
not shown are not used and must be treated as Reserved.
Table 6: Register Memory Map
REG
#
00
01
02
03
04
Address A[10:0]
CH
CH
CH
#1
#2
#3
000
001
002
003
004
Description
CH
#4
S/UNI-TETRA Master Reset and Identity
S/UNI-TETRA Master Configuration
S/UNI-TETRA Master System Interface Config
S/UNI-TETRA Master Clock Monitor
S/UNI-TETRA Master Interrupt Status
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REG
#
05
ISSUE 7
Address A[10:0]
CH
CH
CH
#1
#2
#3
005
105
205
SATURN USER NETWORK INTERFACE (155-TETRA)
Description
CH
#4
305
06
07
08
09
0A
0B
0C
0D
0E
0F
006
007
008
009
00A
00B
00C
00D
00E
00F
106
107
108
109
10A
10B
206
207
208
209
20A
20B
206
307
308
309
30A
30B
10E
10F
20E
20F
30E
30F
10
11
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
20
21
22
23
24
010
011
012
013
014
015
016
017
018
019
01A
01B
01C
01D
01E
01F
020
021
022
023
024
110
111
112
113
114
115
116
117
118
119
11A
11B
11C
11D
11E
11F
120
121
122
123
124
210
211
212
213
214
215
216
217
218
219
21A
21B
21C
21D
21E
21F
220
221
222
223
224
310
311
312
313
314
315
316
317
318
319
31A
31B
31C
31D
31E
31F
320
321
322
323
324
25
26
27
025
026
027
125
126
127
225
226
227
325
326
327
S/UNI-TETRA Channel Reset and Performance
Monitoring Update
S/UNI-TETRA Channel Configuration
S/UNI-TETRA Channel Control
S/UNI-TETRA Channel Control Extensions
Reserved
S/UNI-TETRA Channel Interrupt Status 1
S/UNI-TETRA Channel Interrupt Status 2
CSPI Control and Status (Clock Synthesis)
CSPI Reserved (Clock Synthesis)
CRSI Control and Status (Clock Recovery)
CRSI Reserved PLL Mode Select (Clock
Recovery)
RSOP Control/Interrupt Enable
RSOP Status/Interrupt Status
RSOP Section BIP-8 LSB
RSOP Section BIP-8 MSB
TSOP Control
TSOP Diagnostic
TSOP Reserved
TSOP Reserved
RLOP Control/Status
RLOP Interrupt Enable/Status
RLOP Line BIP-24 LSB
RLOP Line BIP-24
RLOP Line BIP-24 MSB
RLOP Line FEBE LSB
RLOP Line FEBE
RLOP Line FEBE MSB
TLOP Control
TLOP Diagnostic
TLOP Transmit K1
TLOP Transmit K2
S/UNI-TETRA Channel Transmit Synchronization
Message (S1)
S/UNI-TETRA Channel Transmit J0/Z0
Reserved
Reserved
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REG
#
28
29
2A
2B
2C
2D
2E
2F
30
30
31
31
32
33
33
34
35
36
37
38
39
3A
3B
3C
3D
3E
3F
40
41
42
43
44
45
46
47
48
49
4A
ISSUE 7
Address A[10:0]
CH
CH
CH
#1
#2
#3
028
128
228
029
129
229
02A
12A
22A
02B
12B
22B
02C
12C
22C
02D
12D
22D
02E
12E
22E
02F
12F
22F
030
130
230
030
130
230
031
131
231
031
131
231
032
132
232
033
133
233
033
133
233
034
134
234
035
135
235
036
136
236
037
137
237
038
138
238
039
139
239
03A
13A
23A
03B
13B
23B
03C
13C
23C
03D
13D
23D
03E
13E
23E
03F
13F
23F
040
140
240
041
141
241
042
142
242
043
143
243
044
144
244
045
145
245
046
146
246
047
147
247
048
148
248
049
149
249
04A
14A
24A
SATURN USER NETWORK INTERFACE (155-TETRA)
Description
CH
#4
328
329
32A
32B
32C
32D
32E
32F
330
330
331
331
332
333
333
334
335
336
337
338
339
33A
33B
33C
33D
33E
33F
340
341
342
343
344
345
346
347
348
349
34A
SSTB Control
SSTB Status
SSTB Indirect Address
SSTB Indirect Data
SSTB Reserved
SSTB Reserved
SSTB Reserved
SSTB Reserved
RPOP Status/Control (EXTD=0)
RPOP Status/Control (EXTD=1)
RPOP Interrupt Status (EXTD=0)
RPOP Interrupt Status (EXTD=1)
RPOP Pointer Interrupt Status
RPOP Interrupt Enable (EXTD=0)
RPOP Interrupt Enable (EXTD=1)
RPOP Pointer Interrupt Enable
RPOP Pointer LSB
RPOP Pointer MSB and RDI Filter Control
RPOP Path Signal Label
RPOP Path BIP-8 LSB
RPOP Path BIP-8 MSB
RPOP Path FEBE LSB
RPOP Path FEBE MSB
RPOP Auxiliary RDI
RPOP Path BIP-8 Configuration
RPOP Reserved
RPOP Reserved
TPOP Control/Diagnostic
TPOP Pointer Control
TPOP Reserved
TPOP Current Pointer LSB
TPOP Current Pointer MSB
TPOP Arbitrary Pointer LSB
TPOP Arbitrary Pointer MSB
TPOP Path Trace
TPOP Path Signal Label
TPOP Path Status
TPOP Reserved
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#
4B
4C
4D
4E
4F
50
51
52
53
54
55
56
57
58
59
5A
5B
5C
5D
5E
5F
60
61
62
63
64
65
66
67
68
69
6A
6B
6C
6D
6E
6F
70
ISSUE 7
Address A[10:0]
CH
CH
CH
#1
#2
#3
04B
14B
24B
04C
14C
24C
04D
14D
24D
04E
14E
24E
04F
14F
24F
050
150
250
051
151
251
052
152
252
053
153
253
054
154
254
055
155
255
056
156
256
057
157
257
058
158
258
059
159
259
05A
15A
25A
05B
15B
25B
05C
15C
25C
05D
15D
25D
05E
15E
25E
05F
15F
25F
060
160
260
061
161
261
062
162
262
063
163
263
064
164
264
065
165
265
066
166
266
067
167
267
068
168
268
069
169
269
06A
16A
26A
06B
16B
26B
06C
16C
26C
06D
16D
26D
06E
16E
26E
06F
16F
26F
070
170
270
SATURN USER NETWORK INTERFACE (155-TETRA)
Description
CH
#4
34B
34C
34D
34E
34F
350
351
352
353
354
355
356
357
358
359
35A
35B
35C
35D
35E
35F
360
361
362
363
364
365
366
367
368
369
36A
36B
36C
36D
36E
36F
370
TPOP Reserved
TPOP Reserved
TPOP Reserved
TPOP Reserved
TPOP Reserved
SPTB Control
SPTB Status
SPTB Indirect Address
SPTB Indirect Data
SPTB Expected Path Signal Label
SPTB Path Signal Label Status
SPTB Reserved
SPTB Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
RXCP Configuration 1
RXCP Configuration 2
RXCP FIFO/UTOPIA Control & Config
RXCP Interrupt Enables and Counter Status
RXCP Status/Interrupt Status
RXCP LCD Count Threshold (MSB)
RXCP LCD Count Threshold (LSB)
RXCP Idle Cell Header Pattern
RXCP Idle Cell Header Mask
RXCP Corrected HCS Error Count
RXCP Uncorrected HCS Error Count
RXCP Received Cell Count LSB
RXCP Received Cell Count
RXCP Received Cell Count MSB
RXCP Idle Cell Count LSB
RXCP Idle Cell Count
RXCP Idle Cell Count MSB
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Address A[10:0]
CH
CH
CH
#1
#2
#3
071
171
271
072
172
272
073
173
273
074
174
274
075
175
275
076
176
276
077
177
277
078
178
278
079
179
279
07A
17A
27A
07B
17B
27B
07C
17C
27C
07D
17D
27D
07E
17E
27E
07F
17F
27F
080
180
280
081
181
281
082
182
282
083
183
283
084
184
284
085
185
285
086
186
286
087
187
287
088
188
288
089
189
289
08A
18A
28A
08B
18B
28B
08C
18C
28C
08D
18D
28D
08E
18E
28E
08F
18F
28F
090
190
290
091
191
291
092
192
292
CH
#4
371
372
373
374
375
376
377
378
379
37A
37B
37C
37D
37E
37F
380
381
382
383
384
385
386
387
388
389
38A
38B
38C
38D
38E
38F
390
391
392
93
093
193
293
393
94
094
194
294
394
REG
#
71
72
73
74
75
76
77
78
79
7A
7B
7C
7D
7E
7F
80
81
82
83
84
85
86
87
88
89
8A
8B
8C
8D
8E
8F
90
91
92
SATURN USER NETWORK INTERFACE (155-TETRA)
Description
RXCP Reserved
RXCP Reserved
RXCP Reserved
RXCP Reserved
RXCP Reserved
RXCP Reserved
RXCP Reserved
RXCP Reserved
RXCP Reserved
RXCP Reserved
RXCP Reserved
RXCP Reserved
RXCP Reserved
RXCP Reserved
RXCP Reserved
TXCP Configuration 1
TXCP Configuration 2
TXCP Transmit Cell Status/Configuration Options
TXCP Interrupt Enable/Status
TXCP Idle Cell Header Control
TXCP Idle Cell Payload Control
TXCP Transmit Cell Counter LSB
TXCP Transmit Cell Counter
TXCP Transmit Cell Counter MSB
TXCP Reserved
TXCP Reserved
TXCP Reserved
TXCP Reserved
TXCP Reserved
TXCP Reserved
TXCP Reserved
S/UNI-TETRA Channel Auto Line RDI Control
S/UNI-TETRA Channel Auto Path RDI Control
S/UNI-TETRA Channel Auto Enhanced Path RDI
Control
S/UNI-TETRA Channel Receive RDI and
Enhanced RDI Control Extensions
S/UNI-TETRA Channel Receive Line AIS Control
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REG
#
95
96
97
98
99
9A
9B
9C
9D
9E
9F
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
AA
AB
AC
AD
AE
AF
B0
B1
B2
B3
B4
B5
B6
B7
B8
B9
BA
ISSUE 7
Address A[10:0]
CH
CH
CH
#1
#2
#3
095
195
295
096
196
296
097
197
297
098
198
298
099
199
299
09A
19A
29A
09B
19B
29B
09C
19C
29C
09D
19D
29D
09E
19E
29E
09F
19F
29F
0A0
1A0
2A0
0A1
1A1
2A1
0A2
1A2
2A2
0A3
1A3
2A3
0A4
1A4
2A4
0A5
1A5
2A5
0A6
1A6
2A6
0A7
1A7
2A7
0A8
1A8
2A8
0A9
1A9
2A9
0AA 1AA 2AA
0AB 1AB 2AB
0AC 1AC 2AC
0AD 1AD 2AD
0AE 1AE 2AE
0AF
1AF
2AF
0B0
1B0
2B0
0B1
1B1
2B1
0B2
1B2
2B2
0B3
1B3
2B3
0B4
1B4
2B4
0B5
1B5
2B5
0B6
1B6
2B6
0B7
1B7
2B7
0B8
1B8
2B8
0B9
1B9
2B9
0BA 1BA 2BA
SATURN USER NETWORK INTERFACE (155-TETRA)
Description
CH
#4
395
396
397
398
399
39A
39B
39C
39D
39E
39F
3A0
3A1
3A2
3A3
3A4
3A5
3A6
3A7
3A8
3A9
3AA
3AB
3AC
3AD
3AE
3AF
3B0
3B1
3B2
3B3
3B4
3B5
3B6
3B7
3B8
3B9
3BA
S/UNI-TETRA Channel Receive Path AIS Control
S/UNI-TETRA Channel Receive Alarm Control #1
S/UNI-TETRA Channel Receive Alarm Control #2
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
RXFP-50 Configuration
RXFP-50 Configuration/Interrupt Enables
RXFP-50 Interrupt Status
RXFP-50 Minimum Packet Size
RXFP-50 Maximum Packet Size (LSB)
RXFP-50 Maximum Packet Size (MSB)
RXFP-50 Receive Initiation Level
RXFP-50 Receive Packet Available High Mark
RXFP-50 Receive Byte Counter (LSB)
RXFP-50 Receive Byte Counter
RXFP-50 Receive Byte Counter
RXFP-50 Receive Byte Counter (MSB)
RXFP-50 Receive Frame Counter (LSB)
RXFP-50 Receive Frame Counter
RXFP-50 Receive Frame Counter (MSB)
RXFP-50 Aborted Frame Count (LSB)
RXFP-50 Aborted Frame Count (MSB)
RXFP-50 FCS Error Frame Count (LSB)
RXFP-50 FCS Error Frame Count (LSB)
RXFP-50 Min Length Frame Count (LSB)
RXFP-50 Min Length Frame Count (MSB)
RXFP-50 Max Length Frame Count (LSB)
RXFP-50 Max Length Frame Count (MSB)
RXFP-50 Reserved
RXFP-50 Reserved
RXFP-50 Reserved
RXFP-50 Reserved
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ISSUE 7
Address A[10:0]
CH
CH
CH
#1
#2
#3
0BB 1BB 2BB
0BC 1BC 2BC
0BD 1BD 2BD
0BE 1BE 2BE
0BF
1BF
2BF
0C0
1C0
2C0
0C1
1C1
2C1
0C2
1C2
2C2
0C3
1C3
2C3
CH
#4
3BB
3BC
3BD
3BE
3BF
3C0
3C1
3C2
3C3
C4
0C4
1C4
2C4
3C4
C5
C6
C7
C8
C9
CA
CB
CC
0C5
0C6
0C7
0C8
0C9
0CA
0CB
0CC
1C5
1C6
1C7
1C8
1C9
1CA
1CB
1CC
2C5
2C6
2C7
2C8
2C9
2CA
2CB
2CC
3C5
3C6
3C7
3C8
3C9
3CA
3CB
3CC
CD
0CD
1CD
2CD
3CD
CE
0CE
1CE
2CE
3CE
CF
0CF
1CF
2CF
3CF
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
DA
DB
0D0
0D1
0D2
0D3
0D4
0D5
0D6
0D7
0D8
0D9
0DA
0DB
1D0
1D1
1D2
1D3
1D4
1D5
1D6
1D7
1D8
1D9
1DA
1DB
2D0
2D1
2D2
2D3
2D4
2D5
2D6
2D7
2D8
2D9
2DA
2DB
3D0
3D1
3D2
3D3
3D4
3D5
3D6
3D7
3D8
3D9
3DA
3DB
REG
#
BB
BC
BD
BE
BF
C0
C1
C2
C3
SATURN USER NETWORK INTERFACE (155-TETRA)
Description
RXFP-50 Reserved
RXFP-50 Reserved
RXFP-50 Reserved
RXFP-50 Reserved
RXFP-50 Reserved
TXFP-50 Interrupt Enable/Status Configuration 1
TXFP-50 Configuration 2
TXFP-50 Control
TXFP-50 Transmit Packet Available Low Water
Mark
TXFP-50 Transmit Packet Available High Water
Mark
TXFP-50 Transmit Byte Counter (LSB)
TXFP-50 Transmit Byte Counter
TXFP-50 Transmit Byte Counter
TXFP-50 Transmit Byte Counter (MSB)
TXFP-50 Transmit Frame Counter (LSB)
TXFP-50 Transmit Frame Counter
TXFP-50 Transmit Frame Counter (MSB)
TXFP-50 Transmit User Aborted Frame Count
(LSB)
TXFP-50 Transmit User Aborted Frame Count
(MSB)
TXFP-50 Transmit FIFO Error Aborted Frame
Count (LSB)
TXFP-50 Transmit FIFO Error Aborted Frame
Count (MSB)
WANS Configuration Register
WANS Interrupt & Status Register
WANS Phase Word (LSB)
WANS Phase Word
WANS Phase Word
WANS Phase Word (MSB)
WANS Reserved
WANS Reserved
WANS Reserved
WANS Reference Period (LSB)
WANS Reference Period (MSB)
WANS Phase Counter Period (LSB)
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REG
#
DC
DD
DE
DF
E0
E1
E2
E3
E4
E5
E6
E7
E8
E9
EA
EB
EC
ED
EE
EF
F0
F1
F2
F3
F4
F5
F6
F7
F8
F9
FA
FB
FC
FD
FE
FF
Address A[10:0]
CH
CH
CH
#1
#2
#3
0DC 1DC 2DC
0DD 1DD 2DD
0DE 1DE 2DE
0DF 1DF 2DF
0E0
1E0
2E0
0E1
1E1
2E1
0E2
1E2
2E2
0E3
1E3
2E3
0E4
1E4
2E4
0E5
1E5
2E5
0E6
1E6
2E6
0E7
1E7
2E7
0E8
1E8
2E8
0E9
1E9
2E9
0EA 1EA 2EA
0EB 1EB 2EB
0EC 1EC 2EC
0ED 1ED 2ED
0EE 1EE 2EE
0EF
1EF
2EF
0F0
1F0
2F0
0F1
1F1
2F1
0F2
1F2
2F2
0F3
1F3
2F3
0F4
1F4
2F4
0F5
1F5
2F5
0F6
1F6
2F6
0F7
1F7
2F7
0F8
1F8
2F8
0F9
1F9
2F9
0FA
1FA
2FA
0FB
1FB
2FB
0FC 1FC 2FC
0FD 1FD 2FD
0FE
1FE
2FE
0FF
1FF
2FF
400
401
501
601
ISSUE 7
SATURN USER NETWORK INTERFACE (155-TETRA)
Description
CH
#4
3DC
3DD
3DE
3DF
3E0
3E1
3E2
3E3
3E4
3E5
3E6
3E7
3E8
3E9
3EA
3EB
3EC
3ED
3EE
3EF
3F0
3F1
3F2
3F3
3F4
3F5
3F6
3F7
3F8
3F9
3FA
3FB
3FC
3FD
3FE
3FF
701
WANS Phase Counter Period (MSB)
WANS Phase Average Period
WANS Reserved
WANS Reserved
RASE Interrupt Enable
RASE Interrupt Status
RASE Configuration/Control
RASE SF BERM Accumulation Period (LSB)
RASE SF BERM Accumulation Period
RASE SF BERM Accumulation Period (MSB)
RASE SF BERM Saturation Threshold (LSB)
RASE SF BERM Saturation Threshold (MSB)
RASE SF BERM Declaring Threshold (LSB)
RASE SF BERM Declaring Threshold (MSB)
RASE SF BERM Clearing Threshold (LSB)
RASE SF BERM Clearing Threshold (MSB)
RASE SD BERM Accumulation Period (LSB)
RASE SD BERM Accumulation Period
RASE SD BERM Accumulation Period (MSB)
RASE SD BERM Saturation Threshold (LSB)
RASE SD BERM Saturation Threshold (MSB)
RASE SD BERM Declaring Threshold (LSB)
RASE SD BERM Declaring Threshold (MSB)
RASE SD BERM Clearing Threshold (LSB)
RASE SD BERM Clearing Threshold (MSB)
RASE APS K1
RASE APS K2
RASE Synchronization Status S1
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
S/UNI-TETRA Master Test Register
Reserved for Test
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REG
#
ISSUE 7
Address A[10:0]
CH
CH
CH
#1
#2
#3
4FF
5FF
6FF
SATURN USER NETWORK INTERFACE (155-TETRA)
Description
CH
#4
7FF
Notes on Register Memory Map:
•
For all register accesses, CSB must be low.
•
Addresses that are not shown must be treated as Reserved.
•
A[10] is the test resister select (TRS) and should be set to logic zero for
normal mode register access.
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11 NORMAL MODE REGISTER DESCRIPTION
Normal mode registers are used to configure and monitor the operation of the
S/UNI-TETRA. Normal mode registers (as opposed to test mode registers) are
selected when TRS (A[10]) is low.
Notes on Normal Mode Register Bits:
1. Writing values into unused register bits has no effect. However, to ensure
software compatibility with future, feature-enhanced versions of the product,
unused register bits must be written with logic zero. Reading back unused
bits can produce either a logic one or a logic zero; hence, unused register bits
should be masked off by software when read.
2. All Most configuration bits that can be written into can also be read back. This
allows the processor controlling the S/UNI-TETRA to determine the
programming state of the block. Exceptions to this rule are indicated by the
Type field in the register description.
3. Writable normal mode register bits are cleared to logic zero upon reset unless
otherwise noted.
4. Writing into read-only normal mode register bit locations does not affect
S/UNI-TETRA operation unless otherwise noted. Performance monitoring
counters registers are a common exception.
5. Certain register bits are reserved. These bits are associated with megacell
functions that are unused in this application. To ensure that the
S/UNI-TETRA operates as intended, reserved register bits must be written
with their default value as indicated by the register bit description.
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Register 0x00: S/UNI-TETRA Master Reset and Identity
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Type
R/W
R
R
R
R
R
R
R
Function
RESET
TYPE[3]
TYPE[2]
TYPE[1]
TYPE[0]
ID[2]
ID[1]
ID[0]
Default
0
1
1
1
1
0
1
0
This register allows the revision of the S/UNI-TETRA to be read by software
permitting graceful migration to support newer feature enhanced versions of the
S/UNI-TETRA. It also provides software reset capability.
ID[2:0]:
The ID bits can be read to provide a binary S/UNI-TETRA revision number.
TYPE[3:0]:
The TYPE bits distinguish the S/UNI-TETRA from the other members of the
S/UNI family of devices.
RESET:
The RESET bit allows the S/UNI-TETRA to be reset under software control. If
the RESET bit is a logic one, the entire S/UNI-TETRA is held in reset. This bit
is not self-clearing. Therefore, a logic zero must be written to bring the
S/UNI-TETRA out of reset. Holding the S/UNI-TETRA in a reset state places
it into a low power, stand-by mode. A hardware reset clears the RESET bit,
thus negating the software reset. Otherwise, the effect of a software reset is
equivalent to that of a hardware reset.
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Register 0x01: S/UNI-TETRA Master Configuration
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Function
PECLV
Reserved
TFPO_CH[1]
TFPO_CH[0]
TXC_OE
Reserved
Reserved
Reserved
Default
0
0
0
0
0
0
1
1
TXC_OE:
The differential line rate clock output enable (TXC_OE). TXC_OE enables the
TXC+/- outputs. When TXC_OE is set to logic zero TXC+/- is not active (high
impedance). When TXC_OE is set to logic one, TXC+/- provides a line rate
clock output.
TFPO_CH[1:0]:
The transmit frame pulse channel select (TFPO_CH[1:0]) bits selects which
channel’s transmit frame pulse is available on the TFPO output pin. Since the
RFPO1-4 output pins are providing transmit timing information for loop-timed
channels, it is suggested (but not mandatory) that a self-timed channel be
selected. Self-timed channels all operate off the same clock synthesis unit
and thus have a common timing reference (their frequency will be identical
although their frame pulses might not be aligned).
Table 8: TFPO Channel Selection
TFPO_CH[1:0]
Selected Channel
00
Channel #1
01
Channel #2
10
Channel #3
11
Channel #4
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PECLV:
The PECL reveiver input voltage (PECLV) bit configures the PECL receiver
level shifter. When PECLV is set to logic zero, the PECL receivers are
configured to operate with a 3.3V input voltage. When PECLV is set to logic
one, the PECL receivers are configured to operate with a 5.0V input voltage.
Reserved:
The reserved bits must be programmed to their default value proper
operation.
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Register 0x02: S/UNI-TETRA Master System Interface Control
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Function
PHY_ADR[2]
PHY_ADR[1]
PHY_ADR[0]
PHY_EN
Unused
Reserved
POS_PLVL
ATM_POS
Default
0
0
0
0
X
0
0
0
ATM_POS:
The ATM_POS bit selects between the ATM and Packet over SONET/SDH
modes of operation. When ATM_POS is set to logic zero, the device
implements the ATM physical layer. When ATM_POS is set to logic one, the
device implement the Packet over SONET/SDH physical layer. This register
bit affects the SONET/SDH mapping as well as the pin definition on the
System Interface (Utopia) bus.
POS_PLVL:
The POS_PLVL bit selects between byte-level and packet-level transfer when
the device is in POS mode (as selected by the ATM_POS bit). When
POS_PLVL is set to logic zero, the device operates in byte-level transfer
mode. When POS_PLVL is set to logic one, the device operates in packetlevel transfer mode. Refer to the OPERATIONS section for a description of
these modes. PHY_EN:
The PHY_EN enables the System Interface (Utopia bus). When set to logic
zero, all the output signals of the System Interface are held in high impedance
with the exception of TPA and RPA which can still be driven. When set to logic
one, the System Interface is driven. This register bit must be set to logic one
to start using the device. If the System Interface is shared by several PHY
layer devices, they should all be configured with their own unique
PHY_ADR[2:0] (see below) value before enabling them, otherwise conflicts
could occur on the bus resulting in damages to the devices.
PHY_ADR[2:0]:
The PHY_ADR[2:0] is Device Identification Address (PHY_ADR[2:0]). The
PHY_ADR[2:0] register bits are the most-significant bits of the address space
which this S/UNI-TETRA occupies. When the PHY_ADR[2:0] inputs match
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the TADR[4:2] or RADR[4:2] inputs, then one of the four quadrants (as
determined by the TADR[1:0] or RADR[1:0] inputs) in this S/UNI-TETRA is
selected for transmit or receive operations. Note that the null-PHY address
0x1F is the null-PHY address and cannot be assigned to any port on the
S/UNI-TETRA.
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Register 0x03: S/UNI-TETRA Master Clock Monitor
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Type
R
R
R
R
R
R
R
R
Function
RCLK4A
RCLK3A
RCLK2A
RCLK1A
TCLKA
RFCLKA
TFCLKA
REFCLKA
Default
X
X
X
X
X
X
X
X
This register provides activity monitoring on S/UNI-TETRA clocks. When a
monitored clock signal makes a low to high transition, the corresponding register
bit is set high. The bit will remain high until this register is read, at which point, all
the bits in this register are cleared. A lack of transitions is indicated by the
corresponding register bit reading low. This register should be read at periodic
intervals to detect clock failures.
REFCLKA:
The REFCLK active (REFCLKA) bit monitors for low to high transitions on the
REFCLK reference clock input. REFCLKA is set high on a rising edge of
REFCLK, and is set low when this register is read.
TFCLKA:
The TFCLK active (TFCLKA) bit monitors for low to high transitions on the
TFCLK transmit FIFO clock input. TFCLKA is set high on a rising edge of
TFCLK, and is set low when this register is read.
RFCLKA:
The RFCLK active (RFCLKA) bit monitors for low to high transitions on the
RFCLK receive FIFO clock input. RFCLKA is set high on a rising edge of
RFCLK, and is set low when this register is read.
TCLKA:
The TCLK active (TCLKA) bit monitors for low to high transitions on the TCLK
output. TCLKA is set high on a rising edge of TCLK, and is set low when this
register is read.
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RCLK1A:
The Channel #1 RCLK active (RCLK1A) bit monitors for low to high
transitions on the RCLK1 output. RCLK1A is set high on a rising edge of
RCLK1, and is set low when this register is read.
RCLK2A:
The Channel #2 RCLK active (RCLK2A) bit monitors for low to high
transitions on the RCLK2 output. RCLK2A is set high on a rising edge of
RCLK2, and is set low when this register is read.
RCLK3A:
The Channel #3 RCLK active (RCLK3A) bit monitors for low to high
transitions on the RCLK3 output. RCLK3A is set high on a rising edge of
RCLK3, and is set low when this register is read.
RCLK4A:
The Channel #4 RCLK active (RCLK4A) bit monitors for low to high
transitions on the RCLK4 output. RCLK4A is set high on a rising edge of
RCLK4, and is set low when this register is read.
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Register 0x04: S/UNI-TETRA Master Interrupt Status
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Type
R
R
R
R
R
Function
Unused
Unused
Unused
CSUI
CHNL4I
CHNL3I
CHNL2I
CHNL1I
Default
X
X
X
X
X
X
X
X
When the interrupt output INTB goes low, this register allows the source of an
active interrupt to be identified down to the channel level. Further register
accesses are required for the channel in question to determine the cause of an
active interrupt and to acknowledge the interrupt source.
CHNL1I:
The CHNL1I bit is high when an interrupt request is active from the channel
#1. The Channel #1 Interrupt Status register should be read to identify the
source of the interrupt.
CHNL2I:
The CHNL2I bit is high when an interrupt request is active from the channel
#2. The Channel #2 Interrupt Status register should be read to identify the
source of the interrupt.
CHNL3I:
The CHNL3I bit is high when an interrupt request is active from the channel
#3. The Channel #3 Interrupt Status register should be read to identify the
source of the interrupt.
CHNL4I:
The CHNL4I bit is high when an interrupt request is active from the channel
#4. The Channel #4 Interrupt Status register should be read to identify the
source of the interrupt.
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CSUI:
The CSUI bit is high when an interrupt request is active from the Clock
Synthesis and PISO block (CSPI, Clock Synthesis Unit). The CSUI interrupt
sources are enabled in the Clock Synthesis Interrupt Control/Status Register.
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Register 0x05: S/UNI-TETRA Channel Reset and Monitoring Update
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Type
R/W
R
Function
CHRESET
Unused
Unused
Unused
Unused
Unused
Unused
TIP
Default
0
X
X
X
X
X
X
X
This register provides software reset capability on a per channel basis. It also
loads, by writing this register (without setting the CHRESET bit), all the error
counters in the RSOP, RLOP, RPOP, SPTB, SSTB, RXCP, TXCP, RXFP and
TXFP blocks.
TIP:
The TIP bit is set to a logic one when any value with the CHRESET bit set to
logic zero is written to this register. Such a write initiates an accumulation
interval transfer and loads all the performance meter registers in the RSOP,
RLOP, RPOP, SSTB, SPTB, RXCP, TXCP, RXFP and TXFP blocks for
channel #1. TIP remains high while the transfer is in progress, and is set to a
logic zero when the transfer is complete. TIP can be polled by a
microprocessor to determine when the accumulation interval transfer is
complete.
CHRESET:
The CHRESET bit allows the Channel to be reset under software control. If
the CHRESET bit is a logic one, the entire channel is held in reset. This bit is
not self-clearing. Therefore, a logic zero must be written to bring the channel
out of reset. Holding a channel in a reset state places it into a low power,
stand-by mode. A hardware reset clears the CHRESET bit, thus negating the
software reset. Otherwise, the effect of a software reset is equivalent to that
of a hardware reset. Setting the Channel Reset and Monitoring Update
register for channel 1 (Register 0x05) blocks access to the global registers
0x00 to 0x04. Setting the Channel Reset for channels 2 through 4 has no
effect on global registers.
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Register 0x06: S/UNI-TETRA Channel Configuration
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Function
AUTOPFEBE
AUTOLFEBE
AUTOLRDI
AUTOPRDI
TPTBEN
TSTBEN
Z0INS
Reserved
Default
1
1
1
1
0
0
0
1
Z0INS:
The Z0INS bit controls the values inserted in the transmit Z0 bytes. When
Z0INS is logic 1, the value contained in the TSOP Transmit Z0 register is
inserted in the two Z0 bytes. When Z0INS is logic 0, the values 02H and 03H
are inserted in Z0 byte of 2nd and 3rd STS-1 (STM-0/AU3) respectively.
TSTBEN:
The TSTBEN bit controls whether the section trace message stored in the
SSTB block is inserted into the transmit stream (i.e. the J0 byte). When
TSTBEN is a logic one, the message stored in the SSTB is inserted into the
transmit stream. When TSTBEN is a logic zero, the section trace message is
supplied by the TSOP block which forces it to the NULL character (0x00)
TPTBEN:
The TPTBEN bit controls whether the path trace message stored in the SPTB
block is inserted into the transmit stream (i.e. the J1 byte). When TPTBEN is
a logic one, the message stored in the SPTB is inserted into the transmit
stream. When TPTBEN is a logic zero, the path trace message is supplied by
the TPOP block which forces it to a programmable value.
AUTOPRDI
The AUTOPRDI bit determines whether STS path remote defect indication
(RDI) is sent immediately upon detection of an incoming alarm. When
AUTOPRDI is set to logic one, STS path RDI is inserted immediately upon
declaration of several alarms. Each alarm can individually be enabled and
disabled using the S/UNI-TETRA Channel Auto Path RDI Control Registers.
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AUTOLRDI
The AUTOLRDI bit determines if line remote defect indication (RDI) is sent
immediately upon detection of an incoming alarm. When AUTOLRDI is set to
logic one, line RDI is inserted immediately upon declaration of several
alarms. Each alarm can individually be enabled and disabled using the S/UNITETRA Channel Auto Line RDI Control Registers.
AUTOPFEBE
The AUTOPFEBE bit determines if the path far end block errors are sent upon
detection of an incoming path BIP error events. When AUTOPFEBE is set to
logic one, one path FEBE is inserted for each path BIP error event,
respectively. When AUTOPFEBE is set to logic zero, incoming path BIP error
events do not generate FEBE events.
AUTOLFEBE
The AUTOLFEBE bit determines if line far end block errors are sent upon
detection of an incoming line BIP error events. When AUTOLFEBE is set to
logic one, one line FEBE is inserted for each line BIP error event,
respectively. When AUTOLFEBE is set to logic zero, incoming line BIP error
events do not generate FEBE events.
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Register 0x07: S/UNI-TETRA Channel Control
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Function
TFPI_EN
Reserved
RXDINV
Unused
PDLE
LLE
SDLE
LOOPT
Default
0
0
0
X
0
0
0
0
This register controls the timing and high speed loopback features of the
S/UNI-TETRA.
LOOPT:
The LOOPT bit selects the source of timing for the transmit section of the
channel. When LOOPT is a logic zero, the transmitter timing is derived from
input REFCLK (Clock Synthesis Unit) is used. When LOOPT is a logic one,
the transmitter timing is derived from the recovered clock. (Clock Recovery
Unit).
SDLE:
The SDLE bit enables the serial diagnostic loopback. When SDLE is a logic
one, the transmit serial stream is connected to the receive stream. The SDLE
and the LLE bits should not be set high simultaneously.
LLE:
The LLE bit enables the S/UNI-TETRA line loopback. When LLE is a logic
one, the value on RXD+/- differential inputs is synchronously mapped to the
TXD+/- differential outputs, after clock recovery. The SDLE and the LLE bits
should not be set high simultaneously.
PDLE:
The PDLE bit enables the parallel diagnostic loopback. When PDLE is a logic
one, the transmit parallel stream is connected to the receive stream. The
loopback point is between the TPOP and the RPOP blocks. Blocks upstream
of the loopback point continue to operate normally. For example line AIS may
be inserted in the transmit stream upstream of the loopback point using the
TSOP Control register.
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RXDINV:
The RXDINV bit selects the active polarity of the RXD+/- signals. The default
configuration selects RXD+ to be active high and RXD- to be active low.
When RXDINV is set to logic one, RXD+ to be active low and RXD- to be
active high.
TFPI_EN:
The TFPI_EN bit controls the framing alignment in the transmit direction.
When TFPI_EN is set to logic one the transmit SONET/SDH framing is
aligned to a master (available to all four channels) framing pulse counter,
which can also be aligned to the TFPI device input. When TFPI_EN is set to
logic zero the transmit framing alignment is arbitrary. External framing
(TFPI_EN set to logic one) shall only be used when the channel is in selftimed mode. TFPI_EN should always be set to logic zero when the channel is
loop-timed (LOOPT set to logic one) or in line loopback (LLE set to logic one).
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Register 0x08: S/UNI-TETRA Channel Control Extension
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Type
R/W
R/W
R/W
Function
Unused
Unused
Unused
Unused
Unused
Reserved
Reserved
Reserved
Default
X
X
X
X
X
0
0
0
This register controls the timing and high speed loopback features of the
S/UNI-TETRA.
Reserved:
The reserved bits must be programmed to their default value proper
operation.
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Register 0x0A: S/UNI-TETRA Channel Interrupt Status #1
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Type
R
R
R
R
R
R
R
Function
Unused
RASEI
CRUI
TXCPI
RXCPI
RPOPI
RLOPI
RSOPI
Default
X
X
X
X
X
X
X
X
This register allows the source of an active interrupt to be identified down to the
block level within a given channel. Further register accesses are required for the
block in question to determine the cause of an active interrupt and to
acknowledge the interrupt source.
RSOPI:
The RSOPI bit is high when an interrupt request is active from the RSOP
block. The RSOP interrupt sources are enabled in the RSOP
Control/Interrupt Enable Register.
RLOPI:
The RLOPI bit is high when an interrupt request is active from the RLOP
block. The RLOP interrupt sources are enabled in the RLOP Interrupt
Enable/Status Register.
RPOPI:
The RPOPI bit is high when an interrupt request is active from the RPOP
block. The RPOP interrupt sources are enabled in the RPOP Interrupt Enable
Register.
RXCPI:
The RXCPI bit is high when an interrupt request is active from the RXCP
block. The RXCP interrupt sources are enabled in the RXCP Interrupt
Enable/Status Register.
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TXCPI:
The TXCPI bit is high when an interrupt request is active from the TXCP
block. The TXCP interrupt sources are enabled in the TXCP Interrupt
Control/Status Register.
CRUI:
The CRUI bit is high when an interrupt request is active from the Clock
Recovery and SIPO block (CRSI, Clock Recovery Unit). The CRUI interrupt
sources are enabled in the Clock Recovery Interrupt Control/Status Register.
RASEI:
The RASEI bit is high when an interrupt request is active from the RASE
block. The RASE interrupt sources are enabled in the RASE Interrupt Enable
Register.
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Register 0x0B: S/UNI-TETRA Channel Interrupt Status #2
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Type
R
R
R
R
R
Function
Unused
Unused
Unused
TXFPI
RXFPI
WANSI
SSTBI
SPTBI
Default
X
X
X
X
X
X
X
X
This register allows the source of an active interrupt to be identified down to the
block level within a given channel. Further register accesses are required for the
block in question to determine the cause of an active interrupt and to
acknowledge the interrupt source.
SPTBI:
The SPTBI bit is a logic one when an interrupt request is active from the
SPTB block. The SPTB interrupt sources are enabled in the SPTB Control
Register and the SPTB Path Signal Label Status Register.
SSTBI:
The SSTBI bit is a logic one when an interrupt request is active from the
SSTB block. The SSTB interrupt sources are enabled in the SSTB Control
Register and the SSTB Synchronization Message Status Register.
WANSI:
The WANSI bit is a logic one when an interrupt request is active from the
WANS block. The WANS interrupt sources are enabled in the WANS
Interrupt Enable/Status Register.
RXFPI:
The RXFPI bit is high when an interrupt request is active from the RXFP
block. The RXFP interrupt sources are enabled in the RXFP Interrupt
Enable/Status Register.
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TXFPI:
The TXFPI bit is high when an interrupt request is active from the TXFP block.
The TXFP interrupt sources are enabled in the TXFP Interrupt Control/Status
Register.
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Register 0x0C: CSPI (Clock Synthesis) Control and Status
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Type
R/W
R/W
R
R
R/W
R/W
Function
Reserved
Reserved
TROOLI
Unused
TROOLV
Unused
TROOLE
Reserved
Default
0
0
X
X
X
X
0
0
This register controls the clock synthesis and reports the state of the transmit
phase locked loop.
TROOLE:
The TROOLE bit is an interrupt enable for the transmit reference out of lock
status. When TROOLE is set to logic one, an interrupt is generated when the
TROOLV bit changes state.
TROOLV:
The transmit reference out of lock status indicates the clock synthesis phase
locked loop is unable to lock to the reference on REFCLK. TROOLV is a logic
one if the divided down synthesized clock frequency is not within 488 ppm of
the REFCLK frequency.
TROOLI:
The TROOLI bit is the transmit reference out of lock interrupt status bit.
TROOLI is set high when the TROOLV bit of the S/UNI-TETRA Clock
Synthesis Control and Status register changes state. TROOLV indicates the
clock synthesis phase locked loop is unable to lock to the reference on
REFCLK and is a logic one if the divided down synthesized clock frequency is
not within 488 ppm of the REFCLK frequency. TROOLI is cleared when this
register is read.
Reserved:
The reserved bits must be programmed to logic zero for proper operation.
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Register 0x0D: CSPI (Clock Synthesis) Reserved
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Type
R/W
R/W
R/W
R/W
Function
Unused
Unused
Unused
Unused
Reserved
Reserved
Reserved
Reserved
Default
X
X
X
X
0
0
0
0
Reserved:
The reserved bits must be programmed to logic zero for proper operation.
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Register 0x0E: CRSI (Clock Recovery) Control and Status
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Type
R/W
R
R
R
R
R/W
R/W
R/W
Function
Reserved
RROOLI
RDOOLI
RROOLV
RDOOLV
RROOLE
RDOOLE
Reserved
Default
0
X
X
X
X
0
0
0
This register controls the clock recovery and reports the state of the receive
phase locked loop.
RDOOLE:
The RDOOLE bit is an interrupt enable for the receive data out of lock status.
When RDOOLE is set to logic one, an interrupt is generated when the
RDOOLV bit changes state.
RROOLE:
The RROOLE bit is an interrupt enable for the reference out of lock status.
When RROOLE is set to logic one, an interrupt is generated when the
RROOLV bit changes state.
RDOOLV:
The receive data out of lock status indicates the clock recovery phase locked
loop is unable to lock to the incoming data stream. RDOOLV is a logic one if
the divided down recovered clock frequency is not within 488 ppm of the
REFCLK frequency or if no transitions have occurred on the RXD+/- inputs for
more than 80 bit periods.
RROOLV:
The receive reference out of lock status indicates the clock recovery phase
locked loop is unable to lock to the receive reference (REFCLK). RROOLV
should be polled after a power up reset to determine when the CRU PLL is
operational. When RROOLV is a logic one, the CRU is unable to lock to the
receive reference. When RROOLV is a logic zero, the CRU is locked to the
receive reference. The RROOLV bit may remain set at logic one for several
hundred milliseconds after the removal of the power on reset as the CRU PLL
locks to the receive reference clock.
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RDOOLI:
The RDOOLI bit is the receive data out of lock interrupt status bit. RDOOLI is
set high when the RDOOLV bit of the S/UNI-TETRA Clock Recovery Control
and Status register changes state. RDOOLI is cleared when this register is
read.
RROOLI:
The RROOLI bit is the receive reference out of lock interrupt status bit.
RROOLI is set high when the RROOLV bit of the Clock Synthesis Control and
Status register changes state. RROOLI is cleared when this register is read.
LANB_WAN:
When LANB_WAN set high, WAN mode is selected and the device is able to
meet the jitter transfer requirement. When LANB_WAN set low, LAN mode is
selected and the jitter tolerance and noise tolerance will be improved.
Reserved:
The reserved bits must be programmed to logic zero for proper operation.
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Register 0x0F: CRSI (Clock Recovery) PLL Mode Select Reserved
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Type
Function
Default
R/W
Reserved
0
R/W
Reserved
0
R/WPERFCTRLReserved 0
R/W
Reserved
0
R/W
Reserved
0
R/W
Reserved
0
R/W
Reserved
0
R/W
Reserved
0
PERFCTRL:
The Phase Lock Loop Performance Control (PERFCTRL) register bit allows
controlling the frequency response of the clock recovery unit. When
PERFCTRL is set to logic 0, the CRU performance is optimized for jitter
transfer at the expense of jitter tolerance. When PERFCTRL is set to logic 1,
the CRU performance is optimized for jitter tolerance at the expense of jitter
transfer. This bit should not be set to a logic 1, when there areis an external
capacitors attached to the CN1,2,3,4 and CP1,2,3,4 pins.
Reserved:
The reserved bits must be programmed to logic zero for proper operation.
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Register 0x10: RSOP Control/Interrupt Enable
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Type
R/W
R/W
W
R/W
R/W
R/W
R/W
R/W
Function
BIPWORD
DDS
FOOF
ALGO2
BIPEE
LOSE
LOFE
OOFE
Default
0
0
X
0
0
0
0
0
OOFE:
The OOFE bit is an interrupt enable for the out of frame alarm. When OOFE
is set to logic one, an interrupt is generated when the out of frame alarm
changes state.
LOFE:
The LOFE bit is an interrupt enable for the loss of frame alarm. When LOFE
is set to logic one, an interrupt is generated when the loss of frame alarm
changes state.
LOSE:
The LOSE bit is an interrupt enable for the loss of signal alarm. When LOSE
is set to logic one, an interrupt is generated when the loss of signal alarm
changes state.
BIPEE:
The BIPEE bit is an interrupt enable for the section BIP-8 errors. When
BIPEE is set to logic one, an interrupt is generated when a section BIP-8 error
(B1) is detected.
ALGO2:
The ALGO2 bit position selects the framing algorithm used to confirm and
maintain the frame alignment. When a logic one is written to the ALGO2 bit
position, the framer is enabled to use the second of the framing algorithms
where only the first A1 framing byte and the first 4 bits of the last A2 framing
byte (12 bits total) are examined. This algorithm examines only 12 bits of the
framing pattern regardless of the STS mode; all other framing bits are
ignored. When a logic zero is written to the ALGO2 bit position, the framer is
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enabled to use the first of the framing algorithms where all the A1 framing
bytes and all the A2 framing bytes are examined. This algorithm examines all
48 bits of the STS-3c (STM-1/AU3/AU4) framing pattern.
FOOF:
The FOOF bit controls the framing of the RSOP. When a logic one is written
to FOOF, the RSOP is forced out of frame at the next frame boundary. The
FOOF bit is a write only bit, register reads may yield a logic one or a logic
zero.
DDS:
The DDS bit is set to logic one to disable the de-scrambling of the STS-3c
(STM-1) stream. When DDS is a logic zero, de-scrambling is enabled.
BIPWORD:
The BIPWORD bit position enables the accumulating of section block BIP
errors. When a logic one is written to the BIPWORD bit position, one or more
errors in the BIP-8 byte result in a single error accumulated in the B1 error
counter. When a logic zero is written to the BIPWORD bit position, all errors
in the B1 byte are accumulated in the B1 error counter.
Reserved:
The reserved bits must be programmed to logic zero for proper operation.
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Register 0x11: RSOP Status/Interrupt Status
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Type
R
R
R
R
R
R
R
Function
Unused
BIPEI
LOSI
LOFI
OOFI
LOSV
LOFV
OOFV
Default
X
X
X
X
X
X
X
X
OOFV:
The OOFV bit is read to determine the out-of-frame state of the RSOP. When
OOFV is high, the RSOP is out of frame. When OOFV is low, the RSOP is inframe.
LOFV:
The LOFV bit is read to determine the loss of frame state of the RSOP. When
LOFV is high, the RSOP has declared loss of frame.
LOSV:
The LOSV bit is read to determine the loss of signal state of the RSOP. When
LOSV is high, the RSOP has declared loss of signal.
OOFI:
The OOFI bit is the out of frame interrupt status bit. OOFI is set high when a
change in the out-of-frame state occurs. This bit is cleared when this register
is read.
LOFI:
The LOFI bit is the loss of frame interrupt status bit. LOFI is set high when a
change in the loss-of-frame state occurs. This bit is cleared when this register
is read.
LOSI:
The LOSI bit is the loss of signal interrupt status bit. LOSI is set high when a
change in the loss-of-signal state occurs. This bit is cleared when this
register is read.
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BIPEI:
The BIPEI bit is the section BIP-8 interrupt status bit. BIPEI is set high when
a section layer (B1) bit error is detected. This bit is cleared when this register
is read.
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Register 0x12: RSOP Section BIP-8 LSB
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Type
R
R
R
R
R
R
R
R
Function
SBE[7]
SBE[6]
SBE[5]
SBE[4]
SBE[3]
SBE[2]
SBE[1]
SBE[0]
Default
X
X
X
X
X
X
X
X
Register 0x13: RSOP Section BIP-8 MSB
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Type
R
R
R
R
R
R
R
R
Function
SBE[15]
SBE[14]
SBE[13]
SBE[12]
SBE[11]
SBE[10]
SBE[9]
SBE[8]
Default
X
X
X
X
X
X
X
X
SBE[15:0]:
Bits SBE[15:0] represent the number of section BIP-8 errors (individual or
block) that have been detected since the last time the error count was polled.
The error count is polled by writing to either of the RSOP Section BIP-8
Register addresses. Such a write transfers the internally accumulated error
count to the Section BIP-8 registers within approximately 7 µs and
simultaneously resets the internal counter to begin a new cycle of error
accumulation. This transfer and reset is carried out in a manner that ensures
that coincident events are not lost.
The count can also be polled by writing to the Master Reset and Identity /
Load Performance Meters register (0x05). Writing to register 0x05
simultaneously loads all the performance meter registers in the RSOP, RLOP,
RPOP, SPTB, SSTB, RXCP, TXCP, RXFP, and TXFP blocks.
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Register 0x14: TSOP Control
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Function
Unused
DS
Reserved
Reserved
Reserved
Reserved
Reserved
LAIS
Default
X
0
0
0
0
0
0
0
LAIS:
The LAIS bit controls the insertion of line alarm indication signal (AIS). When
LAIS is set to logic one, the TSOP inserts AIS into the transmit SONET/SDH
stream. Activation or deactivation of line AIS insertion is synchronized to
frame boundaries. Line AIS insertion results in all bits of the SONET/SDH
frame being set to one prior to scrambling except for the section overhead.
DS:
The DS bit is set to logic one to disable the scrambling of the STS-3c (STM-1)
stream. When DS is a logic zero, scrambling is enabled.
Reserved:
The reserved bits must be programmed to logic zero for proper operation.
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Register 0x15: TSOP Diagnostic
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Type
R/W
R/W
R/W
Function
Unused
Unused
Unused
Unused
Unused
DLOS
DBIP8
DFP
Default
X
X
X
X
X
0
0
0
DFP:
The DFP bit controls the insertion of a single bit error continuously in the most
significant bit (bit 1) of the A1 section overhead framing byte. When DFP is
set to logic one, the A1 bytes are set to 0x76 instead of 0xF6.
DBIP8:
The DBIP8 bit controls the insertion of bit errors continuously in the section
BIP-8 byte (B1). When DBIP8 is set to logic one, the B1 byte is inverted.
DLOS:
The DLOS bit controls the insertion of all zeros in the transmit stream. When
DLOS is set to logic one, the transmit stream is forced to 0x00.
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Register 0x18: RLOP Control/Status
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Type
R/W
R/W
R/W
R/W
R/W
R/W
R
R
Function
BIPWORD
ALLONES
AISDET
LRDIDET
BIPWORDO
FEBEWORD
LAISV
LRDIV
Default
0
0
0
0
0
0
X
X
LRDIV:
The LRDIV bit is read to determine the remote defect indication state of the
RLOP. When LRDIV is high, the RLOP has declared line RDI.
LAISV:
The LAISV bit is read to determine the line AIS state of the RLOP. When
LAISV is high, the RLOP has declared line AIS.
FEBEWORD:
The FEBEWORD bit controls the accumulation of FEBEs. When
FEBEWORD is logic one, the FEBE event counter is incremented only once
per frame, whenever one or more FEBE bits occur during that frame. When
FEBEWORD is logic zero, the FEBE event counter is incremented for each
and every FEBE bit that occurs during that frame (the counter can be
incremented up to 24).
BIPWORDO:
The BIPWORDO bit controls the indication of B2 errors reported to the TLOP
block for insertion as FEBEs. When BIPWORDO is logic one, the BIP errors
are indicated once per frame whenever one or more B2 bit errors occur
during that frame. When BIPWORD0 is logic zero, BIP errors are indicated
once for every B2 bit error that occurs during that frame. The accumulation of
B2 error events functions independently and is controlled by the BIPWORD
register bit..
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LRDIDET:
The LRDIDET bit determines the Line LRDI detection algorithm. When
LRDIDET is set to logic one, Line LRDI is declared when a 110 binary pattern
is detected in bits 6,7 and 8 of the K2 byte for three consecutive frames.
When LRDIDET is set to logic zero, Line LRDI is declared when a 110 binary
pattern is detected in bits 6,7 and 8 of the K2 byte for five consecutive frames.
AISDET:
The AISDET bit determines the Line AIS detection algorithm. When AISDET is
set to logic one, Line AIS is declared when a 111 binary pattern is detected in
bits 6,7 and 8 of the K2 byte for three consecutive frames. When AISDET is
set to logic zero, Line AIS is declared when a 111 binary pattern is detected in
bits 6,7 and 8 of the K2 byte for five consecutive frames.
ALLONES:
The ALLONES bit controls automatically forcing the SONET frame passed to
downstream blocks to logical all-ones whenever LAIS is detected. When
ALLONES is set to logic one, the SONET frame is forced to logic one
immediately when the LAIS alarm is declared. When LAIS is removed, the
received byte is immediately returned to carrying data. When ALLONES is
set to logic zero, the received byte carries the data regardless of the state of
LAIS.
BIPWORD:
The BIPWORD bit controls the accumulation of B2 errors. When BIPWORD
is logic one, the B2 error event counter is incremented only once per frame
whenever one or more B2 bit errors occur during that frame. When
BIPWORD is logic zero, the B2 error event counter is incremented for each
B2 bit error that occurs during that frame (the counter can be incremented up
to 24 times per frame).
Reserved:
The reserved bits must be programmed to logic zero for proper operation.
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Register 0x19: RLOP Interrupt Enable/Interrupt Status
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Type
R/W
R/W
R/W
R/W
R
R
R
R
Function
FEBEE
BIPEE
LAISE
LRDIE
FEBEI
BIPEI
LAISI
LRDII
Default
0
0
0
0
X
X
X
X
LRDII:
The LRDII bit is the line far end receive failure interrupt status bit. LRDII is set
high when a change in the line RDI state occurs. This bit is cleared when this
register is read.
LAISI:
The LAISI bit is the line AIS interrupt status bit. LAISI is set high when a
change in the line AIS state occurs. This bit is cleared when this register is
read.
BIPEI:
The BIPEI bit is the line BIP interrupt status bit. BIPEI is set high when a line
layer (B2) bit error is detected. This bit is cleared when this register is read.
FEBEI:
The FEBEI bit is the line far end block error interrupt status bit. FEBEI is set
high when a line layer FEBE (M1) is detected. This bit is cleared when this
register is read.
LRDIE:
The LRDIE bit is an interrupt enable for the line remote defect indication
alarm. When LRDIE is set to logic one, an interrupt is generated when line
RDI changes state.
LAISE:
The LAISE bit is an interrupt enable for line AIS. When LAISE is set to logic
one, an interrupt is generated when line AIS changes state.
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BIPEE:
The BIPEE bit is an interrupt enable for the line BIP-24 errors. When BIPEE
is set to logic one, an interrupt is generated when a line BIP-24 error (B2) is
detected.
FEBEE:
The FEBEE bit is an interrupt enable for the line far end block errors. When
FEBEE is set to logic one, an interrupt is generated when FEBE (M1) is
detected.
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Register 0x1A: RLOP Line BIP-24 LSB
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Type
R
R
R
R
R
R
R
R
Function
LBE[7]
LBE[6]
LBE[5]
LBE[4]
LBE[3]
LBE[2]
LBE[1]
LBE[0]
Default
X
X
X
X
X
X
X
X
Register 0x1B: RLOP Line BIP-24
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Type
R
R
R
R
R
R
R
R
Function
LBE[15]
LBE[14]
LBE[13]
LBE[12]
LBE[11]
LBE[10]
LBE[9]
LBE[8]
Default
X
X
X
X
X
X
X
X
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Register 0x1C: RLOP Line BIP-24 MSB
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Type
R
R
R
R
Function
Unused
Unused
Unused
Unused
LBE[19]
LBE[18]
LBE[17]
LBE[16]
Default
X
X
X
X
X
X
X
X
LBE[19:0]
Bits LBE[19:0] represent the number of line BIP-24 errors (individual or block)
that have been detected since the last time the error count was polled. The
error count is polled by writing to any of the RLOP Line BIP Registers or Line
FEBE Register addresses. Such a write transfers the internally accumulated
error count to the Line BIP Registers within approximately 7 µs and
simultaneously resets the internal counter to begin a new cycle of error
accumulation.
The count can also be polled by writing to the Master Reset and Identity /
Load Performance Meters register (0x05). Writing to register 0x05
simultaneously loads all the performance meter registers in the RSOP, RLOP,
RPOP, SPTB, SSTB, RXCP, TXCP, RXFP, and TXFP blocks.
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Register 0x1D: RLOP Line FEBE LSB
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Type
R
R
R
R
R
R
R
R
Function
LFE[7]
LFE[6]
LFE[5]
LFE[4]
LFE[3]
LFE[2]
LFE[1]
LFE[0]
Default
X
X
X
X
X
X
X
X
Register 0x1E: RLOP Line FEBE
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Type
R
R
R
R
R
R
R
R
Function
LFE[15]
LFE[14]
LFE[13]
LFE[12]
LFE[11]
LFE[10]
LFE[9]
LFE[8]
Default
X
X
X
X
X
X
X
X
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Register 0x1F: RLOP Line FEBE MSB
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Type
R
R
R
R
Function
Unused
Unused
Unused
Unused
LFE[19]
LFE[18]
LFE[17]
LFE[16]
Default
X
X
X
X
X
X
X
X
LFE[19:0]
Bits LFE[19:0] represent the number of line FEBE errors (individual or block)
that have been detected since the last time the error count was polled. The
error count is polled by writing to any of the RLOP Line BIP Registers or Line
FEBE Register addresses. Such a write transfers the internally accumulated
error count to the Line FEBE Registers within approximately 7 µs and
simultaneously resets the internal counter to begin a new cycle of error
accumulation.
The count can also be polled by writing to the S/UNI-TETRA Channel Reset
and Monitoring Update register (0x05). Writing to register 0x00
simultaneously loads all the performance meter registers in the RSOP, RLOP,
RPOP, SPTB, SSTB, RXCP, TXCP, RXFP, and TXFP blocks.
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Register 0x20: TLOP Control
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Function
Reserved
Reserved
APSREG
Reserved
Reserved
Reserved
Reserved
LRDI
Default
0
0
0
0
0
0
0
0
LRDI:
The LRDI bit controls the insertion of line far end receive failure (LRDI). When
LRDI is set to logic one, the TLOP inserts line RDI into the transmit
SONET/SDH stream. Line RDI is inserted by transmitting the code 110 in bit
positions 6, 7 and 8 of the K2 byte of the transmit stream.
APSREG:
The APSREG bit selects the source for the transmit APS channel. When
APSREG is a logic zero, 0x0000 hexadecimal is inserted in the transmit APS
channel. When APSREG is a logic one, the transmit APS channel is inserted
from the TLOP Transmit K1 Register and the TLOP Transmit K2 Register.
Reserved:
The reserved bits must be programmed to logic zero for proper operation.
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Register 0x21: TLOP Diagnostic
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Type
R/W
Function
Unused
Unused
Unused
Unused
Unused
Unused
Unused
DBIP
Default
X
X
X
X
X
X
X
0
DBIP:
The DBIP bit controls the insertion of bit errors continuously in the line
BIP byte(s) (B2). When DBIP is set to logic one, the B2 byte(s) are inverted.
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Register 0x22: TLOP Transmit K1
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Function
K1[7]
K1[6]
K1[5]
K1[4]
K1[3]
K1[2]
K1[1]
K1[0]
Default
0
0
0
0
0
0
0
0
K1[7:0]:
The K1[7:0] bits contain the value inserted in the K1 byte when the APSREG
bit in the TLOP Control Register is a logic one. K1[7] is the most significant
bit, corresponding to the first bit (bit 1) transmitted. K1[0] is the least
significant bit, corresponding to the last bit (bit 8) transmitted. The bits in this
register are double buffered so that register writes do not need to be
synchronized to SONET/SDH frame boundaries. The insertion of a new APS
code value is initiated by a write to this register. The contents of this register,
and the TLOP Transmit K2 Register are inserted in the transmit stream
starting at the next frame boundary. Successive writes to this register must
be spaced at least two frames (250 µs) apart.
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Register 0x23: TLOP Transmit K2
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Function
K2[7]
K2[6]
K2[5]
K2[4]
K2[3]
K2[2]
K2[1]
K2[0]
Default
0
0
0
0
0
0
0
0
K2[7:0]:
The K2[7:0] bits contain the value inserted in the K2 byte when the APSREG
bit in the TLOP Control Register is a logic one. K2[7] is the most significant
bit, corresponding to the first bit (bit 1) transmitted. K2[0] is the least
significant bit, corresponding to the last bit (bit 8) transmitted. The bits in this
register are double buffered so that register writes do not need to be
synchronized to SONET/SDH frame boundaries. The insertion of a new APS
code value is initiated by a write to the TLOP Transmit K1 Register. A
coherent APS code value is ensured by writing the desired K2 APS code
value to this register before writing the TLOP Transmit K1 Register.
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Register 0x24: S/UNI-TETRA Channel Transmit Sync. Message (S1)
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Function
Reserved
Reserved
Reserved
Reserved
TS1[3]
TS1[2]
TS1[1]
TS1[0]
Default
0
0
0
0
0
0
0
0
TS1[3:0]:
The value written to these bit positions is inserted in the first S1 byte position
of the transmit stream. The S1 byte is used to carry synchronization status
messages between line terminating network elements. TS1[3] is the most
significant bit, corresponding to the first bittransmitted. TS1[0] is the least
significant bit, corresponding to the last bit transmitted.
Reserved
The reserved bits must be programmed to logic zero for proper operation.
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Register 0x25: S/UNI-TETRA Channel Transmit J0/Z0
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Function
Z0[7]
Z0[6]
Z0[5]
Z0[4]
Z0[3]
Z0[2]
Z0[1]
Z0[0]
Default
1
1
0
0
1
1
0
0
Z0[7:0]:
Z0[7:0] contains the value inserted in Z0 bytes for STS-1 (STM-0/AU3) #2
and #3 in the transmit STS-3 (STM-1/AU3) stream when the Z0INS bit is set
to logic 1. Z0[7] is the most significant bit corresponding to bit 1, the first bit
transmitted. Z0[0] is the least significant bit, corresponding to bit 8, the last bit
transmitted..
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Register 0x28: SSTB Control
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Function
ZEROEN
RRAMACC
RTIUIE
RTIMIE
PER5
TNULL
NOSYNC
LEN16
Default
0
0
0
0
0
1
0
0
This register controls the receive and transmit portions of the SSTB.
LEN16:
The section trace message length bit (LEN16) selects the length of the
section trace message to be 16 bytes or 64 bytes. When LEN16 is a logic
one, a 16 byte section trace message is selected. When LEN16 is a logic
zero, a 64 byte section trace message is selected.
NOSYNC:
The section trace message synchronization bit (NOSYNC) disables the
writing of the section trace message into the trace buffer to be synchronized
to the content of the message. When LEN16 is a logic one and NOSYNC is a
logic zero, the receive section trace message byte with its most significant bit
set will be written to the first location in the buffer. When LEN16 and
NOSYNC are logic zero, the byte after the carriage return/linefeed (CR/LF)
sequence will be written to the first location in the buffer. When NOSYNC is a
logic one, synchronization is disabled, and the section trace message buffer
behaves as a circular buffer.
TNULL:
The transmit null bit (TNULL) controls the insertion of an all-zero section trace
identifier message in the transmit stream. When TNULL is a logic one, the
contents of the transmit buffer is ignored and all-zeros bytes are inserted.
When TNULL is a logic zero, the contents of the transmit section trace buffer
is sent to TSOP for insertion into the J0 transmit section overhead byte.
TNULL should be set high before changing the contents of the trace buffer to
avoid sending partial messages.
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PER5:
The receive trace identifier persistence bit (PER5) controls the number of
times a section trace identifier message must be received unchanged before
being accepted. When PER5 is a logic one, a message is accepted when it is
received unchanged five times consecutively. When PER5 is a logic zero, the
message is accepted after three identical repetitions.
RTIMIE:
The receive trace identifier mis-match bit (RTIMIE) controls the activation of
the interrupt output when the comparison between accepted identifier
message and the expected message changes state. When RTIMIE is a logic
one, changes in match state activates the interrupt (INTB) output.
RTIUIE:
The receive trace identifier unstable bit (RTIUIE) controls the activation of the
interrupt output when the receive identifier message changes state. When
RTIUIE is a logic one, changes in the received section trace identifier
message stable/unstable state will activate the interrupt (INTB) output.
RRAMACC:
The receive RAM access control bit (RRAMACC) directs read and writes
access between the receive and transmit section trace buffer. When
RRAMACC is a logic one, microprocessor accesses are directed to the
receive section trace buffer. When RRAMACC is a logic zero, microprocessor
accesses are directed to the transmit section trace buffer.
ZEROEN:
The zero enable bit (ZEROEN) enables TIM assertion and removal based on
an all ZERO’s section trace message string. When ZEROEN is set high, all
ZERO’s section trace message strings are considered when entering and
exiting TIM states. When ZEROEN is set low, all ZERO’s section trace
message strings are ignored.
Reserved:
The reserved bits must be programmed to logic zero for proper operation.
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Register 0x29: SSTB Section Trace Identifier Status
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Type
R
R
R
R
R
Function
BUSY
Unused
Unused
Unused
RTIUI
RTIUV
RTIMI
RTIMV
Default
0
X
X
X
X
X
X
X
This register reports the section trace identifier status of the SSTB.
RTIMV:
The RTIMV bit reports the match/mismatch status of the identifier message
framer. RTIMV is a logic one when the accepted identifier message differs
from the expected message written by the microprocessor. RTIMV is a logic
zero when the accepted message matches the expected message.
RTIMI:
The RTIMI bit is a logic one when match/mismatch status of the trace
identifier framer changes state. This bit is cleared when this register is read.
RTIUV:
The RTIUV bit reports the stable/unstable status of the identifier message
framer. RTIUV is a logic one when the current received section trace
identifier message has not matched the previous message for eight
consecutive messages. RTIUV is a logic zero when the current message
becomes the accepted message as determined by the PER5 bit in the SSTB
Control register.
RTIUI:
The RTIUI bit is a logic one when stable/unstable status of the trace identifier
framer changes state. This bit is cleared when this register is read.
BUSY:
The BUSY bit reports whether a previously initiated indirect read or write to a
message buffer is completed. BUSY is set to a logic one immediately upon
writing to the SSTB Indirect Address register, and stays high until the initiated
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access is completed (about 0.6 µs). This register should be polled to
determine when new data is available in the SSTB Indirect Data register.
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Register 0x2A: SSTB Indirect Address Register
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Function
RWB
A[6]
A[5]
A[4]
A[3]
A[2]
A[1]
A[0]
Default
0
0
0
0
0
0
0
0
This register supplies the address used to index into section trace identifier
buffers.
A[6:0]:
The indirect read address bits (A[6:0]) are used to address the section trace
identifier buffers. When RRAMACC is set high, addresses 0 to 63 reference
the captured message page while addresses 64 to 127 reference the
expected message page of the receive section trace buffer. The captured
message page contains the identifier bytes extracted from the receive stream.
The expected message page contains the section trace message to which the
captured message page is compared. When RRAMACC is set low,
addresses 0 to 63 reference the transmit section trace buffer which contains
the section trace message inserted in the transmit stream. When RRAMACC
is set low, addresses 64 to 127 are unused and must not be accessed.
RWB:
The access control bit (RWB) selects between an indirect read or write
access to the selected section trace buffer (receive or transmit as determined
by the RRAMACC bit). Writing to this register initiates an access to the
selected section trace buffer. When RWB is a logic one, a read access is
initiated. The addressed location's contents are placed in the SSTB Indirect
Data register. When RWB is a logic zero, a write access is initiated. The data
in the SSTB Indirect Data register is written to the addressed location in the
selected buffer.
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Register 0x2B: SSTB Indirect Data Register
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Function
D[7]
D[6]
D[5]
D[4]
D[3]
D[2]
D[1]
D[0]
Default
0
0
0
0
0
0
0
0
This register contains the data read from the section trace message buffer after a
read operation or the data to be written into the buffer before a write operation.
D[7:0]:
The indirect data bits (D[7:0]) contains the data read from either the transmit
or receive section trace buffer after an indirect read operation is completed.
The data that is written to a buffer is set up in this register before initiating the
indirect write operation.
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Register 0x30 (EXTD=0): RPOP Status/Control
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Type
R/W
R
R
R
R
R
R
R/W
Function
Reserved
LOPCONV
LOPV
PAISONV
PAISV
PRDIV
NEWPTRI
NEWPTRE
Default
0
X
X
X
X
X
X
0
NOTE: To facilitate additional register mapping, shadow registers have been
added to registers 0x30, 0x31 and 0x33. These shadow registers are accessed in
the same way as the normal registers.
The EXTD (extend register) bit must be set in register 0x36 to allow switching
between accessing the normal registers and the shadow registers.
This register allows the status of path level alarms to be monitored.
NEWPTRE:
The NEWPTRE bit is the interrupt enable for the receive new pointer status.
When NEWPTRE is a logic one, an interrupt is generated when the pointer
interpreter validates a new pointer.
NEWPTRI:
The NEWPTRI bit is the receive new pointer interrupt status bit. NEWPTRI is
a logic one when the pointer interpreter has validated a new pointer value
(H1, H2). NEWPTRI is cleared when this register is read.
PRDIV:
The PRDIV bit is read to determine the remote defect indication state. When
PRDIV is a logic one, the S/UNI-TETRA has declared path RDI.
PAISV:
The PAISV bit is read to determine the path AIS state. When PAISV is a logic
one, the S/UNI-TETRA has declared path AIS.
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PAISCONV:
The PAISCONV bit is read to determine the concatenation path AIS state.
When PAISCONV is a logic one, the S/UNI-TETRA has declared a
concatenation path AIS.
PLOPV:
The PLOPV bit is read to determine the loss of pointer state. When PLOPV is
a logic one, the S/UNI-TETRA has declared LOP.
LOPCONV:
The LOPCONV bit is read to determine the loss of pointer concatenation
state. When LOPCONV is a logic one, the S/UNI-TETRA has declared loss of
pointer concatenation.
Reserved:
The reserved bits must be programmed to logic zero for proper operation.
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Register 0x30 (EXTD=1): RPOP Status/Control
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Type
R/W
R/W
R/W
R/W
R
R
R
Function
Reserved
IINVCNT
PSL5
Reserved
Unused
ERDIV[2]
ERDIV[1]
ERDIV[0]
Default
0
0
0
0
X
X
X
X
NOTE: To facilitate additional register mapping, shadow registers have been
added to registers 0x30, 0x31 and 0x33. These shadow registers are accessed in
the same way as the normal registers.
The EXTD (extend register) bit must be set in register 0x36 to allow switching
between accessing the normal registers and the shadow registers.
The Status Register is provided at RPOP read address 0, if the extend register
(EXTD) bit is set in register 0x36.
ERDIV[2:0]:
The ERDIV[2:0] bits reflect the current state of the detected enhanced RDI,
(filtered G1 bits 5, 6, and 7).
IINVCNT:
When a logic one is written to the IINVCNT (Intuitive Invalid Pointer Counter)
bit, if in the LOP state 3 x new point resets the inv_point count. If this bit is set
to 0 the inv_point count will not be reset if in the LOP state and 3 x new
pointers are detected.
PSL5:
The PSL5 bit controls the filtering of the path signal label byte (C2). When
PSL5 is set high, the PSL is updated when the same value is received for 5
consecutive frames. When the PSL5 is set low, the PSL is updated when the
same value is received for 3 consecutive frames.
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Register 0x31 (EXTD=0): RPOP Interrupt Status
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Type
R
R
R
R
R
R
Function
PSLI
Unused
LOPI
Unused
PAISI
PRDII
BIPEI
FEBEI
Default
X
X
X
X
X
X
X
X
NOTE: To facilitate additional register mapping, shadow registers have been
added to registers 0x30, 0x31 and 0x33. These shadow registers are accessed in
the same way as the normal registers.
The EXTD (extend register) bit must be set in register 0x36 to allow switching
between accessing the normal registers and the shadow registers.
This register allows identification and acknowledgment of path level alarm and
error event interrupts.
FEBEI:
The FEBEI bit is the path FEBE interrupt status bit. FEBEI is a logic one
when a FEBE error is detected. This bit is cleared when this register is read.
BIPEI:
The BIPEI bit is the path BIP -8 interrupt status bit. BIPEI is a logic one when
a B3 error is detected. This bit is cleared when this register is read.
PRDII:
The PRDII bit is the path remote defect indication interrupt status bit. PRDII is
a logic one when a change in the path RDI state or the auxiliary path RDI
state occurs. This bit is cleared when this register is read.
PAISI:
The PAISI bit is the path alarm indication signal interrupt status bit. PAISI is a
logic one when a change in the path AIS state occurs. This bit is cleared
when this register is read.
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LOPI:
The LOPI bit is the loss of pointer interrupt status bit. LOPI is a logic one
when a change in the LOP state occurs. This bit is cleared when this register
is read.
PSLI:
The PSLI bit is the change of path signal label interrupt status bit. PSLI is a
logic one when a change is detected in the path signal label register. The
current path signal label can be read from the RPOP Path Signal Label
register. This bit is cleared when this register is read.
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Register 0x31 (EXTD=1): RPOP Interrupt Status
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Type
R
Function
Unused
Unused
Unused
Unused
Unused
Unused
Unused
ERDII
Default
X
X
X
X
X
X
X
X
NOTE: To facilitate additional register mapping, shadow registers have been
added to registers 0x30, 0x31 and 0x33. These shadow registers are accessed in
the same way as the normal registers.
The EXTD (extend register) bit must be set in register 0x36 to allow switching
between accessing the normal registers and the shadow registers
This register allows identification and acknowledgment of path level alarm and
error event interrupts.
ERDII:
The ERDII bit is set to logic one when a change is detected in the received
enhanced RDI state. ERDII is cleared when the RPOP Interrupt Status
register is read.
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Register 0x32: RPOP Pointer Interrupt Status
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Type
R
R
R
R
R
R
R
Function
ILLJREQI
Unused
DISCOPAI
INVNDFI
ILLPTRI
NSEI
PSEI
NDFI
Default
X
X
X
X
X
X
X
X
This register allows identification and acknowledgment of pointer event
interrupts.
NDFI:
The NDFI bit is the new data flag interrupt status bit. NDFI is set to a logic
one when the NDF field is active in the received pointer (H1, H2). This bit is
cleared when this register is read.
PSEI:
The PSEI bit is the positive stuff event interrupt status bit. PSEI is a logic one
when a positive stuff event is detected in the received pointer (H1, H2). This
bit is cleared when this register is read.
NSEI:
The NSEI bit is the negative stuff event interrupt status bit. NSEI is a logic
one when a negative stuff event is detected in the received pointer (H1, H2).
This bit is cleared when this register is read.
ILLPTRI:
The ILLPTRI bit is the illegal pointer interrupt status bit. ILLPTRI is a logic
one when an illegal pointer value is detected. This bit is cleared when this
register is read.
INVNDFI:
The INVNDFI bit is the illegal new data field value interrupt status bit.
INVNDFI is a logic one when an illegal NDF field value is detected in the
receive payload pointer. An illegal NDF field is any one of the following six
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values: 0x0, 0x3, 0x5, 0xA, 0xC, and 0xF. This bit is cleared when this
register is read.
DISCOPAI:
The DISCOPAI bit is the discontinuous change of pointer interrupt status bit.
DISCOPAI is a logic one when a new pointer value is validated without an
accompanying NDF indication. This bit is cleared when this register is read.
ILLJREQI:
The ILLJREQI bit is the illegal justification request interrupt status bit.
ILLJREQI is a logic one when the pointer interpreter detects an illegal pointer
justification request event. This bit is cleared when this register is read.
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Register 0x33 (EXTD=0): RPOP Interrupt Enable
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Function
PSLE
Reserved
LOPE
Reserved
PAISE
PRDIE
BIPEE
FEBEE
Default
0
0
0
0
0
0
0
0
NOTE: To facilitate additional register mapping, shadow registers have been
added to registers 0x30, 0x31 and 0x33. These shadow registers are accessed in
the same way as the normal registers.
The EXTD (extend register) bit must be set in register 0x36 to allow switching
between accessing the normal registers and the shadow registers
This register allows interrupt generation to be enabled for path level alarm and
error events.
FEBEE:
The FEBEE bit is the interrupt enable for path FEBEs. When FEBEE is a
logic one, an interrupt is generated when a path FEBE is detected.
BIPEE:
The BIPEE bit is the interrupt enable for path BIP-8 errors. When BIPEE is a
logic one, an interrupt is generated when a B3 error is detected.
PRDIE:
The PRDIE bit is the interrupt enable for path RDI. When PRDIE is a logic
one, an interrupt is generated when the path RDI state changes.
PAISE:
The PAISE bit is the interrupt enable for path AIS. When PAISE is a logic
one, an interrupt is generated when the path AIS state changes.
LOPE:
The LOPE bit is the interrupt enable for LOP. When LOPE is a logic one, an
interrupt is generated when the LOP state changes.
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PSLE:
The PSLE bit is the interrupt enable for changes in the received path signal
label. When PSLE is a logic one, an interrupt is generated when the received
C2 byte changes.
Reserved:
The reserved bits must be programmed to logic zero for proper operation.
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Register 0x33 (EXTD=1): RPOP Interrupt Enable
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Type
R/W
Function
Unused
Unused
Unused
Unused
Unused
Unused
Unused
ERDIE
Default
X
X
X
X
X
X
X
0
NOTE: To facilitate additional register mapping, shadow registers have been
added to registers 0x30, 0x31 and 0x33. These shadow registers are accessed in
the same way as the normal registers.
The EXTD (extend register) bit must be set in register 0x36 to allow switching
between accessing the normal registers and the shadow registers
This register allows interrupt generation to be enabled for path level alarm and
error events.
ERDIE:
When EREDIE is a logic one, an interrupt is generated when a path
Enhanced RDI is detected.
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Register 0x34: RPOP Pointer Interrupt Enable
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Function
ILLJREQE
Reserved
DISCOPAE
INVNDFE
ILLPTRE
NSEE
PSEE
NDFE
Default
0
0
0
0
0
0
0
0
This register is used to enable pointer event interrupts.
NDFE:
When a logic one is written to the NDFE interrupt enable bit position, a
change in active offset due to the reception of an enabled NDF (NDF_enabled
indication) will activate the interrupt out, INTB.
PSEE:
When a logic one is written to the PSEE interrupt enable bit position, a
positive pointer adjustment event will active the interrupt output, INTB.
NSEE:
When a logic one is written to the NSEE interrupt enable bit position, a
negative pointer adjustment event will activate the interrupt output, INTB.
ILLPTRE:
When a logic one is written to the ILLPTRE interrupt enable bit position, an
illegal pointer will activate the interrupt output, INTB.
INVNDFE:
When a logic one is written to the INVNDFE interrupt enable bit position, an
invalid NDF code will activate the interrupt output, INTB.
DISCOPAE:
When a logic one is written to the DISCOPAE interrupt enable bit position, a
change of pointer alignment event will activate the interrupt output, INTB.
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ILLJREQE:
When a logic one is written tot he ILLJREQE interrupt enable bit position, an
illegal pointer justification request will activate the interrupt output, INTB.
Reserved:
The reserved bits must be programmed to logic zero for proper operation.
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Register 0x35: RPOP Pointer LSB
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Type
R
R
R
R
R
R
R
R
Function
PTR[7]
PTR[6]
PTR[5]
PTR[4]
PTR[3]
PTR[2]
PTR[1]
PTR[0]
Default
X
X
X
X
X
X
X
X
PTR[7:0]:
The PTR[7:0] bits contain the eight LSBs of the current pointer value that is
interpreted from the H1 and H2 bytes. The NDFI, NSEI and PSEI bits of the
RPOP Pointer Interrupt Status register should be read before and after
reading this register to ensure that the pointer value did not change during the
register read.
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Register 0x36: RPOP Pointer MSB and RDI Filter Control
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Type
R/W
R/W
R/W
R
R
R
R
Function
NDFPOR
EXTD
RDI10
Unused
S1
S0
PTR[9]
PTR[8]
Default
0
0
0
X
X
X
X
X
PTR[9:8]:
The PTR[9:8] bits contain the two MSBs of the current pointer value that is
interpreted from the H1 and H2 bytes. The NDFI, NSEI and PSEI bits of the
RPOP Pointer Interrupt Status register should be read before and after
reading this register to ensure that the pointer value did not change during the
register read.
S0, S1:
The S0 and S1 bits contain the two S bits received in the last H1 byte. These
bits should be software debounced by reading this register at least twice.
RDI10:
The RDI10 bit controls the filtering of the remote defect indication and the
auxiliary remote defect indication. When RDI10 is a logic one, the PRDI and
APRDI status is updated when the same value is received in the
corresponding bit of the G1 byte for ten consecutive frames. When RDI10 is
a logic zero, the PRDI and APRDI status is updated when the same value is
received for five consecutive frames.
NDFPOR:
The NDFPOR (new data flag pointer outside range) bit allows an NDF counter
enable, if the pointer value is outside the range (0-782). If this bit is set to
logic one the definition for NDF counter enable is enabled NDF + ss. If this bit
is set to logic zero the definition for NDF counter enable is enabled NDF + ss
+ offset in the range of 0 to 782. Note that this bit only allows the NDF counter
to count towards LOP when the pointer is out of range, no active offset
change will occur.
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EXTD:
The EXTD bit extends the registers to facilitate additional mapping. If this bit
is set to logic one the register mapping, for registers 0x30, 0x31 and 0x33,
are extended.
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Register 0x37: RPOP Path Signal Label
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Type
R
R
R
R
R
R
R
R
Function
PSL[7]
PSL[6]
PSL[5]
PSL[4]
PSL[3]
PSL[2]
PSL[1]
PSL[0]
Default
X
X
X
X
X
X
X
X
PSL[7:0]:
The PSL[7:0] bits contain the path signal label byte (C2). The value in this
register is updated to a new path signal label value if the same new value is
observed for three or five consecutive frames, depending on the status of the
PSL5 bit.
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Register 0x38: RPOP Path BIP-8 LSB
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Type
R
R
R
R
R
R
R
R
Function
PBE[7]
PBE[6]
PBE[5]
PBE[4]
PBE[3]
PBE[2]
PBE[1]
PBE[0]
Default
X
X
X
X
X
X
X
X
Register 0x39: RPOP Path BIP-8 MSB
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Type
R
R
R
R
R
R
R
R
Function
PBE[15]
PBE[14]
PBE[13]
PBE[12]
PBE[11]
PBE[10]
PBE[9]
PBE[8]
Default
X
X
X
X
X
X
X
X
PBE[15:0]:
PBE[15:0] represent the number of B3 errors (individual or block) that have
been detected since the last time the error count was polled. The error count
is polled by writing to either of the RPOP Path BIP-8 Register addresses or to
either of the RPOP Path FEBE Register addresses. Such a write transfers
the internally accumulated error count to the Path BIP-8 registers within a
maximum of 7 µs and simultaneously resets the internal counter to begin a
new cycle of error accumulation. This transfer and reset is carried out in a
manner that ensures that coincident events are not lost.
The count can also be polled by writing to the S/UNI-TETRA Channel Reset
and Monitoring Update register (0x05).
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Register 0x3A: RPOP Path FEBE LSB
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Type
R
R
R
R
R
R
R
R
Function
PFE[7]
PFE[6]
PFE[5]
PFE[4]
PFE[3]
PFE[2]
PFE[1]
PFE[0]
Default
X
X
X
X
X
X
X
X
Register 0x3B: RPOP Path FEBE MSB
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Type
R
R
R
R
R
R
R
R
Function
PFE[15]
PFE[14]
PFE[13]
PFE[12]
PFE[11]
PFE[10]
PFE[9]
PFE[8]
Default
X
X
X
X
X
X
X
X
These registers allow path FEBEs to be accumulated.
PFE[15:0]:
PFE[15:0] represent the number of path FEBE errors (G1) that have been
detected since the last time the error count was polled. The error count is
polled by writing to either of the RPOP Path BIP-8 Register addresses or to
either of the RPOP Path FEBE Register addresses. Such a write transfers
the internally accumulated error count to the Path FEBE Registers within a
maximum of 7 µs and simultaneously resets the internal counter to begin a
new cycle of error accumulation. This transfer and reset is carried out in a
manner that ensures that coincident events are not lost.
The count can also be polled by writing to the S/UNI-TETRA Channel Reset
and Monitoring Update register (0x05).
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Register 0x3C: RPOP Auxiliary RDI
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Type
R/W
R/W
R/W
R/W
R
Function
Unused
Unused
Reserved
BLKFEBE
Unused
Reserved
APRDIE
APRDIV
Default
X
X
0
0
X
0
0
X
APRDIE:
The APRDIE bit is the interrupt enable for auxiliary path RDI. When APRDIE
is a logic one, an interrupt is generated when the auxiliary path RDI state
changes.
APRDIV:
The APRDIV bit is read to determine the auxiliary path RDI state. When
APRDIV is a logic one, the S/UNI-TETRA has declared auxiliary path RDI.
BLKFEBE:
When set to logic one, the block FEBE bitg (BLKFEBE) causes path FEBE
errors to be reported and accumulated on a block basis. A single path FEBE
error is accumulated for a block if the received FEBE code for that block is
between 1 and 8 inclusive. When BLKFEBE is set low, path FEBE errors are
accumulated on an error basis.
Reserved:
The reserved bits must be programmed to logic zero for proper operation.
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Register 0x3D: RPOP Error Event Control
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Function
SOS
ENSS
BLKBIP
Reserved
BLKBIPO
Reserved
Reserved
Reserved
Default
0
0
0
0
0
0
0
0
This register contains error event control bits.
BLKBIPO:
When BLKBIPO is a logic one, path FEBE indications are generated on a
block basis. A single FEBE is transmitted if one or more path B3 error
indications are detected per frame. When BLKBIPO is a logic zero, the
transmitted FEBE indicates the number of B3 errors detected (between 0 and
8 errors per frame).
BLKBIP:
When BLKBIP is a logic one, B3 errors are reported and accumulated on a
block basis. A single B3 error is accumulated and reported to the TPOP if one
or more B3 errors are detected per frame. When BLKBIP is a logic zero,
each B3 error is accumulated and reported.
ENSS:
The ENSS bit controls whether the SS bits in the payload pointer are included
in the pointer interpreter state machine. When ENSS is a logic one, an
incorrect SS bit pattern causes the pointer interpreter to enter the LOP (loss
of pointer) state and prevents a new pointer indication. When ENSS is a logic
zero, the SS bits are ignored by the pointer interpreter.
SOS:
The SOS controls the spacing between consecutive pointer justification
events in the receive stream. When SOS is a logic one, the definition of
inc_ind and dec_ind indications includes the requirement that active offset
changes have occurred at least three frames ago. When SOS is a logic zero,
pointer justification indications in the receive stream are followed without
regard to the proximity of previous active offset changes.
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Reserved:
The reserved bits must be programmed to logic zero for proper operation.
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Register 0x40: TPOP Control/Diagnostic
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Function
Unused
EPRDIEN
EPRDISRC
PERSIST
Reserved
Reserved
DBIP8
PAIS
Default
X
0
0
0
0
0
0
0
This register allows insertion of path level alarms and diagnostic signals.
PAIS:
The PAIS bit controls the insertion of STS path alarm indication signal. When
a logic one is written to this bit position, the complete SPE, and the pointer
bytes (H1, H2, and H3) are overwritten with the all-ones pattern. When a
logic zero is written to this bit position, the pointer bytes and the SPE are
processed normally.
DBIP8:
The DBIP8 bit controls the insertion of bit errors continuously in the B3 byte.
When DBIP8 is a logic one, the B3 byte is inverted.
PERSIST
The path far end receive failure alarm persistence bit (PERSIST) controls the
persistence of the RDI asserted into the transmit stream. When PERSIST is
a logic one, the RDI code inserted into the transmit stream as a result of
consequential actions is asserted for a minimum of 20 frames in nonenhanced RDI mode, or the last valid RDI code before an idle code (idle
codes are when bits 5,6,7 are 000, 001, or 011) is asserted for 20 frames in
enhanced RDI mode. When PERSIST is logic zero, the transmit RDI code
changes immediately based on received alarm conditions.
EPRDISRC
The enhanced path receive defect indication alarm source bit (EPRDISRC)
controls the source of RDI input to be inserted onto the G1 byte.. When
EPRDIEN is logic zero, the extended RDI bits of the G1 byte not overwritten
by the TPOP block, regardless of EPRDISRC. When EPRDIEN is logic one
and EPRDISCR is logic zero, the extended RDI bits of the G1 byte, bits 6 and
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7, are inserted according to the value in the G1[1:0] register bits (register
0x49). When EPRDIEN is logic one and EPRDISCR is logic one, the value
register 0x49 G1[1:0] is ignored and the EPRDI bits in the G1 byte are set
according to the setting of the Channel Auto Enhanced Path RDI Control
registers (0x92 and 0x93).
EPRDIEN
The enhanced path receive defect indication alarm enable bit (EPRDIEN)
controls the use of 3-bit RDI mode. When EPRDIEN is set to logic 0, the
basic path RDI scheme is used and only G1[5] is used to indicate PRDI.
When EPRDIEN is set to logic 1, the enhanced path RDI scheme is used and
the three G1[7:5] bits are used to indicate PRDI. The actual three bit code will
be controlled according to the EPRDISRC.
Reserved:
The reserved bits must be programmed to logic zero for proper operation.
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Register 0x41: TPOP Pointer Control
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Function
H1LOAD
FTPTR
SOS
PLD
NDF
NSE
PSE
Reserved
Default
0
0
0
0
0
0
0
0
This register allows control over the transmitted payload pointer for diagnostic
purposes.
PSE:
The PSE bit controls the insertion of positive pointer movements. A logic zero
to logic one transition on this bit enables the insertion of a single positive
pointer justification in the transmit stream. This register bit is automatically
cleared when the pointer movement is inserted.
NSE:
The NSE bit controls the insertion of negative pointer movements. A logic
zero to logic one transition on this bit enables the insertion of a single
negative pointer justification in the transmit stream. This register bit is
automatically cleared when the pointer movement is inserted.
NDF:
The NDF bit controls the insertion of new data flags in the inserted payload
pointer. When a logic one is written to this bit position, the pattern contained
in the NDF[3:0] bit positions in the TPOP Arbitrary Pointer MSB Register is
inserted continuously in the payload pointer. When a logic zero is written to
this bit position, the normal pattern (0110) is inserted in the payload pointer.
PLD:
The PLD bit controls the loading of the pointer value contained in the TPOP
Arbitrary Pointer Registers. Normally the TPOP Arbitrary Pointer Registers
are written to set up the arbitrary new pointer value, the S-bit values, and the
NDF pattern. A logic one is then written to this bit position to load the new
pointer value. The new data flag bit positions are set to the programmed NDF
pattern for the first frame; subsequent frames have the new data flag bit
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positions set to the normal pattern (0110) unless the NDF bit described above
is set to a logic one. This bit is automatically cleared after the new payload
pointer is loaded.
Note: When loading an out of range pointer (that is a pointer with a value
greater than 782), the TPOP continues to operate with timing based on the
last valid pointer value. The out of range pointer value is inserted in the
transmit stream. Although a valid SPE will continue to be generated, it is
unlikely to be extracted by downstream circuitry which should be in a loss of
pointer state.
SOS:
The SOS bit controls the stuff opportunity spacing between consecutive SPE
positive or negative stuff events. When SOS is a logic zero, stuff events may
be generated every frame as controlled by the PSE and NSE register bits
described above. When SOS is a logic one, stuff events may be generated at
a maximum rate of once every four frames.
FTPTR:
The force transient pointer bit (FTPTR) enables the insertion of the pointer
value contained in the Arbitrary Pointer Registers into the transmit stream for
diagnostic purposes. When FTPTR is a logic one, the APTR[9:0] bits of the
Arbitrary Pointer Registers are inserted into the H1 and H2 bytes of the
transmit stream. At least one corrupted pointer is guaranteed to be sent.
When FTPTR is a logic zero, the pointer value in the Current Pointer registers
is inserted in the transmit stream.
H1LOAD:
The H1 load bit (H1LOAD) controls the periodic updating of the payload
pointer at the H1 byte. When H1LOAD is logic one, the payload pointer is
updated with an adjusted arbitrary payload pointer at every occurrence of the
H1 byte. This adjusted arbitrary payload pointer value is reset with the
Arbitrary Pointer Register by writing to the PLD bit in the Pointer Control
Register, and is adjusted whenever there are outgoing pointer justifications.
When H1LOAD is logic zero, the payload pointer is only updated with the
value in the Arbitrary Pointer Registers by writing to the PLD bit in the Pointer
Control Register.
Reserved:
The reserved bits must be programmed to logic zero for proper operation.
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Register 0x43: TPOP Current Pointer LSB
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Type
R
R
R
R
R
R
R
R
Function
CPTR[7]
CPTR[6]
CPTR[5]
CPTR[4]
CPTR[3]
CPTR[2]
CPTR[1]
CPTR[0]
Default
X
X
X
X
X
X
X
X
CPTR[7:0]:
The CPTR[7:0] bits, along with the CPTR[9:8] bits in the TPOP Current
Pointer MSB Register reflect the value of the current payload pointer being
inserted in the transmit stream. The value may be changed by loading a new
pointer value using the TPOP Arbitrary Pointer LSB and MSB Registers, or by
inserting positive and negative pointer movements using the PSE and NSE
register bits.
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Register 0x44: TPOP Current Pointer MSB
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Type
R
R
Function
Unused
Unused
Unused
Unused
Unused
Unused
CPTR[9]
CPTR[8]
Default
X
X
X
X
X
X
X
X
CPTR[9:8]:
The CPTR[9:8] bits, along with the CPTR[7:0] bits in the TPOP Current
Pointer LSB Register reflect the value of the current payload pointer being
inserted in the transmit stream. The value may be changed by loading a new
pointer value using the TPOP Arbitrary Pointer LSB and MSB Registers, or by
inserting positive and negative pointer movements using the PSE and NSE
register bits.
It is recommended the CPTR[9:0] value be software de-bounced to ensure a
correct value is received.
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Register 0x45: TPOP Arbitrary Pointer LSB
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Function
APTR[7]
APTR[6]
APTR[5]
APTR[4]
APTR[3]
APTR[2]
APTR[1]
APTR[0]
Default
0
0
0
0
0
0
0
0
This register allows an arbitrary pointer to be inserted for diagnostic purposes.
APTR[7:0]:
The APTR[7:0] bits, along with the APTR[9:8] bits in the TPOP Arbitrary
Pointer MSB Register are used to set an arbitrary payload pointer value. The
arbitrary pointer value is inserted in the transmit stream by writing a logic one
to the PLD bit in the TPOP Pointer Control Register.
If the FTPTR bit in the TPOP Pointer Control register is a logic one, the
current APTR[9:0] value is inserted into the payload pointer bytes (H1 and
H2) in the transmit stream.
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Register 0x46: TPOP Arbitrary Pointer MSB
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Function
NDF[3]
NDF[2]
NDF[1]
NDF[0]
S[1]
S[0]
APTR[9]
APTR[8]
Default
1
0
0
1
1
0
0
0
This register allows an arbitrary pointer to be inserted for diagnostic purposes.
APTR[9:8]:
The APTR[9:8] bits, along with the APTR[7:0] bits in the TPOP Arbitrary
Pointer LSB Register are used to set an arbitrary payload pointer value. The
arbitrary pointer value is inserted in the transmit stream by writing a logic one
to the PLD bit in the TPOP Pointer Control Register.
If the FTPTR bit in the TPOP Pointer Control register is a logic one, the
current APTR[9:0] value is inserted into the payload pointer bytes (H1 and
H2) in the transmit stream.
S[1], S[0]:
The S[1:0] bits contain the value inserted in the S[1:0] bit positions (also
referred to as the unused bits) in the payload pointer.
NDF[3:0]:
The NDF[3:0] bits contain the value inserted in the NDF bit positions when an
arbitrary new payload pointer value is inserted (using the PLD bit in the TPOP
Pointer Control Register) or when new data flag generation is enabled using
primary input NDF, or the NDF bit in the TPOP Pointer Control Register.
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Register 0x47: TPOP Path Trace
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Function
J1[7]
J1[6]
J1[5]
J1[4]
J1[3]
J1[2]
J1[1]
J1[0]
Default
0
0
0
0
0
0
0
0
This register allows control over the path trace byte.
J1[7:0]:
The J1[7:0] bits are inserted in the J1 byte position in the transmit stream
when insertion from the SPTB is disabled.
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Register 0x48: TPOP Path Signal Label
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Function
C2[7]
C2[6]
C2[5]
C2[4]
C2[3]
C2[2]
C2[1]
C2[0]
Default
0
0
0
0
0
0
0
1
This register allows control over the path signal label.
C2[7:0]:
The C2[7:0] bits are inserted in the C2 byte position in the transmit stream. .
Upon reset the register defaults to 0x01, which signifies an equipped but not
specific payload. This register should be reprogrammed with the value 0x13
when in Asynchronous Transfer Mode (ATM) mode. This register should be
reprogrammmed with the value 0xCF for non-scrambled data and 0x16 for
scrambled data when in Packet over SONET/SDH (POS) mode. Refer to the
operations sections for more information on how to set the S/UNI-TETRA in
ATM or POS mode.
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Register 0x49: TPOP Path Status
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Function
FEBE[3]
FEBE[2]
FEBE[1]
FEBE[0]
PRDI
APRDI
G1[1]
G1[0]
Default
0
0
0
0
0
0
0
0
This register allows control over the path status byte.
G[1:0]:
The G1[1:0] bits are inserted in bits 1 and 2 of the path status byte G1. These
bits are ignored when EPRDIEN and EPRDISRC are both logic one. See the
description of EPRDIEN and EPRDISRC for more details on how G1 can be
controlled.
APRDI
The APRDI bit controls the insertion of the auxiliary path remote defect
indication. When APRDI is a logic one, the APRDI bit position in the path
status byte is set high. When APRDI is a logic zero, the APRDI bit position in
the path status byte is set low.
PRDI:
The PRDI bit controls the insertion of the path remote defect indication.
When a logic one is written to this bit position, the PRDI bit position in the
path status byte is set high. When a logic zero is written to this bit position,
the PRDI bit position in the path status byte is set low. This bit is ignored
when EPRDIEN and EPRDISRC are both logic one and the EPRDI bits in the
G1 byte (bit 6) isare set according to the setting of the Channel Auto
Enhanced Path RDI Control Registers (0x92 and 0x93).
FEBE[3:0]:
The FEBE[3:0] bits are inserted in the FEBE bit positions in the path status
byte. The value contained in FEBE[3:0] is cleared after being inserted in the
path status byte. Any non-zero FEBE value overwrites the value that would
normally have been inserted based on the number of receive B3 errors during
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the last frame. When reading this register, a non-zero value in these bit
positions indicates that the insertion of this value is still pending.
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Register 0x50: SPTB Control
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Function
ZEROEN
RRAMACC
RTIUIE
RTIMIE
PER5
TNULL
NOSYNC
LEN16
Default
0
0
0
0
0
1
0
0
This register controls the receive and transmit portions of the SPTB.
LEN16:
The LEN16 bit selects the length of the path trace message to be 16 bytes or
64 bytes. When LEN16 is a logic one, a 16 byte path trace message is
selected. When LEN16 is a logic zero, a 64 byte path trace message is
selected.
NOSYNC:
The NOSYNC bit disables the writing of the path trace message into the trace
buffer to be synchronized to the content of the message. When LEN16 is a
logic one and NOSYNC is a logic zero, the receive path trace message byte
with its most significant bit set will be written to the first location in the buffer.
When LEN16 and NOSYNC are logic zero, the byte after the carriage
return/linefeed (CR/LF) sequence will be written to the first location in the
buffer. When NOSYNC is a logic one, synchronization is disabled, and the
path trace message buffer behaves as a circular buffer.
TNULL:
The TNULL bit controls the insertion of an all-zero path trace identifier
message in the transmit stream. When TNULL is a logic one, the contents of
the transmit buffer is ignored and all-zeros bytes are inserted. When TNULL
is a logic zero, the contents of the transmit path trace buffer is sent to TSOP
for insertion into the J1 transmit path overhead byte. TNULL should be set
high before changing the contents of the trace buffer to avoid sending partial
messages.
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PER5:
The PER5 bit controls the number of times a path trace identifier message
must be received unchanged before being accepted. When PER5 is a logic
one, a message is accepted when it is received unchanged five times
consecutively. When PER5 is a logic zero, the message is accepted after
three identical repetitions.
RTIMIE:
The RTIMIE bit controls the activation of the interrupt output when the
comparison between accepted identifier message and the expected message
changes state. When RTIMIE is a logic one, changes in match state
activates the interrupt (INTB) output.
RTIUIE:
The RTIUIE bit controls the activation of the interrupt output when the receive
identifier message changes state. When RTIUIE is a logic one, changes in
the received path trace identifier message stable/unstable state will activate
the interrupt (INTB) output.
RRAMACC:
The RRAMACC bit directs read and writes access to either the receive or
transmit path trace buffer. When RRAMACC is a logic one, microprocessor
accesses are directed to the receive path trace buffer. When RRAMACC is a
logic zero, microprocessor accesses are directed to the transmit path trace
buffer.
ZEROEN:
The zero enable bit (ZEROEN) enables TIM assertion and removal based on
an all ZERO’s path trace message string. When ZEROEN is set high, all
ZERO’s path trace message strings are considered when entering and exiting
TIM states. When ZEROEN is set low, all ZERO’s path trace message strings
are ignored.
Reserved:
The reserved bits must be programmed to logic zero for proper operation.
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Register 0x51: SPTB Path Trace Identifier Status
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Type
R
R
R
R
R
Function
BUSY
Unused
Unused
Unused
RTIUI
RTIUV
RTIMI
RTIMV
Default
0
X
X
X
X
X
X
X
This register reports the path trace identifier status of the SPTB.
RTIMV:
The RTIMV bit reports the match/mismatch status of the identifier message
framer. RTIMV is a logic one when the accepted identifier message differs
from the expected message written by the microprocessor. RTIMV is a logic
zero when the accepted message matches the expected message.
RTIMI:
The RTIMI bit is a logic one when match/mismatch status of the trace
identifier framer changes state. This bit is cleared when this register is read.
RTIUV:
The RTIUV bit reports the stable/unstable status of the identifier message
framer. RTIUV is a logic one when the current received path trace identifier
message has not matched the previous message for eight consecutive
messages. RTIUV is a logic zero when the current message becomes the
accepted message as determined by the PER5 bit in the SPTB Control
register.
RTIUI:
The RTIUI bit is a logic one when stable/unstable status of the trace identifier
framer changes state. This bit is cleared when this register is read.
BUSY:
The BUSY bit reports whether a previously initiated indirect read or write to a
message buffer was completed. BUSY is set to a logic one immediately upon
writing to the SPTB Indirect Address register, and stays high until the initiated
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access is completed (about 0.6 µs). This register should be polled to
determine when new data is available in the SPTB Indirect Data register.
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Register 0x52: SPTB Indirect Address Register
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Function
RWB
A[6]
A[5]
A[4]
A[3]
A[2]
A[1]
A[0]
Default
0
0
0
0
0
0
0
0
This register supplies the address used to index into path trace identifier buffers.
A[6:0]:
The indirect read address bits (A[6:0]) are used to address the path trace
identifier buffers. When RRAMACC is set high, addresses 0 to 63 reference
the captured message page while addresses 64 to 127 reference the
expected message page of the receive path trace buffer. The captured
message page contains the identifier bytes extracted from the receive stream.
The expected message page contains the path trace message to which the
captured message page is compared. When RRAMACC is set low,
addresses 0 to 63 reference the transmit path trace buffer which contains the
path trace message inserted in the transmit stream.
RWB:
The access control bit (RWB) selects between an indirect read or write
access to the selected path trace buffer (receive or transmit as determined by
the RRAMACC bit). Writing to this register initiates an access to the selected
path trace buffer. When RWB is a logic one, a read access is initiated. The
addressed location's contents are placed in the SPTB Indirect Data register.
When RWB is a logic zero, a write access is initiated. The data in the SPTB
Indirect Data register is written to the addressed location in the selected
buffer.
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Register 0x53: SPTB Indirect Data Register
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Function
D[7]
D[6]
D[5]
D[4]
D[3]
D[2]
D[1]
D[0]
Default
0
0
0
0
0
0
0
0
This register contains the data read from the path trace message buffer after a
read operation or the data to be written into the buffer before a write operation.
D[7:0]:
The indirect data bits (D[7:0]) contains the data read from either the transmit
or receive path trace buffer after an indirect read operation is completed. The
data that is written to a buffer is set up in this register before initiating the
indirect write operation.
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Register 0x54: SPTB Expected Path Signal Label
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Function
EPSL[7]
EPSL[6]
EPSL[5]
EPSL[4]
EPSL[3]
EPSL[2]
EPSL[1]
EPSL[0]
Default
0
0
0
0
0
0
0
0
EPSL[7:0]:
The EPSL[7:0] bits contain the expected path signal label byte (C2).
EPSL[7:0] is compared with the C2 byte extracted from the receive stream. A
path signal label match or mismatch is declared based upon the following
table:
Expect
00
00
00
01
01
01
XX
XX
XX
XX
Receive
00
01
XX
00
01
XX
00
01
XX
YY
Action Declared
Match
Mismatch
Mismatch
Mismatch
Match
Match
Mismatch
Match
Match
Mismatch
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Register 0x55: SPTB Path Signal Label Status
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Type
R/W
R/W
R
R
R
R
Function
RPSLUIE
RPSLMIE
Unused
Unused
RPSLUI
RPSLUV
RPSLMI
RPSLMV
Default
0
0
X
X
X
X
X
X
This register reports the path signal label status of the SPTB.
RPSLMV:
The RPSLMV bit reports the match/mismatch status between the expected
and the accepted path signal label. RPSLMV is a logic one when the
accepted PSL results in a mismatch with the expected PSL written by the
microprocessor. RPSLMV is a logic zero when the accepted PSL results in a
match with the expected PSL.
RPSLMI:
The RPSLMI bit is a logic one when the match/mismatch status between the
accepted and the expected path signal label changes state. This bit is
cleared when this register is read.
RPSLUV:
The RPSLUV reports the stable/unstable status of the path signal label in the
receive stream. RPSLUV is a logic one when the current received C2 byte
differs from the previous C2 byte for five consecutive frames. RPSLUV is a
logic zero when the same PSL code is received for five consecutive frames.
RPSLUI:
The RPSLUI bit is a logic one when the stable/unstable status of the path
signal label changes state. This bit is cleared when this register is read.
RPSLMIE:
The RPSLMIE bit is the interrupt enable for the path signal label
match/mismatch status. When RPSLMIE is a logic one changes in the match
state generate an interrupt.
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RPSLUIE:
The RPSLUIE bit is the interrupt enable for the path signal label
stable/unstable status. When RPSLUIE is a logic one, changes in the
stable/unstable state generate an interrupt.
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Register 0x60: RXCP_50 Configuration 1
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Type
R/W
R/W
R/W
R/W
R/W
Function
DDSCR
Reserved
Unused
Unused
Unused
HCSADD
Reserved
DISCOR
Default
0
0
X
X
X
1
0
0
DISCOR:
The DISCOR bit controls the HCS error correction algorithm. When DISCOR
is a logic zero, the error correction algorithm is enabled, and single-bit errors
detected in the cell header are corrected. When DISCOR is a logic one, the
error correction algorithm is disabled, and any error detected in the cell
header is treated as an uncorrectable HCS error.
HCSADD:
The HCSADD bit controls the addition of the coset polynomial, x6+x4+x2+1, to
the HCS octet prior to comparison. When HCSADD is a logic one, the
polynomial is added, and the resulting HCS is compared. When HCSADD is
a logic zero, the polynomial is not added, and the unmodified HCS is
compared.
DDSCR:
The DDSCR bit controls the de-scrambling of the cell payload with the
polynomial x43 + 1. When DDSCR is set to logic one, cell payload descrambling is disabled. When DDSCR is set to logic zero, payload descrambling is enabled.
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Register 0x61: RXCP_50 Configuration 2
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Function
CCDIS
HCSPASS
IDLEPASS
Reserved
Reserved
Reserved
HCSFTR[1]
HCSFTR[0]
Default
0
0
0
0
0
0
0
0
HCSFTR[1:0]:
The HCS filter bits, HCSFTR[1:0] indicate the number of consecutive errorfree cells required, while in detection mode, before reverting back to
correction mode.
HCSFTR[1:0]
00
01
10
11
Cell Acceptance Threshold
One ATM cell with correct HCS before resumption of cell
acceptance. This cell is accepted.
Two ATM cells with correct HCS before resumption of cell
acceptance. The last cell is accepted.
Four ATM cells with correct HCS before resumption of cell
acceptance. The last cell is accepted.
Eight ATM cells with correct HCS before resumption of cell
acceptance. The last cell is accepted.
IDLEPASS:
The IDLEPASS bit controls the function of the Idle Cell filter. When
IDLEPASS is written with a logic zero, all cells that match the Idle Cell Header
Pattern and Idle Cell Header Mask are filtered out. When IDLEPASS is a
logic one, the Idle Cell Header Pattern and Mask registers are ignored. The
default state of this bit and the bits in the Idle Cell Header Mask and Idle Cell
Header Pattern Registers enable the dropping of idle cells.
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HCSPASS:
The HCSPASS bit controls the dropping of cells based on the detection of an
uncorrectable HCS error. When HCSPASS is a logic zero, cells containing an
uncorrectable HCS error are dropped. When HCSPASS is a logic one, cells
are passed to the receive FIFO regardless of errors detected in the HCS.
Additionally, the HCS verification finite state machine never exits the
correction mode.
Regardless of the programming of this bit, cells are always dropped while the
cell delineation state machine is in the 'HUNT' or 'PRESYNC' states unless
the CCDIS bit in this register is set to logic one.
CCDIS:
The CCDIS bit can be used to disable all cell filtering and cell delineation. All
payload data read from the RXCP_50 is passed into its FIFO without the
requirement of having to find cell delineation first. Reserved:
The reserved bits must be programmed to logic zero for proper operation.
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Register 0x62: RXCP_50 FIFO/UTOPIA Control & Config
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Type
R/W
R/W
R/W
R/W
Function
RXPTYP
Unused
RCAINV
RCALEVEL0
Unused
Unused
Unused
FIFORST
Default
0
X
0
1
X
X
X
0
FIFORST:
The FIFORST bit is used to reset the four-cell receive FIFO. When FIFORST
is set to logic zero, the FIFO operates normally. When FIFORST is set to
logic one, the FIFO is immediately emptied and ignores writes. The FIFO
remains empty and continues to ignore writes until a logic zero is written to
FIFORST.
RCALEVEL0:
The RCA (and DRCA[x]) level 0 bit, RCALEVEL0, determines what output
RCA (and DRCA[x]) indicates when it transitions low. When RCALEVEL0 is
set to logic one, a high-to-low transition on output DRCA[x] and RCA indicates
that the receive FIFO is empty. DRCA[x] and RCA, if polled, will de-assert on
the rising RFCLK edge after Payload word 24 is output. When RCALEVEL0
is set to logic zero, a high-to-low transition on output DRCA[x] and RCA, if
polled, indicates that the receive FIFO is near empty. DRCA[x] and RCA, if
polled, will de-assert on the rising RFCLK edge after Payload word 19 is
output.
RCAINV:
The RCAINV bit inverts the polarity of the DRCA[x] and RCA output signal.
When RCAINV is a logic one, the polarity of DRCA[x] and RCA is inverted
(DRCA[x] and RCA at logic zero means there is a receive cell available to be
read). When RCAINV is a logic zero, the polarity of RCA and DRCA[x] is not
inverted.
RXPTYP:
The RXPTYP bit selects even or odd parity for output RPRTY. When set to
logic one, output RPRTY is the even parity bit for outputs RDAT[15:0]. When
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RXPTYP is set to logic zero, RPRTY is the odd parity bit for outputs
RDAT[15:0].
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Register 0x63: RXCP_50 Interrupt Enables and Counter Status
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Type
R
R
R/W
R/W
R/W
R/W
R/W
Function
XFERI
OVR
Unused
XFERE
OOCDE
HCSE
FOVRE
LCDE
Default
X
X
X
0
0
0
0
0
LCDE:
The LCDE bit enables the generation of an interrupt due to a change in the
LCD state. When LCDE is set to logic one, the interrupt is enabled.
FOVRE:
The FOVRE bit enables the generation of an interrupt due to a FIFO overrun
error condition. When FOVRE is set to logic one, the interrupt is enabled.
HCSE:
The HCSE bit enables the generation of an interrupt due to the detection of a
corrected or an uncorrected HCS error. When HCSE is set to logic one, the
interrupt is enabled.
OOCDE:
The OOCDE bit enables the generation of an interrupt due to a change in cell
delineation state. When OOCDE is set to logic one, the interrupt is enabled.
XFERE:
The XFERE bit enables the generation of an interrupt when an accumulation
interval is completed and new values are stored in the RXCP_50 Count
registers. When XFERE is set to logic one, the interrupt is enabled.
OVR:
The OVR bit is the overrun status of the RXCP_50 Performance Monitoring
Count registers. A logic one in this bit position indicates that a previous
transfer (indicated by XFERI being logic one) has not been acknowledged
before the next accumulation interval has occurred and that the contents of
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the RXCP_50 Count registers have been overwritten. OVR is set to logic
zero when this register is read.
XFERI:
The XFERI bit indicates that a transfer of RXCP_50 Performance Monitoring
Count data has occurred. A logic one in this bit position indicates that the
RXCP_50 Count registers have been updated. This update is initiated by
writing to one of the RXCP_50 Count register locations or to the
S/UNI-TETRA Identification, Master Reset, and Global Monitor Update
register. XFERI is set to logic zero when this register is read.
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Register 0x64: RXCP_50 Status/Interrupt Status
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Type
R
R
R
R
R
R
R
Function
OOCDV
LCDV
Unused
OOCDI
CHCSI
UHCSI
FOVRI
LCDI
Default
X
X
X
X
X
X
X
X
LCDI:
The LCDI bit is set high when there is a change in the loss of cell delineation
(LCD) state. This bit is reset immediately after a read to this register.
FOVRI:
The FOVRI bit is set to logic one when a FIFO overrun occurs. This bit is
reset immediately after a read to this register. When the RXCP Interrupt
Status register is read, the FOVRI is cleared and will not assert again even if
FIFO is still in overrun. A FIFO reset should be performed to allow the
reassertion of the FOVRI interrupt.
UHCSI:
The UHCSI bit is set high when an uncorrected HCS error is detected. This
bit is reset immediately after a read to this register.
CHCSI:
The CHCSI bit is set high when a corrected HCS error is detected. This bit is
reset immediately after a read to this register.
OOCDI:
The OOCDI bit is set high when the RXCP_50 enters or exits the SYNC state.
The OOCDV bit indicates whether the RXCP_50 is in the SYNC state or not.
The OOCDI bit is reset immediately after a read to this register.
LCDV:
The LCDV bit gives the Loss of Cell Delineation state. When LCD is logic
one, an out of cell delineation (OCD) defect has persisted for the number of
cells specified in the LCD Count Threshold register. When LCD is logic zero,
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no OCD has persisted for the number of cells specified in the LCD Count
Threshold register. The cell time period can be varied by using the LCDC[7:0]
register bits in the RXCP_50 LCD Count Threshold register.
OOCDV:
The OOCDV bit indicates the cell delineation state. When OOCDV is high,
the cell delineation state machine is in the 'HUNT' or 'PRESYNC' states and is
hunting for the cell boundaries. When OOCDV is low, the cell delineation
state machine is in the 'SYNC' state and cells are passed through the receive
FIFO.
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Register 0x65: RXCP_50 LCD Count Threshold (MSB)
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Type
R/W
R/W
R/W
Function
Unused
Unused
Unused
Unused
Unused
LCDC[10]
LCDC[9]
LCDC[8]
Default
X
X
X
X
X
0
0
1
Register 0x66: RXCP_50 LCD Count Threshold (LSB)
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Function
LCDC[7]
LCDC[6]
LCDC[5]
LCDC[4]
LCDC[3]
LCDC[2]
LCDC[1]
LCDC[0]
Default
0
1
1
0
1
0
0
0
LCDC[10:0]:
The LCDC[10:0] bits represent the number of consecutive cell periods the
receive cell processor must be out of cell delineation before loss of cell
delineation (LCD) is declared. Likewise, LCD is not de-asserted until receive
cell processor is in cell delineation for the number of cell periods specified by
LCDC[10:0].
The default value of LCD[10:0] is 360, which translates to an average cell
period of 2.83 µs and a default LCD integration period of 1.02 ms.
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Register 0x67: RXCP_50 Idle Cell Header Pattern
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Function
GFC[3]
GFC[2]
GFC[1]
GFC[0]
PTI[3]
PTI[2]
PTI[1]
CLP
Default
0
0
0
0
0
0
0
1
GFC[3:0]:
The GFC[3:0] bits contain the pattern to match in the first, second, third, and
fourth bits of the first octet of the 53-octet cell, in conjunction with the Idle Cell
Header Mask Register. The IDLEPASS bit in the Configuration 2 Register
must be set to logic zero to enable dropping of cells matching this pattern.
Note that an all-zeros pattern must be present in the VPI and VCI fields of the
idle or unassigned cell.
PTI[2:0]:
The PTI[2:0] bits contain the pattern to match in the fifth, sixth, and seventh
bits of the fourth octet of the 53-octet cell, in conjunction with the Idle Cell
Header Mask Register. The IDLEPASS bit in the Configuration 2 Register
must be set to logic zero to enable dropping of cells matching this pattern.
CLP:
The CLP bit contains the pattern to match in the eighth bit of the fourth octet
of the 53-octet cell, in conjunction with the Match Header Mask Register. The
IDLEPASS bit in the RXCP_50 Configuration 2 Register must be set to logic
zero to enable dropping of cells matching this pattern.
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Register 0x68: RXCP_50 Idle Cell Header Mask
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Function
MGFC[3]
MGFC[2]
MGFC[1]
MGFC[0]
MPTI2]
MPTI[1]
MPTI[0]
MCLP
Default
1
1
1
1
1
1
1
1
MGFC[3:0]:
The MGFC[3:0] bits contain the mask pattern for the first, second, third, and
fourth bits of the first octet of the 53-octet cell. This mask is applied to the Idle
Cell Header Pattern Register to select the bits included in the cell filter. A
logic one in any bit position enables the corresponding bit in the pattern
register to be compared. A logic zero causes the masking of the
corresponding bit.
MPTI[3:0]:
The MPTI[3:0] bits contain the mask pattern for the fifth, sixth, and seventh
bits of the fourth octet of the 53-octet cell. This mask is applied to the Idle
Cell Header Pattern Register to select the bits included in the cell filter. A
logic one in any bit position enables the corresponding bit in the pattern
register to be compared. A logic zero causes the masking of the
corresponding bit.
MCLP:
The CLP bit contains the mask pattern for the eighth bit of the fourth octet of
the 53-octet cell. This mask is applied to the Idle Cell Header Pattern
Register to select the bits included in the cell filter. A logic one in this bit
position enables the MCLP bit in the pattern register to be compared. A logic
zero causes the masking of the MCLP bit.
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Register 0x69: RXCP_50 Corrected HCS Error Count
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Type
R
R
R
R
R
R
R
R
Function
CHCS[7]
CHCS[6]
CHCS[5]
CHCS[4]
CHCS[3]
CHCS[2]
CHCS[1]
CHCS[0]
Default
X
X
X
X
X
X
X
X
CHCS[7:0]:
The CHCS[7:0] bits indicate the number of corrected HCS error events that
occurred during the last accumulation interval. The contents of these
registers are valid a maximum of 40 RCLK periods after a transfer is triggered
by a write to one of RXCP_50's performance monitor counters or to the
S/UNI-TETRA Channel Reset, and Monitoring Update register.
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Register 0x6A: RXCP_50 Uncorrected HCS Error Count
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Type
R
R
R
R
R
R
R
R
Function
UHCS[7]
UHCS[6]
UHCS[5]
UHCS[4]
UHCS[3]
UHCS[2]
UHCS[1]
UHCS[0]
Default
X
X
X
X
X
X
X
X
UHCS[7:0]:
The UHCS[7:0] bits indicate the number of uncorrectable HCS error events
that occurred during the last accumulation interval. The contents of these
registers are valid a maximum of 40 RCLK periods after a transfer is triggered
by a write to one of RXCP_50's performance monitor counters or to the
S/UNI-TETRA Channel Reset and Monitoring Update register.
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Register 0x6B: RXCP_50 Receive Cell Counter (LSB)
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Type
R
R
R
R
R
R
R
R
Function
RCELL[7]
RCELL[6]
RCELL[5]
RCELL[4]
RCELL[3]
RCELL[2]
RCELL[1]
RCELL[0]
Default
X
X
X
X
X
X
X
X
Register 0x6C: RXCP_50 Receive Cell Counter
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Type
R
R
R
R
R
R
R
R
Function
RCELL[15]
RCELL[14]
RCELL[13]
RCELL[12]
RCELL[11]
RCELL[10]
RCELL[9]
RCELL[8]
Default
X
X
X
X
X
X
X
X
Register 0x6D: RXCP_50 Receive Cell Counter (MSB)
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Type
R
R
R
Function
Unused
Unused
Unused
Unused
Unused
RCELL[18]
RCELL[17]
RCELL[16]
Default
X
X
X
X
X
X
X
X
RCELL[20:0]:
The RCELL[18:0] bits indicate the number of cells received and written into
the receive FIFO during the last accumulation interval. Cells received and
filtered due to HCS errors or Idle cell matches are not counted. The counter
should be polled every second to avoid saturation. The contents of these
registers are valid a maximum of 67 RCLK periods after a transfer is triggered
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by a write to one of RXCP_50's performance monitor counters or to the
S/UNI-TETRA Channel Reset and Monitoring Update register.
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Register 0x6E: RXCP_50 Idle Cell Counter (LSB)
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Type
R
R
R
R
R
R
R
R
Function
ICELL[7]
ICELL[6]
ICELL[5]
ICELL[4]
ICELL[3]
ICELL[2]
ICELL[1]
ICELL[0]
Default
X
X
X
X
X
X
X
X
Register 0x6F: RXCP_50 Idle Cell Counter
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Type
R
R
R
R
R
R
R
R
Function
ICELL[15]
ICELL[14]
ICELL[13]
ICELL[12]
ICELL[11]
ICELL[10]
ICELL[9]
ICELL[8]
Default
X
X
X
X
X
X
X
X
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Register 0x70: RXCP_50 Idle Cell Counter (MSB)
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Type
R
R
R
Function
Unused
Unused
Unused
Unused
Unused
ICELL[18]
ICELL[17]
ICELL[16]
Default
X
X
X
X
X
X
X
X
ICELL[18:0]:
The ICELL[18:0] bits indicate the number of idle cells received during the last
accumulation interval. The counter should be polled every second to avoid
saturation. The contents of these registers are valid a maximum of 67 RCLK
periods after a transfer is triggered by a write to one of RXCP_50's
performance monitor counters or to the S/UNI-TETRA’s Channel Reset, and
Monitoring Update register.
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Register 0x80: TXCP_50 Configuration 1
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Function
TPTYP
TCALEVEL0
Reserved
Reserved
HCSB
HCSADD
DSCR
FIFORST
Default
0
0
0
0
0
1
0
0
FIFORST:
The FIFORST bit is used to reset the four cell transmit FIFO. When FIFORST
is set to logic zero, the FIFO operates normally. When FIFORST is set to logic
one, the FIFO is immediately emptied and ignores writes. The FIFO remains
empty and continues to ignore writes until a logic zero is written to FIFORST.
Null/unassigned cells are transmitted until a subsequent cell is written to the
FIFO.
DSCR:
The DSCR bit controls the scrambling of the cell payload. When DSCR is a
logic one, cell payload scrambling is disabled. When DSCR is a logic zero,
payload scrambling is enabled.
HCSADD:
The HCSADD bit controls the addition of the coset polynomial, x6+x4+x2+1,
to the HCS octet prior to insertion in the synchronous payload envelope.
When HCSADD is a logic one, the polynomial is added, and the resulting
HCS is inserted. When HCSADD is a logic zero, the polynomial is not added,
and the unmodified HCS is inserted. HCSADD takes effect unconditionally
regardless of whether a null/unassigned cell is being transmitted or whether
the HCS octet was read from the FIFO.
HCSB:
The active low HCSB bit enables the internal generation and insertion of the
HCS octet into the transmit cell stream. When HCSB is logic zero, the HCS is
generated and inserted internally. If HCSB is logic one , then no HCS octet is
inserted in the transmit data stream.
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TCALEVEL0:
The active high TCA (and DTCA[x]) level 0 bit, TCALEVEL0 determines what
output TCA (and DTCA[x]) indicates when it transitions low. When
TCALEVEL0 is set to logic one, output TCA (and DTCA[x]) indicates that the
transmit FIFO is full and will de-assert after word 24 of the current cell
transfer. The FIFO can accept no more writes. When TCALEVEL0 is set to
logic zero, output TCA (and DTCA[x]) indicates that the transmit FIFO is near
full and will de-assert after word 19 of the current cell transfer.
TPTYP:
The TPTYP bit selects even or odd parity for input TPRTY. When set to logic
one, input TPRTY is the even parity bit for the TDAT input bus. When set to
logic zero, input TPRTY is the odd parity bit for the TDAT input bus.
Reserved
The reserved bits must be programmed to logic zero for proper operation.
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Register 0x81: TXCP_50 Configuration 2
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Type
R/W
R/W
R/W
R/W
R/W
Function
Unused
Unused
Unused
TCAINV
FIFODP[1]
FIFODP[0]
DHCS
HCSCTLEB
Default
X
X
X
0
0
0
0
0
HCSCTLEB:
The active low HCS control enable, HCSCTLEB bit enables the XORing of
the HCS Control byte with the generated HCS. When set to logic zero, the
HCS Control byte provided in the third word of the 27 word data structure is
XORed with the generated HCS. When set to logic one, XORing is disabled
and the HCS Control byte is ignored.
DHCS:
The DHCS bit controls the insertion of HCS errors for diagnostic purposes.
When DHCS is set to logic one, the HCS octet is inverted prior to insertion in
the synchronous payload envelope. DHCS takes effect unconditionally
regardless of whether a null/unassigned cell is being transmitted or whether
the HCS octet was read from the FIFO. DHCS occurs after any error
insertion caused by the Control Byte in the 27-word data structure.
FIFODP[1:0]:
The FIFODP[1:0] bits determine the transmit FIFO cell depth at which TCA
and DTCA[x] de-assert. FIFO depth control may be important in systems
where the cell latency through the TXCP_50 must be minimized. When the
FIFO is filled to the specified depth, the transmit cell available signal, TCA
(and DTCA[x]) is asserted. Note that regardless of what fill level FIFODP[1:0]
is set to, the transmit cell processor can store 4 complete cells. The
selectable FIFO cell depths are shown below:
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FIFODP[1]
0
0
1
1
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FIFODP[0]
0
1
0
1
FIFO DEPTH
4 cells
3 cells
2 cells
1 cell
TCAINV:
The TCAINV bit inverts the polarity of the TCA (and DTCA[x]) output
signal. When TCAINV is a logic one, the polarity of TCA (and
DTCA[x]) is inverted (TCA (and DTCA[x]) at logic zero means there is
transmit cell space available to be written to). When TCAINV is a logic
zero, the polarity of TCA (and DTCA[x]) is not inverted.
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Register 0x82: TXCP_50 Cell Count Status/Configuration Options
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Type
R/W
R
R
R/W
R/W
R/W
R/W
Function
XFERE
XFERI
OVR
Unused
Reserved
H4INSB
Reserved
Reserved
Default
0
X
X
X
1
0
0
0
H4INSB:
The active low H4 insert enable, H4INSB, determines the contents of the H4
byte in the outgoing path overhead. If H4INSB is set to logic one, the H4 byte
is set to the value of 00 hexadecimal. If H4INSB is set to logic zero, the H4
byte is set to the cell indicator offset value.
XFERI:
The XFERI bit indicates that a transfer of Transmit Cell Count data has
occurred. A logic one in this bit position indicates that the Transmit Cell Count
registers have been updated. This update is initiated by writing to one of the
Transmit Cell Count register locations or to the S/UNI-TETRA Identification,
Master Reset, and Global Monitor Update register. XFERI is set to logic zero
when this register is read.
OVR:
The OVR bit is the overrun status of the Transmit Cell Count registers. A logic
one in this bit position indicates that a previous transfer (indicated by XFERI
being logic one) has not been acknowledged before the next accumulation
interval has occurred and that the contents of the Transmit Cell Count
registers have been overwritten. OVR is set to logic zero when this register is
read.
XFERE:
The XFERE bit enables the generation of an interrupt when an accumulation
interval is completed and new values are stored in the Transmit Cell Count
registers. When XFERE is set to logic one, the interrupt is enabled.
Reserved:
These bits should be set to their default values for proper operation
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Register 0x83: TXCP_50 Interrupt Enable/Status
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Type
R/W
R/W
R/W
R
R
R
Function
TPRTYE
FOVRE
TSOCE
Unused
Unused
TPRTYI
FOVRI
TSOCI
Default
0
0
0
X
X
X
X
X
TSOCI:
The TSOCI bit is set high when the TSOC input is sampled high during any
position other than the first word of the selected data structure. The write
address counter is reset to the first word of the data structure when TSOC is
sampled high. This bit is reset immediately after a read to this register.
FOVRI:
The FOVRI bit is set high when an attempt is made to write into the FIFO
when it is already full. This bit is reset immediately after a read to this register
TPRTYI:
The TPRTYI bit indicates if a parity error was detected on the TDAT input bus.
When logic one, the TPRTYI bit indicates a parity error over the active TDAT
bus. This bit is cleared when this register is read. Odd or even parity is
selected using the TPTYPE bit.
TSOCE:
The TSOCE bit enables the generation of an interrupt when the TSOC input is
sampled high during any position other than the first word of the selected data
structure. When TSOCE is set to logic one, the interrupt is enabled.
FOVRE:
The FOVRE bit enables the generation of an interrupt due to an attempt to
write the FIFO when it is already full. When FOVRE is set to logic one, the
interrupt is enabled.
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TPRTYE:
The TPRTYE bit enables transmit parity interrupts. When set to logic one,
parity errors are indicated on INT and TPRTYI. When set to logic zero, parity
errors are indicated using bit TPRTYI but are not indicated on output INT.
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Register 0x84: TXCP_50 Idle Cell Header Control
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Function
GFC[3]
GFC[2]
GFC[1]
GFC[0]
PTI[2]
PTI[1]
PTI[0]
CLP
Default
0
0
0
0
0
0
0
1
CLP:
The CLP bit contains the eighth bit position of the fourth octet of the
idle/unassigned cell pattern. Cell rate decoupling is accomplished by
transmitting idle cells when the TXCP_50 detects that no outstanding cells
exist in the transmit FIFO.
PTI[3:0]:
The PTI[3:0] bits contains the fifth, sixth, and seventh bit positions of the
fourth octet of the idle/unassigned cell pattern. Idle cells are transmitted
when the TXCP_50 detects that no outstanding cells exist in the transmit
FIFO.
GFC[3:0]:
The GFC[3:0] bits contain the first, second, third, and fourth bit positions of
the first octet of the idle/unassigned cell pattern. Idle/unassigned cells are
transmitted when the TXCP_50 detects that no outstanding cells exist in the
transmit FIFO. The all zeros pattern is transmitted in the VCI and VPI fields of
the idle cell.
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Register 0x85: TXCP_50 Idle Cell Payload Control
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Function
PAYLD[7]
PAYLD[6]
PAYLD[5]
PAYLD[4]
PAYLD[3]
PAYLD[2]
PAYLD[1]
PAYLD[0]
Default
0
1
1
0
1
0
1
0
PAYLD[7:0]:
The PAYLD[7:0] bits contain the pattern inserted in the idle cell payload. Idle
cells are inserted when the TXCP_50 detects that the transmit FIFO contains
no outstanding cells. PAYLD[7] is the most significant bit and is the first bit
transmitted. PAYLD[0] is the least significant bit.
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Register 0x86: TXCP_50 Transmit Cell Count (LSB)
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Type
R
R
R
R
R
R
R
R
Function
TCELL[7]
TCELL[6]
TCELL[5]
TCELL[4]
TCELL[3]
TCELL[2]
TCELL[1]
TCELL[0]
Default
X
X
X
X
X
X
X
X
Register 0x87: TXCP_50 Transmit Cell Count
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Type
R
R
R
R
R
R
R
R
Function
TCELL[15]
TCELL[14]
TCELL[13]
TCELL[12]
TCELL[11]
TCELL[10]
TCELL[9]
TCELL[8]
Default
X
X
X
X
X
X
X
X
Register 0x88: TXCP_50 Transmit Cell Count (MSB)
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Type
R
R
R
Function
Unused
Unused
Unused
Unused
Unused
TCELL[18]
TCELL[17]
TCELL[16]
Default
X
X
X
X
X
X
X
X
TCELL[15:0]:
The TCELL[18:0] bits indicate the number of cells read from the transmit FIFO
and inserted into the transmission stream during the last accumulation
interval. Idle cells inserted into the transmission stream are not counted.
A write to any one of the TXCP_50 Transmit Cell Counter registers or to the
S/UNI-TETRA Channel Reset and Monitoring Update register (Register 0x05)
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loads the registers with the current counter value and resets the internal 19 bit
counter to 1 or 0. The counter reset value is dependent on if there was a
count event during the transfer of the count to the Transmit Cell Counter
registers. The counter should be polled every second to avoid saturating. The
contents of these registers are valid after a maximum of 5 µs after a transfer
is triggered by a write to a TXCP_50 Transmit Cell count Register or the
S/UNI-TETRA Channel Reset and Monitoring Update register (Register
0x05).
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Register 0x90: S/UNI-TETRA Channel Auto Line RDI Control
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Function
SDLRDI
SFLRDI
LOFLRDI
LOSLRDI
RTIMLRDI
RTIULRDI
LAISLRDI
Unused
Default
0
0
1
1
0
0
1
X
This register controls the auto assertion of line RDI in the local TLOP. Since the
S/UNI-TETRA provides STS-3c (STM-1/AU4) mappings, this register controls the
assertion of line RDI for the entire SONET/SDH stream.
LAISLRDI:
The Line Alarm Indication Signal LRDI (LAISLRDI) controls the insertion of a
Line RDI in the transmit data stream upon detection of this alarm condition.
When LAISLRDI is set to logic one, the transmit line RDI will be inserted.
When LAISLRDI is set to logic zero, no action is taken. This register bit has
effect only if the AUTOLRDI register bit is also set to logic one.
RTIULRDI:
The Receive Trace Identifier Unstable LRDI (RTIULRDI) controls the insertion
of a Line RDI in the transmit data stream upon detection of this alarm
condition. When RTIULRDI is set to logic one, the transmit line RDI will be
inserted. When RTIULRDI is set to logic zero, no action is taken. This register
bit has effect only if the AUTOLRDI register bit is also set to logic one.
RTIMLRDI:
The Receive Trace Identifier Mismatch LRDI (RTIMLRDI) controls the
insertion of a Line RDI in the transmit data stream upon detection of this
alarm condition. When RTIMLRDI is set to logic one, the transmit line RDI will
be inserted. When RTIMLRDI is set to logic zero, no action is taken. This
register bit has effect only if the AUTOLRDI register bit is also set to logic one.
LOSLRDI:
The Loss of Signal LRDI (LOSLRDI) controls the insertion of a Line RDI in the
transmit data stream upon detection of this alarm condition. When LOSLRDI
is set to logic one, the transmit line RDI will be inserted. When LOSLRDI is
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set to logic zero, no action is taken. This register bit has effect only if the
AUTOLRDI register bit is also set to logic one.
LOFLRDI:
The Loss of Frame LRDI (LOFLRDI) controls the insertion of a Line RDI in the
transmit data stream upon detection of this alarm condition. When LOFLRDI
is set to logic one, the transmit line RDI will be inserted. When LOFLRDI is
set to logic zero, no action is taken. This register bit has effect only if the
AUTOLRDI register bit is also set to logic one.
SFLRDI:
The Signal Fail BER LRDI (SFLRDI) controls the insertion of a Line RDI in the
transmit data stream upon detection of this alarm condition. When SFLRDI is
set to logic one, the transmit line RDI will be inserted. When SFLRDI is set to
logic zero, no action is taken. This register bit has effect only if the AUTOLRDI
register bit is also set to logic one.
SDLRDI:
The Signal Degrade BER LRDI (SDLRDI) controls the insertion of a Line RDI
in the transmit data stream upon detection of this alarm condition. When
SDLRDI is set to logic one, the transmit line RDI will be inserted. When
SDLRDI is set to logic zero, no action is taken. This register bit has effect only
if the AUTOLRDI register bit is also set to logic one.
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Register 0x91: S/UNI-TETRA Channel Auto Path RDI Control
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Type
Function
R/W
LCDPRDI
R/W
ALRMPRDI
R/W
PAISPRDI
R/W
PSLMPRDI
R/W
LOPPRDI
R/W LOPCONPRDI
R/W
PTIUPRDI
R/W
PTIMPRDI
Default
0
0
1
1
1
1
1
1
This register controls the auto assertion of path RDI (G1 bit 5) in the local TPOP.
Since the S/UNI-TETRA provides STS-3c (STM-1/AU4) mappings, this register
controls the assertion of path RDI for the entire SONET/SDH stream. See also
the S/UNI-TETRA Channel Auto Enhanced Path RDI register.
RTIMPRDI:
The Receive Trace Identifier Mismatch PRDI (RTIMPRDI) controls the
insertion of a Path RDI in the transmit data stream upon detection of this
alarm condition. When RTIMPRDI is set to logic one, the transmit line RDI will
be inserted. When RTIMPRDI is set to logic zero, no action is taken. This
register bit has effect only if the AUTOPRDI register bit is also set to logic
one.
PTIUPRDI:
The Path Trace Identifier Unstable PRDI (PTIUPRDI) controls the insertion of
a Path RDI in the transmit data stream upon detection of this alarm condition.
When PTIUPRDI is set to logic one, the transmit line RDI will be inserted.
When PTIUPRDI is set to logic zero, no action is taken. This register bit has
effect only if the AUTOPRDI register bit is also set to logic one.
LOPCONPRDI:
The Loss of Pointer Concatenation Indication PRDI (LOPCONPRDI) controls
the insertion of a Path RDI in the transmit data stream upon detection of this
alarm condition. When LOPCONPRDI is set to logic one, the transmit line RDI
will be inserted. When LOPCONPRDI is set to logic zero, no action is taken.
This register bit has effect only if the AUTOPRDI register bit is also set to logic
one.
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LOPPRDI:
The Loss of Pointer PRDI (LOPPRDI) controls the insertion of a Path RDI in
the transmit data stream upon detection of this alarm condition. When
LOPPRDI is set to logic one, the transmit line RDI will be inserted. When
LOPPRDI is set to logic zero, no action is taken. This register bit has effect
only if the AUTOPRDI register bit is also set to logic one.
PSLMPRDI:
The Path Signal Label Mismatch PRDI (PSLMPRDI) controls the insertion of
a Path RDI in the transmit data stream upon detection of this alarm condition.
When PSLMPRDI is set to logic one, the transmit line RDI will be inserted.
When PSLMPRDI is set to logic zero, no action is taken. This register bit has
effect only if the AUTOPRDI register bit is also set to logic one.
PAISPRDI:
The Path Alarm Indication Signal PRDI (PAISPRDI) controls the insertion of a
Path RDI in the transmit data stream upon detection of this alarm condition.
When PAISPRDI is set to logic one, the transmit line RDI will be inserted.
When PAISPRDI is set to logic zero, no action is taken. This register bit has
effect only if the AUTOPRDI register bit is also set to logic one.
ALRMPRDI:
The Line Alarm Indication Signal PRDI (ALRMPRDI) controls the insertion of
a Path RDI in the transmit data stream upon detection of one of the following
alarm conditions: Loss of Signal (LOS), Loss of Frame (LOF) and Line Alarm
Indication Signal (LAIS). When ALRMPRDI is set to logic one, the transmit
line RDI will be inserted. When ALRMPRDI is set to logic zero, no action is
taken. This register bit has effect only if the AUTOPRDI register bit is also set
to logic one.
LCDPRDI
The Loss of ATM Cell Delineation Signal PRDI (LCDPRDI) controls the
insertion of Path RDI in the transmit data stream upon detection of this alarm.
When LCDPRDI is set to logic one, the transmit line RDI will be inserted.
When LCDPRDI is set to logic zero, no action is taken. This register bit is
used only if the AUTOPRDI register bit is also set to logic one.
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Register 0x92: S/UNI-TETRA Channel Auto Enhanced Path RDI Control
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Function
LCDEPRDI
ALMEPRDI
PAISEPRDI
PSLMEPRDI
LOPEPRDI
LOPCONEPRDI
TIUEPRDI
TIMEPRDI
Default
0
0
0
1
0
0
0
1
This register and the S/UNI-TETRA Channel Auto Path RDI Control register
controls the auto assertion of enhanced path RDI (G1 bits 5,6,7) in the local
TPOP. Since the S/UNI-TETRA provides a STS-3c (STM-1) mapping, this
register with its companion register controls auto enhanced path RDI assertion
on the entire transmit stream.
TIMEPRDI:
When set high, the TIMEPRDI bit enables enhanced path RDI assertion when
path trace message mismatch (TIM) events are detected in the receive
stream. If enabled, when the event occurs, bit 6 of the G1 bytes set high
while bit 7 of the G1 byte is set low.
When TIMEPRDI is set low, trace identifier mismatch events have no effect
on path RDI. In addition, this bit has no effect when EPRDI_EN is set low.
TIUEPRDI:
When set high, the TIUEPRDI bit enables enhanced path RDI assertion when
path trace message unstable events are detected in the receive stream. If
enabled, when the event occurs, bit 6 of the G1 byte is set high while bit 7 of
the G1 byte is set low.
When TIUEPRDI is set low, trace identifier unstable events have no effect on
path RDI. In addition, this bit has no effect when EPRDI_EN is set low.
LOPCONEPRDI:
When set high, the LOPCONEPRDI bit enables enhanced path RDI assertion
when loss of pointer concatenation (LOPCON) events are detected in the
receive stream. If enabled, when the event occurs, bit 6 of the G1 byte is set
low while bit 7 of the G1 byte is set high. LOPCONEPRDI has precedence
over PSLMERDI, TIUEPRDI, TIMEPRDI and UNEQERDI.
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When LOPCONEPRDI is set low, reporting of enhanced RDI is according to
PSLMERDI, TIUEPRDI, TIMEPRDI and UNEQERDI and the associated
alarm states.
LOPEPRDI:
When set high, the LOPEPRDI bit enables enhanced path RDI assertion
when loss of pointer (LOP) events are detected in the receive stream. If
enabled, when the event occurs, bit 6 of the G1 byte is set low while bit 7 of
the G1 byte is set high. LOPEPRDI has precedence over PSLMERDI,
TIUEPRDI, TIMEPRDI and UNEQERDI.
When LOPEPRDI is set low, reporting of enhanced RDI is according to
PSLMERDI, TIUEPRDI, TIMEPRDI and UNEQERDI and the associated
alarm states.
PSLMEPRDI:
When set high, the PSLMEPRDI bit enables enhanced path RDI assertion
when path signal label mismatch (PSLM) events are detected in the receive
stream. If enabled, when the event occurs, bit 6 of the G1 byte is set high
while bit 7 of the G1 byte is set low.
When PSLMEPRDI is set low, path signal label mismatch events have no
effect on path RDI. In addition, this bit has no effect when EPRDI_EN is set
low.
PAISEPRDI:
When set high, the PAISEPRDI bit enables enhanced path RDI assertion
when the path alarm indication signal state (PAIS) is detected in the receive
stream. If enabled, when the event occurs, bit 6 of the G1 byte is set low
while bit 7 of the G1 byte is set high. PAISEPRDI has precedence over
PSLMERDI, TIUEPRDI, TIMEPRDI and UNEQERDI.
When PAISEPRDI is set low, reporting of enhanced RDI is according to
PSLMERDI, TIUEPRDI, TIMEPRDI and UNEQERDI and the associated
alarm states.
ALMEPRDI:
When set high, the ALMEPRDI bit enables enhanced path RDI assertion
when loss of signal (LOS), loss of frame (LOF) or line alarm indication signal
(LAIS) events are detected in the receive stream. If enabled, when these
events occurs, bit 6 of the G1 byte is set low while bit 7 of the G1 byte is set
high. ALMEPRDI has precedence over PSLMERDI, TIUEPRDI, TIMEPRDI
and UNEQERDI.
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When ALMEPRDI is set low, reporting of enhanced RDI is according to
PSLMERDI, TIUEPRDI, TIMEPRDI and UNEQERDI and the associated
alarm states.
LCDEPRDI:
When set high, the LCDEPRDI bit enables enhanced path RDI assertion
when loss of cell delineation (LCD) events are detected in the receive stream.
If enabled, when the event occurs, bit 6 of the G1 byte is set high while bit 7
of the G1 byte is set low.
When LCDEPRDI is set low, loss of ATM cell delineation has no effect on path
RDI. In addition, this bit has no effect when EPRDI_EN is set low.
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SATURN USER NETWORK INTERFACE (155-TETRA)
Register 0x93: S/UNI-TETRA Channel Receive RDI and Enhanced RDI
Control Extensions
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Type
Function
R/W PAISCONPRDI
R/W PAISCONEPRDI
Unused
Unused
Unused
W
EPRDI_EN
R/W
UNEQPRDI
R/W
UNEQEPRDI
Default
0
0
X
X
X
0
1
1
This register along with the S/UNI-TETRA Channel Path RDI Control register
controls the auto assertion of path RDI on the TPOP transmit stream. This
register along with the S/UNI-TETRA Channel Enhanced Path RDI Control
register controls the auto assertion of enhanced path RDI on the TPOP transmit
stream.
Since the S/UNI-TETRA provides STS-3c (STM-1) mapping, this register controls
the entire SONET/SDH stream.
UNEQEPRDI:
When set high, the UNEQEPRDI bit enables enhanced path RDI assertion
when the path signal label in the receive stream indicates unequipped status.
If enabled, when the event occurs, bit 6 of the G1 byte is set high while bit 7
of the G1 byte is set low.
When UNEQEPRDI is set low, path signal label unequipped status has no
effect on enhanced path RDI.
UNEQPRDI:
When set high, the UNEQPRDI bit enables path RDI assertion when the path
signal label in the receive stream indicates unequipped status. When
UNEQPRDI is set low, the path signal label unequipped status has no effect
on path RDI.
EPRDI_EN:
The EPRDI_EN bit enables the automatic insertion of enhanced RDI in the
local transmitter. When EPRDI_EN is a logic one, auto insertion is enabled
using the event enable bits in this register. When EPRDI_EN is a logic zero,
enhanced path RDI is not automatically inserted in the transmit stream.
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PAISCONEPRDI:
When set high, the PAISCONEPRDI bit enables enhanced path RDI assertion
when path AIS concatenation (PAISCON) events are detected in the receive
stream. If enabled, when the event occurs, bit 6 of the G1 byte is set low
while bit 7 of the G1 byte is set high. PAISCONEPRDI has precedence over
PSLMERDI, TIUEPRDI, TIMEPRDI and UNEQERDI.
When PAISCONEPRDI is set low, reporting of enhanced RDI is according to
PSLMERDI, TIUEPRDI, TIMEPRDI and UNEQERDI and the associated
alarm states.
PAISCONPRDI:
When set high, the PAISCONPRDI bit enables path RDI assertion when path
AIS concatenation (PAISCON) events are detected in the receive stream.
When PAISCONPRDI is set low, path AIS concatenation events have no
effect on path RDI.
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Register 0x94: S/UNI-TETRA Channel Receive Line AIS Control
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Function
SDINS
SFINS
LOFINS
LOSINS
RTIMINS
RTIUINS
Unused
DCCAIS
Default
0
0
1
1
0
0
X
0
DCCAIS:
The DCCAIS bit enables the insertion of all ones in the section DCC (RSD)
and the line DCC (RLD) on certain alarm conditions. When DCCAIS is a logic
one, all ones is inserted in RSD when LOS or LOF is declared and all ones is
inserted in RLD when LOS, LOF or LAIS is declared. When DCCAIS is logic
zero, RSD and RLD are not altered.
RTIUINS:
The RTIUINS bit enables the insertion of line AIS in the receive direction upon
the declaration of section trace unstable. If RTIUINS is a logic one, line AIS is
inserted into the SONET/SDH frame when the current received section trace
identifier message has not matched the previous message for eight
consecutive messages. Line AIS is terminated when the current message
becomes the accepted message.
RTIMINS:
The RTIMINS bit enables the insertion of line AIS in the receive direction upon
the declaration of section trace mismatch. If RTIMINS is a logic one, line AIS
is inserted into the SONET/SDH frame when the accepted identifier message
differs from the expected message. Line AIS is terminated when the
accepted message matches the expected message.
LOSINS:
The LOSINS bit enables the insertion of line AIS in the receive direction upon
the declaration of loss of signal (LOS). If LOSINS is a logic one, line AIS is
inserted into the SONET/SDH frame when LOS is declared. Line AIS is
terminated when LOS is removed.
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LOFINS:
The LOFINS bit enables the insertion of line AIS in the receive direction upon
the declaration of loss of frame (LOF). If LOSINS is a logic one, line AIS is
inserted into the SONET/SDH frame when LOS is declared. Line AIS is
terminated when LOS is removed.
SFINS:
The SFINS bit enables the insertion of line AIS in the receive direction upon
the declaration of signal fail (SF). If SFINS is a logic one, line AIS is inserted
into the SONET/SDH frame when SF is declared. Line AIS is terminated
when SF is removed.
SDINS:
The SDINS bit enables the insertion of line AIS in the receive direction upon
the declaration of signal degrade (SD). If SDINS is a logic one, line AIS is
inserted into the SONET/SDH frame when SD is declared. Line AIS is
terminated when SD is removed.
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SATURN USER NETWORK INTERFACE (155-TETRA)
Register 0x95: S/UNI-TETRA Channel Receive Path AIS Control
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Type
Function
R/W PAISCONPAIS
R/W LOPCONPAIS
R/W
PSLUPAIS
R/W
PSLMPAIS
R/W
LOPPAIS
R/W
PAISPAIS
R/W
TIUPAIS
R/W
TIMPAIS
Default
1
1
1
1
1
1
1
1
This register controls the auto assertion of path AIS on the receive side of the
system interface. In ATM mode,path AIS forces a loss of cell delineation. In POS
mode, path AIS forces the insertion of data flags (7E) in the data stream.
TIMPAIS:
When set high, the TIMPAIS bit enables path AIS insertion on the receive side
of the system interface when path trace message mismatch (TIM) events are
detected in the receive stream. When TIMPAIS is set low, trace identifier
mismatch events will not assert path AIS.
TIUPAIS:
When set high, the TIUPAIS bit enables path AIS insertion when path trace
message unstable events are detected in the receive stream. When TIUPAIS
is set low, trace identifier unstable events will not assert path AIS.
PAISPAIS:
When set high, the PAISPAIS bit enables path AIS insertion when path AIS
events are detected in the receive stream. When PAISPAIS is set low, path
AIS events will not assert path AIS.
LOPPAIS:
When set high, the LOPPAIS bit enables path AIS insertion when loss of
pointer (LOP) events are detected in the receive stream. When LOPPAIS is
set low, loss of pointer events will not assert path AIS.
PSLMPAIS:
When set high, the PSLMPAIS bit enables path AIS insertion when path
signal label mismatch (PSLM) events are detected in the receive stream.
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When PSLMPAIS is set low, path signal label mismatch events will not assert
path AIS.
PSLUPAIS:
When set high, the PSLUPAIS bit enables path AIS insertion when path signal
label unstable (PSLU) events are detected in the receive stream. When
PSLUPAIS is set low, path signal label unstable events will not assert path
AIS.
LOPCONPAIS:
When set high, the LOPCONPAIS bit enables path AIS insertion when loss of
pointer concatenation (LOPCON) events are detected in the receive stream.
When LOPCONPAIS is set low, loss of pointer concatenation events will not
assert path AIS.
PAISCONPAIS:
When set high, the PAISCONPAIS bit enables path AIS insertion when Path
AIS concatenation (PAISCON) events are detected in the receive stream.
When PAISCONPAIS is set low, Path AIS concatenation events will not assert
path AIS.
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ISSUE 7
SATURN USER NETWORK INTERFACE (155-TETRA)
Register 0x96: S/UNI-TETRA Channel Receive Alarm Control #1
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Function
Unused
PTIMEN
PSLMEN
PERDIEN
PRDIEN
PAISEN
LCDEN
LOPEN
Default
X
0
0
0
0
0
0
0
Register 0x97: S/UNI-TETRA Channel Receive Alarm Control #2
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Function
Unused
SFBEREN
SDBEREN
LRDIEN
LAISEN
OOFEN
LOFEN
LOSEN
Default
X
0
0
0
0
0
0
0
LOSEN, LOFEN, OOFEN, LAISEN, LRDIEN, SDBEREN, SFBEREN, LOPEN,
LCDEN, PAISEN, PRDIEN, PERDIEN, PSLMEN, PTIMEN:
The above enable bits allow the corresponding alarm indications to be
reported (Ored) into the RALRM output. When the enable bit is high, the
corresponding alarm indication is combined with other alarm indications and
output on RALRM. When the enable bit is low, the corresponding alarm
indication does not affect the RALRM output.
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ISSUE 7
Alarm
LOS
LOF
OOF
LAIS
LRDI
SDBER
SFBER
LOP
LCD
PAIS
PRDI
PERDI
PSLM
PTIM
SATURN USER NETWORK INTERFACE (155-TETRA)
Description
Loss of signal
Loss of frame
Out of Frame
Line Alarm Indication Signal
Line Remote Defect Indication
Signal Degrade Bit Error Rate
Signal Fail Bit Error Rate
Loss of Pointer
Loss of cell delineation
Path Alarm Indication Signal
Path Remote Defect Indication
Path Enhanced Remote Defect Indication
Path Signal Label Mismatch
Path Trace Identifier Mismatch
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SATURN USER NETWORK INTERFACE (155-TETRA)
Register 0xA0: RXFP Configuration
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Function
RXOTYP
FCSPASS
RPAINV
FCSSEL[1]
FCSSEL[0]
RXPTYP
DDSCR
FIFORST
Default
0
0
0
1
0
0
1
0
FIFORST:
The FIFORST bit is used to reset the 256-byte receive FIFO. When
FIFORST is set to logic zero, the FIFO operates normally. When FIFORST is
set to logic one, the FIFO is immediately emptied and ignores writes. The
FIFO remains empty and continues to ignore writes until a logic zero is written
to FIFORST.
DDSCR:
The DDSCR bit controls the de-scrambling of the frame payload with the
polynomial x43 + 1. When DDSCR is set to logic zero, frame payload descrambling is disabled. When DDSCR is set to logic one, payload descrambling is enabled.
RXPTYP:
The RXPTYP bit selects even or odd parity for output RPRTY. When set to
logic one, output RPRTY is the even parity bit for outputs RDAT[15:0]. When
RXPTYP is set to logic zero, RPRTY is the odd parity bit for outputs
RDAT[15:0].
FCSSEL[1:0]:
The Frame Control Sequence select (FCSSEL[1:0]) bits allow to control the
FCS calculation according to the table below. The FCS is calculated over the
whole packet data, after byte destuffing and de-scrambling.
FCSSEL[1:0]
00
01
FCS Operation
No FCS calculated
CRC-CCITT (2 bytes)
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ISSUE 7
10
11
SATURN USER NETWORK INTERFACE (155-TETRA)
CRC-32 (4 bytes)
Reserved
RPAINV:
The RPAINV bit inverts the polarity of the RPA output signal. When RPAINV
is a logic one, the polarity of RPA is inverted (RPA at logic zero means there is
data available to be read). When RPAINV is a logic zero, the polarity of RPA
is not inverted.
FCSPASS:
The FCSPASS allow to determine if the FCS field will be passed through the
system interface or stripped. When FCSPASS is set to logic one, the POS
frame FCS field is written into the FIFO as part of the packet, and can thus be
read through the system interface. When FCSPASS is set to logic zero, the
FCS field is stripped from the POS frame.
RXOTYP:
The RXOTYP determines if the RXOFF input to the RXFP (this signal is
driven according to register 0x95 so the Rx datastream is killed under a drop
path AIS condition) will stop a packet by simply inserting HDLC flag
characters or will insert an abort sequence followed by flags. When RXOTYP
is set to logic zero, the abort sequence is inserted generating a user abort
error. When the RXOTYP is set to logic one, the frame processor performs a
simple flag insertion and thus the packet will be flagged as a FCS error.
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ISSUE 7
SATURN USER NETWORK INTERFACE (155-TETRA)
Register 0xA1: RXFP Configuration/Interrupt Enables
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Type
R/W
R/W
R/W
R/W
R/W
R/W
Function
Unused
Unused
MINLE
MAXLE
ABRTE
FCSE
FOVRE
Reserved
Default
X
X
0
0
0
0
0
0
FOVRE:
The FOVRE bit enables the generation of an interrupt due to a FIFO overrun
error condition. When FOVRE is set to logic one, the interrupt is enabled.
FCSE:
The FCSE bit enables the generation of an interrupt due to the detection of an
FCS error. When FCSE is set to logic one, the interrupt is enabled.
ABRTE:
The Abort Packet Enable bit enables the generation of an interrupt due to the
reception of an aborted packet. When ABRTE is set to logic one, the interrupt
is enabled.
MAXLE:
The Maximum Length Packet Enable bit enables the generation of an
interrupt due to the reception of an packet exceeding the programmable
maximum packet length. When MAXLE is set to logic one, the interrupt is
enabled.
MINLE:
The Minimum Length Packet Enable bit enables the generation of an interrupt
due to the reception of an packet that is smaller than the programmable
minimum packet length. When MINLE is set to logic one, the interrupt is
enabled.
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ISSUE 7
SATURN USER NETWORK INTERFACE (155-TETRA)
Register 0xA2: RXFP Interrupt Status
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Type
R
R
R
R
R
Function
Unused
Unused
MINLI
MAXLI
ABRTI
FCSI
FOVRI
Unused
Default
X
X
X
X
X
X
X
X
FOVRI:
The FOVRI bit indicates an interrupt due to a FIFO overrun error condition.
This interrupt can be masked using FOVRE.
FCSI:
The FCSI bit indicates an interrupt due to the detection of an FCS error. This
interrupt can be masked using FCSE.
ABRTI:
The ABRTI bit indicates bit enables the generation of an interrupt due to the
reception of an aborted packet. This interrupt can be masked using ABRTE.
MAXLI:
The MAXLI bit indicates an interrupt due to the reception of a packet
exceeding the programmable maximum packet length. This interrupt can be
masked using MAXLE.
MINLI:
The MINLI bit indicates an interrupt due to the reception of a packet that is
smaller than the programmable minimum packet length. This interrupt can be
masked using MINLE.
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ISSUE 7
SATURN USER NETWORK INTERFACE (155-TETRA)
Register 0xA3: RXFP Minimum Packet Length
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Function
MINPL[7]
MINPL[6]
MINPL[5]
MINPL[4]
MINPL[3]
MINPL[2]
MINPL[1]
MINPL[0]
Default
0
0
0
0
0
1
0
0
MINPL[7:0]:
The Minimum Packet Length (MINPL[7:0]) bits are used to set the minimum
packet length. Packets smaller than this length are marked with an error. The
packet length used here is defined as the number of bytes encapsulated into
the POS frame, excluding the FCS and stuffing bytes. The value 0x0000
should not be used.
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242
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ISSUE 7
SATURN USER NETWORK INTERFACE (155-TETRA)
Register 0xA4: RXFP Maximum Packet Length (LSB)
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Function
MAXPL[7]
MAXPL[6]
MAXPL[5]
MAXPL[4]
MAXPL[3]
MAXPL[2]
MAXPL[1]
MAXPL[0]
Default
0
0
0
0
0
0
0
0
Register 0xA5: RXFP Maximum Packet Length (MSB)
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Function
MAXPL[15]
MAXPL[14]
MAXPL[13]
MAXPL[12]
MAXPL[11]
MAXPL[10]
MAXPL[9]
MAXPL[8]
Default
0
0
0
0
0
1
1
0
MAXPL[15:0]:
The Maximum Packet Length (MAXPL[15:0]) bits are used to set the
maximum packet length. Packets larger than this length are marked with an
error by asserting RERR with REOP . . These packets will increment the
RXFP Receive Byte Counter and the MAXLI interrupt will be set. The packet
length used here is defined as the number of bytes encapsulated into the
POS frame excluding byte stuffing and the FCS.
The maximum packet length supported by the RXFP is 65534 (0xFFFE) The
values 0x0000, 0x0001 and 0xFFFF shall not be used.
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ISSUE 7
SATURN USER NETWORK INTERFACE (155-TETRA)
Register 0xA6: RXFP Receive Initiation Level
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Function
Reserved
Reserved
Reserved
Reserved
RIL[3]
RIL[2]
RIL[1]
RIL[0]
Default
1
0
0
0
1
1
0
0
RIL[7:0]:
The Reception Initiation Level (RIL[3:0]) bits are used to set the minimum
number of bytes that must be available in the FIFO before received packets
can be written into it. RIL[R:0] is only used after a FIFO overrun is detected
and FIFO writes have been suspended. The FIFO will wait until the number of
used bytes is smaller than the RIL. This avoids restarting the reception of data
too quickly after an overrun condition. If the system does not cause any FIFO
overrun, then this register will not be used. RIL[3:0] breaks the FIFO in 16
sections; for example a value of 0x4 correspond to a FIFO level of 64 bytes.
The value of RIL must not be too large in order to prevent repetitive FIFO
overruns. The default reception initiation level is 192 octets.
Table 9: Receive Initiation Level Values
RIL[3:0]
0000
0001
0010
0011
0100
0101
0110
0111
FIFO Fill
Level
0
16
32
48
64
80
96
112
RIL[3:0]
1000
1001
1010
1011
1100
1101
1110
1111
FIFO Fill
Level
128
144
160
176
192
208
224
240
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ISSUE 7
SATURN USER NETWORK INTERFACE (155-TETRA)
Register 0xA7: RXFP Receive Packet Available High Water Mark
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Function
RPAHWM[7]
RPAHWM[6]
RPAHWM[5]
RPAHWM[4]
RPAHWM[3]
RPAHWM[2]
RPAHWM[1]
RPAHWM[0]
Default
0
1
0
0
0
0
0
0
RPAHWM[7:0]:
The Receive FIFO High Water Mark (RPAHWM[7:0]) bits are used to
generate the RPA outputs. RPAs are set to logic one when the number of
bytes stored in the FIFO exceed RPAHWM[7:0] or when there is at least one
end of packet in the FIFO. The maximum RPAHWM usable value is 0xF0.
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ISSUE 7
SATURN USER NETWORK INTERFACE (155-TETRA)
Register 0xA8: RXFP Receive Byte Counter (LSB)
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Type
R
R
R
R
R
R
R
R
Function
RBYTE[7]
RBYTE[6]
RBYTE[5]
RBYTE[4]
RBYTE[3]
RBYTE[2]
RBYTE[1]
RBYTE[0]
Default
X
X
X
X
X
X
X
X
Register 0xA9: RXFP Receive Byte Counter
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Type
R
R
R
R
R
R
R
R
Function
RBYTE[15]
RBYTE[14]
RBYTE[13]
RBYTE[12]
RBYTE[11]
RBYTE[10]
RBYTE[9]
RBYTE[8]
Default
X
X
X
X
X
X
X
X
Register 0xAA: RXFP Receive Byte Counter
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Type
R
R
R
R
R
R
R
R
Function
RBYTE[23]
RBYTE[22]
RBYTE[21]
RBYTE[20]
RBYTE[19]
RBYTE[18]
RBYTE[17]
RBYTE[16]
Default
X
X
X
X
X
X
X
X
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ISSUE 7
SATURN USER NETWORK INTERFACE (155-TETRA)
Register 0xAB: RXFP Receive Byte Counter (MSB)
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Type
R
R
R
R
R
R
R
R
Function
RBYTE[31]
RBYTE[30]
RBYTE[29]
RBYTE[28]
RBYTE[27]
RBYTE[26]
RBYTE[25]
RBYTE[24]
Default
X
X
X
X
X
X
X
X
RBYTE[31:0]:
The RBYTE[31:0] bits indicate the number of received bytes written into the
receive FIFO during the last accumulation interval. This counter does not
count any byte from errored and aborted frames.
A write to any one of the RXFP-50 Receive Byte Counter registers loads the
registers with the current counter value and resets the internal 24 bit counter
to 1 or 0. The counter reset value is dependent on if there was a count event
during the transfer of the count to the Receive Byte Counter registers. The
counter should be polled every second to avoid saturating. The contents of
these registers are valid three RCLK cycles after a transfer is triggered by a
write to any of the RXFP-50 Receive Frame Count Registers. Using the TIP
feature by writing to the Channel Reset and Monitoring Register (Register
0x05) will also update the counters.
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PMC-1971240
ISSUE 7
SATURN USER NETWORK INTERFACE (155-TETRA)
Register 0xAC: RXFP Receive Frame Counter (LSB)
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Type
R
R
R
R
R
R
R
R
Function
RFRAME[7]
RFRAME[6]
RFRAME[5]
RFRAME[4]
RFRAME[3]
RFRAME[2]
RFRAME[1]
RFRAME[0]
Default
X
X
X
X
X
X
X
X
Register 0xAD: RXFP Receive Frame Counter
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Type
R
R
R
R
R
R
R
R
Function
RFRAME[15]
RFRAME[14]
RFRAME[13]
RFRAME[12]
RFRAME[11]
RFRAME[10]
RFRAME[9]
RFRAME[8]
Default
X
X
X
X
X
X
X
X
Register 0xAE: RXFP Receive Frame Counter (MSB)
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Type
R
R
R
R
R
R
R
R
Function
RFRAME[23]
RFRAME[22]
RFRAME[21]
RFRAME[20]
RFRAME[19]
RFRAME[18]
RFRAME[17]
RFRAME[16]
Default
X
X
X
X
X
X
X
X
RFRAME[23:0]:
The RFRAME[23:0] bits indicate the number of successfully received POS
frames written into the receive FIFO after their extraction from the
SONET/SDH stream during the last accumulation interval. This counter does
not count any errored and aborted frames.
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ISSUE 7
SATURN USER NETWORK INTERFACE (155-TETRA)
A write to any one of the RXFP-50 Receive Frame Counter registers loads the
registers with the current counter value and resets the internal 24 bit counter
to 1 or 0. The counter reset value is dependent on if there was a count event
during the transfer of the count to the Receive Frame Counter registers. The
counter should be polled every second to avoid saturating. The contents of
these registers are valid three RCLK cycles after a transfer is triggered by a
write to any of the RXFP-50 Receive Frame Count Registers. Using the TIP
feature by writing to the Channel Reset and Monitoring Register (Register
0x05) will also update the counters.
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ISSUE 7
SATURN USER NETWORK INTERFACE (155-TETRA)
Register 0xAF: RXFP Receive Aborted Frame Counter (LSB)
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Type
R
R
R
R
R
R
R
R
Function
RABRF[7]
RABRF[6]
RABRF[5]
RABRF[4]
RABRF[3]
RABRF[2]
RABRF[1]
RABRF[0]
Default
X
X
X
X
X
X
X
X
Register 0xB0: RXFP Receive Aborted Frame Counter (MSB)
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Type
R
R
R
R
R
R
R
R
Function
RABRF[15]
RABRF[14]
RABRF[13]
RABRF[12]
RABRF[11]
RABRF[10]
RABRF[9]
RABRF[8]
Default
X
X
X
X
X
X
X
X
RABRF[15:0]:
The RABRF[15:0] bits indicate the number of aborted POS frames received
and written into the receive FIFO during the last accumulation interval. This
count only includes frames te rminated with an abort flag. Frames that have a
receive error such as length error, FIFO overun error and FCS error are not
included in this count.
A write to any one of the RXFP-50 Receive Aborted Frame Counter registers
loads the registers with the current counter value and resets the internal 16 bit
counter to 1 or 0. The counter reset value is dependent on if there was a
count event during the transfer of the count to these registers. The counter
should be polled every second to avoid saturating. The contents of these
registers are valid three RCLK cycles after a transfer is triggered. Using the
TIP feature by writing to the Channel Reset and Monitoring Register (Register
0x05) will also update the counters.
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ISSUE 7
SATURN USER NETWORK INTERFACE (155-TETRA)
Register 0xB1: RXFP Receive FCS Error Frame Counter (LSB)
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Type
R
R
R
R
R
R
R
R
Function
RFCSEF[7]
RFCSEF[6]
RFCSEF[5]
RFCSEF[4]
RFCSEF[3]
RFCSEF[2]
RFCSEF[1]
RFCSEF[0]
Default
X
X
X
X
X
X
X
X
Register 0xB2: RXFP Receive FCS Error Frame Counter (MSB)
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Type
R
R
R
R
R
R
R
R
Function
RFCSEF[15]
RFCSEF[14]
RFCSEF[13]
RFCSEF[12]
RFCSEF[11]
RFCSEF[10]
RFCSEF[9]
RFCSEF[8]
Default
X
X
X
X
X
X
X
X
RFCSEF[15:0]:
The RFCSEF[15:0] bits indicate the number of POS frames received with an
FCS error and written into the receive FIFO during the last accumulation
interval.
A write to any one of the RXFP-50 Receive FCS Error Frame Counter
registers loads the registers with the current counter value and resets the
internal 16 bit counter to 1 or 0. The counter reset value is dependent on if
there was a count event during the transfer of the count to these registers.
The counter should be polled every second to avoid saturating. The contents
of these registers are valid three RCLK cycles after a transfer is triggered.
Using the TIP feature by writing to the Channel Reset and Monitoring Register
(Register 0x05) will also update the counters.
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ISSUE 7
SATURN USER NETWORK INTERFACE (155-TETRA)
Register 0xB3: RXFP Receive Minimum Length Error Frame Counter (LSB)
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Type
R
R
R
R
R
R
R
R
Function
RMINLF[7]
RMINLF[6]
RMINLF[5]
RMINLF[4]
RMINLF[3]
RMINLF[2]
RMINLF[1]
RMINLF[0]
Default
X
X
X
X
X
X
X
X
Register 0xB4: RXFP Receive Minimum Length Error Frame Counter (MSB)
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Type
R
R
R
R
R
R
R
R
Function
RMINLF[15]
RMINLF[14]
RMINLF[13]
RMINLF[12]
RMINLF[11]
RMINLF[10]
RMINLF[9]
RMINLF[8]
Default
X
X
X
X
X
X
X
X
RMINLF[15:0]:
The RMINLF[15:0] bits indicate the number of minimum packet length POS
frames received and written into the receive FIFO during the last
accumulation interval.
A write to any one of the RXFP-50 Minimum Length Error Frame Counter
registers loads the registers with the current counter value and resets the
internal 16 bit counter to 1 or 0. The counter reset value is dependent on if
there was a count event during the transfer of the count to these registers.
The counter should be polled every second to avoid saturating. The contents
of these registers are valid three RCLK cycles after a transfer is triggered.
Using the TIP feature by writing to the Channel Reset and Monitoring Register
(Register 0x05) will also update the counters.
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ISSUE 7
SATURN USER NETWORK INTERFACE (155-TETRA)
Register 0xB5: RXFP Receive Maximum Length Error Frame Counter (LSB)
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Type
R
R
R
R
R
R
R
R
Function
RMAXLF[7]
RMAXLF[6]
RMAXLF[5]
RMAXLF[4]
RMAXLF[3]
RMAXLF[2]
RMAXLF[1]
RMAXLF[0]
Default
X
X
X
X
X
X
X
X
Register 0xB6: RXFP Receive Maximum Length Error Frame Counter (MSB)
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Type
R
R
R
R
R
R
R
R
Function
RMAXLF[15]
RMAXLF[14]
RMAXLF[13]
RMAXLF[12]
RMAXLF[11]
RMAXLF[10]
RMAXLF[9]
RMAXLF[8]
Default
X
X
X
X
X
X
X
X
RMAXLF[15:0]:
The RMAXLF[15:0] bits indicate the number of POS frames exceeding the
maximum packet length that were received and written into the receive FIFO
during the last accumulation interval.
A write to any one of the RXFP-50 Receive Maximum Length Error Frame
Counter registers loads the registers with the current counter value and resets
the internal 16 bit counter to 1 or 0. The counter reset value is dependent on if
there was a count event during the transfer of the count to these registers.
The counter should be polled every second to avoid saturating. The contents
of these registers are valid three RCLK cycles after a transfer is triggered.
Using the TIP feature by writing to the Channel Reset and Monitoring Register
(Register 0x05) will also update the counters.
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SATURN USER NETWORK INTERFACE (155-TETRA)
Register 0xC0: TXFP Interrupt Enable/Status
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Type
R/W
R
R/W
R
R/W
R
R/W
R
Function
Reserved
FIFO_ERR
FUDRE
FUDRI
FOVRE
FOVRI
TPRTYE
TPRTYI
Default
0
X
0
X
0
X
0
X
TPRTYI:
The TPRTYI bit indicates if a parity error was detected on the TDAT system
interface bus. When logic one, the TPRTYI bit indicates a parity error over the
TDAT_S bus. This bit is cleared when this register is read. Odd or even parity
is selected using the TPTYPE bit.
TPRTYE:
The TPRTYE bit enables transmit parity interrupts. When set to logic one,
parity errors are indicated on INT and TPRTYI. When set to logic zero, parity
errors are indicated using bit TPRTYI but are not indicated on output INTB.
FOVRI:
The FOVRI bit is set high when an attempt is made to write into the FIFO
while it has already been filled-up. This is considered a system error. This bit
is reset immediately after a read to this register.
Overruns on the TXFP FIFO do not necessarily produce an aborted packet,
just a stunted packet that has no indication of error
FOVRE:
The FOVRE bit enables the generation of an interrupt due to an attempt to
write the FIFO when it is already full. When FOVRE is set to logic one, the
interrupt is enabled and cause FOVRI and the output INT to be asserted.
When set to logic zero, FOVRI will be asserted but not INTB.
FUDRI:
The FUDRI bit is set high when the FIFO underruns while reading packet data
from the FIFO. This bit is reset immediately after a read to this register.
FUDRE:
The FUDRE bit enables the generation of an interrupt due to a FIFO
underrun. When FUDRE is set to logic one, the interrupt is enabled and
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cause FUDRI and the output INTB to be asserted. When set to logic zero,
FUDRI will be asserted but not INTB.
FIFO_ERR:
This bit is set to one when an ERROR is detected on the read side of the
FIFO. This error can be caused by an abnormal sequence of SOP and EOP.
This can normally be caused by a previous FIFO overrun or underrun
condition. This bit is reset immediately after a read to this register.
Reserved:
Reserved bits should be set to logic zero for proper operation.
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Register 0xC1: TXFP Configuration
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Function
XOFF
TPAINV
FCSERR
FCSSEL[1]
FCSSEL[0]
TPTYP
DSCR
FIFORST
Default
0
0
0
1
0
0
1
0
FIFORST:
The FIFORST bit is used to reset the 256-byte transmit FIFO. When
FIFORST is set to logic zero, the FIFO operates normally. When FIFORST is
set to logic one, the FIFO is emptied of all octets (including the current packet
being transmitted) and ignores writes. The FIFO remains empty and
continues to ignore writes until a logic zero is written to FIFORST. Flags are
transmitted until a subsequent packet is written to the FIFO.
DSCR:
The DSCR bit controls the scrambling of the POS frames. When DSCR is a
logic one, scrambling is enabled. When DSCR is a logic zero, payload
scrambling is disabled.
TPTYP:
The TPTYP bit selects even or odd parity for input TPRTY. When set to logic
one, the TPRTY input must report even parity bit for the TDAT system
interface bus. When set to logic zero, input TPRTY must report odd parity bit
for the TDAT system interface bus.
FCSSEL[1:0]:
The Frame Control Sequence select (FCSSEL[1:0]) bits allow to control the
FCS calculation according to the table below. The FCS is calculated over the
whole packet data, before byte stuffing and scrambling.
FCSSEL[1:0]
00
01
10
11
FCS Operation
No FCS inserted
CRC-CCITT (2 bytes)
CRC-32 (4 bytes)
Reserved
FCSERR:
The FCSERR bit controls the insertion of FCS errors for diagnostic purposes.
When FCSERR is set to logic one, if FCS insertion is enabled, the FCS octets
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are inverted prior to insertion in the POS frame. When FCSERR is set to logic
zero, the FCS is inserted normally.
TPAINV:
The TPAINV bit inverts the polarity of the TPA output signals. When TPAINV
is a logic one, the polarity of TPA is inverted When TPAINV is a logic zero,
TPA operates normally.
XOFF:
The XOFF serves as a transmission enable bit. When XOFF is set to logic
zero, POS frames are transmitted normally. When XOFF is set to logic one,
the current frame being transmitted is completed and then POS frame
transmission is suspended. When XOFF is asserted the FIFO still accepts
data and can overflow. XOFF is provided to facilitate system debugging
rather than flow control, which is better achieved using inter packet gapping.
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Register 0xC2: TXFP Control
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Function
IPGAP[3]
IPGAP[2]
IPGAP[1]
IPGAP[0]
TIL[3]
TIL[2]
TIL[1]
TIL[0]
Default
0
0
1
0
0
1
0
0
TIL[3:0]:
The Transmit Initiation Level (TIL[3:0]) bits are used to determine when to
initiate a POS frame transmission. After completing transmission of a packet,
data transmission starts only when either there is a complete packet or that
the number of bytes stored in the FIFO exceeds the value of TIL[3:0] times
16. TIL[3:0] breaks the FIFO in 16 sections; for example a value of 0x4
correspond to a FIFO level of 64 bytes. The value of TIL must not be too small
in order to prevent FIFO underruns when transmitting large packets. TIL must
be set lower than the TPALWM for proper operation.
Table 10: Transmit Initiation Level Values
TIL[3:0]
0000
0001
0010
0011
0100
0101
0110
0111
FIFO Fill
Level
0
16
32
48
64
80
96
112
TIL[3:0]
1000
1001
1010
1011
1100
1101
1110
1111
FIFO Fill
Level
128
144
160
176
192
208
224
240
IPGAP[3:0]:
The Inter Packet Gaping (IPGAP[3:0]) bits are used to program the number of
Flag Sequence characters inserted between each POS Frame. The
programmed value is encoded as indicated in Table 11.
In the case of a one byte packet when the FCS insertion is disabled, the
TXFP might not insert the right number of inter packet flags. Although this is
not a functional problem, we are recommending not to send one byte packets.
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Table 11: Inter Packet Gaping Values
IPGAP[3:0]
0000
0001
0010
0011
0100
0101
0110
0111
Number of
Flag
1
2
4
8
16
32
64
128
IPGAP[3:0]
1000
1001
1010
1011
1100
1101
1110
1111
Number of
Flag
256
512
1024
2048
4096
8192
16384
32768
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Register 0xC3: TXFP Transmit Packet Available Low Water Mark
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Function
TPALWM[7]
TPALWM[6]
TPALWM[5]
TPALWM[4]
TPALWM[3]
TPALWM[2]
TPALWM[1]
TPALWM[0]
Default
0
1
0
0
0
0
0
0
TPALWM[7:0]:
The Transmit FIFO Low Water Mark (TPALWM[7:0]) bits are used to
generate the TPA outputs. TPA is set to logic one when the number of bytes
stored in the FIFO is lower than TPALWM[7:0]. Together with TPAHWM[7:0],
TPALWM[7:0] provides a hysteresis in the setting of TPA.
For proper FIFO operation TPALWM[7:0] must be set to a value greater
than zero (0x00 is not a valid value) and it must be smaller than 0xEA
and smaller than TPAHWM[7:0].
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Register 0xC4: TXFP Transmit Packet Available High Water Mark
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Function
TPAHWM[7]
TPAHWM[6]
TPAHWM[5]
TPAHWM[4]
TPAHWM[3]
TPAHWM[2]
TPAHWM[1]
TPAHWM[0]
Default
1
1
1
1
1
0
0
0
TPAHWM[7:0]:
The Transmit FIFO High Water Mark (TPAHWM[7:0]) bits are used to
generate the TPA outputs. TPA is set to logic zero when the number of bytes
stored in the FIFO exceeds TPAHWM[7:0].
Overruns on the TXFP FIFO can falsely assert. This occurs more frequently
with watermarks greater that 0xF8. The TPAHWM value should be set lower
than 0xF8 to avoid the problem. This value must be even smaller if the link
layer device that interfaces with the S/UNI TETRA samples the TPA value.
Thus, a TPAHWM smaller than 0xF2 must be used for a 5 clock cycle latency
between the TPA de-assertion and the de-selection of the channel.
For proper operation, the following relation must be verified:
(TIL<TPALWM<TPAHWM).
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Register 0xC5: TXFP Transmit Byte Counter (LSB)
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Type
R
R
R
R
R
R
R
R
Function
TBYTE[7]
TBYTE[6]
TBYTE[5]
TBYTE[4]
TBYTE[3]
TBYTE[2]
TBYTE[1]
TBYTE[0]
Default
X
X
X
X
X
X
X
X
Register 0xC6: TXFP Transmit Byte Counter
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Type
R
R
R
R
R
R
R
R
Function
TBYTE[15]
TBYTE[14]
TBYTE[13]
TBYTE[12]
TBYTE[11]
TBYTE[10]
TBYTE[9]
TBYTE[8]
Default
X
X
X
X
X
X
X
X
Register 0xC7: TXFP Transmit Byte Counter
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Type
R
R
R
R
R
R
R
R
Function
TBYTE[23]
TBYTE[22]
TBYTE[21]
TBYTE[20]
TBYTE[19]
TBYTE[18]
TBYTE[17]
TBYTE[16]
Default
X
X
X
X
X
X
X
X
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Register 0xC8: TXFP Transmit Byte Counter (MSB)
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Type
R
R
R
R
R
R
R
R
Function
TBYTE[31]
TBYTE[30]
TBYTE[29]
TBYTE[28]
TBYTE[27]
TBYTE[26]
TBYTE[25]
TBYTE[24]
Default
X
X
X
X
X
X
X
X
TBYTE[31:0]:
The TBYTE[31:0] bits indicate the number of bytes read from the transmit
FIFO and transmitted during the last accumulation interval. This counter does
not count bytes within aborted frames.
A write to any one of the TXFP-50 Transmit Byte Counter registers loads the
registers with the current counter value and resets the internal 32 bit counter
to 1 or 0. The counter reset value is dependent on if there was a count event
during the transfer of the count to the Transmit Byte Counter registers. The
counter should be polled every second to avoid saturating. The contents of
these registers are valid three TCLK cycles after a transfer is triggered by a
write to any of the TXFP-50 Transmit Byte Count Registers. Using the TIP
feature by writing to the Channel Reset and Monitoring Register (Register
0x05) will also update the counters.
The TXFP does not increment the Byte Counter (0xC5 to 0xC8) for packets at
or larger than 64k. If sending these packets the Byte Counter will remain
zeroed and never saturate.
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Register 0xC9: TXFP Transmit Frame Counter (LSB)
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Type
R
R
R
R
R
R
R
R
Function
TFRAME[7]
TFRAME[6]
TFRAME[5]
TFRAME[4]
TFRAME[3]
TFRAME[2]
TFRAME[1]
TFRAME[0]
Default
X
X
X
X
X
X
X
X
Register 0xCA: TXFP Transmit Frame Counter
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Type
R
R
R
R
R
R
R
R
Function
TFRAME[15]
TFRAME[14]
TFRAME[13]
TFRAME[12]
TFRAME[11]
TFRAME[10]
TFRAME[9]
TFRAME[8]
Default
X
X
X
X
X
X
X
X
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Register 0xCB: TXFP Transmit Frame Counter (MSB)
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Type
R
R
R
R
R
R
R
R
Function
TFRAME[23]
TFRAME[22]
TFRAME[21]
TFRAME[20]
TFRAME[19]
TFRAME[18]
TFRAME[17]
TFRAME[16]
Default
X
X
X
X
X
X
X
X
TFRAME[23:0]:
The TFRAME[23:0] bits indicate the number of POS frames read from the
transmit FIFO and inserted into the transmission stream during the last
accumulation interval. This counter does not count aborted frames.
A write to any one of the TXFP-50 Transmit Frame Counter registers loads
the registers with the current counter value and resets the internal 24 bit
counter to 1 or 0. The counter reset value is dependent on if there was a
count event during the transfer of the count to the Transmit Frame Counter
registers. The counter should be polled every second to avoid saturating. The
contents of these registers are valid three TCLK cycles after a transfer is
triggered by a write to any of the TXFP-50 Transmit Frame Count Registers.
Using the TIP feature by writing to the Channel Reset and Monitoring Register
(Register 0x05) will also update the counters.
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SATURN USER NETWORK INTERFACE (155-TETRA)
Register 0xCC: TXFP Transmit User Aborted Frame Counter (LSB)
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Type
R
R
R
R
R
R
R
R
Function
TUSRABF[7]
TUSRABF[6]
TUSRABF[5]
TUSRABF[4]
TUSRABF[3]
TUSRABF[2]
TUSRABF[1]
TUSRABF[0]
Default
X
X
X
X
X
X
X
X
Register 0xCD: TXFP Transmit User Aborted Frame Counter (MSB)
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Type
R
R
R
R
R
R
R
R
Function
TUSRABF[15]
TUSRABF[14]
TUSRABF[13]
TUSRABF[12]
TUSRABF[11]
TUSRABF[10]
TUSRABF[9]
TUSRABF[8]
Default
X
X
X
X
X
X
X
X
TUSRABF[15:0]:
The TUSRABF[15:0] bits indicate the number of user aborted POS frames
read from the transmit FIFO and inserted into the transmission stream during
the last accumulation interval. User can abort frames by asserting TERR.
A write to any one of the TXFP-50 Transmit User Aborted Frame Counter
registers loads the registers with the current counter value and resets the
internal 16 bit counter to 1 or 0. The counter reset value is dependent on if
there was a count event during the transfer of the count to these registers.
The counter should be polled every second to avoid saturating. The contents
of these registers are valid three TCLK cycles after a transfer is triggered.
Using the TIP feature by writing to the Channel Reset and Monitoring Register
(Register 0x05) will also update the counters.
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SATURN USER NETWORK INTERFACE (155-TETRA)
Register 0xCE: TXFP Transmit FIFO Error Aborted Frame Counter (LSB)
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Type
R
R
R
R
R
R
R
R
Function
TFERABF[7]
TFERABF[6]
TFERABF[5]
TFERABF[4]
TFERABF[3]
TFERABF[2]
TFERABF[1]
TFERABF[0]
Default
X
X
X
X
X
X
X
X
Register 0xCF: TXFP Transmit FIFO Error Aborted Frame Counter (MSB)
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Type
R
R
R
R
R
R
R
R
Function
TFERABF[15]
TFERABF[14]
TFERABF[13]
TFERABF[12]
TFERABF[11]
TFERABF[10]
TFERABF[9]
TFERABF[8]
Default
X
X
X
X
X
X
X
X
TFERABF[15:0]:
The TFERABF[15:0] bits indicate the number of FIFO error aborted POS
frames read from the transmit FIFO and inserted into the transmission stream
during the last accumulation interval. FIFO errors are caused when the FIFO
runs empty and the last byte read was not an end of packet or also when the
FIFO overruns and corrupts the EOP and SOP sequence. This is considered
a system error and should not occur when the system works normally. This
counter added to the Transmit User Aborted counter should account for all
aborted packets being sent on the line.
A write to any one of the TXFP-50 Transmit FIFO Error Aborted Frame
Counter registers loads the registers with the current counter value and resets
the internal 16 bit counter to 1 or 0. The counter reset value is dependent on
if there was a count event during the transfer of the count to these registers.
The counter should be polled every second to avoid saturating. The contents
of these registers are valid three TCLK cycles after a transfer is triggered.
Using the TIP feature by writing to the Channel Reset and Monitoring Register
(Register 0x05) will also update the counters.
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SATURN USER NETWORK INTERFACE (155-TETRA)
Register 0xD0: WANS Configuration
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Type
R/W
R/W
R/W
R/W
Function
Reserved
Unused
Unused
Unused
FORCEREAC
AUTOREAC
INTEN
PHACOMPEN
Default
0
X
X
X
0
0
0
0
PHACOMPEN:
The Phase Comparison Enable (PHACOMPEN) bit is used to enable the
phase comparison process. Setting this bit to a logic one will enable the
phase comparison process. When set to logic zero, the phase and reference
period counters are kept in reset state, further disabling the WANS process.
INTEN:
The Interrupt Enable (INTEN) bit controls the generation of the interrupt
signal. When set to logic one, this bit allows the generation of an interrupt
signal at the beginning of the Phase Detector averaging period. Setting this
bit to logic zero disable the generation of the interrupts.
AUTOREAC:
The Auto Reacquisition Mode Select (AUTOREAC) bit can be used to set the
WANS to automatic phase reacquisition mode. When operating in this mode,
the WANS will automatically align the phase sampling point toward the middle
of the Phase Counter period upon detection of two consecutive phase
samples located on each side of the Phase Counter wrap around value. The
Phase Word register will keep its previous value tillSetting this bit to logic
enables the automatic reacquisition mode.
FORCEREAC:
The Force Phase Reacquisition (FORCEREAC) bit can be used to force a
phase reacquisition of the Phase Detector. A logic zero to logic one transition
on this bit triggers a phase reacquisition sequence of the Phase Detector.
Setting this bit to logic zero allows the Phase detector to operate normally.
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DATASHEET
PMC-1971240
ISSUE 7
SATURN USER NETWORK INTERFACE (155-TETRA)
Register 0xD1: WANS Interrupt & Status
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Type
R
R
Function
Unused
Unused
Unused
Unused
Unused
Unused
RPHALGN
TIMI
Default
X
X
X
X
X
X
X
X
TIMI:
The Timer Interrupt (TIMI) bit indicates a Timer Interrupt condition. This bit will
be raised at the beginning of the Phase Detector averaging period. In addition
of indicating the interrupt status, this bit can also be polled to implement
synchronization of read access to WANS output register. This interrupt can be
masked using the INTEN bit of the configuration register. A read access to the
Interrupt & Status Register resets the value of this bit.
RPHALGN:
The Reference Phase Alignment (RPHALNG) bit indicates a Reference
Phase Alignment event. In normal operating mode, this bit remains to logic
zero. Upon the occurrence of a Reference Phase Alignment, this bit is set to
logic one, indicating that the phase averaging process was aborted and that
the value of the Phase Word register is frozen to the previous valid value.
This bit is reset to logic zero after the completion of a valid phase averaging
cycle.
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ISSUE 7
SATURN USER NETWORK INTERFACE (155-TETRA)
Register 0xD2: WANS Phase Word [7:0]
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Type
R
R
R
R
R
R
R
R
Function
PHAWORD[7]
PHAWORD[6]
PHAWORD[5]
PHAWORD[4]
PHAWORD[3]
PHAWORD[2]
PHAWORD[1]
PHAWORD[0]
Default
X
X
X
X
X
X
X
X
Register 0xD3: WANS Phase Word [15:8]
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Type
R
R
R
R
R
R
R
R
Function
PHAWORD[15]
PHAWORD[14]
PHAWORD[13]
PHAWORD[12]
PHAWORD[11]
PHAWORD[10]
PHAWORD[9]
PHAWORD[8]
Default
X
X
X
X
X
X
X
X
Register 0xD4: WANS Phase Word [23:16]
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Type
R
R
R
R
R
R
R
R
Function
PHAWORD[23]
PHAWORD[22]
PHAWORD[21]
PHAWORD[20]
PHAWORD[19]
PHAWORD[18]
PHAWORD[17]
PHAWORD[16]
Default
X
X
X
X
X
X
X
X
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ISSUE 7
SATURN USER NETWORK INTERFACE (155-TETRA)
Register 0xD5: WANS Phase Word [30:24]
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Type
R
R
R
R
R
R
R
R
Function
Unused
PHAWORD[30]
PHAWORD[29]
PHAWORD[28]
PHAWORD[27]
PHAWORD[26]
PHAWORD[25]
PHAWORD[24]
Default
X
X
X
X
X
X
X
PHAWORD[30:0]:
The Phase Word (PHAWORD[30:0]) bits are the output bus of the Phase
Detector. This bus outputs the result of the Phase Count Averaging function.
Depending on the number of samples included in the averaging, from 0 to 15
of the LSB(s) of the PHAWORD bus may represent the fractional part of the
average value while the 16 following bits hold the integer part. This value can
be used to externally implement in software the PLL filtering function and
bypass the Digital Loop Filter block.
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ISSUE 7
SATURN USER NETWORK INTERFACE (155-TETRA)
Register 0xD9: WANS Reference Period [7:0]
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Function
REFPER[7]
REFPER[6]
REFPER[5]
REFPER[4]
REFPER[3]
REFPER[2]
REFPER[1]
REFPER[0]
Default
0
0
0
0
0
0
0
0
Register 0xDA: WANS Reference Period [15:8]
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Function
REFPER[15]
REFPER[14]
REFPER[13]
REFPER[12]
REFPER[11]
REFPER[10]
REFPER[9]
REFPER[8]
Default
0
0
0
0
0
0
0
0
REFPER[15:0]:
The Reference Period REFPER[15:0] bits are used to program the timing
reference period of the Phase Detector. These bits are used to set the end of
count of the Reference Period Counter. The Reference Period Counter is
reset on the next clock cycle following the detection of its end of count. The
Reference Period Counter counts (Nref) is equal to the REFPER value plus 1.
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PMC-1971240
ISSUE 7
SATURN USER NETWORK INTERFACE (155-TETRA)
Register 0xDB: WANS Phase Counter Period[7:0]
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Function
PHCNTPER[7]
PHCNTPER[6]
PHCNTPER[5]
PHCNTPER[4]
PHCNTPER[3]
PHCNTPER[2]
PHCNTPER[1]
PHCNTPER[0]
Default
0
0
0
0
0
0
0
0
Register 0xDC: WANS Phase Counter Period[15:8]
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Function
PHCNTPER[15]
PHCNTPER[14]
PHCNTPER[13]
PHCNTPER[12]
PHCNTPER[11]
PHCNTPER[10]
PHCNTPER[9]
PHCNTPER[8]
Default
0
0
0
0
0
0
0
0
PHCNTPER[15:0]:
The Phase Counter Period (PHCNTPER15:0]) bits are used to program the
Phase Counter period of the Phase Detector. These bits are used to set the
end of count of the Phase Counter. The Phase Counter is reset on the next
clock cycle following the detection of its end of count. The Phase Counter
count (Nphcnt) is equal to the PHCNTPER value plus 1.
For the system to operate properly, Nphcnt need to be greater than 1023.
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S/UNI-TETRA
DATASHEET
PMC-1971240
ISSUE 7
SATURN USER NETWORK INTERFACE (155-TETRA)
Register 0xDD: WANS Phase Average Period [3:0]
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Type
R/W
R/W
R/W
R/W
Function
Unused
Unused
Unused
Unused
PHAVGPER[3]
PHAVGPER[2]
PHAVGPER[1]
PHAVGPER[0]
Default
X
X
X
X
0
0
0
0
PHAVGPER[3:0]:
The Phase Average Period (FRACQPER[3:0]) bits are used to set the number
of consecutive valid Phase Samples accumulated together to form the Phase
Word. The number of samples is expressed as a power of 2, i.e.:
Nfracq = 2exp(FRACQPER)
The Phase Average Period (AVGPER[3:0]) bits are used to set the number of
consecutive valid Phase Samples accumulated together to form the Phase
Word. The number of samples is expressed as a power of 2, i.e.:
Navg = 2exp(AVGPER)
To avoid abnormal behavior of the WANS, the AVGPER value should be
programmed into the WANS prior to enabling the phase comparison process
(setting the PHACOMPEN bit to logic 1).
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PMC-1971240
ISSUE 7
SATURN USER NETWORK INTERFACE (155-TETRA)
Register 0xE0: RASE Interrupt Enable
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Function
PSBFE
COAPSE
Z1/S1E
SFBERE
SDBERE
Unused
Unused
Unused
Default
0
0
0
0
0
X
X
X
SDBERE:
The SDBERE bit is the interrupt enable for the signal degrade threshold
alarm. When SDBERE is a logic one, an interrupt is generated when the SD
alarm is declared or removed.
SFBERE:
The SFBERE bit is the interrupt enable for the signal fail threshold alarm.
When SFBERE is a logic one, an interrupt is generated when the SF alarm is
declared or removed.
Z1/S1E:
The Z1/S1 interrupt enable is an interrupt mask for changes in the received
synchronization status. When Z1/S1E is a logic one, an interrupt is generated
when a new synchronization status message is extracted into the Receive
Z1/S1 register.
COAPSE:
The COAPS interrupt enable is an interrupt mask for changes in the received
APS code. When COAPSE is a logic one, an interrupt is generated when a
new K1/K2 code value is extracted into the RASE Receive K1 and RASE
Receive K2 registers.
PSBFE:
The PSBF interrupt enable is an interrupt mask for protection switch byte
failure alarms. When PSBFE is a logic one, an interrupt is generated when
PSBF is declared or removed.
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S/UNI-TETRA
DATASHEET
PMC-1971240
ISSUE 7
SATURN USER NETWORK INTERFACE (155-TETRA)
Register 0xE1: RASE Interrupt Status
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Type
R
R
R
R
R
R
R
R
Function
PSBFI
COAPSI
Z1/S1I
SFBERI
SDBERI
SFBERV
SDBERV
PSBFV
Default
X
X
X
X
X
X
X
X
PSBFV:
The PSBFV bit indicates the protection switching byte failure alarm state. The
alarm is declared (PSBFV is set high) when twelve successive frames have
been received without three consecutive frames containing identical K1 bytes.
The alarm is removed (PSBFV is set low) when three consecutive frames
containing identical K1 bytes have been received.
SDBERV:
The SDBERV bit indicates the signal degrade threshold crossing alarm state.
The alarm is declared (SDBERV is set high) when the bit error rate exceeds
the threshold programmed in the RASE SD Declaring Threshold registers.
The alarm is removed (SDBERV is set low) when the bit error rate is below
the threshold programmed in the RASE SD Clearing Threshold registers.
SFBERV:
The SFBERV bit indicates the signal failure threshold crossing alarm state.
The alarm is declared (SFBERV is set high) when the bit error rate exceeds
the threshold programmed in the RASE SF Declaring Threshold registers.
The alarm is removed (SFBERV is set low) when the bit error rate is below
the threshold programmed in the RASE SF Clearing Threshold registers.
SDBERI:
The SDBERI bit is set high when the signal degrade threshold crossing alarm
is declared or removed. This bit is cleared when the RASE Interrupt Status
register is read.
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ISSUE 7
SATURN USER NETWORK INTERFACE (155-TETRA)
SFBERI:
The SFBERI bit is set high when the signal failure threshold crossing alarm is
declared or removed. This bit is cleared when the RASE Interrupt Status
register is read.
Z1/S1I:
The Z1/S1I bit is set high when a new synchronization status message is
extracted into the RASE Receive Z1/S1 register. This bit is cleared when the
RASE Interrupt Status register is read.
COAPSI:
The COAPSI bit is set high when a new APS code value is extracted into the
RASE Receive K1 and RASE Receive K2 registers. This bit is cleared when
the RASE Interrupt Status register is read.
PSBFI:
The PSBFI bit is set high when the protection switching byte failure alarm is
declared or removed. This bit is cleared when the RASE Interrupt Status
register is read.
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ISSUE 7
SATURN USER NETWORK INTERFACE (155-TETRA)
Register 0xE2: RASE Configuration/Control
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Function
Z1/S1_CAP
SFBERTEN
SFSMODE
SFCMODE
SDBERTEN
SDSMODE
SDCMODE
S1_BYTE
Default
0
0
0
0
0
0
0
0
SDCMODE:
The SDCMODE alarm bit selects the RASE window size to use for clearing
the SD alarm. When SDCMODE is a logic zero the RASE clears the SD
alarm using the same window size used for declaration. When SDCMODE is
a logic one the RASE clears the SD alarm using a window size that is 8 times
longer than the alarm declaration window size. The declaration window size is
determined by the RASE SD Accumulation Period registers.
SDSMODE:
The SDSMODE bit selects the RASE saturation mode. When SDSMODE is a
logic zero the RASE limits the number of B2 errors accumulated in one frame
period to the RASE SD Saturation Threshold register value. When
SDSMODE is a logic one the RASE limits the number of B2 errors
accumulated in one window subtotal accumulation period to the RASE SD
Saturation Threshold register value. Note that the number of frames in a
window subtotal accumulation period is determined by the RASE SD
Accumulation Period register value.
SDBERTEN:
The SDBERTEN bit selects automatic monitoring of line bit error rate
threshold events by the RASE. When SDBERTEN is a logic one, the RASE
continuously monitors line BIP errors over a period defined in the RASE
configuration registers. When SDBERTEN is a logic zero, the RASE BIP
accumulation logic is disabled, and the RASE logic is reset to the declaration
monitoring state.
All RASE accumulation period and threshold registers should be set up
before SDBERTEN is written.
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ISSUE 7
SATURN USER NETWORK INTERFACE (155-TETRA)
SFCMODE:
The SFCMODE alarm bit selects the RASE window size to use for clearing
the SF alarm. When SFCMODE is a logic zero the RASE clears the SF alarm
using the same window size used for declaration. When SFCMODE is a logic
one the RASE clears the SF alarm using a window size that is 8 times longer
than the alarm declaration window size. The declaration window size is
determined by the RASE SF Accumulation Period registers.
SFSMODE:
The SFSMODE bit selects the RASE saturation mode. When SFSMODE is a
logic zero the RASE limits the number of B2 errors accumulated in one frame
period to the RASE SF Saturation Threshold register value. When SFSMODE
is a logic one the RASE limits the number of B2 errors accumulated in one
window subtotal accumulation period to the RASE SF Saturation Threshold
register value. Note that the number of frames in a window subtotal
accumulation period is determined by the RASE SF Accumulation Period
register value.
SFBERTEN:
The SFBERTEN bit enables automatic monitoring of line bit error rate
threshold events by the RASE. When SFBERTEN is a logic one, the RASE
continuously monitors line BIP errors over a period defined in the RASE
configuration registers. When SFBERTEN is a logic zero, the RASE BIP
accumulation logic is disabled, and the RASE logic is reset to the declaration
monitoring state.
All RASE accumulation period and threshold registers should be set up
before SFBERTEN is written.
Z1/S1_CAP:
The Z1/S1_CAP bit enables the Z1/S1 Capture algorithm. When Z1/S1_CAP
is a logic one, the Z1/S1 clock synchronization status message nibble must
have the same value for eight consecutive frames before writing the new
value into the RASE Receive Z1/S1 register. When Z1/S1_CAP is logic zero,
the Z1/S1 nibble value is written directly into the RASE Receive Z1/S1
register.
S1_BYTE:
The S1_BYTE register bit selects if S1 is treated as a nibble or a complete
byte. When S1_BYTE is logic 0, only the S1 nibble is used for filtering. When
S1_BYTE is logic 1, the whole byte is used for filtering. In both cases the
whole S1 byte is extracted.
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PMC-1971240
ISSUE 7
SATURN USER NETWORK INTERFACE (155-TETRA)
Register 0xE3: RASE SF Accumulation Period
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Function
SFSAP[7]
SFSAP[6]
SFSAP[5]
SFSAP[4]
SFSAP[3]
SFSAP[2]
SFSAP[1]
SFSAP[0]
Default
0
0
0
0
0
0
0
0
Register 0xE4: RASE SF Accumulation Period
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Function
SFSAP[15]
SFSAP[14]
SFSAP[13]
SFSAP[12]
SFSAP[11]
SFSAP[10]
SFSAP[9]
SFSAP[8]
Default
0
0
0
0
0
0
0
0
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ISSUE 7
SATURN USER NETWORK INTERFACE (155-TETRA)
Register 0xE5: RASE SF Accumulation Period
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Function
SFSAP[23]
SFSAP[22]
SFSAP[21]
SFSAP[20]
SFSAP[19]
SFSAP[18]
SFSAP[17]
SFSAP[16]
Default
0
0
0
0
0
0
0
0
SFSAP[23:0]:
The SFSAP[23:0] bits represent the number of 8 KHz frames used to
accumulate the B2 error subtotal. The total evaluation window to declare the
SF alarm is broken into 8 subtotals, so this register value represents 1/8 of
the total sliding window size. Refer to the Operations section for
recommended settings.
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ISSUE 7
SATURN USER NETWORK INTERFACE (155-TETRA)
Register 0xE6: RASE SF Saturation Threshold
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Function
SFSTH[7]
SFSTH[6]
SFSTH[5]
SFSTH[4]
SFSTH[3]
SFSTH[2]
SFSTH[1]
SFSTH[0]
Default
0
0
0
0
0
0
0
0
Register 0xE7: RASE SF Saturation Threshold
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Type
R/W
R/W
R/W
R/W
Function
Unused
Unused
Unused
Unused
SFSTH[11]
SFSTH[10]
SFSTH[9]
SFSTH[8]
Default
X
X
X
X
0
0
0
0
SFSTH[11:0]:
The SFSTH[11:0] value represents the allowable number of B2 errors that can
be accumulated during an evaluation window before an SF threshold event is
declared. Setting this threshold to 0xFFF disables the saturation functionality.
Refer to the Operations section for the recommended settings.
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ISSUE 7
SATURN USER NETWORK INTERFACE (155-TETRA)
Register 0xE8: RASE SF Declaring Threshold
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Function
SFDTH[7]
SFDTH[6]
SFDTH[5]
SFDTH[4]
SFDTH[3]
SFDTH[2]
SFDTH[1]
SFDTH[0]
Default
0
0
0
0
0
0
0
0
Register 0xE9: RASE SF Declaring Threshold
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Type
R/W
R/W
R/W
R/W
Function
Unused
Unused
Unused
Unused
SFDTH[11]
SFDTH[10]
SFDTH[9]
SFDTH[8]
Default
X
X
X
X
0
0
0
0
SFDTH[11:0]:
The SFDTH[11:0] value determines the threshold for the declaration of the SF
alarm. The SF alarm is declared when the number of B2 errors accumulated
during an evaluation window is greater than or equal to the SFDTH[11:0]
value. Refer to the Operations section for the recommended settings.
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ISSUE 7
SATURN USER NETWORK INTERFACE (155-TETRA)
Register 0xEA: RASE SF Clearing Threshold
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Function
SFCTH[7]
SFCTH[6]
SFCTH[5]
SFCTH[4]
SFCTH[3]
SFCTH[2]
SFCTH[1]
SFCTH[0]
Default
0
0
0
0
0
0
0
0
Register 0xEB: RASE SF Clearing Threshold
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Type
R/W
R/W
R/W
R/W
Function
Unused
Unused
Unused
Unused
SFCTH[11]
SFCTH[10]
SFCTH[9]
SFCTH[8]
Default
X
X
X
X
0
0
0
0
SFCTH[11:0]:
The SFCTH[11:0] value determines the threshold for the removal of the SF
alarm. The SF alarm is removed when the number of B2 errors accumulated
during an evaluation window is less than the SFCTH[11:0] value. Refer to the
Operations section for the recommended settings.
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Register 0xEC: RASE SD Accumulation Period
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Function
SDSAP[7]
SDSAP[6]
SDSAP[5]
SDSAP[4]
SDSAP[3]
SDSAP[2]
SDSAP[1]
SDSAP[0]
Default
0
0
0
0
0
0
0
0
Register 0xED: RASE SD Accumulation Period
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Function
SDSAP[15]
SDSAP[14]
SDSAP[13]
SDSAP[12]
SDSAP[11]
SDSAP[10]
SDSAP[9]
SDSAP[8]
Default
0
0
0
0
0
0
0
0
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Register 0xEE: RASE SD Accumulation Period
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Function
SDSAP[23]
SDSAP[22]
SDSAP[21]
SDSAP[20]
SDSAP[19]
SDSAP[18]
SDSAP[17]
SDSAP[16]
Default
0
0
0
0
0
0
0
0
SDSAP[23:0]:
The SDSAP[23:0] bits represent the number of 8 KHz frames used to
accumulate the B2 error subtotal. The total evaluation window to declare the
SD alarm is broken into 8 subtotals, so this register value represents 1/8 of
the total sliding window size. Refer to the Operations section for
recommended settings.
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Register 0xEF: RASE SD Saturation Threshold
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Function
SDSTH[7]
SDSTH[6]
SDSTH[5]
SDSTH[4]
SDSTH[3]
SDSTH[2]
SDSTH[1]
SDSTH[0]
Default
0
0
0
0
0
0
0
0
Register 0xF0: RASE SD Saturation Threshold
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Type
R/W
R/W
R/W
R/W
Function
Unused
Unused
Unused
Unused
SDSTH[11]
SDSTH[10]
SDSTH[9]
SDSTH[8]
Default
X
X
X
X
0
0
0
0
SDSTH[11:0]:
The SDSTH[11:0] value represents the allowable number of B2 errors that
can be accumulated during an evaluation window before an SD threshold
event is declared. Setting this threshold to 0xFFF disables the saturation
functionality. Refer to the Operations section for the recommended settings.
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Register 0xF1: RASE SD Declaring Threshold
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Function
SDDTH[7]
SDDTH[6]
SDDTH[5]
SDDTH[4]
SDDTH[3]
SDDTH[2]
SDDTH[1]
SDDTH[0]
Default
0
0
0
0
0
0
0
0
Register 0xF2: RASE SD Declaring Threshold
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Type
R/W
R/W
R/W
R/W
Function
Unused
Unused
Unused
Unused
SDDTH[11]
SDDTH[10]
SDDTH[9]
SDDTH[8]
Default
X
X
X
X
0
0
0
0
SDDTH[11:0]:
The SDDTH[11:0] value determines the threshold for the declaration of the
SD alarm. The SD alarm is declared when the number of B2 errors
accumulated during an evaluation window is greater than or equal to the
SDDTH[11:0] value. Refer to the Operations section for the recommended
settings.
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SATURN USER NETWORK INTERFACE (155-TETRA)
Register 0xF3: RASE SD Clearing Threshold
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Function
SDCTH[7]
SDCTH[6]
SDCTH[5]
SDCTH[4]
SDCTH[3]
SDCTH[2]
SDCTH[1]
SDCTH[0]
Default
0
0
0
0
0
0
0
0
Register 0xF4: RASE SD Clearing Threshold
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Type
R/W
R/W
R/W
R/W
Function
Unused
Unused
Unused
Unused
SDCTH[11]
SDCTH[10]
SDCTH[9]
SDCTH[8]
Default
X
X
X
X
0
0
0
0
SDCTH[11:0]:
The SDCTH[11:0] value determines the threshold for the removal of the SD
alarm. The SD alarm is removed when the number of B2 errors accumulated
during an evaluation window is less than the SDCTH[11:0] value. Refer to the
Operations section for the recommended settings.
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SATURN USER NETWORK INTERFACE (155-TETRA)
Register 0xF5: RASE Receive K1
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Type
R
R
R
R
R
R
R
R
Function
K1[7]
K1[6]
K1[5]
K1[4]
K1[3]
K1[2]
K1[1]
K1[0]
Default
X
X
X
X
X
X
X
X
K1[7:0]:
The K1[7:0] bits contain the current K1 code value. The contents of this
register are updated when a new K1 code value (different from the current K1
code value) is received for three consecutive frames. An interrupt may be
generated when a new code value is received (using the COAPSE bit in the
RASE Interrupt Enable Register). K1[7] is the most significant bit
corresponding to bit 1, the first bit received. K1[0] is the least significant bit,
corresponding to bit 8, the last bit received.
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Register 0xF6: RASE Receive K2
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Type
R
R
R
R
R
R
R
R
Function
K2[7]
K2[6]
K2[5]
K2[4]
K2[3]
K2[2]
K2[1]
K2[0]
Default
X
X
X
X
X
X
X
X
K2[7:0]:
The K2[7:0] bits contain the current K2 code value. The contents of this
register are updated when a new K2 code value (different from the current K2
code value) is received for three consecutive frames. An interrupt may be
generated when a new code value is received (using the COAPSE bit in the
RASE Interrupt Enable Register). K2[7] is the most significant bit
corresponding to bit 1, the first bit received. K2[0] is the least significant bit,
corresponding to bit 8, the last bit received.
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Register 0xF7: RASE Receive Z1/S1
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Type
R
R
R
R
R
R
R
R
Function
Z1/S1[7]
Z1/S1[6]
Z1/S1[5]
Z1/S1[4]
Z1/S1[3]
Z1/S1[2]
Z1/S1[1]
Z1/S1[0]
Default
X
X
X
X
X
X
X
X
Z1/S1[3:0]:
The lower nibble of the first Z1/S1 byte contained in the receive stream is
extracted into this register. The Z1/S1 byte is used to carry synchronization
status messages between line terminating network elements. Z1/S1[3] is the
most significant bit corresponding to bit 5, the first bit received. Z1/S1[0] is
the least significant bit, corresponding to bit 8, the last bit received. An
interrupt may be generated when a byte value is received that differs from the
value extracted in the previous frame (using the Z1/S1E bit in the RASE
Interrupt Enable Register). In addition, debouncing can be performed where
the register is not loaded until eight of the same consecutive nibbles are
received. Debouncing is controlled using the Z1/S1_CAP bit in the RASE
Configuration/Control register.
Z1/S1[7:4]:
The upper nibble of the first Z1/S1 byte contained in the receive stream is
extracted into this register. No interrupt is asserted on the change of this
nibble. In addition, when the Z1/S1_CAP bit in the RASE
Configuration/Control register selects debouncing, the upper nibble is only
updated when eight of the same consecutive lower nibbles are received.
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12 TEST FEATURES DESCRIPTION
Simultaneously asserting (low) the CSB, RDB and WRB inputs causes all digital
output pins and the data bus to be held in a high-impedance state. This test
feature may be used for board testing.
Test mode registers are used to apply test vectors during production testing of
the S/UNI-TETRA. Test mode registers (as opposed to normal mode registers)
are selected when TRS (A[10]) is high.
Test mode registers may also be used for board testing. When all of the TSBs
within the S/UNI-TETRA are placed in test mode 0, device inputs may be read
and device outputs may be forced via the microprocessor interface (refer to the
section "Test Mode 0" for details).
In addition, the S/UNI-TETRA also supports a standard IEEE 1149.1 five-signal
JTAG boundary scan test port for use in board testing. All digital device inputs
may be read and all digital device outputs may be forced via the JTAG test port.
Table 12: Test Mode Register Memory Map
Address
0x000-0x3FF
0x400
0x401-0x7FF
Register
Normal Mode Registers
Master Test Register
Reserved For Test
12.1 Master Test Register
Notes on Test Mode Register Bits:
1. Writing values into unused register bits has no effect. However, to ensure
software compatibility with future, feature-enhanced versions of the product,
unused register bits must be written with logic zero. Reading back unused
bits can produce either a logic one or a logic zero; hence, unused register bits
should be masked off by software when read.
2. Writable test mode register bits are not initialized upon reset unless otherwise
noted.
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Register 0x400: Master Test
Bit
Type
Bit 7
Function
Default
Unused
X
Bit 6
W
BYPASS
X
Bit 5
W
PMCATST
X
Bit 4
W
PMCTST
X
Bit 3
W
DBCTRL
0
Bit 2
R/W
IOTST
0
Bit 1
W
HIZDATA
0
Bit 0
R/W
HIZIO
0
This register is used to enable S/UNI-TETRA test features. All bits, except
PMCTST, PMCATST and BYPASS are reset to zero by a reset of the
S/UNI-TETRA using either the RSTB input or the Master Reset register.
PMCTST and BYPASS are reset when CSB is logic one. PMCATST is reset
when both CSB is high and RSTB is low. PMCTST, PMCATST and BYPASS can
also be reset by writing a logic zero to the corresponding register bit.
HIZIO, HIZDATA:
The HIZIO and HIZDATA bits control the tri-state modes of the S/UNI-TETRA .
While the HIZIO bit is a logic one, all output pins of the S/UNI-TETRA except
the data bus and output TDO are held tri-state. The microprocessor interface
is still active. While the HIZDATA bit is a logic one, the data bus is also held
in a high-impedance state which inhibits microprocessor read cycles. The
HIZDATA bit is overridden by the DBCTRL bit.
IOTST:
The IOTST bit is used to allow normal microprocessor access to the test
registers and control the test mode in each TSB block in the S/UNI-TETRA for
board level testing. When IOTST is a logic one, all blocks are held in test
mode and the microprocessor may write to a block's test mode 0 registers to
manipulate the outputs of the block and consequentially the device outputs
(refer to the "Test Mode 0 Details" in the "Test Features" section).
DBCTRL:
The DBCTRL bit is used to pass control of the data bus drivers to the CSB
pin. When the DBCTRL bit is set to logic one and either IOTST or PMCTST
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are logic one, the CSB pin controls the output enable for the data bus. While
the DBCTRL bit is set, holding the CSB pin high causes the S/UNI-TETRA to
drive the data bus and holding the CSB pin low tri-states the data bus. The
DBCTRL bit overrides the HIZDATA bit. The DBCTRL bit is used to measure
the drive capability of the data bus driver pads.
PMCTST:
The PMCTST bit is used to configure the S/UNI-TETRA for PMC's
manufacturing tests. When PMCTST is set to logic one, the S/UNI-TETRA
microprocessor port becomes the test access port used to run the PMC
"canned" manufacturing test vectors. The PMCTST bit is logically "ORed"
with the IOTST bit, and can be cleared by setting CSB to logic one or by
writing logic zero to the bit.
PMCATST:
The PMCATST bit is used to configure the analog portion of the
S/UNI-TETRA for PMC's manufacturing tests.
BYPASS
The BYPASS bit forces the clock recovery and clock synthesis units into a
reset, and permits the input data and clock to feed directly into the serial-toparallel converter. BYPASS is available for PMC manufacturing test purposes
only.
MKT: Reserved:
12.2 Test Mode 0 Details
The S/UNI-TETRA does not support chip level Test Mode 0 read and write
access. JTAG shall be used for board level testing.
12.3 JTAG Test Port
The S/UNI-TETRA JTAG Test Access Port (TAP) allows access to the TAP
controller and the 4 TAP registers: instruction, bypass, device identification and
boundary scan. Using the TAP, device input logic levels can be read, device
outputs can be forced, the device can be identified and the device scan path can
be bypassed. For more details on the JTAG port, please refer to the Operations
section.
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Table 13: Instruction Register (Length - 3 bits)
Instructions
Selected Register
Instruction Codes,
IR[2:0]
EXTEST
Boundary Scan
000
IDCODE
Identification
001
SAMPLE
Boundary Scan
010
BYPASS
Bypass
011
BYPASS
Bypass
100
STCTEST
Boundary Scan
101
BYPASS
Bypass
110
BYPASS
Bypass
111
Table 14: Identification Register (Length – 32 bits)
Length
32 bits
Version number
0H
Part Number
5351H
Manufacturer's identification code
0CDH
Device identification
053510CDH
Table 15: S/UNI-TETRA Boundary Scan Register (Length – 155 bits)
PIN/ENABLE
RALRM1
RALRM2
RALRM3
RALRM4
RDAT[0]
RDAT[1]
RDAT[2]
RDAT[3]
RDAT[4]
RDAT[5]
RDAT[6]
RDAT[7]
RDAT[8]
RDAT[9]
REG. BIT
154
153
152
151
150
149
148
147
146
145
144
143
142
141
CELL TYPE
T
T
T
T
T
T
T
T
T
T
T
T
T
T
ID
1
0
1
1
0
0
1
1
0
0
0
0
1
0
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CONTROL
HIZ_OEB
HIZ_OEB
HIZ_OEB
HIZ_OEB
RX_UTOPIA_OEB
RX_UTOPIA_OEB
RX_UTOPIA_OEB
RX_UTOPIA_OEB
RX_UTOPIA_OEB
RX_UTOPIA_OEB
RX_UTOPIA_OEB
RX_UTOPIA_OEB
RX_UTOPIA_OEB
RX_UTOPIA_OEB
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RDAT[10]
RDAT[11]
RDAT[12]
RDAT[13]
RDAT[14]
RDAT[15]
RPRTY
RADR[0]
RADR[1]
RADR[2]
RADR[3]
RADR[4]
RFCLK
RENB
RVAL
REOP
RERR
RSOC_RSOP
DTCA_DTPA[1]
DTCA_DTPA[2]
DTCA_DTPA[3]
DTCA_DTPA[4]
RCA_PRPA
DRCA_DRPA[1]
DRCA_DRPA[2]
DRCA_DRPA[3]
DRCA_DRPA[4]
TCA_PTPA
TFCLK
TENB
TSOC_TSOP
TPRTY
TADR[0]
TADR[1]
TADR[2]
TADR[3]
TADR[4]
TMOD
TDAT[0]
TDAT[1]
TDAT[2]
TDAT[3]
TDAT[4]
TDAT[5]
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
SATURN USER NETWORK INTERFACE (155-TETRA)
T
T
T
T
T
T
T
I
I
I
I
I
I
I
T
T
T
T
T
T
T
T
T
T
T
T
T
T
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
0
0
1
0
1
0
1
1
0
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
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RX_UTOPIA_OEB
RX_UTOPIA_OEB
RX_UTOPIA_OEB
RX_UTOPIA_OEB
RX_UTOPIA_OEB
RX_UTOPIA_OEB
RX_UTOPIA_OEB
RX_UTOPIA_OEB
RX_UTOPIA_OEB
RX_UTOPIA_OEB
RX_UTOPIA_OEB
HIZ_OEB
HIZ_OEB
HIZ_OEB
HIZ_OEB
RCA_PRPA_OEB
HIZ_OEB
HIZ_OEB
HIZ_OEB
HIZ_OEB
TCA_PTPA_OEB
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TDAT[6]
TDAT[7]
TDAT[8]
TDAT[9]
TDAT[10]
TDAT[11]
TDAT[12]
TDAT[13]
TDAT[14]
TDAT[15]
STPA
STPA_OEB
TEOP
TERR
PHY_OEN
D_OEB[0]
D[0]
D_OEB[1]
D[1]
D_OEB[2]
D[2]
D_OEB[3]
D[3]
D_OEB[4]
D[4]
D_OEB[5]
D[5]
D_OEB[6]
D[6]
D_OEB[7]
D[7]
A[0]
A[1]
A[2]
A[3]
A[4]
A[5]
A[6]
A[7]
A[8]
A[9]
A[10]
CSB
SATURN USER NETWORK INTERFACE (155-TETRA)
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
I
I
I
I
I
I
I
I
I
I
T
E
I
I
I
E
B
E
B
E
B
E
B
E
B
E
B
E
B
E
B
I
I
I
I
I
I
I
I
I
I
I
I
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
STPA_OEB
D_OEB[0]
D_OEB[1]
D_OEB[2]
D_OEB[3]
D_OEB[4]
D_OEB[5]
D_OEB[6]
D_OEB[7]
298
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ISSUE 7
ALE
RDB
WRB
RSTB
INTB
HIZ_OEB
RX_UTOPIA_OEB
TCA_PTPA_OEB
RCA_PRPA_OEB
TFPI
REFCLK
TSD1
TSD2
TSD3
TSD4
TLD1
TLD2
TLD3
TLD4
TSDCLK1
TSDCLK2
TSDCLK3
TSDCLK4
TLDCLK1
TLDCLK2
TLDCLK3
TLDCLK4
TFPO
TCLK
RFPO1
RFPO2
RFPO3
RFPO4
RCLK1
RCLK2
RCLK3
RCLK4
RLD1
RLD2
RLD3
RLD4
RSD1
RSD2
SATURN USER NETWORK INTERFACE (155-TETRA)
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
I
I
I
I
O
E
E
E
E
I
I
I
I
I
I
I
I
I
I
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
HIZ_OEB
HIZ_OEB
HIZ_OEB
HIZ_OEB
HIZ_OEB
HIZ_OEB
HIZ_OEB
HIZ_OEB
HIZ_OEB
HIZ_OEB
HIZ_OEB
HIZ_OEB
HIZ_OEB
HIZ_OEB
HIZ_OEB
HIZ_OEB
HIZ_OEB
HIZ_OEB
HIZ_OEB
HIZ_OEB
HIZ_OEB
HIZ_OEB
HIZ_OEB
HIZ_OEB
299
PMC-Sierra, Inc.
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RSD3
RSD4
RLDCLK1
RLDCLK2
RLDCLK3
RLDCLK4
RSDCLK1
RSDCLK2
RSDCLK3
RSDCLK4
RMOD
SATURN USER NETWORK INTERFACE (155-TETRA)
10
9
8
7
6
5
4
3
2
1
0
T
T
T
T
T
T
T
T
T
T
T
0
0
0
0
0
0
0
0
0
0
0
HIZ_OEB
HIZ_OEB
HIZ_OEB
HIZ_OEB
HIZ_OEB
HIZ_OEB
HIZ_OEB
HIZ_OEB
HIZ_OEB
HIZ_OEB
RX_UTOPIA_OEB
NOTES:
1. D_OENB[7:0] is the active low output enable for D[7:0].
2. RX_UTOPIA_OEB is the active low output enable for RSOC/RSOP,
RDAT[15:0], RXPRTY, RMOD, RERR, RVAL.
3. TCA_PTPA_OEB is the active low output enable for TCA/PTPA.
4. RCA_PRPA_OEB is the active low output enable for RCA/PRPA.
5. STPA_OEB is the active low output enable for STPA.
6. When set high, INTB will be set to high impedance.
7. HIZ_OEB is the active low output enable for all OUT_CELL types except
those listed above.
8. A[7] is the first bit of the boundary scan chain.
Table 16: S/UNI-QUAD Boundary Scan Register (Length – 114 bits)
PIN/ENABLE
RALRM1
RALRM2
RALRM3
RALRM4
RDAT[0]
RDAT[1]
RDAT[2]
RDAT[3]
RDAT[4]
RDAT[5]
REG. BIT
113
112
111
110
109
108
107
106
105
104
CELL TYPE
T
T
T
T
T
T
T
T
T
T
ID
1
0
1
1
0
0
1
1
0
0
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CONTROL
HIZ_OEB
HIZ_OEB
HIZ_OEB
HIZ_OEB
RX_UTOPIA_OEB
RX_UTOPIA_OEB
RX_UTOPIA_OEB
RX_UTOPIA_OEB
RX_UTOPIA_OEB
RX_UTOPIA_OEB
300
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RDAT[6]
RDAT[7]
RDAT[8]
RDAT[9]
RDAT[10]
RDAT[12]
RDAT[11]
RDAT[13]
RDAT[14]
RDAT[15]
RPRTY
RADR[0]
RADR[1]
RADR[2]
RADR[3]
RADR[4]
RFCLK
RENB
DTCA_DTPA[1]
DTCA_DTPA[2]
DTCA_DTPA[3]
DTCA_DTPA[4]
RSOC_RSOP
RCA_PRPA
DRCA_DRPA[1]
DRCA_DRPA[2]
DRCA_DRPA[3]
DRCA_DRPA[4]
TCA_PTPA
TFCLK
TENB
TSOC_TSOP
TPRTY
TADR[0]
TADR[1]
TADR[2]
TADR[3]
TADR[4]
TDAT[0]
TDAT[1]
TDAT[2]
TDAT[3]
TDAT[4]
TDAT[5]
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
SATURN USER NETWORK INTERFACE (155-TETRA)
T
T
T
T
T
T
T
T
T
T
T
I
I
I
I
I
I
I
T
T
T
T
T
T
T
T
T
T
T
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
0
0
1
0
0
1
0
0
1
0
1
1
0
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
RX_UTOPIA_OEB
RX_UTOPIA_OEB
RX_UTOPIA_OEB
RX_UTOPIA_OEB
RX_UTOPIA_OEB
RX_UTOPIA_OEB
RX_UTOPIA_OEB
RX_UTOPIA_OEB
RX_UTOPIA_OEB
RX_UTOPIA_OEB
RX_UTOPIA_OEB
HIZ_OEB
HIZ_OEB
HIZ_OEB
HIZ_OEB
RX_UTOPIA_OEB
RCA_OEB
HIZ_OEB
HIZ_OEB
HIZ_OEB
HIZ_OEB
TCA_OEB
301
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TDAT[6]
TDAT[7]
TDAT[8]
TDAT[9]
TDAT[10]
TDAT[11]
TDAT[12]
TDAT[13]
TDAT[14]
TDAT[15]
PHY_OEN
D_OEB[0]
D[0]
D_OEB[1]
D[1]
D_OEB[2]
D[2]
D_OEB[3]
D[3]
D_OEB[4]
D[4]
D_OEB[5]
D[5]
D_OEB[6]
D[6]
D_OEB[7]
D[7]
A[0]
A[1]
A[2]
A[3]
A[4]
A[5]
A[6]
A[7]
A[8]
A[9]
A[10]
CSB
ALE
RDB
WRB
RSTB
SATURN USER NETWORK INTERFACE (155-TETRA)
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
I
I
I
I
I
I
I
I
I
I
I
E
B
E
B
E
B
E
B
E
B
E
B
E
B
E
B
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
D_OEB[0]
D_OEB[1]
D_OEB[2]
D_OEB[3]
D_OEB[4]
D_OEB[5]
D_OEB[6]
D_OEB[7]
302
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INTB
HIZ_OEB
RX_UTOPIA_OEB
TCA_PTPA_OEB
RCA_PRPA_OEB
TFPI
REFCLK
TFPO
TCLK
RFPO1
RFPO2
RFPO3
RFPO4
RCLK1
RCLK2
RCLK3
RCLK4
SATURN USER NETWORK INTERFACE (155-TETRA)
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
O
E
E
E
E
I
I
T
T
T
T
T
T
T
T
T
T
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
HIZ_OEB
HIZ_OEB
HIZ_OEB
HIZ_OEB
HIZ_OEB
HIZ_OEB
HIZ_OEB
HIZ_OEB
HIZ_OEB
HIZ_OEB
NOTES:
9. D_OENB[7:0] is the active low output enable for D[7:0].
10. RX_UTOPIA_OEB is the active low output enable for RSOC, RDAT[15:0],
RXPRTY.
11. TCA_OEB is the active low output enable for TCA.
12. RCA_OEB is the active low output enable for RCA.
13. When set high, INTB will be set to high impedance.
14. HIZ_OEB is the active low output enable for all OUT_CELL types except
those listed above.
15. A[7] is the first bit of the boundary scan chain.
12.3.1 Boundary Scan Cells
In the following diagrams, CLOCK-DR is equal to TCK when the current
controller state is SHIFT-DR or CAPTURE-DR, and unchanging otherwise. The
multiplexer in the center of the diagram selects one of four inputs, depending on
the status of select lines G1 and G2. The ID Code bit is as listed in the Boundary
Scan Register table located above.
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Figure 14: Input Observation Cell (IN_CELL)
IDCODE
Scan Chain Out
INPUT
to internal
logic
Input
Pad
G1
G2
SHIFT-DR
12
1 2 MUX
12
I.D. Code bit
D
C
12
CLOCK-DR
Scan Chain In
Figure 15: Output Cell (OUT_CELL)
Scan Chain Out
G1
EXTEST
Output or Enable
from system logic
IDOODE
SHIFT-DR
1
G1
G2
1
OUTPUT
or Enable
MUX
1 2
1 2 MUX
I.D. code bit
1 2
1 2
D
C
D
C
CLOCK-DR
UPDATE-DR
Scan Chain In
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Figure 16: Bidirectional Cell (IO_CELL)
Scan Chain Out
G1
EXTEST
OUTPUT from
internal logic
IDCODE
1
SHIFT-DR
INPUT
from pin
I.D. code bit
MUX
1
G1
G2
12
1 2 MUX
12
12
D
C
INPUT
to internal
logic
OUTPUT
to pin
D
C
CLOCK-DR
UPDATE-DR
Scan Chain In
Figure 17: Layout of Output Enable and Bidirectional Cells
Scan Chain Out
OUTPUT ENABLE
from internal
logic (0 = drive)
INPUT to
internal logic
OUTPUT from
internal logic
OUT_CELL
IO_CELL
I/O
PAD
Scan Chain In
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13 OPERATION
13.1 SONET/SDH Frame Mappings and Overhead Byte Usage
13.1.1 ATM Mapping
The S/UNI-TETRA processes the ATM cell mapping for STS-3c (STM-1) as
shown below in Figure 18. The S/UNI-TETRA processes the transport and path
overhead required to support ATM UNIs and NNIs. In addition, the S/UNI-TETRA
provides support for the APS bytes, the data communication channels and
provides full control and observability of the transport and path overhead bytes
through register access. In Figure 18, the STS-3c (STM-1) mapping is shown. In
this mapping, no stuff columns are included in the SPE. The entire SPE is used
for ATM cells.
Figure 18: ATM Mapping into the STS-3c (STM-1) SPE
270 by tes
9
by tes
261 bytes
S e c tion
Overh ead
(Reg en.
Section)
J1
A T M Cell
B3
C2
Pointer
9
bytes
G1
A T M Cell
Line
Overh ead
(M u lt iple x
Section)
H4
ATM Cell
ATM Cell
S T S-3c T ransport Ov erhead
S T M -1 Section Ov erhead
A1
A1 A1
A2 A 2 A2
J0
D2
D3
Z0 Z0
B1
D1
H 1 H1 H 1 H 2 H 2 H 2 H3 H 3 H 3
B2
D4
B2 B2
K1
K2
D5
D6
D7
D8
D9
D10
D11
D12
S1
M 1 E2
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13.1.2 Packet over SONET/SDH Mapping
The S/UNI-TETRA processes the Packet over SONET mapping for STS-3c
(STM-1) as shown below in Figure 19. The S/UNI-TETRA processes the
transport and path overhead required to support Packet over SONET/SDH
applications. In addition, the S/UNI-TETRA provides support for the APS bytes,
the data communication channels and provides full control and observability of
the transport and path overhead bytes through register access. In Figure 19, the
STS-3c (STM-1) mapping is shown. In this mapping, the entire SPE is used for
POS Frames.
Figure 19: POS Mapping into the STS-3c (STM-1) SPE
270 by tes
9
bytes
261 by tes
Sectio n
O verh ead
(Reg en.
S e c tion )
POS Fr a m e
J1
B3
C2
Pointer
9
byt es
G1
PO S Fr a m e
Line
O verh ead
(M u ltip lex
S e c tion )
H4
POS F r a m e
STS-3c T r ansport O ve rhead
STM -1 Secti on Ov erhead
A 1 A1 A 1 A 2 A2
A2
J0
Z 0 Z0
B1
D1
D2
D3
H 1 H 1 H 1 H 2 H 2 H2 H3 H 3 H3
B 2 B2 B 2 K 1
K2
D4
D5
D6
D7
D8
D9
D10
D11
S1
D12
M1 E2
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13.1.3 Transport and Path Overhead Bytes
Under normal operating conditions, the S/UNI-TETRA processes a subset of the
complete transport overhead present in an STS-3c (STM-1) stream. The byte
positions processed by the S/UNI-TETRA are indicated in Figure 20.
Figure 20: STS-3c (STM-1) Overhead
A1
A1
A1
A2
A2
A2
J0
Z0
Z0
B1
J1
B3
D1
D3
D2
H1
H1
H1
H2
H2
B2
B2
B2
K1
K2
D4
D5
D6
D7
D8
D9
D 10
D 11
D12
S1
H2
H3
C2
H3
H3
G1
H4
M1
TRANSPORT OVE RHEAD
SOH
PATH OVERHEAD
POH
Transport Overhead Bytes
A1, A2:
The frame alignment bytes (A1, A2) locate the SONET/SDH
frame in the STS-3c (STM-1) serial stream.
J0
The J0 byte is currently defined as the STS-3c (STM-1) section
trace byte for SONET/SDH. J0 byte is not scrambled by the
frame synchronous scrambler.
Z0:
The Z0 bytes are currently defined as the STS-3c (STM-1) section
growth bytes for SONET/SDH. Z0 bytes are not scrambled by the
frame synchronous scrambler.
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B1:
The section bit interleaved parity byte provides a section error
monitoring function.
D1 - D3:
The section data communications channel provides a 192 kbit/s
data communications channel for network element to network
element communications.
H1, H2:
The pointer value bytes locate the path overhead column in the
SONET/SDH frame.
H3:
The pointer action bytes contain synchronous payload envelope
data when a negative stuff event occurs. The all zeros pattern is
inserted in the transmit direction. This byte is ignored in the
receive direction unless a negative stuff event is detected.
B2:
The line bit interleaved parity bytes provide a line error monitoring
function.
K1, K2:
The K1 and K2 bytes provide the automatic protection switching
channel. The K2 byte is also used to identify line layer
maintenance signals. Line RDI is indicated when bits 6, 7, and 8
of the K2 byte are set to the pattern '110'. Line AIS is indicated
when bits 6, 7, and 8 of the K2 byte are set to the pattern '111'.
D4 - D12:
The line data communications channel provides a 576 kbit/s data
communications channel for network element to network element
communications.
S1:
The S1 byte provides the synchronization status byte. Bits 5
through 8 of the synchronization status byte identifies the
synchronization source of the STS-3c (STM-1) signal. Bits 1
through 4 are currently undefined.
M1:
The M1 byte is located in the third STS-1 locations of a STS-3c
(STM-1) and provides a line far end block error function for
remote performance monitoring.
Path Overhead Bytes
J1:
The Path Trace byte is used to repetitively transmit a 64-byte
CLLI message (for SONET networks), or a 16-byte E.164 address
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(for SDH networks). When not used, this byte should be set to
transmit continuous null characters. Null is defined as the ASCII
code, 0x00.
B3:
The path bit interleaved parity byte provides a path error
monitoring function.
C2:
The path signal label indicator identifies the equipped payload
type. For ATM payloads, the identification code is 0x13: For
Packet over SONET/SDH (including X 43 + 1 payload scrambling),
the identification code is 0x16.
G1:
The path status byte provides a path FEBE function, and a path
remote defect indication function. Three bits are allocated for
remote defect indications: bit 5 (the path RDI bit), bit 6 (the
auxiliary path RDI bit) and bit 7 (Enhanced RDI bit). Taken
together these bits provide a eight state path RDI code that can
be used to categorize path defect indications.
H4:
The multiframe indicator byte is a payload specific byte, and is not
used for ATM payloads. This byte is forced to 0x00 in the
transmit direction, and is ignored in the receive direction.
13.2 ATM Cell Data Structure
ATM cells may be passed to/from the S/UNI-TETRA using a twenty-seven word,
16-bit Utopia level 2 compliant data structure. This data structure is shown in
Figure 21.
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Figure 21: 16-bit Wide, 27 Word ATM Cell Structure
Bit 15
Bit 8
Bit 7
Bit 0
Word 1
H1
H2
Word 2
H3
H4
Word 3
H5
HCS
STATUS/CONTROL
Word 4
PAYLOAD1
PAYLOAD2
Word 5
PAYLOAD3
PAYLOAD4
Word 6
PAYLOAD5
PAYLOAD6
PAYLOAD47
PAYLOAD48
Word 27
Bit 15 of each word is the most significant bit (which corresponds to the first bit
transmitted or received). The header check sequence octet (HCS) is passed
through this structure. The start of cell indication input and output (TSOC and
RSOC) are coincident with Word 1 (containing the first two header octets). Word
3 of this structure contains the HCS octet in bits 15 to 8.
In the receive direction, the lower 8 bits of Word 3 contain the HCS status octet.
An all-zeros pattern in these 8 bits indicates that the associated header is error
free. An all-ones pattern indicates that the header contains an uncorrectable
error (if the HCSPASS bit in the RXCP Control Register is set to logic zero, the
all-ones pattern will never be passed in this structure). An alternating ones and
zeros pattern (0xAA) indicates that the header contained a correctable error. In
this case the header passed through the structure is the "corrected" header.
In the transmit direction, the HCS bit in the TXCP Control register determines
whether the HCS is calculated internally or is inserted directly from the upper 8
bits of Word 3. The lower 8 bits of Word 3 contain the HCS control octet. The
HCS control octet is an error mask that allows the insertion of one or more errors
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in the HCS octet. A logic one in a given bit position causes the inversion of the
corresponding HCS bit position (for example a logic one in bit 7 causes the most
significant bit of the HCS to be inverted).
13.3 Packet over SONET/SDH Data Structure
Packets may be written into the TXFP FIFO and read from the RXFP FIFO using
one defined data structure. Octets are written in the same order they are to be
transmitted or they were received on the SONET/SDH line. Within an octet, the
MSB (bit 7) is the first bit to be transmitted. All words are composed of two octets,
except the last word of a packet which can have one or two bytes. If the TXFP
does not insert the FCS field, then these bytes should be included at the end of
the packet. If the RXFP does not strip the FCS field, then these bytes will be
included at the end of the packet.
Figure 22: Packet Data Structure
Bit 1 5
Bit 8
Bit 7
Bit 0
Word 1
Byte 1
By te 2
Word 2
Byte 3
By te 4
Word 7
Byte 13
By te 14
Word 8
Byte 15
XX
A 15 byte packet
13.4 Bit Error Rate Monitor
The S/UN-TETRA provides two BERM blocks. One can be dedicated to monitor
at the Signal Degrade (SD) error rate and the other dedicated to monitor at the
Signal Fail (SF) error rate.
The Bit Error Rate Monitor (BERM) block counts and monitor line BIP errors over
programmable periods of time (window size). It can monitor to declare an alarm
or to clear it if the alarm is already set. A different threshold and accumulation
period must be used to declare or clear the alarm, whether or not those two
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operations are not performed at the same BER. The following table list the
recommended content of the BERM registers for different error rates (BER). Both
BERMs in the TSB are equivalent and are programmed similarly. In a normal
application they will be set to monitor different BER.
When the SF/SD CMODE bit is 1 this indicates that the clearing monitoring is
recommended to be performed using a window size that is 8 times longer than
the declaration window size. When the SF/SD CMODE bit is 0 this indicates that
the clearing monitoring is recommended to be performed using a window size
equal to the declaration window size. In all cases the clearing threshold is
calculated for a BER that is 10 times lower than the declaration BER, as required
in the references. The table indicates the declare BER and evaluation period
only.
The Saturation threshold is not listed in the table, and should be programmed
with the value 0xFFF by default, deactivating saturation. Saturation capabilities
are provided to allow the user to address issues associated with error bursts.
Table 17: Recommended BERM settings
declare
BER
10-3
10-4
10-5
10-6
10-7
10-8
10-9
Eval Per SF/SD
(s)
SMODE
0.008
0
0.013
0
0.100
0
1.000
0
10.000
0
83.000
0
667.000
0
SF/SD
CMODE
0
1
1
1
1
1
1
SF/SD
SAP
0x000008
0x00000D
0x000064
0x0003E8
0x002710
0x014438
0x0A2D78
SF/SD
DTH
0x245
0x0A3
0x084
0x085
0x085
0x06D
0x055
SF/SD
CTH
0x083
0x0B4
0x08E
0x08E
0x08E
0x077
0x061
It is important to notice that the Table 17 was designed around the Bellcore
GR-253 specification. Please refer to the SONET/SDH/SDH Bit error Threshold
Monitoring application note for more details as well as a recommended
programming meeting the ITU G.783 specification.
13.5 Clocking Options
The S/UNI-TETRA supports several clocking modes. Figure 23 is an abstraction
of the clocking topology.
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Figure 23: Conceptual Clocking Structure
Conceptual Clocking Structure
RE F C L K
C
Int ernal
Tx Clock
Sourc e
A
Clo ck Sy nthesizer
B
÷8
T CLK
Internal
Rx Clo ck
Sour ce
R X D+ /-
Mode A
Source timed
Mode B
Internally
Loop timed
Clock Recover y
÷8
W AN
Synchroniz ati on
RC LK
Mode C
Externally
Loop timed
CBI to
Micr ocon troller
Mode A is provided for all public user network interfaces (UNIs) and for private
UNIs and private network node interfaces (NNIs) that are not synchronized to the
recovered clock.
The transmit clock in a public UNI must conform to SONET Network Element
(NE) requirements specified in Bellcore GR-253-CORE. These requirements
include jitter generation, short term clock stability, phase transients during
synchronization failure, and possibly holdover. The 19.44 MHz clock source is
typically a VCO (or temperature compensated VCXO) locked to a primary
reference source for public UNI applications. The accuracy of this clock source
should be within ±20 ppm of 19.44 MHz to comply with the SONET/SDH network
element free-run accuracy requirements. The S/UNI-TETRA WANS block allows
to effectively implement the system timing reference.
The transmit clock in a private UNI or a private NNI may be locked to an external
reference or may free-run. The simplest implementation requires an oscillator
free-running at 19.44 MHz.
Mode A is selected by clearing the LOOPT bit of the Channel Control register.
REFCLK is multiplied by 8 to become the 155.52 MHz MHz transmit clock.
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REFCLK must be jitter free. The source REFCLK is also internally used as the
clock recovery reference.
Mode B is provided for private UNIs and private NNIs that require
synchronization to the recovered clock. Mode B is selected by setting the LOOPT
bit of the Master Control register. Normally, the transmit clock is locked to the
receive data. In the event of a loss of signal condition, the transmit clock is
synthesized from REFCLK.
Mode C is the external loop timing mode which make use of the WAN
Synchronization block capabilities. This mode can be achieved when LOOPT is
set to logic zero. The timing loop is achieved at the system level, through a
microprocessor, an external VCXO and back into the REFCLK input. This mode
allows to meet Bellcore wander transfer and holdover stability requirements.
13.6 Loopback Operation
The S/UNI-TETRA supports three loopback functions: line loopback, parallel
diagnostic loopback and serial diagnostic loopback. Each channel's loopback
modes operate independently. The loopback modes are activated by the PDLE,
LLE and SDLE bits contained in the S/UNI-TETRA Channel Control Register.
The line loopback, see Figure 24, connects the high speed receive data and
clock to the high speed transmit data and clock, and can be used for line side
investigations (including clock recovery and clock synthesis). While in this mode,
the entire receive path is operating normally and cells can be received through
the FIFO interface.
The serial diagnostic loopback, see Figure 25, connects the high speed transmit
data and clock to the high speed receive data and clock. While in this mode, the
entire transmit path is operating normally and data is transmitted on the TXD+/outputs.
The parallel diagnostic loopback, see Figure 26, connects the byte wide transmit
data and clock to the byte wide receive data and clock. While in this mode, the
entire transmit path is operating normally and data is transmitted on the TXD+/outputs.
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Line
DCC
Extract
RLDCLK1-4
RLD1-4
Section
DCC
Extract
Rx
APS,
Sync,
BERM
Rx
Line O/H
Processor
Rx
Section O/H
Processor
Section
Trace
Buffer
Rx
Path O/H
Processor
Path
Trace
Buffer
Rx
ATM Cell
processor
Rx
POS Frame
Processor
Tx
POS Frame
Processor
Utopia / POS-PHY
System Inte rface
Micro processor
I/F
STPA
TMOD
TERR
TEOP
DTCA[4:1]/DTPA[4:1]
TDAT[15:0]
TPRTY
TSOC/TSOP
T C A/PTPA
TADR[4:0]
TENB
TFCL K
PHY_O E N
RFCLK
RENB
RADR[4:0]
RCA/PRPA
RSOC/RSOP
RPRTY
RDAT[15:0]
DRCA[4:1]/DRP[4:1]
REOP
RERR
RMOD
RVAL
ISSUE 7
CP1-4
CN1-4
Rx Line
I/F
TCLK
TFPO
TFPI
RXD1-4 +
RXD1-4 SD1-4
TSDCLK1-4
TSD1-4
REFCLK
Tx
Path O/H
Processor
TDI
Tx
Line O/H
Processor
TDO
Tx
Section O/H
Processor
Tx
ATM Cell
Processor
TMS
ATB0-3
Tx Line
I/F
Line
DCC
Insert
PMC-1971240
TXD1-4 +
TXD1-4 -
TXC1-4 +
TXC1-4 -
TLDCLK1-4
TLD1-4
Section
DCC
Insert
TCK
JTAG Test
Access Port
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Figure 24: Line Loopback Mode
TRSTB
INTB
RSTB
RDB
WRB
CSB
ALE
A[10:0]
D[7:0]
RSDCLK1-4
RSD1-4
RCLK1-4
RFPO1-4
RALRM1-4
WAN
Synchronization
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DCC
Extract
RLDCLK1-4
RLD1-4
Section
DCC
Extract
Rx
APS,
Sync,
BERM
Rx
Line O/H
Processor
Rx
Section O/H
Processor
Section
Trace
Buffer
Rx
Path O/H
Processor
Path
Trace
Buffer
Rx
ATM Cell
processor
Rx
POS Frame
Processor
Tx
POS Frame
Processor
Utopia / POS-PHY
System Inte rface
Microprocessor
I/F
STPA
TMOD
TERR
TEOP
DTCA[4:1]/DTPA[4:1]
TDAT[15:0]
TPRTY
TSOC/TSOP
T C A/PTPA
TADR[4:0]
TENB
TFCL K
P H Y _O E N
RFCLK
RENB
RADR[4:0]
RCA/PRPA
RSOC/RSOP
RPRTY
RDAT[15:0]
DRCA[4:1]/DRP[4:1]
REOP
RERR
RMOD
RVAL
ISSUE 7
CP1-4
CN1-4
Rx Line
I/F
TCLK
TFPO
TFPI
RXD1-4 +
RXD1-4 SD1-4
TSDCLK1-4
TSD1-4
REFCLK
Tx
Path O/H
Processor
TDI
Tx
Line O/H
Processor
TDO
Tx
Section O/H
Processor
Tx
ATM Cell
Processor
TMS
ATB0-3
Tx Line
I/F
Line
DCC
Insert
PMC-1971240
TXD1-4 +
TXD1-4 -
TXC1-4 +
TXC1-4 -
TLDCLK1-4
TLD1-4
Section
DCC
Insert
TCK
JTAG Test
Access Port
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Figure 25: Serial Diagnostic Loopback Mode
TRSTB
INTB
RSTB
RDB
WRB
CSB
ALE
A[10:0]
D[7:0]
RSDCLK1-4
RSD1-4
RCLK1-4
RFPO1-4
RALRM1-4
WAN
Synchronization
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Line
DCC
Extract
RLDCLK1-4
RLD1-4
Section
DCC
Extract
Rx
APS,
Sync,
BERM
Rx
Line O/H
Processor
Rx
Section O/H
Processor
Section
Trace
Buffer
Rx
Path O/H
Processor
Path
Trace
Buffer
Rx
ATM Cell
processor
Rx
POS Frame
Processor
Tx
POS Frame
Processor
Utopia / POS-PHY
System Inte rface
Micro processor
I/F
STPA
TMOD
TERR
TEOP
DTCA[4:1]/DTPA[4:1]
TDAT[15:0]
TPRTY
TSOC/TSOP
T C A/PTPA
TADR[4:0]
TENB
TFCL K
PHY_O E N
RFCLK
RENB
RADR[4:0]
RCA/PRPA
RSOC/RSOP
RPRTY
RDAT[15:0]
DRCA[4:1]/DRP[4:1]
REOP
RERR
RMOD
RVAL
ISSUE 7
CP1-4
CN1-4
Rx Line
I/F
TCLK
TFPO
TFPI
RXD1-4 +
RXD1-4 SD1-4
TSDCLK1-4
TSD1-4
REFCLK
Tx
Path O/H
Processor
TDI
Tx
Line O/H
Processor
TDO
Tx
Section O/H
Processor
Tx
ATM Cell
Processor
TMS
ATB0-3
Tx Line
I/F
Line
DCC
Insert
PMC-1971240
TXD1-4 +
TXD1-4 -
TXC1-4 +
TXC1-4 -
TLDCLK1-4
TLD1-4
Section
DCC
Insert
TCK
JTAG Test
Access Port
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Figure 26: Parallel Diagnostic Loopback Mode
TRSTB
INTB
RSTB
RDB
WRB
CSB
ALE
A[10:0]
D[7:0]
RSDCLK1-4
RSD1-4
RCLK1-4
RFPO1-4
RALRM1-4
WAN
Synchronization
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13.7 JTAG Support
The S/UNI-TETRA supports the IEEE Boundary Scan Specification as described
in the IEEE 1149.1 standards. The Test Access Port (TAP) consists of the five
standard pins, TRSTB, TCK, TMS, TDI and TDO used to control the TAP
controller and the boundary scan registers. The TRSTB input is the active-low
reset signal used to reset the TAP controller. TCK is the test clock used to
sample data on input, TDI and to output data on output, TDO. The TMS input is
used to direct the TAP controller through its states. The basic boundary scan
architecture is shown below.
Figure 27: Boundary Scan Architecture
Boundary Scan
Register
TDI
Device Identification
Register
Bypass
Register
Instruction
Register
and
Decode
Mux
DFF
TDO
Control
TMS
Test
Access
Port
Controller
Select
Tri-state Enable
TRSTB
TCK
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The boundary scan architecture consists of a TAP controller, an instruction
register with instruction decode, a bypass register, a device identification register
and a boundary scan register. The TAP controller interprets the TMS input and
generates control signals to load the instruction and data registers. The
instruction register with instruction decode block is used to select the test to be
executed and/or the register to be accessed. The bypass register offers a singlebit delay from primary input, TDI to primary output, TDO. The device
identification register contains the device identification code.
The boundary scan register allows testing of board inter-connectivity. The
boundary scan register consists of a shift register place in series with device
inputs and outputs. Using the boundary scan register, all digital inputs can be
sampled and shifted out on primary output, TDO. In addition, patterns can be
shifted in on primary input, TDI and forced onto all digital outputs.
13.7.1 TAP Controller
The TAP controller is a synchronous finite state machine clocked by the rising
edge of primary input, TCK. All state transitions are controlled using primary
input, TMS. The finite state machine is described below.
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Figure 28: TAP Controller Finite State Machine
TRSTB=0
Test-Logic-Reset
1
0
1
1
Run-Test-Idle
1
Select-IR-Scan
Select-DR-Scan
0
0
0
1
1
Capture-IR
Capture-DR
0
0
Shift-IR
Shift-DR
1
0
1
0
1
1
Exit1-IR
Exit1-DR
0
0
Pause-IR
Pause-DR
0
1
0
0
1
0
Exit2-IR
Exit2-DR
1
1
Update-IR
Update-DR
1
0
1
0
All transitions dependent on input TMS
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States
Test-Logic-Reset
The test logic reset state is used to disable the TAP logic when the device is in
normal mode operation. The state is entered asynchronously by asserting input,
TRSTB. The state is entered synchronously regardless of the current TAP
controller state by forcing input, TMS high for 5 TCK clock cycles. While in this
state, the instruction register is set to the IDCODE instruction.
Run-Test-Idle
The run test/idle state is used to execute tests.
Capture-DR
The capture data register state is used to load parallel data into the test data
registers selected by the current instruction. If the selected register does not
allow parallel loads or no loading is required by the current instruction, the test
register maintains its value. Loading occurs on the rising edge of TCK.
Shift-DR
The shift data register state is used to shift the selected test data registers by one
stage. Shifting is from MSB to LSB and occurs on the rising edge of TCK.
Update-DR
The update data register state is used to load a test register's parallel output
latch. In general, the output latches are used to control the device. For example,
for the EXTEST instruction, the boundary scan test register's parallel output
latches are used to control the device's outputs. The parallel output latches are
updated on the falling edge of TCK.
Capture-IR
The capture instruction register state is used to load the instruction register with a
fixed instruction. The load occurs on the rising edge of TCK.
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Shift-IR
The shift instruction register state is used to shift both the instruction register and
the selected test data registers by one stage. Shifting is from MSB to LSB and
occurs on the rising edge of TCK.
Update-IR
The update instruction register state is used to load a new instruction into the
instruction register. The new instruction must be scanned in using the Shift-IR
state. The load occurs on the falling edge of TCK.
The Pause-DR and Pause-IR states are provided to allow shifting through the
test data and/or instruction registers to be momentarily paused.
Boundary Scan Instructions
The following is an description of the standard instructions. Each instruction
selects an serial test data register path between input, TDI and output, TDO.
13.7.1.2
Instructions
BYPASS
The bypass instruction shifts data from input, TDI to output, TDO with one TCK
clock period delay. The instruction is used to bypass the device.
EXTEST
The external test instruction allows testing of the interconnection to other
devices. When the current instruction is the EXTEST instruction, the boundary
scan register is place between input, TDI and output, TDO. Primary device
inputs can be sampled by loading the boundary scan register using the
Capture-DR state. The sampled values can then be viewed by shifting the
boundary scan register using the Shift-DR state. Primary device outputs can be
controlled by loading patterns shifted in through input TDI into the boundary scan
register using the Update-DR state.
SAMPLE
The sample instruction samples all the device inputs and outputs. For this
instruction, the boundary scan register is placed between TDI and TDO. Primary
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device inputs and outputs can be sampled by loading the boundary scan register
using the Capture-DR state. The sampled values can then be viewed by shifting
the boundary scan register using the Shift-DR state.
IDCODE
The identification instruction is used to connect the identification register between
TDI and TDO. The device's identification code can then be shifted out using the
Shift-DR state.
STCTEST
The single transport chain instruction is used to test out the TAP controller and
the boundary scan register during production test. When this instruction is the
current instruction, the boundary scan register is connected between TDI and
TDO. During the Capture-DR state, the device identification code is loaded into
the boundary scan register. The code can then be shifted out output, TDO using
the Shift-DR state.
13.8 Board Design Recommendations
The noise environment and signal integrity are often the limiting factors in system
performance. Therefore, the following board design guidelines must be followed
in order to ensure proper operation:
1. Use a single plane for both digital and analog grounds.
2. Provide separate +3.3 volt analogue and analog transmit, +3.3 volt analog
receive, and +3.3 volt digital supply with filtering between the power supply
rail and the analogue power pins ( see Figure 29: WAN Mode Analog Power
PIN Passive-Filtering with 3.3V Supply, Figure 30: WAN Mode Analog Power
Filters with 3.3V Supply (1) and Figure 31: LAN Mode Analog Power Filters
with 3.3V Supply (2) )ies, but otherwise connect the supply voltages together
at one point close to the connector where +3.3 volts is brought to the card.
3. Ferrite beads are not advisable in digital switching circuits because inductive
spiking (di/dt noise) is introduced into the power rail. Simple RC filtering is
probably the best approach provided care is taken to ensure the IR drop in
the resistance does not lower the supply voltage below the recommended
operating voltage.
4. Separate high-frequency decoupling capacitors are recommended for each
analog power (TAVD, RAVD and QAVD) pin as close to the package pin as
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possible. Separate decoupling is required to prevent the transmitter from
coupling noise into the receiver and to prevent transients from coupling into
some reference circuitry.
5. The high speed serial streams (TXD+/- and RXD+/) must be routed with
controlled impedance circuit board traces and must be terminated with a
matched load. Normal TTL-type design rules are not recommended and will
reduce the performance of the device.
13.9 Analog Power Supply Filtering
The noise environment and signal integrity are often the limiting factors of the
system performance. The analog circuitry is particularly susceptible to noise and
thus we recommend the following analog power filtering scheme.
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Figure 29: WAN Mode Analog Power PIN Passive-Filtering with 3.3V Supply
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0.1uF
3.2 by
2.5 mm
RAVD1-C
0.1uF
3.2 by
2.5 mm
RAVD1-C
47uF
7.3 by
4.3mm
0.1uF
3.2 by
2.5 mm
0.1uF
3.2 by
2.5 mm
47uF
7.3 by
4.3mm
0.1uF
3.2 by
2.5 mm
27 ohm
47uF
7.3 by
4.3mm
0.1uF
3.2 by
2.5 mm
0.1uF
3.2 by
2.5 mm
0.1uF
3.2 by
2.5 mm
27 ohm
TAVD1_A
27 ohm
4.7uF
7.3 by
4.3mm
0.1uF
3.2 by
2.5 mm
TETRA 31
by 31 mm
0.1uF
3.2 by
2.5 mm
0.1uF
3.2 by
2.5 mm
0.1uF
3.2 by
2.5 mm
27 ohm
47uF
7.3 by
4.3mm
47uF
7.3 by
4.3mm
27 ohm
27 ohm
RAVD1-B
RAVD2-B
RAVD3-B
RAVD4-B
RAVD1-C
47uF
7.3 by
4.3mm
0.1uF
3.2 by
2.5 mm
RAVD1-C
0.1uF
3.2 by
2.5 mm
0.1uF
3.2 by
2.5 mm
0.1uF
3.2 by
2.5 mm
47uF
7.3 by
4.3mm
TAVD1_B
47uF
7.3 by
4.3mm
0.1uF
3.2 by
2.5 mm
0.1uF
3.2 by
2.5 mm
47uF
7.3 by
4.3mm
47uF
7.3 by
4.3mm
0.1uF
3.2 by
2.5 mm
0.1uF
3.2 by
2.5 mm
0.1uF
3.2 by
2.5 mm
2.7 ohm
0.1uF
3.2 by
2.5 mm
0.1uF
3.2 by
2.5 mm
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0.1uF
3.2 by
2.5 mm
RAVD1-C
0.1uF
3.2 by
2.5 mm
RAVD1-C
47uF
7.3 by 4.3mm
0.1uF
3.2 by
2.5 mm
0.1uF
3.2 by
2.5 mm
47uF
7.3 by 4.3mm
0.1uF
3.2 by
2.5 mm
27 ohm
47uF
7.3 by 4.3mm
0.1uF
3.2 by
2.5 mm
0.1uF
3.2 by
2.5 mm
0.1uF
3.2 by
2.5 mm
27 ohm
TAVD1
27 ohm
4.7uF
7.3 by
4.3mm
0.1uF
3.2 by
2.5 mm
TETRA 31
by 31 mm
47uF
7.3 by 4.3mm
0.1uF
3.2 by
2.5 mm
27 ohm
27 ohm
27 ohm
0.1uF
3.2 by
2.5 mm
RAVD1-B
RAVD2-B
RAVD3-B
RAVD4-B
47uF
7.3 by 4.3mm
TAVD2
RAVD1-C
47uF
7.3 by 4.3mm
0.1uF
3.2 by
2.5 mm
RAVD1-C
0.1uF
3.2 by
2.5 mm
0.1uF
3.2 by
2.5 mm
0.1uF
3.2 by
2.5 mm
47uF
7.3 by 4.3mm
0.1uF
3.2 by
2.5 mm
47uF
7.3 by 4.3mm
0.1uF
3.2 by
2.5 mm
0.1uF
3.2 by
2.5 mm
47uF
7.3 by 4.3mm
47uF
7.3 by 4.3mm
0.1uF
3.2 by
2.5 mm
0.1uF
3.2 by
2.5 mm
0.1uF
3.2 by
2.5 mm
2.7 ohm
0.1uF
3.2 by
2.5 mm
0.1uF
3.2 by
2.5 mm
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Figure 30: WAN Mode Analog Power Filters with 3.3V Supply (1)
27 Ω
3.3V
RAVD1-C
+
47uF
RAVD1-B
27 Ω
RAVD2-B
3.3V
RAVD4-B
+
47uF
+
0.1uF
RAVD3-B
47uF
0.1uF
27 Ω
3.3V
RAVD2-C
+
47uF
+
47uF
100 Ω
0.1uF
QAVD1
3.3V
QAVD2
0.1uF
27 Ω
3.3V
RAVD3-C
+
47uF
+
47uF
0.1uF
NOTES
27 Ω
3.3V
RAVD4-C
+
47uF
2) place 0.1uF as close to power pin as possible
+
47uF
0.1uF
3) 47uF and resistors do not have to be
very
close to power pins
27 Ω
3.3V
TAVD1_A
+
1) Use 0.1uF on all other analog and digital
power pins
4.7uF
4) This configuration should be used when jitter
transfer is required (i.e. PERFCTRL is 0 in
register 0x0F.
0.1uF
2.7Ω
3.3V
TAVD1_B
+
47uF
0.1uF
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Figure 31: LAN Mode Analog Power Filters with 3.3V Supply (2)
27 Ω
TAVD1_A
3.3V
+
4.7uF
0.1uF
2.7 Ω
TAVD1_B
3.3V
+
47uF
0.1uF
100 Ω
3.3V
QAVD1
+
QAVD2
0.1uF
NOTES
1) Use 0.1uF on all other analog and digital power pins
2) place 0.1uF as close to power pin as possible.
3) 47uF and resistors do not have to be very close to power pins
4) This configuration should be used when jitter transfer is NOT
required (i.e. PERFCTRL = 1 in register 0x0F)
13.10 Power Supplies Sequencing
Due to ESD protection structures in the pads it is necessary to exercise caution
when powering a device up or down. ESD protection devices behave as diodes
between power supply pins and from I/O pins to power supply pins. Under
extreme conditions it is possible to blow these ESD protection devices or trigger
latch up. The recommended power supply sequencing follows:
1.)
To prevent damage to the ESD protection on the device inputs the
maximum DC input current specification must be respected. This is
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accomplished by either ensuring that the VDD power is applied before input
pins are driven or by increasing the source impedance of the driver so that
the maximum driver short circuit current is less than the maximum DC input
current specification. (20 mA)
2.)
QAVD power must be supplied either after VDD or simultaneously with VDD
to prevent current flow through the ESD protection devices which exist
between QAVD and VDD power supplies. To prevent forward biasing the
ESD protection diode between QAVD supplies and VDD the differential
voltage measured between these power supplies must be less than 0.5 volt.
This recommended differential voltage is to include peak to peak noise on
the VDD power supply as digital noise will otherwise be coupled into the
analog circuitry. Current limiting can be accomplished by using an off chip
three terminal voltage regulator supplied by a quiet high voltage supply.
3.)
BIAS voltage must be supplied either before VDD or simultaneously with
VDD to prevent current flow through the ESD protection devices which exist
between BIAS and VDD power supplies.
4.)
Analog power supplies (AVD, includes RAVDs, TAVDs but not QAVD)
should be applied after QAVD, but can be applied at the same time as
QAVD providing the 100ohm resistor in series with QAVD (shown in Figure
29 and Figure 30) is in place. The AVD supplies should also be current
limited to the maximum latchup current specification (100 mA). To prevent
forward biasing the ESD protection diode between AVD supplies and QAVD
the differential voltage measured between these power supplies must be
less than 0.5 volt. This recommended differential voltage is to include peak
to peak noise on the QAVD and AVD power supplies as digital noise will
otherwise be coupled into the analog circuitry. Current limiting can be
accomplished by using an off chip three terminal voltage regulator supplied
by a quiet high voltage supply. If the VDD power supply is relatively quiet,
VDD can be filtered using a ferrite bead and a high frequency decoupling
capacitor to supply AVD. The relative power sequencing of the multiple
AVD power supplies is not important.
5.)
Power down the device in the reverse sequence. Use the above current
limiting technique for the analog power supplies. Small offsets in VDD /
AVD discharge times will not damage the device.
Figure 32 illustrates a power sequencing circuit to avoid latch-up or damage to
3.3V devices that are 5V tolerant. This circuit will ensure V bias is greater than V dd
and protect against designs which require the 3.3V power supply appearing
before the 5V supply. The Schottky diode shown on Figure 32 is optional.
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Figure 32: Power Sequencing Circuit
1KΩ
Vbias
5V
0.1µ F
Schottky
Diode
3.3V
Vdd
13.11 Interfacing to ECL or PECL Devices
Although the TXD+/- and TXC+/- outputs are TTL compatible, only a few passive
components are required to convert the signals to ECL (or PECL) logic levels.
Figure 33 illustrates the recommended configuration. The capacitors AC couple
the outputs so that the ECL inputs are free to swing around the ECL bias voltage
(V BB). The combination of the RS, RS1 and Z0 resistors divide the voltage down
to a nominally 800mV swing. The Z0 resistors also terminate the signals.
The RXD+/- inputs to the S/UNI-TETRA are DC coupled as shown. The device
has a true PECL receiver so only termination resistors are required.
Ceramic coupling capacitors are recommended.
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Figure 33: Interfacing to ECL or PECL
Optics
PMD
S/UNI-TETRA
RxD+
RD+
Zo
2*Zo
Rd
RD-
RxD-
Zo
Gnd
Rd
Gnd
RS1
TD+
0.1 uF
TxD+
Zo
Zo
RS1
Zo
TD-
VDD
VDD
0.1uF
TxD-
Zo
R1
0.01uF or
0.1 uF
Vdd * R2/(R1+R2) = Vbb
R2
Gnd
SD
SD
Rd
Gnd
RS1
0.1 uF
Zo
TxC+
Zo
PECL
Differential
Clock Out
Zo
RS1
0.1uF
Zo
VDD
0.01uF or
0.1 uF
TxC-
VDD
R1
Vdd * R2/(R1+R2) = Vbb
R2
Gnd
Notes: Vpp is minimum input swing required by the optical PMD device.
Vbb is the switching threshold of the PMD device (typically Vdd - 1.3 volts)
Vpp is Voh - Vol (typically 800 mVolts)
Vpp = (Zo/((RS1+Rs)+Z0) * Vdd
- Vdd (S/UNI-TETRA’s analog transmit power) 3.3V
- Zo (trace impedance) typically 50 Ω
- Rs (TxD source impedance) typically 15-20Ω
- RS1 : ~ 158 Ω
For interfacing to 5.0V ODL, R1 : 237Ω , R2 : 698Ω
Rd : 330Ω
For interfacing to 3.3V ODL, R1 : 220Ω, R2: 330Ω
Rd : 150Ω
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13.12 Clock Recovery Loop Filter
In order to meet jitter transfer requirements for WAN applications, the clock
recovery unit requires an external 220nF X7R 10% ceramic loop capacitor. This
capacitor is placed across pins C1 and C2 in close proximity to the chip pins.
The external loop filter capacitor is used as a floating capacitor which means that
neither of C1 and C2 is grounded. Figure 34 is an abstraction of the clock
recovery phase lock loop illustrating the connections to external components.
Figure 34: Clock Recovery External Components
Differential Loop Filter
RXD+/
REFCLK
Phase
Detector
Charge
Pump
VCO
Recovered Clock
On-Chip Circuitry
Off-Chip Circuitry
C1
220nF
C2
13.13 Setting the S/UNI-TETRA in ATM Mode
The S/UNI-TETRA defaults to the Asynchronous Transfer Mode (ATM) operation
but it is recommended to implement the following initialization sequence.
1. Reset the device. This can be done by asserting the RSTB pin or setting the
RESET bit in the Master Reset and ID Register (Register 00).
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2. Set the S/UNI-TETRA in ATM mode by setting to logic 0 the ATM_POS bit in
the Master System Interface Control register (Register 02). It is also
recommended to set the TPOP Path Signal Label (Register 0x48 ) to 0x13,
which indicates an ATM payload.
3. For every channel, reset all the Rx and Tx ATM FIFO’s by setting the
FIFORST register bit in the TXCP and RXCP blocks. Keep this bit set for at
least 1 µs, then set the bit back to its inactive logic zero value.
4. For every channel, reset the performance monitoring counters in TXCP and
RXCP blocks, and preferably in all the blocks. The easiest way to do this is to
use the TIP register bit.
5. It is suggested to set the H4INSB bit in register TXCP_50 Cell Count
Status/Configuration Options (Register 0x82) to logic one. In most
applications, where cell delineation is accomplished using the HCS byte, it is
more appropriate to set the H4 bytes to 0x00 rather then the cell offset.
13.14 Setting the S/UNI-TETRA in POS Mode
The S/UNI-TETRA defaults to the Asynchronous Transfer Mode (ATM) opration.
The following sequence of operation should be used to prepare the device for the
Packet over SONET/SDH (POS) operation.
1. Reset the device. This can be done by asserting the RSTB pin or setting the
RESET bit in the Master Reset and ID Register (Register 00).
6. Set the S/UNI-TETRA in POS mode by setting to logic 1 the ATM_POS bit in
the Master System Interface Control register (Register 02). It is also
recommended to set the TPOP Path Signal Label (Register 0x48 ) to 0x16
which indicates a scrambled POS payload, 0xCF which indicates a nonscrambled POS payload, whatever is appropriate.
7. For every channel, reset all the Rx and Tx POS FIFO’s by setting the
FIFORST register bit in the TXFP and RXFP blocks. Keep this bit set for at
least 1 µs, then set the bit back to its inactive logic zero value.
8. For every channel, reset the performance monitoring counters in TXFP and
RXFP blocks, and preferably in all the blocks. The easiest way to do this is to
use the TIP register bit.
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13.15 Setting the S/UNI-TETRA for SONET or SDH Applications
The SONET and SDH standards for optical networking are very similar, with only
minor differences in overhead processing. The main difference between the
SONET and SDH standards lies in the handling of some of the overhead bytes.
Other details, like framing, and data payload mappings are equivalent in SONET
and SDH. By default, PMC's S/UNI TETRA powers up in SONET mode.
However, it can be configured to operate in SDH mode.
The bit error rate (BER) monitoring requirements are also slightly different
between Bellcore GR-253-CORE (SONET) and ITU.707 (SDH) An application
note, PMC-950820, explains in detail the different parameters for the RASE
block.
The list below shows the various register settings to configure the TETRA for
either SONET or SDH mode
Table 18 – Settings for SONET or SDH Applications
Configuration Bit
Z0INS 1
ENSS (0x3D)2
LEN16 (Path, 0x28)3
LEN16 (Section, 0x50)3
S[1:0] (0x46)4
SONET
0
0
0
0
00
SDH
X
1
1
1
10
Notes:
1 - SONET requires Z0 bytes to be set to the number corrsponding to the STS-1 column number.
SDH consider those bits as reserved.
2 - SDH specification requires the detection of SS bits to be “10”
3 - SONET uses 64 bytes message/SDH uses 16 bytes message
4 - SS is undefined for SONET but must be set to “10” for SDH
13.16 Using the S/UNI-TETRA with a 5 Volt ODL
The S/UNI-TETRA defaults to a 3.3V PECL optical data link (ODL) module
interface. It can also be used with a 5V ODL. This is accomplished by setting to
logic 1 the PECLV bit located in the Master Configuration Register (Register
0x01). Notice that all four channels are reconfigured.
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14 FUNCTIONAL TIMING
All functional timing diagrams assume that polarity control is not being applied to
input and output data and clock lines (i.e. polarity control bits in the
S/UNI-TETRA registers are set to their default states).
14.1 ATM Utopia Level 2 System Interface
Figure 35: Multi-PHY Polling and Addressing Transmit Cell Interface
TFCLK
TCA
CA(A)
CA(B)
X
CA(C)
CA(B)
CA(A)
TENB
TADR[4:0]
A
1Fh
B
1Fh
C
1Fh
X
B
1Fh
A
1Fh
C
X
W1
W2
W3
W4
TSOC
TDAT[15:0]
W (n-7) W (n-6)
W (n-5) W (n-4) W (n-3)
W (n-2) W (n-1)
W (n)
X
TPRTY
Figure 66 is an example of the multi-PHY polling and selection sequence
supported by the S/UNI-TETRA. "A", "B", and "C" represent any arbitrary
address values of PHY devices which may be occupied by the S/UNI-TETRA.
The ATM Layer device is not restricted in its polling order. The PHY associated
with address "A" indicates it cannot accept a cell, but PHY "B" indicates it is
willing to accept a cell. As a result, the ATM Layer places address "B" on
TADR[4:0] the cycle before TENB is asserted to select PHY "B" as the next cell
destination. In this example, the PHY "C" status is ignored. The ATM Layer
device is not constrained to select the latest PHY polled. As soon as the cell
transfer is started, the polling process may be restarted.
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During multi-PHY operation, several PHY layer devices share the TCA signal. As
a result, this signals must be tri-stated in all PHY devices which have not been
selected for polling by the ATM Layer. The value of TADR[4:0] selects the PHY
being polled for the TCA signal, and all devices not corresponding to this address
must tri-state its TCA output. This multi-PHY operation is directly supported by
the S/UNI-TETRA.
Figure 36: Multi-PHY Polling and Addressing Receive Cell Interface
RFCLK
RCA
CA(A)
CA(B)
X
CA(C)
CA(B)
CA(D)
RENB
RADR[4:0]
A
1Fh
B
1Fh
C
1Fh
X
B
1Fh
D
1Fh
W1
W2
E
RSOC
RDAT[15:0] W (n-7)
W (n-6) W (n-5) W (n-4)
W (n-3) W (n-2)
W (n-1)
W (n)
W3
RPRTY
Figure 67 shows an example of the multi-PHY polling and selection sequence
supported by the S/UNI-TETRA. "A", "B", "C", "D", and "E" represent any
arbitrary address values which may be occupied by the S/UNI-TETRA. The ATM
Layer device is not restricted in its polling order. The PHY associated with
address "A" indicates it does not have a cell available, but PHY "B" indicates that
it does. As a result, the ATM Layer places address "B" on RADR[4:0] the cycle
before RENB is asserted to select PHY "B" as the next cell source. In this
example, PHY "C"s status is ignored. The ATM Layer device is not constrained
to select the latest PHY polled. As soon as the cell transfer is started, the polling
process may be restarted.
During multi-PHY operation, several PHY layer devices share the RDAT[15:0],
RSOC, RPRTY, and RCA signals. As a result, these signals must be tri-stated in
all PHY devices which have not been selected for reading or polling by the ATM
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Layer. Selection of which PHY layer device is being read is made by the value
on RADR[4:0] the cycle before RENB is asserted and affects the RDAT[15:0],
RSOC, and RPRTY signals. The value of RADR[4:0] selects the PHY being
polled for the RCA signal, and all devices not corresponding to this address must
tri-state its RCA output. These multi-PHY operations are directly supported by
the S/UNI-TETRA.
14.2 Packet over SONET/SDH (POS) System Interface
The Packet over SONET/SDH (POS) System Interface is compatible with the
POS-PHY Level 2 specification (see References). The S/UNI-TETRA supports
both the byte level and packet level transfer modes of POS-PHY. The Packet
over SONET/SDH System interface supports two modes of operation. The
system interface can perform a byte-level transfer and a packet-level transfer, as
selected by Master Configuration register POS_PLVL bit. Packet level transfer
operates the same way Utopia level 2 does, with PHY polling and PHY selection.
Byte-level transfer is illustrated below. In that mode, direct status indication is
provided and the PHY address is looked at every cycle to determine which PHY
is being selected. There is no selection phase and no polling. This mode should
be more suitable for most applications.
The POS Transmit Synchronous FIFO Timing Diagram (Figure 37) illustrates the
operation of the system side transmit FIFO interface. Assertion of the transmit
packet available output, TPA, indicate that there is space available in the transmit
FIFO. Deassertion of TPA occurs when the FIFO is filled to the depth indicated by
the register TPAHWM[7:0]. The exact octet that triggers the deassertion of TPA
depends on the particular timing relationship between the internal SONET/SDH
clock and TFCLK, and for that reason is not precise. However the TXFP is
always conservative, thus when DTPA is deasserted there is for sure not more
than TPAHWM[7:0] bytes in the FIFO. If DTPA is asserted and the upstream is
ready to write a byte, the upstream device should assert TENB. At anytime, if the
upstream does not have a byte to write, it must deassert TENB. In addition, the
register bit TPAINV can be used to invert the meaning of DTPA.
TSOP must be high during the first word of the packet and must be present
(reasserted) for each packet. TEOP must be high during the last packet word.
During a packet transfer every word must be composed of two bytes and TMOD
shall be high. It is only for the last packet word that TMOD is used to determine if
this word is composed of one or two bytes. It is legal to assert TSOP and TEOP
at the same time. This happens when a 1-byte or a 2-byte packet is transferred.
When TSOP is asserted and the previous word transfer was not marked with
TEOP, the Input Interface realigns itself to the new timing, and the previous
packet is marked to be aborted.
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The byte-level transfer mode is intended to simplify the bus protocol and improve
throughput by avoiding the PHY selection cycles required in packet-level transfer
mode. Skipping the PHY selection cycle will work reliably only if the POS-PHY
bus is a point to point bus; that is connecting a single Link Layer device to a
single PHY Layer device. This is a typical application for the S/UNI-TETRA as it
uses most of the bandwidth on a Utopia Level 2 interface. As an alternative, the
system integrator can build the Link Layer device such that it forces the Null PHY
address for one cycle whenever TADR[4:0] or RADR[4:0] changes, inserting a
single dead cycle during which the bus is tristated. Although more complex,
packet-level transfer may offer a solution when multiple PHY’s are implemented
within several integrated circuits. Furthermore, the packet-level transfer
configuration scales with fewer pins than byte-level transfer as the number of
PHY increases.
Figure 37: Transmit POS System Interface Timing
TFCLK
TS OP
T EO P
TM O D
TERR
T PA
TENB
TDAT[15 :0 ]
PKT 1 P KT 1 PKT 1 PKT 1
B1
B3
B5
B7
B2
B4
B6
B8
PK T 1 P KT 1 P KT 1
B3 7
B3 9
B 41
B3 8
B4 0
B 42
P KT 1 PKT 1
B 43
B 45
XX
B 44
PK T 2
B1
B2
TP R TY
The POS Receive Synchronous FIFO Timing Diagram of Figure 38 illustrates the
operation of the system side receive interface. The RXFP indicates that the FIFO
level is above the high water mark or that the end of a packet is available by
asserting the receive packet available output, DRPA. When a channel is
selected, RVAL qualifies the data coming from the receive POS-PHY interface.
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The RVAL signal will de-assert after the transmission of a REOP flag or when the
FIFO empty. Once the RVAL signal de-asserts, it can not re-assert before the
channel is de-selected. The DRPA signal may assert and de-assert meanwhile in
conformity with the FIFO level, the water mark and the presence of end of packet
in the FIFO.
RSOP is high during the first word of the packet. REOP is high during the last
packet word. During a packet transfer every word must be composed of two
bytes. It is only for the last packet word that RMOD is used to determine if this
last word is composed of one or two bytes. It is legal to assert RSOP and REOP
at the same time. This happens when a 1-byte or a 2-byte packet is transferred.
Packets that were subject to an error (aborted, length violation, FIFO overrun,
etc) will be marked by RERR high during the last word transfer.
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Figure 38: Receive POS System Interface
RFCLK
RENB
DRPA[x]
RVAL
RSOP
REOP
RERR
RMOD
RDAT[15:0]
W1
W2
W3
W N-5 W N-4 W N-3 W N-2 WN-1 WN
RXPRTY
P1
P2
P3
PN-5 PN-4 PN-3 PN-2
PN-1
PN
More information can be found on the POS-PHY bus interface by referring to the
POS-PHY Level 2 specification.
14.3 Section and Line Data Communication Channels
The Transport Overhead Data Link Clock and Data Extraction timing diagram
(Figure 39) shows the relationship between the RSD, and RLD serial data
outputs, and their associated clocks, RSDCLK and RLDCLK. RSDCLK is a 216
kHz, 50% duty cycle clock that is gapped to produce a 192 kHz nominal rate.
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RLDCLK is a 2.16 MHz, 67%(high)/33%(low) duty cycle clock that is gapped to
produce a 576 kHz nominal rate. RSD (RLD) is updated on the falling RSDCLK
(RLDCLK) edge. The D1-D3, and D4-D12 bytes shifted out of the S/UNI-TETRA
in the frame shown are extracted from the corresponding receive line overhead
channels in the previous frame.
Figure 39: Transport Overhead Data Link Clock and Data Extraction
125 µs
RSDCLK
RSD
B1
B2 B3 B4 B5 B6 B7 B8 B1 B2 B3 B4 B5 B6 B7 B8 B1 B2 B3 B4 B5 B6 B7 B8
approx. 2 MHz DLCLK bursts
RLDCLK
RLD
RLDCLK
RLD
B1 B2 B3 B4 B5 B6 B7 B8 B1 B2 B3 B4 B5 B6 B7 B8 B1 B2 B3 B4 B5 B6 B7 B8
The Transport Overhead Data Link Clock and Data Insertion timing diagram
(Figure 40) shows the relationship between the TSD, and TLD serial data inputs,
and their associated clocks, TSDCLK and TLDCLK respectively. TSDCLK is a
216 kHz, 50% duty cycle clock that is gapped to produce a 192 kHz nominal rate.
TLDCLK is a 2.16 MHz, 67%(high)/33%(low) duty cycle clock that is gapped to
produce a 576 kHz nominal rate. TSD (TLD) is sampled on the rising TSDCLK
(TLDCLK) edge. The D1-D3, and D4-D12 bytes shifted into the S/UNI-TETRA in
the frame shown are inserted in the corresponding transport overhead channels
in the following frame.
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Figure 40: Transport Overhead Data Link Clock and Data Insertion
125 µs
TSDCLK
TSD
B1
B2 B3 B4 B5 B6 B7 B8 B1 B2 B3 B4 B5 B6 B7 B8 B1 B2 B3 B4 B5 B6 B7 B8
approx. 2 MHz DLCLK bursts
TLDCLK
TLD
TLDCLK
TLD
B1 B2 B3 B4 B5 B6 B7 B8 B1 B2 B3 B4 B5 B6 B7 B8 B1 B2 B3 B4 B5 B6 B7 B8
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15 ABSOLUTE MAXIMUM RATINGS
Maximum rating are the worst case limits that the device can withstand without
sustaining permanent damage. They are not indicative of normal mode operation
conditions.
Table 19: Absolute Maximum Ratings
Ambient Temperature under Bias
-40°C to +85°C
Storage Temperature
-40°C to +125°C
Supply Voltage
-0.3V to +4.6V
Bias Voltage (V BIAS)
(V DD - .3) to +5.5V
Voltage on Any Pin
-0.3V to V BIAS+0.3V
Static Discharge Voltage
±1000 V
Latch-Up Current
±100 mA
DC Input Current
±20 mA
Lead Temperature
+230°C
Absolute Maximum Junction
Temperature
+150°C
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16 D.C. CHARACTERISTICS
TA = -40°C to +85°C, V DD = 3.3V ±10%, V DD < BIAS < 5.5V
(Typical Conditions: T A = 25°C, V DD = 3.3V, V BIAS = 5V)
Table 20: D.C Characteristics
Symbol
Parameter
Min
Typ
Max
Units Conditions
VDD
Power Supply
2.97
3.3
3.63
Volts
BIAS
5V Tolerant Bias
VDD
5.0
5.5
Volts
VIL
Input Low Voltage
(TTL Only)
0
0.8
Volts
Guaranteed Input Low
voltage.
VPIL
Input Low Voltage
(PECL Only)
AVD
- 1.8
AVD
- 1.6
Volts
Guaranteed Input Low
voltage.
VIH
Input High
Voltage
(TTL Only)
2.0
Volts
Guaranteed Input High
voltage.
VPIH
Input HighLow
Voltage (PECL
Only)
AVD
AVD
–0.8
Volts
Guaranteed Input High
voltage.
0.4
Volts
Guaranteed output Low
voltage at VDD=2.97V and
IOL =maximum rated for
pad. Note 4.
–1.0
VOL
Output or Bidirectional Low
Voltage
VOH
Output or Bidirectional High
Voltage
2.4
Volts
Guaranteed output High
voltage at VDD=2.97V and
IOH =maximum rated
current for pad. Note 4.
VT+
Reset Input High
Voltage
2.0
Volts
Applies to RSTB and
TRSTB only.
VT-
Reset Input Low
Voltage
Volts
Applies to RSTB and
TRSTB only.
VTH
Reset Input
Hysteresis
Voltage
Volts
Applies to RSTB and
TRSTB only.
0.8
0.4
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IILPU
Input Low Current
-100
-50
-4
µA
VIL = GND. Notes 1 and 3.
IIHPU
Input High Current
-10
0
+10
µA
VIH = V DD. Notes 1 and 3.
IIL
Input Low Current
-10
0
+10
µA
VIL = GND. Notes 2 and 3.
IIH
Input High Current
-10
0
+10
µA
VIH = V DD. Notes 2 and 3.
IIL PECL
Input Low Current
-10
0
+100
µA
PECL inputs only. Note 3
IIH PECL
Input High Current -100
0
+10
µA
PECL inputs only. Note 3
CIN
Input Capacitance
5
pF
tA=25°C, f = 1 MHz
COUT
Output
Capacitance
5
pF
tA=25°C, f = 1 MHz
CIO
Bi-directional
Capacitance
5
pF
tA=25°C, f = 1 MHz
IDDOP1
Operating Current
350
530
mA
VDD = 3.63V for max, 3.3V
for typical, outputs
unloaded (ATM mode)
with TXC disabled
410
570
mA
VDD = 3.63V for max, 3.3V
for typical, outputs
unloaded (ATM mode)
with TXC enabled
560
720
mA
VDD = 3.63V for max, 3.3V
for typical, outputs
unloaded (POS mode)
with TXC disabled
620
770
mA
VDD = 3.63V for max, 3.3V
for typical, outputs
unloaded (POS mode)
with TXC enabled
(Case 1 including
all four channels)
IDDOP2
Operating Current
(Case 2 including
all four channels)
IDDOP3
Operating Current
(Case 3 including
all four channels)
IDDOP4
Operating Current
(Case 4 including
all four channels)
Notes on D.C. Characteristics:
1. Input pin or bi-directional pin with internal pull-up resistor.
2. Input pin or bi-directional pin without internal pull-up resistor
3. Negative currents flow into the device (sinking), positive currents flow out of
the device (sourcing).
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4. Refer to the footnotes at the bottom of the PIN DESCRIPTION table for the
DC current rating of each device output.
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17 MICROPROCESSOR INTERFACE TIMING CHARACTERISTICS
(TC = -40°C to +85°C, V DD = 3.3V ±10%)
Table 21: Microprocessor Interface Read Access (Figure 41)
Symbol
Parameter
Min
Max
Units
tSAR
Address to Valid Read Set-up Time
10
ns
tHA R
Address to Valid Read Hold Time
5
ns
tSALR
Address to Latch Set-up Time
10
ns
tHALR
Address to Latch Hold Time
10
ns
tVL
Valid Latch Pulse Width
5
ns
tSLR
Latch to Read Set-up
0
ns
tHLR
Latch to Read Hold
5
ns
tPRD
Valid Read to Valid Data Propagation Delay
70
ns
tZRD
Valid Read Negated to Output Tri-state
20
ns
tZINTH
Valid Read Negated to Output Tri-state
50
ns
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Figure 41: Microprocessor Interface Read Timing
tSAR
A[10:0]
Valid
Address
tHAR
tS ALR
tV L
tH ALR
ALE
tHLR
tS LR
(CSB+RDB)
tZ INTH
INTB
tZ RD
tPRD
D[7:0]
Valid Data
Notes on Microprocessor Interface Read Timing:
1. Output propagation delay time is the time in nanoseconds from the 1.4 Volt
point of the reference signal to the 1.4 Volt point of the output.
2. Maximum output propagation delays are measured with a 100 pF load on the
Microprocessor Interface data bus, (D[7:0]).
3. A valid read cycle is defined as a logical OR of the CSB and the RDB signals.
4. In non-multiplexed address/data bus architectures, ALE should be held high
so parameters tS ALR, tHALR, tV L , tS LR , and tH LR are not applicable.
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5. Parameter tHAR is not applicable if address latching is used.
6. When a set-up time is specified between an input and a clock, the set-up time
is the time in nanoseconds from the 1.4 Volt point of the input to the 1.4 Volt
point of the clock.
7. When a hold time is specified between an input and a clock, the hold time is
the time in nanoseconds from the 1.4 Volt point of the input to the 1.4 Volt
point of the clock.
Table 22: Microprocessor Interface Write Access (Figure 42)
Symbol
Parameter
Min
Max
Units
tSAW
Address to Valid Write Set-up Time
10
ns
tSDW
Data to Valid Write Set-up Time
20
ns
tSALW
Address to Latch Set-up Time
10
ns
tHALW
Address to Latch Hold Time
10
ns
tVL
Valid Latch Pulse Width
5
ns
tSLW
Latch to Write Set-up
0
ns
tHLW
Latch to Write Hold
5
ns
tH DW
Data to Valid Write Hold Time
5
ns
tHAW
Address to Valid Write Hold Time
5
ns
tVWR
Valid Write Pulse Width
40
ns
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Figure 42: Microprocessor Interface Write Timing
A[10:0]
Valid Address
tS ALW
tV L
tH ALW
tS LW
tHLW
ALE
tSAW
tVWR
tH AW
(CSB+WRB)
tS DW
D[7:0]
tH DW
Valid Data
Notes on Microprocessor Interface Write Timing:
1 A valid write cycle is defined as a logical OR of the CSB and the WRB
signals.
2 In non-multiplexed address/data bus architectures, ALE should be held high
so parameters tS ALW , tHALW , tV L, tS LW , and tH LW are not applicable.
3 Parameter tHAW is not applicable if address latching is used.
4 When a set-up time is specified between an input and a clock, the set-up time
is the time in nanoseconds from the 1.4 Volt point of the input to the 1.4 Volt
point of the clock.
5 When a hold time is specified between an input and a clock, the hold time is
the time in nanoseconds from the 1.4 Volt point of the input to the 1.4 Volt
point of the clock.
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18 A.C. TIMING CHARACTERISTICS
(TC = -40°C to +85°C, V DD = 3.3V ±10%)
18.1 System Reset Timing
Table 23: RSTB Timing (Figure 43)
Symbol
tVRSTB
Description
RSTB Pulse Width
Min
100
Max
Units
ns
Min
Max
Units
19.44
19.44
MHz
REFCLK Duty Cycle
30
70
%
REFCLK Frequency Tolerance
-50
+50
ppm
Figure 43: RSTB Timing Diagram
tV RSTB
RSTB
18.2 Reference Timing
Line Side Reference Clock
Symbol
Description
REFCLK Nominal Frequency
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18.3 ATM System Interface Timing
Table 24: Transmit ATM System Interface Timing (Figure 44)
Symbol
f TFCLK
Description
TFCLK Frequency
Min
Max
50
Units
MHz
DTFCLK
TFCLK Duty Cycle
40
60
%
tSTENB
TENB Set-up time to TFCLK
3
ns
tH TENB
TENB Hold time to TFCLK
0
ns
tSTADR
TADR[4:0] Set-up time to TFCLK
3
ns
tH TADR
TADR[4:0] Hold time to TFCLK
0
ns
tSTDAT
TDAT[15:0] Set-up time to TFCLK
3
ns
tH TDAT
TDAT[15:0] Hold time to TFCLK
0
ns
tSTPRTY
TPRTY Set-up time to TFCLK
3
ns
tH TPRTY
TPRTY Hold time to TFCLK
0
ns
tSTSOC
TSOC Set-up time to TFCLK
3
ns
tH TSOC
TSOC Hold time to TFCLK
0
ns
tPDTCA
TFCLK High to DTCA[4:1] Valid
1
12
ns
tPTCA
TFCLK High to TCA Valid
1
12
ns
tZTCA
TFCLK High to TCA Tri-state
1
10
ns
tZB TCA
TFCLK High to TCA Driven
0
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Figure 44: Transmit ATM System Interface Timing Diagram
TFCLK
tS
TFC LK
tH
T FC LK
TENB
tS
T FC LK
tH
T FC LK
TDAT[15:0]
tS
tH
tS
tH
T FC LK
T FC LK
TPRTY
T FC LK
T FC LK
TSOC
tP DTC A,
TC A
DTCA[x]/TCA
tZ TC A
TCA
tZB TC A
TCA
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Table 25: Receive ATM System Interface Timing (Figure 45)
Symbol
Description
Min
Max
Units
50
MHz
60
%
fRFCLK
RFCLK Frequency
DRFCLK
RFCLK Duty Cycle
40
tSRENB
RENB Set-up time to RFCLK
3
ns
tH RENB
RENB Hold time to RFCLK
0
ns
tSRADR
RADR[4:0] Set-up time to RFCLK
3
ns
tH RADR
RADR[4:0] Hold time to RFCLK
0
ns
tPRDAT
RFCLK High to RDAT Valid
1
12
ns
tZRDAT
RFCLK High to RDAT Tri-state
1
12
ns
tZB RDAT
RFCLK High to RDAT Driven
0
tPRSOC
RFCLK High to RSOC Valid
1
12
ns
tZRSOC
RFCLK High to RSOC Tri-state
1
12
ns
tZB RSOC
RFCLK High to RSOC Driven
0
tPRPRTY
RFCLK High to RPRTY Valid
1
12
ns
tZRPRTY
RFCLK High to RPRTY Tri-state
1
12
ns
tZB RPRTY
RFCLK High to RPRTY Driven
0
tPRCA
RFCLK High to RCA Valid
1
12
ns
tZRCA
RFCLK High to RCA Tri-state
1
12
ns
tZB RCA
RFCLK High to RCA Driven
0
tPDRCA
RFCLK High to DRCA[4:1] Valid
1
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ns
ns
12
356
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Figure 45: Receive ATM System Interface Timing Diagram
RFCLK
tS RA D R
tH RA DR
RE N B
RE N B
RADR[4:0]
RENB
tP RDA T, RSO C,
RPR TY
RDAT[15:0]
RXPRTY
RSOC
tZ RDA T, RSO C,
RPR TY
RDAT[15:0]
RXPRTY
RSOC
tZB RDAT, RSOC ,
RPRTY
RDAT[15:0]
RXPRTY
RSOC
tP D RC A
DRCA[4:1]
tP R CA
RCA
tZR CA
RCA
tZB
R CA
RCA
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18.4 POS System Interface Timing
Table 26: Transmit POS System Interface Timing (Figure 46)
Symbol
f TFCLK
Description
TFCLK Frequency
Min
Max
50
Units
MHz
DTFCLK
TFCLK Duty Cycle
40
60
%
tSTENB
TENB Set-up time to TFCLK
3
ns
tH TENB
TENB Hold time to TFCLK
0
ns
tSTADR
TADR[4:0] Set-up time to TFCLK
3
ns
tH TADR
TADR[4:0] Hold time to TFCLK
0
ns
tSTDAT
TDAT[15:0] Set-up time to TFCLK
3
ns
tH TDAT
TDAT[15:0] Hold time to TFCLK
0
ns
tSTPRTY
TPRTY Set-up time to TFCLK
3
ns
tH TPRTY
TPRTY Hold time to TFCLK
0
ns
tSTSOP
TSOP Set-up time to TFCLK
3
ns
tH TSOP
TSOP Hold time to TFCLK
0
ns
tSTEOP
TEOP Set-up time to TFCLK
3
ns
tH TEOP
TEOP Hold time to TFCLK
0
ns
tSTMOD
TMOD Set-up time to TFCLK
3
ns
tH TMOD
TMOD Hold time to TFCLK
0
ns
tSTERR
TERR Set-up time to TFCLK
3
ns
tH TERR
TERR Hold time to TFCLK
0
ns
tPDTPA
TFCLK High to DTPA[4:1] Valid
1
12
ns
tPPTPA
TFCLK High to PTPA Valid
1
12
ns
tZPTPA
TFCLK High to PTPA Tri-state
1
10
ns
tZBPTPA
TFCLK High to PTPA Driven
0
tPSTPA
TFCLK High to STPA Valid
1
12
ns
tZSTPA
TFCLK High to STPA Tri-state
1
10
ns
tZBSTPA
TFCLK High to STPA Driven
0
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ns
ns
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Figure 46: Transmit POS System Interface Timing
TFCLK
tS TADR
TADR[4:0]
TENB
TDAT[15:0]
TPRTY
TSOP
TEOP
TMOD
TERR
TENB
TDAT
TPRTY
TSOP
TEOP
TMOD
TERR
tHTADR
TENB
TDAT
TPR TY
TSOP
TEOP
TMOD
TERR
tP DTPA,
PTPA,
STPA
DTPA[x]
PTPA
STPA
tZ PTPA,
STPA
PTPA
STPA
tZB PTPA,
STPA
PTPA
STPA
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Table 27: Receive POS System Interface Timing (Figure 47)
Symbol
Description
Min
Max
Units
50
MHz
60
%
fRFCLK
RFCLK Frequency
DRFCLK
RFCLK Duty Cycle
40
tSRENB
RENB Set-up time to RFCLK
3
ns
tH RENB
RENB Hold time to RFCLK
0
ns
tSRADR
RADR[4:0] Set-up time to RFCLK
3
ns
tH RADR
RADR[4:0] Hold time to RFCLK
0
ns
tPRDAT
RFCLK High to RDAT Valid
1
12
ns
tZRDAT
RFCLK High to RDAT Tri-state
1
12
ns
tZB RDAT
RFCLK High to RDAT Driven
0
tPRPRTY
RFCLK High to RPRTY Valid
1
12
ns
tZRPRTY
RFCLK High to RPRTY Tri-state
1
12
ns
tZB RPRTY
RFCLK High to RPRTY Driven
0
tPRSOP
RFCLK High to RSOP Valid
1
12
ns
tZRSOP
RFCLK High to RSOPTri-state
1
12
ns
tZB RSOP
RFCLK High to RSOP Driven
0
tPREOP
RFCLK High to REOP Valid
1
12
ns
tZREOP
RFCLK High to REOPTri-state
1
12
ns
tZB REOP
RFCLK High to REOP Driven
0
tPRMOD
RFCLK High to RMOD Valid
1
12
ns
tZRMOD
RFCLK High to RMODTri-state
1
12
ns
tZB RMOD
RFCLK High to RMOD Driven
0
tPRERR
RFCLK High to RERR Valid
1
12
ns
tZRERR
RFCLK High to RERR Tri-state
1
12
ns
tZB RERR
RFCLK High to RERR Driven
0
tPRVAL
RFCLK High to RVAL Valid
1
12
ns
tZRVAL
RFCLK High to RVAL Tri-state
1
12
ns
tZBPVAL
RFCLK High to RVAL Driven
0
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ns
ns
ns
ns
ns
ns
ns
360
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tPRPA
RFCLK High to PRPA Valid
1
12
ns
tZRPA
RFCLK High to PRPA Tri-state
1
12
ns
tZB RPA
RFCLK High to PRPA Driven
0
tPDRPA
RFCLK High to DRPA Valid
1
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ns
12
361
ns
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Figure 47: Receive POS System Interface Timing
RFCLK
tS R A DR
tH RA D R
R E NB
RE N B
RADR[4:0]
RENB
tP RDA T, RS OP,
R P RTY, RE OP,
RMO D , R ERR,
R V AL
tZ
RDAT[15:0 ]
RXPRTY
RSOP
REOP
RMOD
RERR
RVAL
RDAT, R S OP,
RPRTY, R E OP,
RMOD, RERR ,
RV A L
tZB
RDAT, R S OP,
RPRTY, R E OP,
RMOD, R ERR ,
RV AL
tP DR PA
DRPA[4:1]
tP P RPA
PRPA
tZP R PA
PRPA
tZB
PR PA
PRPA
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18.5 Line and Section DCC Timing
Table 28: Section DCC Timing (Figure 48)
Symbol
tSTSD
Description
TSD Set-up Time to TSDCLK
tH TSD
TSD Hold Time to TSDCLK
tPRSD
Min
25
Max
25
RSDCLK Low to RSD Valid
-15
ns
5
Figure 48: Section DCC Timing Diagram
T S D C LK
tS
TSD
tH
TSD
TSD
RSDCLK
tP RS D
RSD
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Units
ns
363
ns
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Table 29: Line DCC Timing (Figure 49)
Symbol
Description
Min
tSTLD
TLD Set-up Time to TLDCLK
25
ns
tH TLD
TLD Hold Time to TLDCLK
25
ns
tPRLD
RLDCLK Low to RLD Valid
-15
Max
5
Figure 49: Line DCC Timing Diagram
TLD CLK
tS
TL D
tH
TL D
TL D
RLDCLK
tP RL D
RLD
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364
Units
ns
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18.6 Transmit and Receive Frame Pulses
Table 30: Transmit and Receive Frame Pulse Timing (Figure 50)
Symbol
tSTFPI
Description
TFPI Set-up Time to TCLK High
tH TFPI
TFPI Hold Time to TCLK High
Min
15
Max
0
Units
ns
ns
tPTFPO
TCLK High to TFPO Valid
0
10
ns
tPRFPO
RCLK1-4 High to RFPO1-4 Valid
0
10
ns
Figure 50: Transmit and Receive Frame Pulses
TC LK
tS
TF PI
tH
TF PI
TFP I
tP TFPO
TFPO
RCLK1-4
tP RF PO
RFPO1-4
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18.7 Transmit Line Timing in Sincle Ended TXD/TXC Mode
Table 31: Line Side Transmit Timign (TXC_OE=1 Only) (Figure 51)
Symbol
tPTXD
Description
TXC+/- Falling to TXD+/- Valid
Min
-2
Max
2
Units
ns
Figure 51: Line Side Transmit Timing Diagram (TXC_OE=1)
TXC+/tP
TXD
TXD+/-
18.8 JTAG Test Port Timing
Table 32: JTAG Port Interface (Figure 52)
Symbol
Description
Min
TCK Frequency
Max
Units
1
MHz
60
%
TCK Duty Cycle
40
tSTMS
TMS Set-up time to TCK
50
ns
tHTMS
TMS Hold time to TCK
50
ns
tSTDI
TDI Set-up time to TCK
50
ns
tHTDI
TDI Hold time to TCK
50
ns
tPTDO
TCK Low to TDO Valid
2
tVTRSTB
TRSTB Pulse Width
100
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
50
ns
ns
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Figure 52: JTAG Port Interface Timing
TCK
tS TMS
tH TMS
tS TDI
tH TDI
TMS
TDI
TCK
tP TDO
TDO
tV TRSTB
TRSTB
Notes on Input Timing:
1. When a set-up time is specified between an input and a clock, the set-up time
is the time in nanoseconds from the 1.4 Volt point of the input to the 1.4 Volt
point of the clock.
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2. When a hold time is specified between an input and a clock, the hold time is
the time in nanoseconds from the 1.4 Volt point of the clock to the 1.4 Volt
point of the input.
Notes on Output Timing:
1. Output propagation delay time is the time in nanoseconds from the 1.4 Volt
point of the reference signal to the 1.4 Volt point of the output.
2. Maximum output propagation delays are measured with a 50 pF load on the
outputs with the exception of the RDAT[15:0], RPRTY, RSOC/RSOP, REOP,
RMOD, RERR, RCA/PRPA, DRCA[4:1]/DRPA[4:1], TCA/PTPA, STPA,
DTCA[4:1]/DTPA[4:1] for which propagation delays are measured with a
30 pF load.
3. Output propagation delay time for TXD+/- relative to TXC+/- is based on a
differential voltage for which the signal transition time is defined at the
moment at which the positive and negative voltages are equal.
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19 ORDERING AND THERMAL INFORMATION
Table 33: Ordering Information
PART NO.
PM5351-BI
DESCRIPTION
304-pin Ball Grid Array (SBGA)
Table 34: Thermal Information
PART NO.
PM5351-BI
AMBIENT TEMPERATURE
-40°C to 85°C
Theta Ja
22 °C/W
Theta Jc
1 °C/W
30
25
20
15
10
5
0
Conv
100
200
Dense Board
300
400
500
JEDEC Board
The junction temperature (Tj) is less than 105°C for a ambient temperature (Ta) of
60°C and a 300LFM of airflow. The device must operate at Ta=70°C with 100LFM
and must not be damaged with Ta=70°C and no airflow. This assumes a dense
board and a ThetaJA of 16.
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Loaded power at 3.63V POS mode, with TXC pins enable, mean = 2.83W
Loaded power at 3.63V POS mode, with TXC pins enable, mean + 2 sigma = 2.89W
The junction temperature = 105°C.
Therefore, the package is approved for use without enhanced cooling.
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20 MECHANICAL INFORMATION
Figure 53:- Mechanical Drawing 304 Pin Super Ball Grid Array (SBGA)
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NOTES
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CONTACTING PMC-SIERRA, INC.
PMC-Sierra, Inc.
105-8555 Baxter Place Burnaby, BC
Canada V5A 4V7
Tel:
(604) 415-6000
Fax:
(604) 415-6200
Document Information:
Corporate Information:
Application Information:
Web Site:
[email protected]
[email protected]
[email protected]
http://www.pmc-sierra.com
None of the information contained in this document constitutes an express or implied warranty by PMC -Sierra, Inc. as to the sufficiency, fitness or
suitability for a particular purpose of any such information or the fitness, or suitability for a particular purpose, merchantability, performance,
compatibility with other parts or systems, of any of the products of PMC -Sierra, Inc., or any portion thereof, referred to in this document.
PMC-Sierra, Inc. expressly disclaims all representations and warranties of any kind regarding the contents or use of the information, including, but not
limited to, express and implied warranties of accuracy, completeness, merchantability, fitness for a particular use, or non-infringement.
In no event will PMC -Sierra, Inc. be liable for any direct, indirect, special, incidental or consequential damages, including, but not limited to, lost profits,
lost business or lost data resulting from any use of or reliance upon the information, whether or not PMC -Sierra, Inc. has been advised of the possibility
of such damage.
© 1997, 1998, 1999, 2000 PMC-Sierra, Inc.
PMC-971240 (R7) ref PMC-971028 (R7)
PMC-Sierra, Inc..
.415.6000
Issue date: February 2000
105 - 8555 Baxter Place Burnaby, BC Canada V5A 4V7