PM7349 S/UNI®-4xD3F PMC-Sierra,Inc. Quad J2, E3 and DS-3 Framer FEATURES • Quad DS-3, E3 (G.751 and G.832), and J2 framers. • Each channel can be independently configured to be a DS-3, E3, or J2 Framer. • Gapped transmit and receive clocks can be optionally generated for interface to devices which only need access to payload data bits. • Provides programmable pseudorandom test pattern generation, detection, and analysis features. • Provides integral transmit and receive HDLC controllers with 128-byte FIFO depths. • Provides performance monitoring counters suitable for accumulation periods of up to 1 second. • Provides an 8-bit microprocessor interface for configuration, control and status monitoring. • Provides a standard five signal P1149.1 JTAG test port for boundary scan board test purposes. • Low power 3.3 V CMOS technology with 5 V tolerant inputs. • Available in a high density 256-pin SBGA package (27 mm x 27 mm). • RECEIVER SECTION • Provides frame synchronization for the M23 or C-bit parity DS3 applications, alarm detection, and accumulates line code violations, framing errors, parity errors, path parity errors and FEBE events. In addition, far end alarm channel codes are detected, and an integral HDLC receiver is provided to terminate the path maintenance data link. • Provides frame synchronization for the G.751 or G.832 E3 applications, alarm detection, and accumulates line code violations, framing errors, parity errors, and FEBE events. In addition, in G.832, the Trail Trace is detected, and an integral HDLC receiver is provided to terminate either the Network • • • Requirement or the General Purpose data link. Provides frame synchronization for G.704 and NTT 6.312 Mbit/s J2 applications, alarm detection, and accumulates line code violations, framing errors, and CRC parity errors. An integral HDLC receiver is provided to terminate the data link. Provides a receive HDLC controller with a 128-byte FIFO to accumulate data link information. Provides detection of yellow alarm and loss of frame (LOF), and accumulates BIP-8 errors, framing errors and FEBE events. Provides programmable pseudorandom test-sequence detection (up to 232-1 bit length patterns conforming to ITU-T O.151 standards) and analysis features. TRANSMITTER SECTION • Provides frame insertion for the M23 or C-bit parity DS3 applications, alarm Line Decode FRMR J2, E3, or DS3 Receive Framer RDLC Rx HDLC PMON Perf. Monitor Rx O/H Access ROH [4:1] ROHCLK [4:1] ROHPF [4:1] RBOC Rx FEAC PMC-2000369 (R2) TRSTB TMS TCK TDI TDO Microprocessor I/F 1/2 TTB Rx Trail Buffer PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE RSTB INTB TRAN J2, E3, or DS3 Transmit Framer CSB WRB RDB Line Encode D[7:0] RNEG/RLCV[4:1] IEEE P1149.1 JTAG Test Access Port 1/2 TTB Tx Trail Buffer A[10:0] ALE RCLK[4:1] RPOS/RDATI[4:1] Tx O/H Access PRGD BER Tester TPOS/TDATO[4:1] TNEG/TOHM[4:1] TCLK[4:1] TDPR Tx HDLC RDATO [4:1] ROVRHD [4:1] FRMSTAT[4:1] RSCLK/RGAPCLK[4:1] REF8KD/RFPO/ RMFOP[4:1] XBOC Tx FEAC TFPO/TMFPO/ TGAPCLK[4:1] TOHINS[4:1] TOH[4:1] TOHCLK[4:1] TOHFP[4:1] TDAT[4:1] TFPI/TMFP[4:1] TICLK[4:1] BLOCK DIAGRAM © Copyright PMC-Sierra, Inc. 2000 PM7349 S/UNI®-4xD3F Quad J2, E3 and DS-3 Framer insertion, and diagnostic features. In addition, far end alarm channel codes may be inserted, and an integral HDLC transmitter is provided to insert the path maintenance data link. • Provides frame insertion for the G.751 or G.832 E3 applications, alarm insertion, and diagnostic features. In addition, for G.832, the Trail Trace is inserted, and an integral HDLC transmitter is provided to insert either the Network Requirement or the General Purpose data link. • Provides frame insertion for G.704 6.312 Mbit/s J2 applications, alarm insertion, and diagnostic features. An integral HDLC transmitter is provided to insert the path maintenance data link. • Provides a transmit HDLC controller with a 128-byte FIFO. • Provides programmable pseudorandom test sequence generation (up to 232-1 bit length sequences conforming to ITU-T O.151 standards). Diagnostic abilities include single bit error insertion or error insertion at bit error rates ranging from 10-1 to 10-7. LOOPBACK FEATURES • Provides for diagnostic loopbacks, line loopbacks, and payload loopbacks. APPLICATIONS • SONET/SDH Mux E3/DS-3 Tributary Interfaces. • PDH Mux J2/E3/DS-3 Line Interfaces. • DS-3/E3/J2 Digital Cross Connect Interfaces. • DS-3/E3/J2 PPP Internet Access Interfaces. • DS-3/E3/J2 Frame Relay Interfaces. TYPICAL APPLICATIONS FRAME RELAY SWITCH/ROUTER UPLINK SIDE ACCESS SIDE PM4388 TOCTL PCI Bus PM4314 QDSX PCI Bus 8 Port Channelized T1 Card PM7366 FREEDM-8 IP Switch/Router Core Unchannelized DS-3/E3/J2 Card DS-3/E3/J2 LIU PM7366 FREEDM-8 DS-3/E3/J2 LIU PM7349 S/UNI-4xD3F DS-3/E3/J2 LIU 4 Port Channelized E1 Card Switch Fabric PM4314 QDSX PM6344 EQUAD PM7366 FREEDM-8 DS-3/E3/J2 LIU 28 Port Unchannelized T1 Card (M13) PM4388 TOCTL DS-3 LIU Egress Device Packet-Over-SONET Card (3 DS-3s Over OC-3) PM7322 RCMP-800 PM7364 FREEDM-32 PM7366 FREEDM-8 PM7349 S/UNI-4xD3F PM7366 FREEDM-8 PM8313 D3MX PM5342 SPECTRA-155 Optics WIRELESS BASE STATION APPLICATION Public Switched Telephone Network DS-3 or Fibre Optics Switch PM7349 Fabric S/UNI-4xD3F or PM5342 SPECTRA-155 PM7349 S/UNI-4xD3F Base Station Controller Head Office: PMC-Sierra, Inc. #105 - 8555 Baxter Place Burnaby, B.C. V5A 4V7 Canada Tel: 604.415.6000 Fax: 604.415.6200 To order documentation, send email to: [email protected] or contact the head office, Attn: Document Coordinator DS-3/E3/J2 LIU DS-3/E3/J2 LIU DS-3/E3/J2 LIU DS-3/E3/J2 LIU DS-3/E3/J2 LIU DS-3/E3/J2 LIU DS-3/E3/J2 LIU DS-3/E3/J2 LIU PM7349 S/UNI-4xD3F Tx/Rx RF Subsystem µP CDMA/TDMA/GSM Base Transceiver Station All product documentation is available on our web site at: http://www.pmc-sierra.com For corporate information, send email to: [email protected] PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE PMC-2000369 (R2) © Copyright PMC-Sierra, Inc. 2000. All rights reserved. July 2000 S/UNI is a registered trademark of PMC-Sierra, Inc.