SN54HC02, SN74HC02 QUADRUPLE 2-INPUT POSITIVE-NOR GATES SCLS076E – DECEMBER 1982 – REVISED AUGUST 2003 D D D Wide Operating Voltage Range of 2 V to 6 V Outputs Can Drive Up To 10 LSTTL Loads Low Power Consumption, 20-µA Max ICC D D D Typical tpd = 8 ns ±4-mA Output Drive at 5 V Low Input Current of 1 µA Max SN54HC02 . . . FK PACKAGE (TOP VIEW) 1 14 2 13 3 12 4 11 5 10 6 9 7 8 VCC 4Y 4B 4A 3Y 3B 3A 1B NC 2Y NC 2A 4 3 2 1 20 19 18 5 17 6 16 7 15 8 14 9 10 11 12 13 4B NC 4A NC 3Y 2B GND NC 3A 3B 1Y 1A 1B 2Y 2A 2B GND 1A 1Y NC VCC 4Y SN54HC02 . . . J OR W PACKAGE SN74HC02 . . . D, DB, N, NS, OR PW PACKAGE (TOP VIEW) NC – No internal connection description/ordering information The ’HC02 devices contain four independent 2-input NOR gates. They perform the Boolean function Y = A + B or Y = A • B in positive logic. ORDERING INFORMATION PACKAGE† TA PDIP – N SOIC – D –40°C –40 C to 85 85°C C Tube of 25 SN74HC02N Tube of 50 SN74HC02D Reel of 2500 SN74HC02DR TOP-SIDE MARKING SN74HC02N HC02 Reel of 250 SN74HC02DT SOP – NS Reel of 2000 SN74HC02NSR HC02 SSOP – DB Reel of 2000 SN74HC02DBR HC02 Tube of 90 SN74HC02PW Reel of 2000 SN74HC02PWR Reel of 250 SN74HC02PWT CDIP – J Tube of 25 SNJ54HC02J SNJ54HC02J CFP – W Tube of 150 SNJ54HC02W SNJ54HC02W LCCC – FK Tube of 55 SNJ54HC02FK TSSOP – PW –55°C 125°C –55 C to 125 C ORDERABLE PART NUMBER HC02 SNJ54HC02FK † Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 2003, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. On products compliant to MIL-PRF-38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SN54HC02, SN74HC02 QUADRUPLE 2-INPUT POSITIVE-NOR GATES SCLS076E – DECEMBER 1982 – REVISED AUGUST 2003 FUNCTION TABLE (each gate) INPUTS A OUTPUT Y B H X L X H L L L H logic diagram (positive logic) A Y B absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V Input clamp current, IIK (VI < 0 or VI > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Output clamp current, IOK (VO < 0 or VO > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Package thermal impedance, θJA (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86°C/W DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96°C/W N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80°C/W NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76°C/W PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51-7. recommended operating conditions (see Note 3) SN54HC02 VCC VIH Supply voltage High-level input voltage VCC = 2 V VCC = 4.5 V VCC = 6 V VCC = 2 V VIL Low-level input voltage VI VO Input voltage ∆t/∆v t/ v NOM MAX 2 5 6 MIN NOM MAX 2 5 6 1.5 1.5 3.15 3.15 4.2 VCC = 4.5 V VCC = 6 V 0 VCC = 2 V VCC = 4.5 V UNIT V V 4.2 0.5 0.5 1.35 1.35 1.8 0 Output voltage Input transition rise/fall time SN74HC02 MIN VCC VCC V 1.8 0 0 VCC VCC 1000 1000 500 500 V V ns VCC = 6 V 400 400 TA Operating free-air temperature –55 125 –40 85 °C NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN54HC02, SN74HC02 QUADRUPLE 2-INPUT POSITIVE-NOR GATES SCLS076E – DECEMBER 1982 – REVISED AUGUST 2003 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC IOH = –20 µA A VOH VI = VIH or VIL IOH = –4 mA IOH = –5.2 mA IOL = 20 µA A VOL VI = VIH or VIL IOL = 4 mA IOL = 5.2 mA II ICC VI = VCC or 0 VI = VCC or 0, IO = 0 MIN TA = 25°C TYP MAX SN74HC02 MIN MIN MAX 2V 1.9 1.998 1.9 1.9 4.5 V 4.4 4.499 4.4 4.4 6V 5.9 5.999 5.9 5.9 4.5 V 3.98 4.3 3.7 3.84 6V 5.48 5.8 5.2 MAX UNIT V 5.34 2V 0.002 0.1 0.1 0.1 4.5 V 0.001 0.1 0.1 0.1 6V 0.001 0.1 0.1 0.1 4.5 V 0.17 0.26 0.4 0.33 6V 0.15 0.26 0.4 0.33 6V ±0.1 ±100 ±1000 ±1000 nA 2 40 20 µA 3 10 10 10 pF 6V Ci SN54HC02 2 V to 6 V V switching characteristics over recommended operating free-air temperature range, CL = 50 pF (unless otherwise noted) (see Figure 1) TA = 25°C TYP MAX SN54HC02 SN74HC02 MIN MIN PARAMETER FROM (INPUT) TO (OUTPUT) VCC 2V 45 90 135 115 tpd A or B Y 4.5 V 9 18 27 23 6V 8 15 23 20 tt Y MIN MAX MAX 2V 38 75 110 95 4.5 V 8 15 22 19 6V 6 13 19 16 UNIT ns ns operating characteristics, TA = 25°C PARAMETER Cpd TEST CONDITIONS Power dissipation capacitance per gate POST OFFICE BOX 655303 No load • DALLAS, TEXAS 75265 TYP 22 UNIT pF 3 SN54HC02, SN74HC02 QUADRUPLE 2-INPUT POSITIVE-NOR GATES SCLS076E – DECEMBER 1982 – REVISED AUGUST 2003 PARAMETER MEASUREMENT INFORMATION From Output Under Test Test Point Input VCC 50% 50% 0V CL = 50 pF (see Note A) tPLH In-Phase Output LOAD CIRCUIT 50% 10% tPHL 90% 90% tr Input 50% 10% 90% 90% tr tPHL VCC 50% 10% 0 V Out-of-Phase Output 90% tf VOH 50% 10% VOL tf tPLH 50% 10% tf 50% 10% 90% VOH VOL tr VOLTAGE WAVEFORMS PROPAGATION DELAY AND OUTPUT TRANSITION TIMES VOLTAGE WAVEFORM INPUT RISE AND FALL TIMES NOTES: A. CL includes probe and test-fixture capacitance. B. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 6 ns, tf = 6 ns. C. The outputs are measured one at a time with one input transition per measurement. D. tPLH and tPHL are the same as tpd. Figure 1. Load Circuit and Voltage Waveforms 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PACKAGE OPTION ADDENDUM www.ti.com 12-Jan-2006 PACKAGING INFORMATION Orderable Device Status (1) Package Type 5962-8404101VCA ACTIVE CDIP J 14 1 TBD Call TI N / A for Pkg Type 5962-8404101VDA ACTIVE CFP W 14 1 TBD Call TI N / A for Pkg Type Package Drawing Pins Package Eco Plan (2) Qty Lead/Ball Finish MSL Peak Temp (3) 84041012A ACTIVE LCCC FK 20 1 TBD Call TI N / A for Pkg Type 8404101CA ACTIVE CDIP J 14 1 TBD Call TI N / A for Pkg Type 8404101DA ACTIVE CFP W 14 1 TBD Call TI N / A for Pkg Type JM38510/65101B2A ACTIVE LCCC FK 20 1 TBD Call TI N / A for Pkg Type JM38510/65101BCA ACTIVE CDIP J 14 1 TBD Call TI N / A for Pkg Type JM38510/65101BDA ACTIVE CFP W 14 1 TBD Call TI N / A for Pkg Type N / A for Pkg Type SN54HC02J ACTIVE CDIP J 14 1 TBD Call TI SN74HC02D ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU SN74HC02DBLE OBSOLETE SSOP DB 14 SN74HC02DBR ACTIVE SSOP DB 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74HC02DBRE4 ACTIVE SSOP DB 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74HC02DE4 ACTIVE SOIC D 14 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74HC02DR ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74HC02DRE4 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74HC02DRG4 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74HC02DT ACTIVE SOIC D 14 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74HC02DTE4 ACTIVE SOIC D 14 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74HC02N ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type TBD Call TI 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type TBD 50 Call TI Level-1-260C-UNLIM Call TI SN74HC02N3 OBSOLETE PDIP N 14 SN74HC02NE4 ACTIVE PDIP N 14 SN74HC02NSR ACTIVE SO NS 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74HC02NSRG4 ACTIVE SO NS 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74HC02PW ACTIVE TSSOP PW 14 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74HC02PWE4 ACTIVE TSSOP PW 14 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74HC02PWG4 ACTIVE TSSOP PW 14 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74HC02PWLE OBSOLETE TSSOP PW 14 SN74HC02PWR ACTIVE TSSOP PW 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74HC02PWRE4 ACTIVE TSSOP PW 14 2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM TBD Addendum-Page 1 Call TI Call TI Call TI PACKAGE OPTION ADDENDUM www.ti.com 12-Jan-2006 Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty SN74HC02PWRG4 ACTIVE TSSOP PW 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74HC02PWT ACTIVE TSSOP PW 14 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74HC02PWTE4 ACTIVE TSSOP PW 14 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SNJ54HC02FK ACTIVE LCCC FK 20 1 TBD Call TI N / A for Pkg Type SNJ54HC02J ACTIVE CDIP J 14 1 TBD Call TI N / A for Pkg Type SNJ54HC02W ACTIVE CFP W 14 1 TBD Call TI N / A for Pkg Type SNV54HC02J ACTIVE CDIP J 14 TBD Call TI Call TI SNV54HC02W ACTIVE CFP W 14 TBD Call TI Call TI Lead/Ball Finish MSL Peak Temp (3) no Sb/Br) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 MECHANICAL DATA MLCC006B – OCTOBER 1996 FK (S-CQCC-N**) LEADLESS CERAMIC CHIP CARRIER 28 TERMINAL SHOWN 18 17 16 15 14 13 NO. OF TERMINALS ** 12 19 11 20 10 A B MIN MAX MIN MAX 20 0.342 (8,69) 0.358 (9,09) 0.307 (7,80) 0.358 (9,09) 28 0.442 (11,23) 0.458 (11,63) 0.406 (10,31) 0.458 (11,63) 21 9 22 8 44 0.640 (16,26) 0.660 (16,76) 0.495 (12,58) 0.560 (14,22) 23 7 52 0.739 (18,78) 0.761 (19,32) 0.495 (12,58) 0.560 (14,22) 24 6 68 0.938 (23,83) 0.962 (24,43) 0.850 (21,6) 0.858 (21,8) 84 1.141 (28,99) 1.165 (29,59) 1.047 (26,6) 1.063 (27,0) B SQ A SQ 25 5 26 27 28 1 2 3 4 0.080 (2,03) 0.064 (1,63) 0.020 (0,51) 0.010 (0,25) 0.020 (0,51) 0.010 (0,25) 0.055 (1,40) 0.045 (1,14) 0.045 (1,14) 0.035 (0,89) 0.045 (1,14) 0.035 (0,89) 0.028 (0,71) 0.022 (0,54) 0.050 (1,27) 4040140 / D 10/96 NOTES: A. B. C. D. E. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. This package can be hermetically sealed with a metal lid. The terminals are gold plated. Falls within JEDEC MS-004 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MECHANICAL DATA MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001 DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE 28 PINS SHOWN 0,38 0,22 0,65 28 0,15 M 15 0,25 0,09 8,20 7,40 5,60 5,00 Gage Plane 1 14 0,25 A 0°–ā8° 0,95 0,55 Seating Plane 2,00 MAX 0,10 0,05 MIN PINS ** 14 16 20 24 28 30 38 A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90 A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12,30 DIM 4040065 /E 12/01 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. Falls within JEDEC MO-150 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MECHANICAL DATA MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999 PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 14 PINS SHOWN 0,30 0,19 0,65 14 0,10 M 8 0,15 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 1 7 0°– 8° A 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 8 14 16 20 24 28 A MAX 3,10 5,10 5,10 6,60 7,90 9,80 A MIN 2,90 4,90 4,90 6,40 7,70 9,60 DIM 4040064/F 01/97 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. Falls within JEDEC MO-153 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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