TRS202E www.ti.com SLLS847C – JULY 2007 – REVISED MAY 2010 5-V DUAL RS-232 LINE DRIVER/RECEIVER WITH ±15-kV ESD PROTECTION Check for Samples: TRS202E FEATURES 1 • • • • • • IEC61000-4-2 (Level 4) ESD Protection for RS-232 Bus Pins – ±8-kV Contact Discharge – ±15-k-V Air-Gap Discharge – ±15-kV Human-Body Model Meets or Exceeds the Requirements of TIA/EIA-232-F and ITU v.28 Standards Operates at 5-V VCC Supply Operates Up To 120 kbit/s External Capacitors . . . 4 × 0.1 mF or 4 × 1 mF Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II APPLICATIONS • • • • • • Battery-Powered Systems PDAs Notebooks Laptops Palmtop PCs Hand-Held Equipment D, DW, N, OR PW PACKAGE (TOP VIEW) C1+ V+ C1C2+ C2VDOUT2 RIN2 1 16 2 15 3 14 4 13 5 12 6 11 7 10 8 9 VCC GND DOUT1 RIN1 ROUT1 DIN1 DIN2 ROUT2 DESCRIPTION/ORDERING INFORMATION The TRS202E device consists of two line drivers, two line receivers, and a dual charge-pump circuit. TRS202E has IEC61000-4-2 (Level 4) ESD protection pin-to-pin (serial-port connection pins, including GND). The device meets the requirements of TIA/EIA-232-F and provides the electrical interface between an asynchronous communication controller and the serial-port connector. The charge pump and four small external capacitors allow operation from a single 5-V supply. The device operates at data signaling rates up to 120 kbit/s and a maximum of 30-V/ms driver output slew rate. The TRS202E can work with both 0.1-mF or 1-mF external capacitors. 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2007–2010, Texas Instruments Incorporated TRS202E SLLS847C – JULY 2007 – REVISED MAY 2010 www.ti.com ORDERING INFORMATION TA PACKAGE PDIP – N SOIC – D 0°C to 70°C SOIC – DW TSSOP – PW PDIP – N SOIC – D –40°C to 85°C SOIC – DW TSSOP – PW (1) (2) (1) (2) ORDERABLE PART NUMBER Tube of 25 TRS202ECN Tube of 40 TRS202ECD Reel of 2500 TRS202ECDR Tube of 40 TRS202ECDW Reel of 2000 TRS202ECDWR Tube of 90 TRS202EPW Reel of 2000 TRS202EPWR Tube of 25 TRS202EIN Tube of 40 TRS202EID Reel of 2500 TRS202EIDR Tube of 40 TRS202EIDW Reel of 2000 TRS202EIDWR Tube of 90 TRS202EIPW Reel of 2000 TRS202EIPWR TOP-SIDE MARKING TRS202ECN TRS202EC TRS202EC RU02EC TRS202EIN TRS202EI TRS202EI RU02EI Package drawings, thermal data, and symbolization are available at www.ti.com/packaging. For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com. FUNCTION TABLES xxx Each Driver (1) (1) INPUT DIN OUTPUT DOUT L H H L H = high level, L = low level Each Receiver (1) (1) INPUT RIN OUTPUT ROUT L H H L Open H H = high level, L = low level, Open = input disconnected or connected driver off LOGIC DIAGRAM (POSITIVE LOGIC) 11 14 DIN1 DOUT1 10 7 DIN2 DOUT2 12 13 ROUT1 RIN1 9 8 ROUT2 2 RIN2 Submit Documentation Feedback Copyright © 2007–2010, Texas Instruments Incorporated Product Folder Link(s): TRS202E TRS202E www.ti.com SLLS847C – JULY 2007 – REVISED MAY 2010 Absolute Maximum Ratings (1) (2) over operating free-air temperature range (unless otherwise noted) VCC Supply voltage range (2) V+ Positive charge pump voltage range (2) V– Negative charge pump voltage range VI Input voltage range VO Output voltage range DOUT Short-circuit duration TJ Operating virtual junction temperature Tstg Storage temperature range (1) (2) MIN MAX –0.3 6 V VCC – 0.3 14 V –14 0.3 V –0.3 V+ + 0.3 Drivers Receivers UNIT V ±30 Drivers V– –0.3 V+ + 0.3 –0.3 VCC + 0.3 Receivers V Continuous –65 150 °C 150 °C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltages are with respect to network GND. Package Thermal Impedance over operating free-air temperature range (unless otherwise noted) UNIT qJA Package thermal impedance (1) (2) D package 73 DW package 57 N package 67 PW package (1) (2) °C/W 108 Maximum power dissipation is a function of TJ(max), qJA, and TA. The maximum allowable power dissipation at any allowable ambient temperature is PD = (TJ(max) – TA)/qJA. Operating at the absolute maximum TJ of 150°C can affect reliability. The package thermal impedance is calculated in accordance with JESD 51-7. Recommended Operating Conditions (1) (see Figure 4) MIN NOM MAX 4.5 5 5.5 Supply voltage VIH Driver high-level input voltage DIN VIL Driver low-level input voltage DIN Driver input voltage DIN VI TA (1) Receiver input voltage TRS202EI V 2 V 0.8 0 5.5 –30 30 0 70 –40 85 TRS202EC Operating free-air temperature UNIT V V °C Test conditions are C1–C4 = 0.1 mF at VCC = 5 V ±0.5 V. Electrical Characteristics (1) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 4) PARAMETER ICC (1) (2) Suppy current TEST CONDITIONS No load, VCC = 5 V MIN TYP (2) MAX 8 15 UNIT mA Test conditions are C1–C4 = 0.1 mF at VCC = 5 V + 0.5 V. All typical values are at VCC = 5 V, and TA = 25°C. Submit Documentation Feedback Copyright © 2007–2010, Texas Instruments Incorporated Product Folder Link(s): TRS202E 3 TRS202E SLLS847C – JULY 2007 – REVISED MAY 2010 www.ti.com DRIVER SECTION Electrical Characteristics (1) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 4) PARAMETER TEST CONDITIONS MIN TYP (2) MAX UNIT VOH High-level output voltage DOUT at RL = 3 kΩ to GND, DIN = GND 5 9 VOL Low-level output voltage DOUT at RL = 3 kΩ to GND, DIN = VCC –5 –9 IIH High-level input current VI = VCC 15 200 mA Low-level input current VI at 0 V –15 –200 mA Short-circuit output current VCC = 5.5 V VO = 0 V –10 –60 mA Output resistance VCC, V+, and V– = 0 V VO = ±2 V IIL IOS (3) ro (1) (2) (3) V V Ω 300 Test conditions are C1–C4 = 0.1 mF at VCC = 5 V + 0.5 V. All typical values are at VCC = 5 V, and TA = 25°C. Short-circuit durations should be controlled to prevent exceeding the device absolute power-dissipation ratings, and not more than one output should be shorted at a time. Switching Characteristics (1) over recommended ranges of suply voltage and operating free-air temperature (unless otherwise noted) (see Figure 4) PARAMETER TEST CONDITIONS MIN TYP (2) MAX UNIT Maximum data rate CL = 50 to 1000 pF, One DOUT switching, RL = 3 kΩ to 7 kΩ, See Figure 1 tPLH(D) Propagation delay time, low- to high-level output CL = 2500 pF, All drivers loaded, RL = 3 kΩ, See Figure 1 2 ms tPHL(D) Propagation delay time, high- to low-level output CL = 2500 pF, All drivers loaded, RL = 3 kΩ, See Figure 1 2 ms tsk(p) Pulse skew (3) CL = 150 to 2500 pF, RL = 3 kΩ to 7 kΩ, See Figure 2 300 ns SR(tr) Slew rate, transition region (see Figure 1) CL = 50 to 1000 pF, VCC = 5 V RL = 3 kΩ to 7 kΩ, (1) (2) (3) 120 3 kbit/s 6 30 V/ms Test conditions are C1–C4 = 0.1 mF at VCC = 5 V + 0.5 V. All typical values are at VCC = 5 V, and TA = 25°C. Pulse skew is defined as |tPLH – tPHL| of each channel of the same device. ESD Protection PIN TEST CONDITIONS Human-Body Model DOUT, RIN 4 TYP UNIT ±15 Contact Discharge ±8 Air-gap Discharge ±15 Submit Documentation Feedback kV Copyright © 2007–2010, Texas Instruments Incorporated Product Folder Link(s): TRS202E TRS202E www.ti.com SLLS847C – JULY 2007 – REVISED MAY 2010 RECEIVER SECTION Electrical Characteristics (1) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 4) PARAMETER TEST CONDITIONS VOH High-level output voltage IOH = –1 mA VOL Low-level output voltage IOL = 1.6 mA VIT+ Positive-going input threshold voltage VCC = 5 V, TA = 25°C VIT– Negative-going input threshold voltage VCC = 5 V, TA = 25°C Vhys Input hysteresis (VIT+ – VIT–) ri Input resistance (1) (2) MIN TYP (2) 3.5 VCC – 0.4 1.7 MAX UNIT V 0.4 V 2.4 V 0.8 1.2 0.2 0.5 1 V 3 5 7 kΩ VI = ±3 V to ±25 V V Test conditions are C1–C4 = 0.1 mF at VCC = 5 V + 0.5 V. All typical values are at VCC = 5 V, and TA = 25°C. Switching Characteristics (1) over recommended ranges of suply voltage and operating free-air temperature (unless otherwise noted) (see Figure 3) PARAMETER TEST CONDITIONS tPLH(R) Propagation delay time, low- to high-level output CL = 150 pF tPHL(R) Propagation delay time, high- to low-level output CL = 150 pF tsk(p) Pulse skew (3) (1) (2) (3) MIN TYP (2) MAX 0.5 10 ms 0.5 10 ms 300 UNIT ns Test conditions are C1–C4 = 0.1 mF at VCC = 5 V + 0.5 V. All typical values are at VCC = 5 V, and TA = 25°C. Pulse skew is defined as |tPLH – tPHL| of each channel of the same device. Submit Documentation Feedback Copyright © 2007–2010, Texas Instruments Incorporated Product Folder Link(s): TRS202E 5 TRS202E SLLS847C – JULY 2007 – REVISED MAY 2010 www.ti.com PARAMETER MEASUREMENT INFORMATION 3V Input Generator (see Note B) 1.5 V RS-232 Output 50 W RL 1.5 V 0V tTHL (D) CL (see Note A) Output tTLH (D) 3V 3V –3 V –3 V TEST CIRCUIT SR(tf) = 6V tTHL(D) or tTLH(D) VOH VOL VOLTAGE WAVEFORMS NOTES: A. CL includes probe and jig capacitance. B. The pulse generator has the following characteristics: PRR = 120 kbit/s, ZO = 50 W, 50% duty cycle, tr £ 10 ns, tf £ 10 ns. Figure 1. Driver Slew Rate 3V Generator (see Note B) RS-232 Output 50 W RL Input 1.5 V 1.5 V 0V CL (see Note A) tPHL (D) tPLH (D) VOH 50% 50% Output VOL TEST CIRCUIT VOLTAGE WAVEFORMS NOTES: A. CL includes probe and jig capacitance. B. The pulse generator has the following characteristics: PRR = 120 kbit/s, ZO = 50 W, 50% duty cycle, tr £ 10 ns, tf £ 10 ns. Figure 2. Driver Pulse Skew Input Generator (see Note B) 3V 1.5 V 1.5 V -3 V Output 50 W CL (see Note A) tPHL (R) tPLH (R) VOH 50% Output 50% VOL TEST CIRCUIT VOLTAGE WAVEFORMS NOTES: A. CL includes probe and jig capacitance. B. The pulse generator has the following characteristics: ZO = 50 W, 50% duty cycle, tr £ 10 ns, tf £ 10 ns. Figure 3. Receiver Propagation Delay Times 6 Submit Documentation Feedback Copyright © 2007–2010, Texas Instruments Incorporated Product Folder Link(s): TRS202E TRS202E www.ti.com SLLS847C – JULY 2007 – REVISED MAY 2010 APPLICATION INFORMATION 1 C1 + † C3 + 0.1 mF, – 0.1 mF 6.3 V – 16 V 2 3 VCC C1+ V+ GND 16 15 14 C1– DOUT1 13 4 C2 0.1 mF, 16 V 5 kW 5 C2– 12 C4 0.1 mF, 16 V RIN1 C2+ + – + CBYPASS – = 0.1 mF, 6 11 V– – ROUT1 DIN1 + DOUT2 RIN2 7 10 8 9 DIN2 ROUT2 5 kW † C3 can be connected to VCC or GND. NOTES: A . Resistor values shown are nominal. B . Nonpolarized ceramic capacitors are acceptable. If polarized tantalum or electrolytic capacitors are used, they should be connected as shown. Figure 4. Typical Operating Circuit and Capacitor Values Capacitor Selection The capacitor type used for C1-C4 is not critical for proper operation. The TRS202E requires 0.1-mF capacitors, although capacitors up to 10 mF can be used without harm. Ceramic dielectrics are suggested for the 0.1-mF capacitors. When using the minimum recommended capacitor values, make sure the capacitance value does not degrade excessively as the operating temperature varies. If in doubt, use capacitors with a larger (e.g., 2×) nominal value. The capacitors' effective series resistance (ESR), which usually rises at low temperatures, influences the amount of ripple on V+ and V–. Use larger capacitors (up to 10 mF) to reduce the output impedance at V+ and V–. Bypass VCC to ground with at least 0.1 mF. In applications sensitive to power-supply noise generated by the charge pumps, decouple VCC to ground with a capacitor the same size as (or larger than) the charge-pump capacitors (C1–C4). Submit Documentation Feedback Copyright © 2007–2010, Texas Instruments Incorporated Product Folder Link(s): TRS202E 7 TRS202E SLLS847C – JULY 2007 – REVISED MAY 2010 www.ti.com ESD Protection TI TRS202E devices have standard ESD protection structures incorporated on the pins to protect against electrostatic discharges encountered during assembly and handling. In addition, the RS232 bus pins (driver outputs and receiver inputs) of these devices have an extra level of ESD protection. Advanced ESD structures were designed to successfully protect these bus pins against ESD discharge of ±15-kV when powered down. ESD Test Conditions Stringent ESD testing is performed by TI, based on various conditions and procedures. Please contact TI for a reliability report that documents test setup, methodology, and results. Human-Body Model (HBM) The HBM of ESD testing is shown in Figure 5. Figure 6 shows the current waveform that is generated during a discharge into a low impedance. The model consists of a 100-pF capacitor, charged to the ESD voltage of concern, and subsequently discharged into the device under test (DUT) through a 1.5-kΩ resistor. RD 1.5 kW VHBM CS + – DUT 100 pF Figure 5. HBM ESD Test Circuit 1.5 VHBM = 2 kV DUT = 10-V, 1-W Zener Diode | IDUT (A) 1.0 0.5 0.0 0 50 100 150 200 Time (ns) Figure 6. Typical HBM Current Waveform 8 Submit Documentation Feedback Copyright © 2007–2010, Texas Instruments Incorporated Product Folder Link(s): TRS202E TRS202E www.ti.com SLLS847C – JULY 2007 – REVISED MAY 2010 Machine Model (MM) The MM ESD test applies to all pins using a 200-pF capacitor with no discharge resistance. The purpose of the MM test is to simulate possible ESD conditions that can occur during the handling and assembly processes of manufacturing. In this case, ESD protection is required for all pins, not just RS-232 pins. However, after PC board assembly, the MM test no longer is as pertinent to the RS-232 pins. Submit Documentation Feedback Copyright © 2007–2010, Texas Instruments Incorporated Product Folder Link(s): TRS202E 9 PACKAGE OPTION ADDENDUM www.ti.com 21-Apr-2010 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty TRS202ECD ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TRS202ECDG4 ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TRS202ECDR ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TRS202ECDRG4 ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TRS202ECDW ACTIVE SOIC DW 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TRS202ECDWG4 ACTIVE SOIC DW 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TRS202ECDWR ACTIVE SOIC DW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TRS202ECDWRG4 ACTIVE SOIC DW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TRS202ECN ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type TRS202ECNE4 ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type TRS202ECPW ACTIVE TSSOP PW 16 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TRS202ECPWG4 ACTIVE TSSOP PW 16 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TRS202ECPWR ACTIVE TSSOP PW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TRS202ECPWRG4 ACTIVE TSSOP PW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TRS202EID ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TRS202EIDG4 ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TRS202EIDR ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TRS202EIDRG4 ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TRS202EIDW ACTIVE SOIC DW 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TRS202EIDWG4 ACTIVE SOIC DW 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TRS202EIDWR ACTIVE SOIC DW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TRS202EIDWRG4 ACTIVE SOIC DW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TRS202EIN ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type TRS202EINE4 ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type TRS202EIPW ACTIVE TSSOP PW 16 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Addendum-Page 1 Lead/Ball Finish MSL Peak Temp (3) PACKAGE OPTION ADDENDUM www.ti.com 21-Apr-2010 Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty TRS202EIPWG4 ACTIVE TSSOP PW 16 TRS202EIPWR ACTIVE TSSOP PW TRS202EIPWRG4 ACTIVE TSSOP PW 90 Lead/Ball Finish MSL Peak Temp (3) Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 30-Jul-2010 TAPE AND REEL INFORMATION *All dimensions are nominal Device TRS202ECDR Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1 TRS202ECDWR SOIC DW 16 2000 330.0 16.4 10.75 10.7 2.7 12.0 16.0 Q1 TRS202ECPWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 TRS202EIDR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1 TRS202EIDWR SOIC DW 16 2000 330.0 16.4 10.75 10.7 2.7 12.0 16.0 Q1 TRS202EIPWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 30-Jul-2010 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TRS202ECDR SOIC D 16 2500 346.0 346.0 33.0 TRS202ECDWR SOIC DW 16 2000 346.0 346.0 33.0 TRS202ECPWR TSSOP PW 16 2000 346.0 346.0 29.0 TRS202EIDR SOIC D 16 2500 346.0 346.0 33.0 TRS202EIDWR SOIC DW 16 2000 346.0 346.0 33.0 TRS202EIPWR TSSOP PW 16 2000 346.0 346.0 29.0 Pack Materials-Page 2 MECHANICAL DATA MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999 PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 14 PINS SHOWN 0,30 0,19 0,65 14 0,10 M 8 0,15 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 1 7 0°– 8° A 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 8 14 16 20 24 28 A MAX 3,10 5,10 5,10 6,60 7,90 9,80 A MIN 2,90 4,90 4,90 6,40 7,70 9,60 DIM 4040064/F 01/97 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. Falls within JEDEC MO-153 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. 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