SN54AHCT594, SN74AHCT594 8-BIT SHIFT REGISTERS WITH OUTPUT REGISTERS SCLS417C – JUNE 1998 – REVISED JANUARY 2000 D D 15 3 14 4 13 5 12 6 11 7 10 8 9 VCC QA SER RCLR RCLK SRCLK SRCLR QH′ SN54AHCT594 . . . FK PACKAGE (TOP VIEW) QD QE NC QF QG description The ’AHCT594 devices contain an 8-bit serial-in, parallel-out shift register that feeds an 8-bit D-type storage register. Separate clocks and direct overriding clear (SRCLR, RCLR) inputs are provided on both the shift and storage registers. A serial (QH′) output is provided for cascading purposes. 16 2 4 3 2 1 20 19 18 5 17 6 16 7 15 8 14 9 10 11 12 13 SER RCLR NC RCLK SRCLK SRCLR D 1 NC VCC QA D QB QC QD QE QF QG QH GND GND NC Q H′ D SN54AHCT594 . . . J OR W PACKAGE SN74AHCT594 . . . D, DB, N, OR PW PACKAGE (TOP VIEW) QC QB D D EPIC (Enhanced-Performance Implanted CMOS) Process Inputs Are TTL-Voltage Compatible 8-Bit Serial-In, Parallel-Out Shift Registers With Storage Independent Direct Overriding Clears on Shift and Storage Registers Independent Clocks for Both Shift and Storage Registers Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II ESD Protection Exceeds JESD 22 – 2000-V Human-Body Model (A114-A) – 200-V Machine Model (A115-A) – 1000-V Charged-Device Model (C101) Package Options Include Plastic Small-Outline (D), Shrink Small-Outline (DB), Thin Shrink Small-Outline (PW), and Ceramic Flat (W) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) DIPs QH D NC – No internal connection Both the shift register (SRCLK) and storage register (RCLK) clocks are positive edge triggered. If both clocks are connected together, the shift register always is one count pulse ahead of the storage register. The SN54AHCT594 is characterized for operation over the full military temperature range of –55°C to 125°C. The SN74AHCT594 is characterized for operation from –40°C to 85°C. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. EPIC is a trademark of Texas Instruments Incorporated. Copyright 2000, Texas Instruments Incorporated UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SN54AHCT594, SN74AHCT594 8-BIT SHIFT REGISTERS WITH OUTPUT REGISTERS SCLS417C – JUNE 1998 – REVISED JANUARY 2000 FUNCTION TABLE INPUTS FUNCTION SER SRCLK SRCLR RCLK RCLR X X L X X Shift register is cleared. L ↑ H X X First stage of shift register goes low. Other stages store the data of previous stage, respectively. H ↑ H X X First stage of shift register goes high. Other stages store the data of previous stage, respectively. L ↓ H X X Shift-register state is not changed. X X X X L Storage register is cleared. X X X ↑ H Shift-register data is stored in the storage register. X X X ↓ H Storage-register state is not changed. logic symbol† 13 RCLR RCLK 12 10 SRCLR SRCLK SER 11 R3 C2 SRG8 R C1/ 14 1D 2D 3 15 1 2 3 4 5 6 2D 3 7 9 QA QB QC QD QE QF QG QH QH′ † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. Pin numbers shown are for the D, DB, J, N, PW, and W packages. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN54AHCT594, SN74AHCT594 8-BIT SHIFT REGISTERS WITH OUTPUT REGISTERS SCLS417C – JUNE 1998 – REVISED JANUARY 2000 logic diagram (positive logic) 13 RCLR 12 RCLK 10 SRCLR SRCLK SER 11 14 1D Q C1 R 2D Q C2 R 2D Q C2 R 2D Q C2 R 2D Q C2 R 2D Q C2 R 2D Q C2 R 2D Q C2 R R 3D Q C3 15 R 3D Q C3 1 R 3D Q C3 2 R 3D Q C3 3 R 3D Q C3 4 R 3D Q C3 5 R 3D Q C3 6 R 3D Q C3 7 QA QB QC QD QE QF QG QH 9 QH′ Pin numbers shown are for the D, DB, J, N, PW, and W packages. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 SN54AHCT594, SN74AHCT594 8-BIT SHIFT REGISTERS WITH OUTPUT REGISTERS SCLS417C – JUNE 1998 – REVISED JANUARY 2000 timing diagram SRCLK SER RCLK SRCLR RCLR ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ QA QB QC QD QE QF QG QH QH’ 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN54AHCT594, SN74AHCT594 8-BIT SHIFT REGISTERS WITH OUTPUT REGISTERS SCLS417C – JUNE 1998 – REVISED JANUARY 2000 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 7 V Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –20 mA Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 20 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 25 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 75 mA Package thermal impedance, θJA (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73°C/W DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82°C/W N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67°C/W PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51. recommended operating conditions (see Note 3) SN54AHCT594 SN74AHCT594 MIN MAX MIN MAX 4.5 5.5 4.5 5.5 UNIT VCC VIH Supply voltage VIL VI Low-level input voltage 0.8 V Input voltage 0 5.5 0 5.5 V VO IOH Output voltage 0 0 VCC –8 V High-level output current VCC –8 mA IOL Dt/Dv Low-level output current 8 8 mA 20 20 ns/V High-level input voltage 2 2 0.8 Input transition rise or fall rate V V TA Operating free-air temperature –55 125 –40 85 °C NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VOH TEST CONDITIONS VCC IOH = –50 mA IOH = –8 mA 45V 4.5 VOL IOL = 50 mA IOL = 8 mA II ICC VI = VCC or GND VI = VCC or GND, IO = 0 5.5 V ∆ICC‡ One input at 3.4 V, Other inputs at VCC or GND 5.5 V Ci VI = VCC or GND MIN 4.4 TA = 25°C TYP MAX 4.5 3.94 45V 4.5 0 V to 5.5 V 5V 2 SN54AHCT594 MIN MAX SN74AHCT594 MIN 4.4 4.4 3.8 3.8 MAX UNIT V 0.1 0.1 0.1 0.36 0.44 0.44 ±0.1 ±1* ±1 2 20 20 mA mA 1.35 1.5 1.5 mA 10 pF 10 V * On products compliant to MIL-PRF-38535, this parameter is not production tested at VCC = 0 V. ‡ This is the increase in supply current for each input at one of the specified TTL voltage levels rather than 0 V or VCC. PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 SN54AHCT594, SN74AHCT594 8-BIT SHIFT REGISTERS WITH OUTPUT REGISTERS SCLS417C – JUNE 1998 – REVISED JANUARY 2000 timing requirements over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1) TA = 25°C MIN MAX tw Pulse duration tsu Setup time RCLK or SRCLK high or low SN54AHCT594 MIN SN74AHCT594 MAX MIN 5 5.5 5.5 RCLR or SRCLR low 5.2 5.5 5.5 SER before SRCLK↑ 3 3 3 SRCLK↑ before RCLK↑† 5 5 5 SRCLR low before RCLK↑ 5 5 5 SRCLR high (inactive) before SRCLK↑ 2.9 3.3 3.3 RCLR high (inactive) before RCLK↑ 3.4 3.8 3.8 MAX UNIT ns ns th Hold time SER after SRCLK↑ 2 2 2 ns † This setup time allows the storage register to receive stable data from the shift register. The clocks can be tied together, in which case the shift register is one clock pulse ahead of the storage register. switching characteristics over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) fmax 135* 170* 115* 115 CL = 50 pF 120 140 95 95 QA–Q QH CL = 15 pF tPLH tPHL SRCLK QH′ CL = 15 pF tPHL RCLR QA–QH tPHL tPLH SRCLR QH′ tPHL SN74AHCT594 CL = 15 pF RCLK tPHL tPHL SN54AHCT594 MIN tPLH tPHL tPHL tPLH TA = 25°C TYP MAX LOAD CAPACITANCE MIN MAX MIN MAX UNIT MHz 3.3* 6.2* 1* 6.5* 1 6.5 3.7* 6.5* 1* 6.9* 1 6.9 3.7* 6.8* 1* 7.2* 1 7.2 4.1* 7.2* 1* 7.6* 1 7.6 CL = 15 pF 4.5* 7.6* 1* 8.2* 1 8.2 ns CL = 15 pF 4.1* 7.1* 1* 7.6* 1 7.6 ns 4.9 7.8 1 8.3 1 8.3 5.8 8.9 1 9.7 1 9.7 5.5 8.6 1 9.1 1 9.1 6 9.2 1 10.1 1 10.1 ns ns RCLK QA–Q QH CL = 50 pF ns SRCLK QH′ CL = 50 pF RCLR QA–QH CL = 50 pF 6.6 10 1 10.7 1 10.7 ns SRCLR QH′ CL = 50 pF 6 9.2 1 10.1 1 10.1 ns ns * On products compliant to MIL-PRF-38535, this parameter is not production tested. noise characteristics, VCC = 5 V, CL = 50 pF, TA = 25°C (see Note 4) SN74AHCT594 PARAMETER MIN MAX UNIT VOL(P) VOL(V) Quiet output, maximum dynamic VOL 1 V Quiet output, minimum dynamic VOL –0.6 V VOH(V) VIH(D) Quiet output, minimum dynamic VOH 3.8 V High-level dynamic input voltage 2 VIL(D) Low-level dynamic input voltage NOTE 4: Characteristics are for surface-mount packages only. POST OFFICE BOX 655303 V 0.8 PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. 6 TYP • DALLAS, TEXAS 75265 V SN54AHCT594, SN74AHCT594 8-BIT SHIFT REGISTERS WITH OUTPUT REGISTERS SCLS417C – JUNE 1998 – REVISED JANUARY 2000 operating characteristics, VCC = 5 V, TA = 25°C PARAMETER Cpd TEST CONDITIONS Power dissipation capacitance No load, f = 1 MHz TYP UNIT 112 pF PARAMETER MEASUREMENT INFORMATION RL = 1 kΩ From Output Under Test Test Point From Output Under Test S1 VCC Open TEST GND CL (see Note A) CL (see Note A) S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open Drain Open VCC GND VCC LOAD CIRCUIT FOR 3-STATE AND OPEN-DRAIN OUTPUTS LOAD CIRCUIT FOR TOTEM-POLE OUTPUTS 3V 1.5 V Timing Input 0V tw 3V 1.5 V Input 1.5 V th tsu 3V 1.5 V Data Input 1.5 V 0V 0V VOLTAGE WAVEFORMS PULSE DURATION VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 3V 1.5 V Input 1.5 V 0V tPLH In-Phase Output tPHL 50% VCC tPHL Out-of-Phase Output VOH 50% VCC VOL Output Waveform 1 S1 at VCC (see Note B) VOH 50% VCC VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS 1.5 V 1.5 V 0V tPZL tPLZ ≈VCC 50% VCC tPZH tPLH 50% VCC 3V Output Control Output Waveform 2 S1 at GND (see Note B) VOL + 0.3 V VOL tPHZ 50% VCC VOH – 0.3 V VOH ≈0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤ 3 ns, tf ≤ 3 ns. D. The outputs are measured one at a time with one input transition per measurement. Figure 1. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. 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