PCF8574A REMOTE 8-BIT I/O EXPANDER FOR I2C BUS www.ti.com SCPS069D – JULY 2001 – REVISED OCTOBER 2005 FEATURES • 16 2 15 3 14 4 13 5 12 6 11 7 10 8 9 VCC SDA SCL INT P7 P6 P5 P4 P7 1 1 20 DGV OR PW PACKAGE (TOP VIEW) 3 4 19 P6 18 NC 17 P5 5 6 16 P4 15 GND 7 8 14 P3 13 NC 9 12 P2 2 SCL NC SDA VCC A0 A1 NC A2 10 11 P1 A0 A1 A2 P0 P1 P2 P3 GND Compatible With Most Microcontrollers Latched Outputs With High-Current Drive Capability for Directly Driving LEDs Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II RGY PACKAGE (TOP VIEW) DW OR N PACKAGE (TOP VIEW) INT • • • • Low Standby-Current Consumption of 10 µA Max I2C to Parallel-Port Expander Open-Drain Interrupt Output P0 • INT SCL NC SDA VCC A0 A1 NC A2 P0 1 20 2 3 19 18 4 5 17 16 6 7 15 14 8 13 9 10 12 11 P7 P6 NC P5 P4 GND P3 NC P2 P1 NC − No internal connection NC − No internal connection DESCRIPTION/ORDERING INFORMATION This 8-bit input/output (I/O) expander for the two-line bidirectional bus (I2C) is designed for 2.5-V to 6-V VCC operation. The PCF8574A provides general-purpose remote I/O expansion for most microcontroller families via the I2C interface [serial clock (SCL), serial data (SDA)]. The device features an 8-bit quasi-bidirectional I/O port (P0–P7), including latched outputs with high-current drive capability for directly driving LEDs. Each quasi-bidirectional I/O can be used as an input or output without the use of a data-direction control signal. At power on, the I/Os are high. In this mode, only a current source to VCC is active. An additional strong pullup to VCC allows fast rising edges into heavily loaded outputs. This device turns on when an output is written high and is switched off by the negative edge of SCL. The I/Os should be high before being used as inputs. ORDERING INFORMATION PACKAGE (1) TA –40°C to 85°C (1) ORDERABLE PART NUMBER TOP-SIDE MARKING QFN – RGY Tape and reel PCF8574ARGYR PF574A PDIP – N Tube PCF8574AN PCF8574AN Tube PCF8574ADW Tape and reel PCF8574ADWR TSSOP – PW Tape and reel PCF8574APWR PF574A TVSOP – DGV Tape and reel PCF8574ADGVR PF574A SOIC – DW PCF8574A Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2001–2005, Texas Instruments Incorporated PCF8574A REMOTE 8-BIT I/O EXPANDER FOR I2C BUS www.ti.com SCPS069D – JULY 2001 – REVISED OCTOBER 2005 DESCRIPTION/ORDERING INFORMATION (CONTINUED) The PCF8574A provides an open-drain output (INT) that can be connected to the interrupt input of a microcontroller. An interrupt is generated by any rising or falling edge of the port inputs in the input mode. After time, tiv, INT is valid. Resetting and reactivating the interrupt circuit is achieved when data on the port is changed to the original setting or data is read from, or written to, the port that generated the interrupt. Resetting occurs in the read mode at the acknowledge bit after the rising edge of the SCL signal, or in the write mode at the acknowledge bit after the high-to-low transition of the SCL signal. Interrupts that occur during the acknowledge clock pulse can be lost (or be very short) due to the resetting of the interrupt during this pulse. Each change of the I/Os after resetting is detected and, after the next rising clock edge, is transmitted as INT. Reading from, or writing to, another device does not affect the interrupt circuit. By sending an interrupt signal on this line, the remote I/O can inform the microcontroller if there is incoming data on its ports without having to communicate via the I2C bus. Therefore, the PCF8574A can remain a simple slave device. LOGIC DIAGRAM (POSITIVE LOGIC) INT A0 A1 A2 SCL SDA PCF8574A 13 Interrupt Logic LP Filter 1 4 2 5 3 6 14 15 Input Filter I2C Bus Control 7 Shift Register 8 Bit I/O Port 9 10 11 12 Write Pulse VCC GND Read Pulse 16 8 Power-On Reset Pin numbers shown are for the DW and N packages. 2 P0 P1 P2 P3 P4 P5 P6 P7 PCF8574A REMOTE 8-BIT I/O EXPANDER FOR I2C BUS www.ti.com SCPS069D – JULY 2001 – REVISED OCTOBER 2005 SIMPLIFIED SCHEMATIC DIAGRAM OF EACH P-PORT INPUT/OUTPUT VCC Write Pulse 100 µA Data From Shift Register D Q FF P0 to P7 CI S Power-On Reset D Q GND FF CI Read Pulse S To Interrupt Logic Data To Shift Register I2C Interface I2C communication with this device is initiated by a master sending a start condition, a high-to-low transition on the SDA I/O while the SCL input is high. After the start condition, the device address byte is sent, most-significant bit (MSB) first, including the data direction bit (R/W). This device does not respond to the general call address. After receiving the valid address byte, this device responds with an acknowledge, a low on the SDA I/O during the high of the acknowledge-related clock pulse. The address inputs (A0–A2) of the slave device must not be changed between the start and the stop conditions. The data byte follows the address acknowledge. If the R/W bit is high, the data from this device are the values read from the P port. If the R/W bit is low, the data are from the master, to be output to the P port. The data byte is followed by an acknowledge sent from this device. If other data bytes are sent from the master, following the acknowledge, they are ignored by this device. Data are output only if complete bytes are received and acknowledged. The output data will be valid at time, tpv, after the low-to-high transition of SCL and during the clock cycle for the acknowledge. A stop condition, a low-to-high transition on the SDA I/O while the SCL input is high, is sent by the master. Interface Definition BYTE I2C slave address I/O data bus BIT 7 (MSB) 6 5 4 3 2 1 0 (LSB) L H H H A2 A1 AO R/W P7 P6 P5 P4 P3 P2 P1 P0 3 PCF8574A REMOTE 8-BIT I/O EXPANDER FOR I2C BUS www.ti.com SCPS069D – JULY 2001 – REVISED OCTOBER 2005 Address Reference INPUTS I2C BUS SLAVE ADDRESS A2 A1 A0 L L L L L H 57 (decimal), 39 (hexadecimal) L H L 58 (decimal), 3A (hexadecimal) L H H 59 (decimal), 3B (hexadecimal) H L L 60 (decimal), 3C (hexadecimal) H L H 61 (decimal), 3D (hexadecimal) H H L 62 (decimal), 3E (hexadecimal) H H H 63 (decimal), 3F (hexadecimal) 56 (decimal), 38 (hexadecimal) Absolute Maximum Ratings (1) over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT VCC Supply voltage range –0.5 7 V VI Input voltage range (2) –0.5 VCC + 0.5 V VO Output voltage range (2) –0.5 VCC + 0.5 IIK Input clamp current VI < 0 IOK Output clamp current VO < 0 IOK Input/output clamp current VO < 0 or VO > VCC IOL Continuous output low current VO = 0 to VCC IOH Continuous output high current VO = 0 to VCC Continuous current through VCC or GND θJA Tstg (1) (2) (3) (4) Package thermal impedance Storage temperature range mA –20 mA ±400 µA 50 mA –4 mA ±100 mA DGV package (3) 92 DW package (3) 57 N package (3) 67 PW package (3) 83 RGY package (4) 37 –65 V –20 °C/W °C 150 Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed. The package thermal impedance is calculated in accordance with JESD 51-7. The package thermal impedance is calculated in accordance with JESD 51-5. Recommended Operating Conditions MIN MAX 2.5 6 V High-level input voltage 0.7 × VCC VCC + 0.5 V VIL Low-level input voltage –0.5 0.3 × VCC IOH High-level output current –1 mA IOL Low-level output current 25 mA TA Operating free-air temperature 85 °C VCC Supply voltage VIH 4 –40 UNIT V PCF8574A REMOTE 8-BIT I/O EXPANDER FOR I2C BUS www.ti.com SCPS069D – JULY 2001 – REVISED OCTOBER 2005 Electrical Characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC VIK Input diode clamp voltage II = –18 mA VPOR Power-on reset voltage (2) VI = VCC or GND, IOH P port VO = GND IOHT P-port transient pullup current High during acknowledge, VOH = GND SDA VO = 0.4 V P port VO = 1 V INT VO = 0.4 V IOL 2.5 V to 6 V IO = 0 MIN TYP (1) MAX –1.2 6V 2.5 V to 6 V 2.5 V to 6 V V 1.3 30 2.5 V INT 300 ICC Ci Cio 25 mA 3 5V 10 2.5 V to 6 V 1.6 ±5 2.5 V to 6 V (1) (2) µA ±5 P port VI ≥ VCC or VI ≤ GND Operating mode VI = VCC or GND, IO = 0, fSCL = 100 kHz Standby mode VI = VCC or GND, IO = 0 SCL VI = VCC or GND P port µA ±5 VI = VCC or GND SDA V mA A0, A1, A2 IIHL 2.4 –1 SCL, SDA II UNIT VIO = VCC or GND ±400 2.5 V to 6 V 6V 2.5 V to 6 V 2.5 V to 6 V 40 100 2.5 10 1.5 7 3 7 4 10 µA µA pF pF All typical values are at VCC = 5 V, TA = 25°C. The power-on reset circuit resets the I2C-bus logic with VCC < VPOR and sets all I/Os to logic high (with current source to VCC). I2C Interface Timing Requirements over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1) MIN MAX UNIT 100 kHz fscl I2C clock frequency tsch I2C tscl I2C clock low time tsp I2C spike time tsds I2C tsdh I2C serial-data hold time ticr I2C input rise time ticf I2C input fall time tocf I2C tbuf I2C bus free time between stop and start 4.7 µs tsts I2C start or repeated start condition setup 4.7 µs tsth I2C 4 µs tsps I2C stop-condition setup tvd Valid-data time Cb I2C clock high time µs 100 serial-data setup time 250 ns 1 µs 0.3 µs 300 start or repeated start condition hold ns µs 4 SCL low to SDA output valid ns ns 0 output fall time (10-pF to 400-pF bus) bus capacitive load µs 4 4.7 3.4 µs 400 pF 5 PCF8574A REMOTE 8-BIT I/O EXPANDER FOR I2C BUS www.ti.com SCPS069D – JULY 2001 – REVISED OCTOBER 2005 Switching Characteristics over recommended operating free-air temperature range, CL ≤ 100 pF (unless otherwise noted) (see Figure 2) PARAMETER FROM (INPUT) TO (OUTPUT) SCL P port MIN MAX µs tpv Output data valid tsu Input data setup time P port SCL 0 th Input data hold time P port SCL 4 tiv Interrupt valid time P port INT 4 µs tir Interrupt reset delay time SCL INT 4 µs 6 4 UNIT µs µs PCF8574A REMOTE 8-BIT I/O EXPANDER FOR I2C BUS www.ti.com SCPS069D – JULY 2001 – REVISED OCTOBER 2005 PARAMETER MEASUREMENT INFORMATION VCC RL = 1 kΩ Pn DUT CL = 10 pF to = 400 pF LOAD CIRCUIT 2 Bytes for Complete Device Programming Stop Condition (P) Start Condition (S) Bit 7 (MSB) Bit 0 LSB (R/W) Bit 6 tscl Acknowledge (A) Stop Condition (P) tsch 0.7 × VCC SCL 0.3 × VCC ticr tPHL ticf tbuf tsts tPLH tsp 0.7 × VCC SDA 0.3 × VCC ticf ticr tsth Start or Repeat Start Condition tsdh tsds tsps Repeat Start Condition Stop Condition VOLTAGE WAVEFORMS Figure 1. I2C Interface Load Circuit and Voltage Waveforms 7 PCF8574A REMOTE 8-BIT I/O EXPANDER FOR I2C BUS www.ti.com SCPS069D – JULY 2001 – REVISED OCTOBER 2005 PARAMETER MEASUREMENT INFORMATION (continued) Acknowledge From Slave Start Condition Acknowledge From Slave R/W Slave Address S Data From Port 0 1 1 1 A2 A1 A0 1 A 1 2 3 4 A 5 6 7 8 Data From Port Data 1 A Data 3 1 A tir tir B B INT A tiv tsps A Data Into Port Data 1 Data 2 0.7 × VCC INT 0.7 × VCC SCL 0.3 × VCC Data 3 R/W A tiv 0.3 × VCC tir 0.7 × VCC Pn 0.7 × VCC INT 0.3 × VCC 0.3 × VCC View A−A View B−B Figure 2. Interrupt Voltage Waveforms SCL 0.7 × VCC W A D Slave Acknowledge SDA Pn Unstable Data tpv Last Stable Bit Figure 3. I2C Write Voltage Waveforms 8 0.3 × VCC P PCF8574A REMOTE 8-BIT I/O EXPANDER FOR I2C BUS www.ti.com SCPS069D – JULY 2001 – REVISED OCTOBER 2005 PARAMETER MEASUREMENT INFORMATION (continued) VCC VCC RL = 1 kΩ DUT RL = 4.7 kΩ SDA DUT INT CL = 10 pF to 400 pF GND CL = 10 pF to 400 pF GND SDA LOAD CONFIGURATION INTERRUPT LOAD CONFIGURATION Figure 4. Load Circuits 9 PACKAGE OPTION ADDENDUM www.ti.com 21-Dec-2009 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty PCF8574ADGVR ACTIVE TVSOP DGV 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM PCF8574ADGVRE4 ACTIVE TVSOP DGV 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM PCF8574ADGVRG4 ACTIVE TVSOP DGV 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM PCF8574ADW ACTIVE SOIC DW 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM PCF8574ADWE4 ACTIVE SOIC DW 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM PCF8574ADWG4 ACTIVE SOIC DW 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM PCF8574ADWR ACTIVE SOIC DW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM PCF8574ADWRE4 ACTIVE SOIC DW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM PCF8574ADWRG4 ACTIVE SOIC DW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM PCF8574AN ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type PCF8574ANE4 ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type PCF8574APW ACTIVE TSSOP PW 20 70 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM PCF8574APWE4 ACTIVE TSSOP PW 20 70 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM PCF8574APWG4 ACTIVE TSSOP PW 20 70 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM PCF8574APWR ACTIVE TSSOP PW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM PCF8574APWRE4 ACTIVE TSSOP PW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM PCF8574APWRG4 ACTIVE TSSOP PW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM PCF8574ARGYR ACTIVE VQFN RGY 20 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR PCF8574ARGYRG4 ACTIVE VQFN RGY 20 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered Addendum-Page 1 PACKAGE OPTION ADDENDUM www.ti.com 21-Dec-2009 at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 21-Dec-2009 TAPE AND REEL INFORMATION *All dimensions are nominal Device PCF8574ADGVR Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant TVSOP DGV 20 2000 330.0 12.4 7.0 5.6 1.6 8.0 12.0 Q1 PCF8574ADWR SOIC DW 16 2000 330.0 16.4 10.75 10.7 2.7 12.0 16.0 Q1 PCF8574APWR TSSOP PW 20 2000 330.0 16.4 6.95 7.1 1.6 8.0 16.0 Q1 PCF8574ARGYR VQFN RGY 20 3000 180.0 12.4 3.8 4.8 1.6 8.0 12.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 21-Dec-2009 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) PCF8574ADGVR TVSOP DGV 20 2000 346.0 346.0 29.0 PCF8574ADWR SOIC DW 16 2000 346.0 346.0 33.0 PCF8574APWR TSSOP PW 20 2000 346.0 346.0 33.0 PCF8574ARGYR VQFN RGY 20 3000 190.5 212.7 31.8 Pack Materials-Page 2 MECHANICAL DATA MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000 DGV (R-PDSO-G**) PLASTIC SMALL-OUTLINE 24 PINS SHOWN 0,40 0,23 0,13 24 13 0,07 M 0,16 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 0°–8° 1 0,75 0,50 12 A Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,08 14 16 20 24 38 48 56 A MAX 3,70 3,70 5,10 5,10 7,90 9,80 11,40 A MIN 3,50 3,50 4,90 4,90 7,70 9,60 11,20 DIM 4073251/E 08/00 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side. Falls within JEDEC: 24/48 Pins – MO-153 14/16/20/56 Pins – MO-194 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MECHANICAL DATA MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999 PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 14 PINS SHOWN 0,30 0,19 0,65 14 0,10 M 8 0,15 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 1 7 0°– 8° A 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 8 14 16 20 24 28 A MAX 3,10 5,10 5,10 6,60 7,90 9,80 A MIN 2,90 4,90 4,90 6,40 7,70 9,60 DIM 4040064/F 01/97 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. 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