RF2861 0 CDMA LOW NOISE AMPLIFIER/MIXER 900MHz DOWNCONVERTER Typical Applications • CDMA/JCDMA Cellular Systems • General Purpose LNA and Downconverter • CDMA450 Handsets/Data Cards • Commercial and Consumer Systems • AMPS Cellular Systems • Portable Battery-Powered Equipment Product Description 0.10 C A -A- The RF2861 is a receiver front-end for CDMA cellular applications, including JCDMA and CDMA450. It is designed to amplify and downconvert RF signals, using a three gain state LNA to obtain 17dB of stepped gain control. Features include digital control of LNA gain and power down mode, along with an integrated TX LO buffer amplifier. Another feature of the chip is adjustable IIP3 of the LNA and mixer using off-chip current setting resistors to allow for minimum DC current consumption. Noise figure, IIP3, and other specs are designed to be compatible with the TIA/EIA 98D standard for CDMA cellular communications. The IC is manufactured on an advanced Silicon Germanium Bi-CMOS process and is in a 3mmx3mm, 16-pin, QFN. 3.00 0.05 C 2 PLCS 0.90 0.85 1.50 TYP 0.70 0.65 0.05 0.00 2 PLCS 0.10 C B 3.00 12° MAX 2 PLCS 0.10 C B -B- 1.37 TYP 2 PLCS SEATING PLANE -CDimensions in mm. 2.75 SQ 0.10 C A 0.10 M C A B 0.60 0.24 TYP 0.30 0.18 2 PIN 1 ID R.20 NOTES: 1. Shaded lead is pin 1. 2 Dimension applies to plated terminal: to be measured between 0.20 mm and 0.25 mm from terminal end. 1.65 SQ. 1.35 0.50 0.30 0.50 Optimum Technology Matching® Applied Si BJT GaAs HBT GaAs MESFET Si Bi-CMOS SiGe HBT Si CMOS InGaP/HBT GaN HEMT 9SiGe Bi-CMOS Package Style: QFN, 16-Pin, 3x3 Features • 3mmx3mm LNA/Mixer Solution ENABLE TX BUFF ENABLE LO OUT VCC • Adjustable LNA and Mixer Current/IIP3 16 15 14 13 • Meets IMD Tests with Three Gain States/Two Logic Control Pins G2 1 12 LO IN LNA IN 2 11 GND 5 6 7 8 MIX IN 9 IF OUT+ G1 LNA OUT 4 ISET1 10 IF OUT- ISET2 LNA EMITTER 3 Functional Block Diagram Rev A2 040107 • Integrated TX LO Buffer Amplifier • Full ESD Protection on all Pins Ordering Information RF2861 CDMA Low Noise Amplifier/Mixer 900MHz Downconverter RF2861 PCBA-410 Fully Assembled Evaluation Board RF Micro Devices, Inc. 7628 Thorndike Road Greensboro, NC 27409, USA Tel (336) 664 1233 Fax (336) 664 0454 http://www.rfmd.com 8-1 RF2861 Absolute Maximum Ratings Parameter Supply Voltage Input LO and RF Levels Operating Ambient Temperature Storage Temperature Parameter Rating Unit -0.5 to +5.0 +6 -40 to +85 -40 to +150 VDC dBm °C °C Specification Min. Typ. Max. Caution! ESD sensitive device. RF Micro Devices believes the furnished information is correct and accurate at the time of this printing. However, RF Micro Devices reserves the right to make changes to its products without notice. RF Micro Devices does not assume responsibility for the use of the described product(s). Unit T = 25°C, VCC =2.75V Overall RF Frequency Range IF Frequency Range Condition 460 to 900 0.1 400 MHz MHz Power Supply Supply Voltage Logic High Logic Low 2.65 1.8 2.75 3.15 0.4 V V V Cellular CDMA Band JCDMA Band LNA (High Gain) Gain Noise Figure Input IP3 Current Isolation Freq=869MHz to 894MHz Freq=832MHz to 870MHz LNA 50Ω match 13.0 9.0 14.5 1.1 11.0 7.0 16.0 1.3 dB dB dBm mA dB 6.0 3.0 9.0 3.5 7.0 3.3 dB dB dBm mA dB -2.5 2.5 +27.0 0 -1.0 4.0 dB dB dBm mA dB 10.5 7.5 +8.5 12.0 8.0 dB dB dBm dB 18.5 LNA (Mid Gain) Gain Noise Figure Input IP3 Current Isolation 4.0 7.0 12.5 LNA (Low Gain) Gain Noise Figure Input IP3 Current Isolation -4.0 +25.0 1.0 Mixer - CDMA/JCDMA/FM Gain Noise Figure Input IP3 LO to RF Isolation IF tune set for nominal mixer gain, high IIP3 9.0 +6.0 36 Mixer - CDMA/JCDMA/FM Gain Noise Figure Input IP3 LO to RF Isolation 13.0 7.5 +6.5 36 184MHz IF (NF=8.3dB, 85MHz IF) LO=1064MHz IF tune set for high mixer gain, nominal IIP3 dB dB dBm dB LO=1064MHz mA TX LO Buffer Off 184MHz IF (NF=8.3dB, 85MHz IF) Cascade - High Gain Current 8-2 25 30 Rev A2 040107 RF2861 Parameter Specification Min. Typ. Max. Unit Condition Cellular CDMA Band JCDMA Band, cont’d Other LO-IF Isolation RF-IF Isolation LNA Out to Mixer In Isolation LO-LNA In Isolation, Any State 30 45 45 40 dB dB dB dB LO=1064MHz 1 pF G1, G2, ENABLE, TX BUFF ENABLE 0 710 1078 809 979 dBm MHz MHz MHz MHz IF=184MHz IF=184MHz IF=85MHz IF=85MHz 0 760 980 dBm MHz MHz IF=110MHz IF=110MHz 0 575 dBm MHz LO=1064MHz Control Lines Input Capacitance Local Oscillator Input Cellular - CDMA or FM Input Power Input Frequency Cellular - JCDMA Input Power Input Frequency CDMA450 Input Power Input Frequency -10 685 1053 784 954 -4 -10 722 942 -4 -10 505 -4 CDMA450 Band LNA (High Gain) Gain Noise Figure Input IP3 Current Isolation 15.0 1.4 +8.0 8.7 dB dB dBm mA dB +2.5 2.9 +14.0 4.7 dB dB dBm mA dB -4.0 4.0 +25.0 0 dB dB dBm mA dB 12.0 7.5 5.0 36 dB dB dBm dB 25 40 40 30 dB dB dB dB 18.5 IF=85MHz Freq=463MHz to 467MHz LNA 50Ω match LNA (Mid Gain) Gain Noise Figure Input IP3 Current Isolation 12.5 LNA (Low Gain) Gain Noise Figure Input IP3 Current Isolation 1.0 Mixer Gain Noise Figure Input IP3 LO to RF Isolation IF tune set for high mixer gain, nominal IIP3 LO=549MHz CDMA450 Isolation LO-IF Isolation RF-IF Isolation LNA Out to Mixer In Isolation LO-LNA In Isolation, Any State Rev A2 040107 LO=549MHz LO=549MHz 8-3 RF2861 Parameter Specification Min. Typ. Max. Unit Condition TX (Local Oscillator) Buffer Output Cellular - CDMA or FM Output Power Output Frequency Current Consumption Cellular - JCDMA Output Power Output Frequency Current Consumption CDMA450 Output Power Output Frequency Current Consumption 8-4 -7 685 1053 784 954 -5 -3 710 1078 809 979 dBm MHz MHz MHz MHz mA Single-ended 50Ω load IF=184MHz IF=184MHz IF=85MHz IF=85MHz -3 760 980 dBm MHz MHz mA Single-ended 50Ω load IF=110MHz IF=110MHz -3 575 dBm MHz mA Single-ended 50Ω load IF=85MHz 2 -7 722 942 -5 2 -7 505 -5 2 Rev A2 040107 RF2861 Gain Control Logic Table Gain State ENABLE G1 G2 High Gain 1 0 0 Mid Gain 1 1 0 Low Gain 1 1 1 Low Gain (alternate) 1 0 1 NOTES: All IDC current numbers include bias circuitry current of 1.5mA to 2.0mA (dependent on mode). TX Buffer On: Add 2mA to total current. Cell Band Cascaded Performance High Mixer Gain Nominal IIP3 (Typical Values for VCC =2.75V) NOTE: All total current numbers include bias circuitry current of 1.5mA to 2.0mA (dependent on mode). Parameter LNA (High Gain) CELL CDMA LNA (Mid Gain) Cascaded: Gain (dB) 25.0 Noise Figure (dB) 2.1 Input IP3 (dBm) -5.6 Total Current (mA) 25.0 NOTE: Assumes 2.5dB image filter insertion loss. The TX Buffer is off. 16.5 6.3 +2.0 21.5 LNA (Low Gain) 8.0 12.5 +11.4 18.0 Cell Band Cascaded Performance Nominal Mixer Gain High IIP3 (Typical Values for VCC =2.75V) Parameter LNA (High Gain) CELL CDMA LNA (Mid Gain) Cascaded: Gain (dB) 22.5 Noise Figure (dB) 2.1 Input IP3 (dBm) -3.7 Total Current (mA) 25.0 NOTE: Assumes 2.5dB image filter insertion loss. The TX Buffer is off. 14.0 6.3 +3.5 21.5 LNA (Low Gain) 5.5 12.5 +13.3 18.0 CDMA450 Band Cascaded Performance (Typical Values for VCC =2.75V) Parameter LNA (High Gain) CDMA450 LNA (Mid Gain) Cascaded: Gain (dB) 24.5 Noise Figure (dB) 2.2 Input IP3 (dBm) -7.6 Total Current (mA) 29.5 NOTE: Assumes 2.5dB image filter insertion loss. The TX Buffer is off. Rev A2 040107 12.0 8.5 +4.5 25 LNA (Low Gain) 5.5 14.0 +11.3 21 8-5 RF2861 Pin 1 Function G2 Type Description DI Gain control logic input. See logic control table. Interface Schematic G2 2 LNA IN AI Cellular LNA input. VCC LNA OUT LNA IN LNA EMITTER 3 AO Cellular LNA emitter. A small inductor connects this pin to ground. Cellular LNA gain can be adjusted by the inductance. See pin 2. 4 LNA EMITTER LNA OUT AO See pin 2. 5 ISET2 AO 6 ISET1 AO 7 G1 DI Cellular LNA output. Simple external L-C components required for matching and VCC supply. An external resistor connected to this pin sets the current of the mixer. Increasing resistance decreases current. An external resistor connected to this pin sets the current of the LNA. Increasing resistance decreases current. Gain control logic input. See logic control table. G1 8 MIX IN AI Cellular mixer RF single-end input. MIX IN 9 IF OUT+ AO CDMA IF output. Open collector. 10 11 12 IF OUTGND LO IN AO P AI CDMA IF output. Open collector. IF OUT+ IF OUT- See pin 9. Ground. LO single-end input. Matched to 50Ω. LO IN 70 Ω 13 14 15 16 VCC LO OUT TX BUFF ENABLE P AO DI ENABLE DI LO amplifier VCC external bypass capacitor may be required. LO output. Internal DC block. Drives 50Ω. Logic input. High enables TX LO output buffer amplifiers. TX BUFF ENABLE Logic input. Low level powers down the IC. ENABLE Pkg Base Legend: 8-6 GND P Ground connection. The backside of the package should be soldered to a top side ground pad which is connected to the ground plane with multiple vias. DI=Digital Input from Baseband Chip AI=Analog Input AO=Analog Output P=VCC or GND Rev A2 040107 RF2861 Application Schematic Differential IF Matching G2 TX BUFF ENABLE ENABLE LO OUT V CC 2.2 nH 33 nF 0603 Wire-wound Inductors 33 nF 16 CELL LNA IN 33 nH 15 14 13 LO IN 1 12 2 11 C3 IF Saw V CC L1 1.2 nH 33 nF 3 10 4 9 10 nH 5 V CC 6 7 L3 DNI 5 9 4 10 IFIF+ 33 nF C1 R1 L2 8 C2 G1 3.9 pF 9.1 kΩ 4 GND GND GND GND OUT 1 5 Rev A2 040107 33 nF C1 R1 85 MHz IF (LO 22 pF 2.7 kΩ FREQ=965 MHz) 184 MHz IF (LO 5.0 pF 2.7 kΩ FREQ=1064 MHz) 2 IN RF Saw 20 kΩ 3 6 L1 L2 L3 IF SAW FILTER 72 nH 72 nH 5.1 pF 5.1 pF C2 C3 220 nH SAWTEK 855845 55 nH 55 nH 10 pF 43 nH EPCOS B4955 10 pF DNI 22 nH 8-7 RF2861 Application Schematic Single-End Matching G2 TX BUFF ENABLE ENABLE LO OUT 2.2 nH 33 nF 16 CELL LNA IN 33 nH 15 14 33 nF 13 1 12 2 11 3 10 LO IN C1 1.2 nH 33 nF VCC IF Saw VCC L1 10 nH 4 9 5 VCC 6 7 C2 C3 R1 5 9 4 10 IFIF+ 33 nF L2 8 C4 G1 C5 L3 3.9 pF 9.1 kΩ 20 kΩ 4 GND GND GND OUT 1 IN RF Saw 2 5 GND 3 6 33 nF + C1 (pF) C2 (pF) C3 R1 (kΩ) L1 (nH) L2 (nH) C4 (pF) C5 L3 (nH) IF SAW FILTER 85 MHz IF (LO FREQ=965 MHz) 43 43 DNI 2.7 72 72 5.1 DNI 220 SAWTEK 855845 184 MHz IF (LO FREQ=1064 MHz) 13 13 DNI 2.7 55 55 10 DNI 43 EPCOS B4955 22 nH DNI 8-8 Rev A2 040107 RF2861 Application Schematic Single-End Matching CDMA450 Band G2 TX BUFF ENABLE ENABLE LO OUT 2.2 nH 33 nF 16 CELL LNA IN 33 nH 15 14 33 nF 0603 Wire-wound Inductors 13 1 12 2 11 3 10 LO IN C1* 5.6 nH 100 pF VCC IF Saw L1* VCC 27 nH 4 9 5 VCC 6 7 C2* C3* R1* 5 9 4 10 IFIF+ 33 nF L2* 8 C4* G1 27 pF C5* L3* *Values determined by choice of IF SAW. 6.8 kΩ 22 kΩ GND GND GND GND OUT 1 4 IN RF Saw 2 3 + 6 33 nF 5 + 2.2 pF Rev A2 040107 33 nH 8-9 RF2861 Evaluation Board Schematic TX BUFF ENABLE ENABLE VCC J6 LO OUT C46 33 nF P1 P1-1 + C20 1 uF L17 2.2 nH C54 33 nF P2 1 VCC1 P2-1 1 ENABLE 2 GND P2-2 2 TX BUF EN 3 GND P2-3 3 G1 4 G2 CON3 C6 33 nF J1 CELL LNA IN C4 33 nF C25 33 nF VCC J2 CELL LNA OUT C7 33 nF C55 33 nF 16 L1 33 nH G2 L24 1.2 nH 14 2 11 3 10 4 9 L21 10 nH 5 6 7 C5 C35 R2 L6 L11 8 L3 DNI C8 1 pF J4 CDMA IF R6 9.1 kΩ C2 33 nF C9 22.0 nH C22 VCC C17 C3 3.9 pF CON4 J5 LO IN 13 12 R4 20.0 kΩ 8-10 15 1 P2-4 Freq IF (MHz) Freq LO (MHz) C3 (pF) C5 (pF) C35 (pF) R2 (kΩ) L11 (nH) L6 (nH) C22 (nF) C17 (pF) 85 965 47 47 DNI 5.1 150 180 33 8 184 1064 13 13 DNI 2.7 82 150 33 11 G1 C1 33 nF J3 CELL MIX IN Rev A2 040107 RF2861 Evaluation Board Schematic CDMA450 Band TX BUFF ENABLE ENABLE VCC J6 LO OUT C46 33 nF P1 P1-1 + C20 1 uF L17 2.2 nH C54 33 nF P2 1 VCC1 P2-1 1 ENABLE 2 GND P2-2 2 TX BUF EN 3 GND P2-3 3 G1 P2-4 4 G2 CON3 C6 33 nF J1 CELL LNA IN C4 33 nF C7 33 nF C55 33 nF 16 L1 33 nH G2 L24 5.6 nH C25 33 nF L21 27 nH 14 13 1 12 2 11 3 10 4 9 VCC J2 CELL LNA OUT 15 5 6 7 C5 C35 R2 L6 L11 8 2.7 pF CON4 J5 LO IN C22 VCC J4 CDMA IF C17 C3 R6 6.8 kΩ R4 22 kΩ Freq IF (MHz) Freq LO (MHz) C3 (pF) C5 (pF) C35 (pF) R2 (kΩ) L11 (nH) L6 (nH) C22 (nF) C17 (pF) 85 549 91 91 DNI 6.8 68 270 33 27 C2 33 nF L3 33 nH G1 C9 2.2 pF C8 DNI Rev A2 040107 C1 33 nF J3 CELL MIX IN 8-11 RF2861 IF Output Interface Network Single-End IF Matching C1 C3 IF+ 10 4 IF- 9 5 IF+ VCC L2 L1 R C2 IF- IF Saw 33 nF C1 L1, C1, C2, and R form a current combiner which performs a differential to single-ended conversion at the IF frequency and sets the output impedance. In most cases, the resonance frequency is independent of R and can be set according to the following equation: 1 f IF = ----------------------------------------------------------L1 2π ------ ( C 1 + 2C 2 + C EQ ) 2 Where CEQ is the equivalent stray capacitance and capacitance looking into pins 9 and 10. An average value to use for CEQ is 2.5pF. R can then be used to set the output impedance according to the following equation: 1 –1 1 R = --------------------- – ------ 4 ⋅ R OUT R P where ROUT is the desired output impedance and RP is the parasitic equivalent parallel resistance of L1. C2 should first be set to 0 and C1 should be chosen as high as possible (not greater than 39pF), while maintaining an RP of L1 that allows for the desired ROUT. If the self-resonant frequencies of the selected C1 produce unsatisfactory linearity performance, their values may be reduced and compensated for by including C2 capacitor with a value chosen to maintain the desired FIF frequency. L2 and C3 serve dual purposes. L2 serves as an output bias choke, and C3 serves as a series DC block. In addition, L2 and C3 may be chosen to form an impedance matching network if the input impedance of the IF filter is not equal to ROUT. Otherwise, L2 is chosen to be large (suggested 120nH) and C3 is chosen to be large (suggested 22nF) if a DC path to ground is present in the IF filter, or omitted if the filter is DC-blocked. 8-12 Rev A2 040107 RF2861 Differential IF Matching C2 IF Saw IF+ VCC IF+ IF- 10 4 9 5 L1 R C1 IF- L2 33 nF C2 L1 L1 and C1 are chosen to resonate at the desired IF frequency. C1 can be omitted and the value of L1 increased and utilized solely as a choke to provide VCC to the open-collector outputs, but it is strongly recommended that at least some small-valued C1 (a few pF) be retained for better mixer linearity performance. R is normally selected to match the input impedance of the IF filter. However, mixer performance can be modified by selecting an R value that is different from the IF filter input impedance, and inserting a conjugate matching network between the Resistive Output Network and the IF filter. C2 serve dual purposes. C2 serves as a series DC block when a DC path to ground is present in the IF filter. In addition, C2 may be chosen to improve the combine performance of the mixer and IF filter. L2 should choose to resonate with the internal capacitance of the SAW filter. Usually, SAW filter has some capacitance. Otherwise, L2 could be eliminated. A practical approach to obtain the differential matching is to tune the mixer to the correct load point for gain, IIP3, and NF using the single-end current combiner method. Second, use the component values found in the single-end approach as starting point for the differential matching. The two-shunt capacitors in the single-end could be converted in a parallel capacitor and the parallel inductor in the single-end need to be converted in two-choke inductor. Third, set the DC block capacitors (C2) in the differential-end matching to a high value (i.e., 100pF) and retune the resonate circuit (C1 & L1) and the resistor (R) for optimal performance. After optimal performance is achieved and if performance is not satisfactory, decrease the series capacitors until optimal performance is achieved. Rev A2 040107 8-13 RF2861 PCB Design Requirements PCB Surface Finish The PCB surface finish used for RFMD’s qualification process is electroless nickel, immersion gold. Typical thickness is 3µinch to 8µinch gold over 180µinch nickel. PCB Land Pattern Recommendation PCB land patterns are based on IPC-SM-782 standards when possible. The pad pattern shown has been developed and tested for optimized assembly at RFMD; however, it may require some modifications to address company specific assembly processes. The PCB land pattern has been developed to accommodate lead and package tolerances. PCB Metal Land Pattern A = 0.64 x 0.28 (mm) Typ. B = 0.28 x 0.64 (mm) Typ. C = 1.50 (mm) Sq. Dimensions in mm. 1.50 Typ. 0.50 Typ. Pin 16 B B B B Pin 1 Pin 12 A A 0.50 Typ. A A C A A A A 0.75 Typ. 1.50 Typ. 0.55 Typ. B B B B Pin 8 0.55 Typ. 0.75 Typ. Figure 1. PCB Metal Land Pattern (Top View) 8-14 Rev A2 040107