RF2905 11 433/868/915MHZ FM/FSK/ASK/OOK TRANSCEIVER Typical Applications • Wireless Meter Reading • Wireless Data Transceiver • Keyless Entry Systems • Wireless Security Systems • 433/868/915MHz ISM Band Systems • Battery Powered Portable Devices 9.00 + 0.20 sq. The RF2905 is a monolithic integrated circuit intended for use as a low cost FM transceiver. The device is provided in 7mmx7mm, 48-lead plastic LQFP packaging and is designed to provide a fully functional FM transceiver. The chip is intended for linear (AM, FM) or digital (ASK, FSK, OOK) applications in the North American 915MHz ISM band and European 433MHz and 868MHz ISM bands. The integrated VCO, dual modulus/dual divide (128/129 or 64/65) prescaler, and reference oscillator require only the addition of an external crystal to provide a complete phase-locked oscillator. 0.35 0.25 0.50 7.00 + 0.10 sq. 0.22 + 0.05 Dimensions in mm. 7° MAX 0° MIN 0.60 + 0.15 0.10 Optimum Technology Matching® Applied VREF P LOCK DET OSC B1 OSC E OSC B2 Si CMOS LOOP FLT SiGe HBT RESNTR+ Si Bi-CMOS RESNTR- GaAs MESFET MOD IN GaAs HBT LVL ADJ ü Si BJT 47 34 31 30 41 42 43 40 39 38 Gain Control TX OUT 3 RX IN 5 LNA OUT 7 MIX IN 9 MIX OUT+ 11 MIX OUT- 12 0.127 Package Style: LQFP-48, 7x7 11 Features • Fully Monolithic Integrated Transceiver • 2.7V to 5.0V Supply Voltage • Narrow Band and Wide Band FM/FSK Lock Detector Phase Detector & Charge Pump Ref Select 37 OSC SEL 45 PRESCL OUT Prescaler 128/129 or 64/65 36 MOD CTRL 35 DIV CTRL • 300MHz to 1000MHz Frequency Range • 10dB Cascaded Noise Figure • 10mW Output Power at 433MHz 24 RSSI Linear RSSI 25 FM OUT 13 14 15 16 17 18 20 21 22 28 27 23 IF1 IN+ IF1 IN- IF1 BP+ IF1 BP- IF1 OUT IF2 IN VREF IF IF2 BP+ IF2 BP- IF2 OUT DEMOD IN MUTE 26 DATA OUT Functional Block Diagram Rev B11 010516 1.40 + 0.05 Ordering Information RF2905 RF2905 PCBA-L RF2905 PCBA-M RF2905 PCBA-H 433/868/915MHz FM/FSK/ASK/OOK Transceiver Fully Assembled Evaluation Board (433MHz) Fully Assembled Evaluation Board (868MHz) Fully Assembled Evaluation Board (915MHz) RF Micro Devices, Inc. 7628 Thorndike Road Greensboro, NC 27409, USA Tel (336) 664 1233 Fax (336) 664 0454 http://www.rfmd.com 11-53 TRANSCEIVERS Product Description RF2905 Absolute Maximum Ratings Parameter Ratings Unit Supply Voltage Control Voltages Input RF Level Output Load VSWR Operating Ambient Temperature Storage Temperature -0.5 to +5.5 -0.5 to +5.0 +10 50:1 -40 to +85 -40 to +150 VDC VDC dBm Parameter °C °C Caution! ESD sensitive device. RF Micro Devices believes the furnished information is correct and accurate at the time of this printing. However, RF Micro Devices reserves the right to make changes to its products without notice. RF Micro Devices does not assume responsibility for the use of the described product(s). Specification Min. Typ. Max. Unit 300 to 1000 MHz 300 to 1000 64/65 or 128/129 50 -75 MHz Ω dBc/Hz -100 dBc/Hz Condition T=25 °C, VCC =3.6V, Freq=915MHz Overall RF Frequency Range VCO and PLL Section VCO Frequency Range Prescaler divide ratio Prescaler Output Impedance PLL Phase Noise Reference Frequency Crystal RS Charge Pump Current TBD 50 -40 17 100 +40 Freq=915MHz, 10kHz Offset, 5kHz Loop Bandwidth Freq=915MHz, 100kHz Offset, 5kHz loop Bandwidth MHz Ω µA Transmit Section Max Modulation Frequency Min Modulation Frequency Maximum Power Level TRANSCEIVERS 11 Power Control Range Power Control Sensitivity Max FM Deviation Antenna Port Impedance Antenna Port VSWR Modulation Input Impedance Harmonics Spurious 2 MHz Set by loop filter bandwidth +7 +10 0 +3 8 12 10 200 dBm dBm dB dB/V kHz 50 Ω 1.5:1 4 kΩ dBc dBc -23 Freq=433MHz Freq=915MHz Instantaneous frequency deviation is inversely proportional with the modulation voltage TX ENABL=“1”. RX ENABL=“0” TX Mode Compliant to Part 15.249 and I-ETS 300 220 Overall Receive Section Frequency Range Cascaded Voltage Gain Cascaded Noise Figure Cascaded Input IP3 RX Sensitivity LO Leakage RSSI DC Output Range RSSI Sensitivity RSSI Dynamic Range 11-54 -95 300 to 1000 35 23 10 -31 -26 -101 0.5 to 2.5 MHz dB dB dB dBm dBm dBm dBm V 25 80 mV/dB dB -70 70 Freq=433MHz Freq=915MHz Freq=433MHz Freq=915MHz IF BW =180kHz, Freq=915MHz, S/N=8dB RLOAD =51kΩ Rev B11 010516 RF2905 Parameter Specification Min. Typ. Max. Unit 23 16 4.8 5.5 -27 -20 -37 -30 50 dB dB dB dB dBm dBm dBm dBm Ω Condition LNA Voltage Gain Noise Figure Input IP3 Input P1dB Antenna Port Impedance Antenna Port VSWR Output Impedance 1.5:1 Open Collector Open Collector Ω Ω 8 7 10 17 -21 -17 -31 -28 dB dB dB dB dBm dBm dBm dBm VPP Mixer Conversion Voltage Gain Noise Figure (SSB) Input IP3 Input P1dB Maximum Output Voltage 433MHz 915MHz 433MHz 915MHz 433MHz 915MHz 433MHz 915MHz RX ENABL=“1”. TX ENABL=“0” RX Mode 433MHz 915MHz Single-ended configuration 433MHz 915MHz 433MHz 915MHz 433MHz 915MHz 433MHz 915MHz Balanced First IF Section IF Frequency Range Voltage Gain Noise Figure IF1 Input Impedance IF1 Output Impedance 0.1 10.7 34 13 330 330 25 10.7 60 330 1 10 500 >1 25 MHz dB dB Ω Ω IF=10.7MHz, ZL =330Ω Second IF Section 500 MHz dB Ω kΩ kΩ Ω ΜΩ kHz Data Output Bandwidth 500 kHz Data Output Level 0.3 FM Output DC Level FM Output AC Level Rev B11 010516 0.1 VCC -0.3 2.6 200 V V mVPP 11 IF=10.7MHz At IF2 OUT- pin 3dB Bandwidth, Dependent upon IF bandwidth and Discriminator. 3dB Bandwidth, ZLOAD=1MΩ || 3pF; Dependent upon IF bandwidth and Discriminator. ZLOAD=1MΩ || 3pF; Output voltage is proportional with the instantaneous frequency deviation. ZLOAD>10kΩ ZLOAD>10kΩ 11-55 TRANSCEIVERS IF Frequency Range Voltage Gain IF2 Input Impedance IF2 Output Impedance Demod Input Impedance FM Output Impedance Data Output Impedance FM Output Bandwidth RF2905 Parameter Specification Min. Typ. Max. Unit Condition Power Down Control Logical Controls “ON” Logical Controls “OFF” Control Input Impedance Turn On Time Turn Off Time RX to TX and TX to RX Time 2.0 Voltage supplied to the input Voltage supplied to the input 4 4 4 V V Ω ms ms ms 34.5 13.5 12 1 V V mA mA mA µA 10 mA Specifications Operating limits TX Mode, LVL ADJ=3.6V TX Mode, LVL ADJ=0V RX Mode Power Down Mode which sets: PLL ENABL, TX ENABL, RX ENABL, LVL ADJ, OSC SEL, and MUTE=0V PLL Only Mode 1.0 25k Reference Crystal=7.075MHz Dependent upon reference crystal. Higher frequencies reduce turn on/off times Power Supply Voltage Current Consumption 22 8 7 3.6 2.7 to 5.0 25 10 9 5.3 8 TRANSCEIVERS 11 11-56 Rev B11 010516 RF2905 Pin 1 2 3 Function RX ENABL TX ENABL TX OUT Description Enable pin for the receiver circuits. RX ENABL>2.0V powers up all receiver functions. RX ENABL<1.0V turns off all receiver functions except the PLL functions and the RF mixer. Enables the transmitter circuits. TX ENABL>2.0V powers up all transmitter functions. TX ENABL<1.0V turns off all transmitter functions except the PLL functions. Interface Schematic 50 kΩ RX ENABL 20 kΩ TX ENABL 40 kΩ RF output pin for the transmitter electronics. TX OUT output impedance is a low impedance when the transmitter is enabled. TX OUT is a high impedance when the transmitter is disabled. VCC 20 TX OUT 4 GND2 5 RX IN Ground connection for the 40dB IF limiting amplifier and Tx PA functions. Keep traces physically short and connect immediately to ground plane for best performance. RF input pin for the receiver electronics. RX IN input impedance is a low impedance when the transmitter is enabled. RX IN is a high impedance when the receiver is disabled. RX IN 500 GND1 7 LNA OUT 8 9 GND3 MIX IN 10 GND5 11 MIX OUT+ 12 MIX OUT- Rev B11 010516 Ground connection for RF receiver functions. Keep traces physically short and connect immediately to ground plane for best performance. Output pin for the receiver RF low noise amplifier. This pin is an open collector output and requires an external pull up coil to provide bias and tune the LNA output. VCC LNA OUT Same as pin 4. RF input to the RF Mixer. An LC matching network between LNA OUT and MIX IN can be used to connect the LNA output to the RF mixer input in applications where an image filter is not needed or desired. 11 MIX IN GND5 is the ground connection shared by the input stage of the transmit power amplifier and the receiver RF mixer. Complementary (with respect to pin 12) IF output from the RF mixer. MIX OUT+ Interfaces directly to 10.7MHz ceramic IF filters as shown in the application schematic. A pull-up inductor and series matching capacitor should be used to present a 330Ω termination impedance to the 15 pF ceramic filter. Alternately, an IF tank can be used to tailor the IF freGND5 quency and bandwidth to meet the needs of a given application. IF output from the RF mixer. For a balanced mixer output, pull-up induc- See pin 11. tors from pin 11 and 12 to VCC and a capacitor between the pins should be used. The sum of the total pull-up inductance should be used to resonate the capacitor between pins 11 and 12. DC blocking capacitors of 10nF can then be used to connect the balanced output to IF1 IN+ (pin 13) and IF1 IN- (pin 14). GND5 MIX OUT- 15 pF GND5 11-57 TRANSCEIVERS 6 RF2905 Pin 13 Function IF1 IN+ Description Balanced IF input to the 40dB limiting amplifier strip. A 10nF DC blocking capacitor is required on this input. Interface Schematic IF1 BP+ 60 kΩ IF1 BP60 kΩ 330 330 IF1 IN+ 14 IF1 IN- 15 IF1 BP+ 16 IF1 BP- 17 IF1 OUT 18 IF2 IN Functionally the same as pin 13 except inverting node amplifier input. In single-ended applications, this input should be bypassed directly to ground through a 10nF capacitor. DC feedback node for the 40dB limiting amplifier strip. A 10nF bypass capacitor from this pin to ground is required. Same as pin 15. IF1 IN- See pin 13. See pin 13. See pin 13. IF output from the 40dB limiting amplifier. The IF1 OUT output presents a nominal 330Ω output resistance and interfaces directly to 10.7MHz ceramic filters. IF1 OUT Balanced IF input to the 60dB limiting amplifier strip. A 10nF DC blocking capacitor is required on this input. The IF2 IN input presents a nominal 330Ω input resistance and interfaces directly to 10.7MHz ceramic filters. IF2 BP+ 60 kΩ IF2 BP60 kΩ 330 330 IF2 IN TRANSCEIVERS 11 19 GND6 20 VREF IF 21 IF2 BP+ 22 23 IF2 BPMUTE Ground connection for 60dB IF limiting amplifier. Keep traces physically short and connect immediately to ground plane for best performance. DC voltage reference for the IF limiting amplifiers. A 10nF capacitor from this pin to ground is required. DC feedback node for the 60dB limiting amplifier strip. A 10nF bypass capacitor from this pin to ground is required. Same as pin 21. This pin is used to mute the data output (DATA OUT). MUTE>2.0V turns the DATA OUT signal on. MUTE<1.0V turns the DATA OUT signal off. The MUTE signal should be logic low in the Sleep Mode. See pin 18. See pin 18. 75 kΩ MUTE 25 kΩ 24 RSSI A DC voltage proportional to the received signal strength is output from this pin. The output voltage range is 0.5V to 2.5V, into 51k Ω load, and increases with increasing signal strength. VCC RSSI 25 26 11-58 FM OUT DATA OUT Linear output from the FM demodulator. This pin is used in analog applications when signal fidelity is important. This output is inverted for low side injection of the LO and normal for high side injection. Demodulated data output from the demodulator. Output levels on this are TTL/CMOS compatible. The magnitude of the load impedance is intended to be 1MΩ or greater. When using a RF2905 transmitter and receiver back to back a data inversion will occur, when the LO is low side injected. A high side injection will add an inversion of the Rx data. FM OUT DATA OUT Rev B11 010516 RF2905 Pin 27 28 Function DEMOD IN IF2 OUT 29 VCC6 30 RESNTR+ Description This pin is the input to the FM demodulator. This pin is NOT AC coupled. Therefore, a DC blocking capacitor is required on this pin to avoid shorting the demodulator input with the LC tank. A ceramic discriminator or DC blocked LC tank resonant at the IF should be connected to this pin. Interface Schematic VCC 10 kΩ DEMOD IN Balanced IF output from the 60dB limiting amplifier strip. This pin is intended to be connected to pin 27 through a 4pF (suggested) capacitor and an FM discriminator circuit. This pin is used is supply DC bias to the second IF amplifier, Demodulator and Data Slicer. An IF bypass capacitor should be connected directly to this pin and returned to ground. A 10nF capacitor is recommended for 10.7MHz IF applications. This port is used to supply DC voltage to the VCO as well as to tune the center frequency of the VCO. Equal value inductors should be connected to this pin and pin 31 although a small imbalance can be used to tune in the proper frequency range. IF2 OUT ESNTR+ RESNTR- 4 kΩ MOD IN RESNTRVCC2 33 GND4 34 MOD IN 35 DIV CTRL 36 MOD CTRL 37 OSC SEL 38 OSC B2 Rev B11 010516 See RESNTR+ description. See pin 30. This pin is used is supply DC bias to the VCO, prescaler, and PLL. An RF bypass capacitor should be connected directly to this pin and returned to ground. A 22pF capacitor is recommended for 915MHz applications. A 68pF capacitor is recommended for 433MHz applications. GND4 is the ground shared on chip by the VCO, prescaler, and PLL electronics. FM analog or digital modulation can be imparted to the VCO through See pin 30. this pin. The VCO varies in accordance to the voltage level presented to this pin. To set the deviation to a desired level, a voltage divider referenced to Vcc is the recommended. This deviation is also dependent upon the overall capacitance of the external resonant circuit. This pin is used to select the desired prescaler divisor. A logic high (DIVCTRL>2.0V) selects the 64/65 divisor. A logic low DIV CTL (DIVCTRL<1.0V) selects the 128/129 divisor. This pin is used to select the prescaler modulus. A logic high (MOD CTRL>2.0V) selects 64 or 128 for the prescaler divisor. A logic low (MOD CTRL<1.0V) selects 65 or 129 for the prescaler divisor. Due to design timing constraints, the prescaler in the divide by 65 or 129 modes has a limited frequency range for accurate operation. These two modes are not recommended for use from 400MHz to 460MHz. A logic high (OSC SEL>2.0V) applied to this pin powers on reference oscillator 2 and powers down reference oscillator 1. A logic low (OSC SEL<1.0V) applied to this pin powers on reference oscillator 1 and powers down reference oscillator 2. This pin is connected directly to the reference oscillator 2 transistor base. The intended reference oscillator configuration is a modified Colpitts. 11 TRANSCEIVERS 31 32 MOD CTL OSC B1 OSC B2 OSC E 11-59 RF2905 Pin 39 Function OSC E 40 OSC B1 41 LOOP FLT Description Interface Schematic This pin is connected directly to the emitter of the reference oscillator See pin 38. transistors. This pin is connected directly to the reference oscillator 1 transistor See pin 38. base. The intended reference oscillator configuration is a modified Colpitts. Output of the charge pump, and input to the VCO control. An RC netVCC work from this pin to ground is used to establish the PLL bandwidth. LOOP FLT 42 VREF P 43 LOCK DET Bypass pin for the prescaler reference voltage. A 33nF capacitor to ground is needed to suppress reference spurs in the device. This value may be different for different PCB arrangements. This pin provides an analog output indicating the lock status of the PLL. The amplitude of this signal is typically 200mVPP around a DC level of VCC-0.1V. VCC 20 kΩ LOCK DET 44 VCC1 45 PRESCL OUT 46 VCC3 47 LVL ADJ TRANSCEIVERS 11 This pin is used to supply DC bias to the LNA, Mixer, first IF Amp, and Bandgap reference. A RF bypass capacitor should be connected directly to this pin and returned to ground. A 22pF capacitor is recommended for 915MHz applications. A 68pF capacitor is recommended for 433MHz applications. Dual-modulus/Dual-divide prescaler output. The output can be interfaced to an external PLL IC for additional flexibility in frequency programming. PRESCL OUT This pin is used to supply DC bias and collector current to the transmitter PA. A RF bypass capacitor should be connected directly to this pin and returned to ground. A 22pF capacitor is recommended for 915MHz applications. A 68pF capacitor is recommended for 433MHz applications. This pin is used to vary the transmitter output power. An output level adjustment range greater than 12dB is provided through analog voltage control of this pin. DC current of the transmitter power amp ia also reduced with output power. This pin MUST be low when the transmitter is disabled. 40 kΩ LVL ADJ 400 48 11-60 PLL ENABL This pin is used to power up or down the VCO and PLL. A logic high (PLLENABL>2.0V) powers up the VCO and PLL electronics. A logic low (PLLENABL<1.0V) powers down the PLL and VCO. 4 kΩ 50 kΩ PLL ENABL Rev B11 010516 RF2905 RF2905 Theory of Operation and Application Information In its basic form, the RF2905 can implement a two-way half duplex FSK transceiver with the addition of some crystals, filters, and passive components. There are two reference crystals that allow for the transmit carrier and the receiver LO to be independently generated with a common PLL and VCO. The receiver IF section is optimized to interface with low cost 10.7MHz ceramic filters but has a -3 dB bandwidth of 25MHz and can still be used (with lower gain) at higher frequency with the other type of filters. The PA output and LNA input are available on separate pins and are designed to be connected together through a DC blocking capacitor. In the Transmit mode, the PA will have a 50Ω impedance and the LNA will be a high impedance. In Receive mode, the LNA will have a 50Ω interface and the PA will have a high impedance. This eliminates the need for a TX/RX switch and allows a single RF filter to be used in transmit and receive modes. Separate access to the PA and LNA allow the RF2905 to interface with external components such as higher power PA’s, lower NF LNA’s, upconverters, and downconverters for a variety of implementations. FM/FSK SYSTEMS The MOD IN pin drives an internal varactor for modulating the VCO. This pin can be driven with a voltage level needed to generate the desired deviation. This voltage can be carried on a DC bias to select the desired slope (deviation/volt) for FM systems. Or, a resistor divider network referenced to Vcc or ground can divide down logic level signals to the appropriate level for a desired deviation in FSK systems. On the receiver demod, two outputs are available, an analog FM output and a digital FSK output. The FM output is a buffered signal coming off of the quadrature demodulator. The digital output is generated by a data slicer that is DC coupled differentially to the demodulator. An on-chip 1.6MHz RC filter is provided at the demodulator output to filter the undesired 2xIF product. This balanced data slicer has a speed advantage over a conventional adaptive data slicer where a large capacitor is used to provide DC reference for bit decision. Since the balanced data slicer does not have to Rev B11 010516 charge a large capacitor, the RF2905 exhibits a very fast response time. For best operation of the on-chip data slicer, FM deviation needs to exceed the carrier frequency error anticipated between the receiver and transmitter with margin. The data slicer itself is a transconductance amp and the DATA OUT pin is capable of driving rail to rail output only into a very high impedance and small capacitance. The amount of capacitance will determine the bandwidth of the DATA OUT. At a 3pF load, the bandwidth is in excess of 500kHz. The rail to rail output of the data slicer is also limited by the frequency deviation and bandwidth of the IF filters. With the 180kHz bandwidth filters on the eval boards, the rail to rail output is limited to less than 140kHz. Choosing the right IF bandwidth and deviation vs. data rate (mod index) is important in evaluating the applicability of the RF2905 for a given data rate. While this type of data slicer is best for wideband deviation, it can also work for narrowband if care is taken to minimize frequency differences. By loading down the DATA OUT pin, the output will be limited to a small data signal on a DC carrier. With this signal, an external data slicer can be used to achieve higher data rates or improve performance in narrow deviations. Alternatively, an AFC loop can be added to correct for frequency errors with a few external components. For FM or FSK modulation, an internal varactor is used to directly modulate the VCO with the baseband data. The primary consideration when directly modulating the VCO is the data rate verses PLL loop bandwidth. The PLL will track out the modulation to the extent of its loop bandwidth which distorts the modulating data. Therefore, the lower frequency components of the modulating data should be 5 to 10 times the loop bandwidth to minimize the distortion. The lower frequency components are generated by long strings of 1’s or 0’s in the data stream. By limiting the number of consecutive, same bits, the lower frequency component can be set. In addition, the data stream should be balanced to minimize distortion. Using a coding pattern such as Manchester is highly recommended to optimize system performance. The PLL loop bandwidth is important in several other system parameters. For example, switching from transmit to receive requires the VCO to retune to another frequency. The switching speed is proportional to the loop bandwidth, the higher the loop bandwidth, the 11-61 11 TRANSCEIVERS The RF2905 is a part of a family of low-power RF transceiver IC’s that was developed for wireless data communication devices operating in the European 433/ 868MHz ISM bands or 915MHz US ISM band.This IC has been implemented in a 15GHz silicon bipolar process technology that allows low-power transceiver operation in a variety of commercial wireless products. RF2905 faster the switching times. Phase noise of the VCO is another factor. Phase noise outside of the loop bandwidth is due to the noise of the VCO itself rather than the crystal reference. A design trade-off must be made here in selecting a PLL loop bandwidth with acceptable phase noise and switching characteristics and minimal distortion of the modulation data. TRANSCEIVERS 11 AM/ASK SYSTEMS The transmitter of the RF2905 has an output power level adjustment (LVL ADJ) that can be used to provide approximately 18dB of power control for amplitude modulation. The RSSI output of the receiver section can be used to recover the modulation. The RSSI output is from a current source and needs to have a resistor to convert to a voltage. A 51kΩ resistive load will produce an RSSI voltage of 0.7V to 2.5V, typically. A parallel capacitor is suggested to limit the bandwidth and filter noise. For ASK applications, the 18dB range of the LVL ADJ does not produce enough voltage swing in the RSSI for reliable communication. The OnOff keying (OOK) is suggested to provide reliable communications. To achieve this, both the LVL ADJ and TX ENABL need to be controlled together (please note that LVL ADJ cannot be left high when TX ENABL is low). This will provide a on/off ratio of >50dB. One unfortunate consequence of modulating this way is VCO pulling by the power amp. This results in a spurious output outside the desired transmit band as the PLL momentarily loses lock and reacquires. This can be avoided by pulse shaping the TX data to slow the change in the VCO load to a pace that the PLL can track with its given loop bandwidth. The loop bandwidth can also be increased to allow it to track faster changes due to load pulling. be needed to separate the DC of RX IN and TX OUT. These are RF signals and care should be taken to route these signals keeping them physically short. Because of the 50Ω/high impedance nature of these two signals, they may be connected together into a signal 50Ω device such as a filter. An external LNA or PA can be used, if desired, but an external RX/TX switch may be required. The VCO is a very sensitive block in this system. RF signals feeding back into the VCO either radiated or coupled by traces may cause the PLL to become unlocked. The trace(s) for the anode of the tuning varactor should also be kept short. The layout of the resonators and varactor are very important. The capacitor and varactor should be closest to the RF2905 pins and the trace length should be as short as possible. The inductors can be placed further away and any trace inductance can be compensated by reducing the value of the inductors. Printed inductors may also be used with careful design. For best results, the physical layout should be as symmetrical as possible. Figure 1 is a recommended layout pattern for the VCO components. When using loop bandwidths lower than the 5kHz shown on the eval board, better filtering of the Vcc at the resonators (and lower Vcc noise as well) will help reduce phase noise of the VCO. A series resistor of 100Ω to 200Ω and a 1µF or larger capacitor can be used. Loop Voltage GND 33 For the ASK/OOK receiver demodulator, an external data slicer is required. The RSSI output is used to provide both the filtered data and a very low pass filtered (relative to the data rate) DC reference to a data slicer. Because the very low pass filter has a slow time constant, a longer preamble may be required to allow for the DC reference to get to a stable state. Here, as in the case of the FSK transmitter, the data pattern also affects the DC reference and the reliability of the received data. Again, a coding scheme such as Manchester such should be used to improve data integrity. APPLICATION AND LAYOUT CONSIDERATIONS Both the RX IN and TX OUT have a DC bias on them. Therefore, DC blocking caps are required. If the RF filter has DC blocking characteristics like a ceramic dielectric filter, then only 1 DC blocking capacitor would 11-62 32 31 30 29 28 Not to Scale Representative of Size GND Vcc Figure 1. Recommended VCO Layout For the interface between the LNA/mixer, the coupling capacitor should be as close to the RF2905 pins as possible with the bias inductor being further away. Once again, the value of the inductor can be changed to compensate to trace inductance. The output impedance of the LNA is in the order of several kΩ which makes matching to 50Ω very hard. If image filtering is desired, a high impedance filter is recommended. Rev B11 010516 RF2905 The quad tank of the discriminator can be implemented with ceramic discriminators available from a couple of sources. This design works well for wideband applications and where the temperature range is limited. The temperature coefficient of a ceramic discriminator can be in the order of +/- 50ppm per degree C. An automatic frequency control loop can be implemented using the DC level of the FM OUT for feedback to an external varactor on the reference crystal. An alternative to the ceramic discriminator is a LC tank. Figure 2 shows a schematic implementation of a LC tank. To lock faster, we need to minimize C. 1. To this end, use the divide by 128 rather than the 64, and a correspondingly lower frequency reference crystal to achieve the desired output frequency. 2. Design the loop filter for the minimum phase margin possible without causing loop instability problems; this allows C to be kept at a minimum. 3. Design the loop filter for the highest loop cut frequency possible without distorting low frequency modulation components; this also allows C to be kept at a minimum. 28 39 pF 3.3 µH 4-22 pF R opt. C16 10 nF Figure 2. LC Type Discriminator Circuit The DEMOD IN pin has a DC bias on it and must be DC blocked. This can be done either at the pin or at the ground side of the LC tank (this must also be done if a parallel resistor is used with a ceramic discriminator). The decision whether to used a LC or a ceramic discriminator should be based upon the frequency deviation in the system, discriminator Q needed, and frequency and temperature tolerances. Tuning of the LC tank is required to overcome the component tolerances in the tank. PREDICTING AND MINIMIZING PLL LOCK TIME The RF2905 implements a conventional PLL on chip, with a VCO followed by a prescaler dividing the output frequency down to be compared with a signal from the reference oscillator. The output of the phase discriminator is a sequence of pulse width modulated current pulses in the required direction to steer the VCO’s control voltage to maintain phase lock, with a loop filter integrating the current pulses. The lock time of this PLL is a combination of the loop transient response time and the slew rate set by the phase discriminator output current combined with the magnitude of the loop filter capacitance. A good approximation for total lock time of the RF29.5 is: CRYSTAL SELECTION Several issues arise in the selection of the crystals. Timing specifications such as start-up and switching are related to the crystal specifications, as well as external circuitry. The tolerance of the crystals are also an issue in optimum radio performance. In general, tighter tolerance crystals lead to better performance and are more critical to higher data rates. Frequency offsets between the TX crystal, RX crystal and discriminator generate duty cycle variations in the receive demodulator. The crystals used on the RF2905 evaluation boards are specified as a parallel resonant, 30pF crystal with a maximum ESR of 80Ω. The initial tolerance is +20ppm and temperature stability is +30ppm for -10°C to 70°C. The transistor oscillator will work with a variety of different crystals and the final crystal specifications should be evaluated for each application. Faster start-up or switching times are achievable by specifying crystals with low motion inductance and low motional resistance. Additionally, the feedback caps of the oscillator can be changed to increase the voltage on the crystal. Generally, crystals in the leaded HC-49U packages will provide better start-up times than the smaller surface-mount types used on the evaluation board. Lock time=D/fc+35000*C*dV Where D is a factor to account for the loop damping. For loops with low phase margin (30° to 40°), use D=2 whereas for loops with better phase margin (50° to 60°), use D=1. fc is the loop cut frequency. C is the sum of all shunt capacitors in the loop filter. dV is the required step voltage change to produce the desired frequency change during the transient. Rev B11 010516 11-63 11 TRANSCEIVERS C17 7 pF 27 RF2905 PLL ENABL LVL ADJ VCC3 PRESCL OUT VCC1 LOCK DET VREF P LOOP FLT OSC B1 OSC E OSC B2 OSC SEL Pin Out 48 47 46 45 44 43 42 41 40 39 38 37 RX ENABL 1 36 MOD CTRL TX ENABL 2 35 DIV CTRL TX OUT 3 11-64 GND2 4 33 GND4 RX IN 5 32 VCC2 GND1 6 31 RESNTR- LNA OUT 7 30 RESNTR+ 13 14 15 16 17 18 19 20 21 22 23 24 MUTE RSSI 25 FM OUT IF2 BP- MIX OUT- 12 IF2 BP+ 26 DATA OUT VREF IF MIX OUT+ 11 GND6 27 DEMOD IN IF2 IN GND5 10 IF1 OUT 28 IF2 OUT IF1 BP- MIX IN 9 IF1 BP+ 29 VCC6 IF1 IN- GND3 8 IF1 IN+ TRANSCEIVERS 11 34 MOD IN Rev B11 010516 RF2905 Application Schematic 915MHz VCC 4.7 uF LOCK DET+ 3.9 kΩ 10 nF 10 Ω 10 nF 22 pF 22 pF 4.7 nH 47 nF 4.7 nH D1 LVL ADJ 2.7 kΩ 3.3 nF TX DATA 100 pF 10 Ω 100 100 pF pF 0.1 uF 5 pF VCC 10 nF 22 pF PLL ENABL 47 46 34 48 RX ENABL 1 TX ENABL 2 Filter 31 30 43 41 42 40 39 38 Gain Control Lock Detector 100 pF 22 pF Phase Detector & Charge Pump Ref Select 5 100 pF 10 Ω 10 nH 10 nF 22 pF Prescaler 128/129 or 64/65 7 VCC 10 Ω VCC 32 3 VCC 44 10 nF 37 OSC SEL 45 PRESCL OUT 36 MOD CTRL 35 DIV CTRL 10 pF 9 11 8.2 µH 24 Linear RSSI 10 Ω 25 FM OUT 26 DATA OUT 12 10 nF 22 pF 11 pF 13 14 15 16 17 18 20 21 22 Filter 10 nF 10 nF 27 29 10 nF 10 nF RSSI 23 10 pF 51 kΩ 10 nF Filter 10 nF 28 5 pF FM Disc. MUTE 11 VCC Rev B11 010516 PLL LOOP BANDWIDTH ~5 kHz 22 pF 10 nF 10 Ω TRANSCEIVERS D1 : SMV1233-011 11-65 RF2905 Application Schematic 868MHz VCC 4.7 uF LOCK DET+ 3.9 kΩ 10 nF 10 Ω 10 nF 22 pF 22 pF 6.8 nH TX DATA LVL ADJ 47 nF 6.8 nH D1 100 pF 2.7 kΩ 3.3 nF 10 Ω 100 100 pF pF 0.1 uF 3 pF VCC 10 nF 22 pF PLL ENABL 47 46 34 48 RX ENABL 1 TX ENABL 2 Filter 31 30 43 41 42 40 39 38 Gain Control Lock Detector 100 pF 22 pF Phase Detector & Charge Pump Ref Select 5 100 pF 10 Ω 10 nH 10 nF 22 pF Prescaler 128/129 or 64/65 7 VCC 10 Ω VCC 32 3 VCC 44 10 nF 37 OSC SEL 45 PRESCL OUT 36 MOD CTRL 35 DIV CTRL 10 pF 9 24 Linear RSSI 10 Ω 11 8.2 uH 25 FM OUT 26 DATA OUT 12 10 nF 22 pF 11 pF 13 14 15 16 17 18 20 21 22 Filter 10 nF 10 nF 10 nF 27 29 10 nF 10 nF RSSI 23 10 pF 51 kΩ 10 nF Filter 11 28 5 pF FM Disc. MUTE TRANSCEIVERS VCC D1 : SMV1233-011 11-66 PLL LOOP BANDWIDTH ~5 kHz 22 pF 10 nF 10 Ω Rev B11 010516 RF2905 Application Schematic 433MHz VCC 4.7 uF LOCK DET+ 3.9 kΩ 10 nF 10 Ω 10 nF 22 pF 22 pF 27 nH TX DATA LVL ADJ 47 nF 27 nH D1 100 pF 2.7 kΩ 3.3 nF 10 Ω 100 100 pF pF 0.1 uF 3 pF VCC 10 nF 22 pF PLL ENABL 47 46 34 48 RX ENABL 1 TX ENABL 2 Filter 31 30 43 41 42 40 39 38 Gain Control Lock Detector 100 pF 22 pF Phase Detector & Charge Pump Ref Select 5 100 pF 10 Ω 47 nH 10 nF 22 pF Prescaler 128/129 or 64/65 7 VCC 10 Ω VCC 32 3 VCC 44 10 nF 37 OSC SEL 45 PRESCL OUT 36 MOD CTRL 35 DIV CTRL 33 pF 9 24 Linear RSSI 10 Ω 11 8.2 uH 25 FM OUT 26 DATA OUT 12 10 nF 22 pF 11 pF 13 14 15 16 17 18 20 21 22 Filter 10 nF 10 nF 27 29 10 nF 10 nF RSSI 23 10 pF 51 kΩ 10 nF Filter 10 nF 28 5 pF FM Disc. 11 MUTE D1 : SMV1233-011 Rev B11 010516 PLL LOOP BANDWIDTH ~5 kHz 22 pF 10 nF TRANSCEIVERS VCC 10 Ω 11-67 RF2905 Evaluation Board Schematic (Download Bill of Materials from www.rfmd.com.) P1 P 1-1 P 1-3 P2 P3 1 T X E N A B L P 2-1 1 LV L A D J 2 GND 2 GND 3 P LL E N A B L P 2-3 3 N /C P4 1 P 3-1 P 3-3 GND P 4-2 2 RX ENABL P 4-3 3 O SC SEL P 4-4 4 D IV C T R L P 4-5 5 M U TE C 34 4.7 µF M O D CTRL 2 GND 3 VCC S LIC E R IN R 10 50 kΩ C 29 1nF R 11 1M Ω C 28 10 nF R 21 50 kΩ P 5-1 3 4 1 LO C K D E T 2 GND C 32 10 nF C 33 22 pF C 41 3-10 pF R 23 0Ω C 24 100pF X 2* LV L A D J C 26 3.3 nF C 42 3-10 pF 48 RX ENABL 47 46 45 44 1 TX ENABL R 9* X 1* 42 41 40 39 38 O SC SEL 37 Lock D etector G ain C ontrol 2 43 R ef S elect C 1 100 pF 3 L6* L7* C 35* C 36* C 27 47nF C 25 C 23 100 pF100 pF P LL E N A B L J1 RF C 39* P rescaler 128/129 or 64/65 4 C2 100 pF R1 10 Ω L1* C3 10 nF C4 22 pF VCC 36 M OD CTRL 35 D IV C TR L J6 M O D IN 34 5 P hase D etector & C harge P um p 7 30 C 18* D1 10 27 11 26 C 16 10 nF C7 22 pF 12 R4 8.2 kΩ TRANSCEIVERS C8 10 pF C 22 10 nF L4* C 19 22 pF C 20 10 nF R 6 10 Ω R 13 1.5 kΩ C D F107B -A 0.001 J5 D A TA O U T J4 FM O U T 25 13 14 15 16 17 18 19 20 21 22 23 24 R 15 0Ω C9 C 10 C 11 10 nF 10 nF 10 nF F1 S FE C V 10.7 M S 3S -A -T C B W =180kH z R8 0Ω D IS C L2 8.2 uH C6 10 nF C 21 22 pF 28 C 17 4 pF R3 10 Ω L5* S M V 1233-011 29 Linear RSSI 9 VCC VCC R7 10 Ω 32 31 8 R 17 3.9 kΩ 33 6 C 5* 11 LO C K D E T U3 LM C 7211 R 18 TB D C ircuit not populated. O ptional Lock D etector or O O K D ata S licer R 16 TBD C 31 22 pF 1 Q1 2N 3904 C 38 0.1 µF C 30 10 nF 2 5 C 40 33 nF P5 R 12 10 Ω VCC 1 C 12 C 13 C 14 10 nF 10 nF 10 nF J3 C 15 1 nF R5 51 kΩ R 22 N /C M UTE S LIC E R IN F2 S FE C V 10.7 M S 3S -A -T C B W =180kH z R 14 C 37 0 Ω 120 pF J2 M IX O U T L3 2.2 µH 2905400-, 401-, 402- Te st O n ly N ot P o p ula te d B oard 11-68 C 35 (pF) L6 (nH ) L7 (nH ) C 39 (pF ) L1 (nH ) C 5 (pF) C 18 (pF) L4,L5(nH ) R 9 (kΩ) X 1 (M H z) L (433M H z) 8 22 22 8 47 35 3 27 2.4 6.78 X 2 (M H z) 6.612 M (868M H z) 4 8.2 Jum per N /C 10 10 5 4.7 2.7 13.577344 13.410156 H (915M H z) 4 8.2 Jum per N /C 10 10 5 4.7 2.7 7.15909 7.07549 Rev B11 010516 RF2905 Evaluation Board Layout Board Size 3.05” x 3.05” Board Thickness 0.031”, Board Material FR-4, Multi-Layer (Same board layout is used for the -L, -M, and -H versions.) TRANSCEIVERS 11 Rev B11 010516 11-69 RF2905 TRANSCEIVERS 11 11-70 Rev B11 010516 RF2905 TRANSCEIVERS 11 Rev B11 010516 11-71 RF2905 0.8 Swp Max 1.2GHz 2.0 0.6 RXonTXoff 1.0 LNA S11 RXoffTXoff 0. 4 0 3. 4.0 5.0 0.2 0.3GHz 10.0 4.0 5.0 3.0 2.0 1.0 0.8 0.6 0.4 0.2 0 10.0 0.3GHz -10.0 -0.2 -4. 0 -5.0 .0 .0 -2 -1.0 -0. 6 -0.8 Swp Min 0.3GHz Swp Max 1.2GHz 2.0 0.6 0.8 1.0 RF OUT S22 TXonRXoff 0. 4 11 -3 .4 -0 0 3. 4.0 5.0 0.2 10.0 10.0 4.0 5.0 3.0 2.0 1.0 0.8 0.6 0.4 0.2 0 TRANSCEIVERS 0.3GHz -10.0 -0.2 -4. 0 -5.0 .0 .0 -2 -1.0 -0.8 -0. 6 11-72 -3 .4 -0 Swp Min 0.3GHz Rev B11 010516 RF2905 RSSI Ω Freq. = 915 MHz, VCC = 3.6V, RLoad = 51 kΩ 2.5 Modulation Deviation Freq. = 915 MHz, VCC = 2.7 V, LVL ADJ = 2.7 V 600.0 500.0 Deviation From Carrier (kHz) RSSI Output (Volts) 2.0 1.5 1.0 400.0 300.0 200.0 0.5 100.0 0.0 -100.0 -80.0 -60.0 -40.0 0.0 0.5 1.0 Received Power (dBm) Modulation Deviation Freq. = 915 MHz, VCC = 3.3 V, LVL ADJ = 3.3 V 2.0 2.5 3.0 Modulation Deviation Freq. = 915 MHz, VCC = 5.0 V, LVL ADJ = 5.0 V 600.0 1200.0 500.0 1000.0 Deviation From Carrier (kHz) Deviation From Carrier (kHz) 1.5 MOD IN (Volts) 400.0 300.0 200.0 100.0 800.0 600.0 400.0 11 200.0 0.0 0.0 0.0 0.5 1.0 1.5 2.0 MOD IN (Volts) Rev B11 010516 2.5 3.0 3.5 0.0 1.0 2.0 3.0 4.0 5.0 6.0 MOD IN (Volts) 11-73 TRANSCEIVERS 0.0 -120.0 RF2905 RX Mode Current versus VCC Freq = 905 MHz 12.00 TX Power Output and ICC versus VCC at 905 MHz, LVL ADJ = VCC 10.00 40.00 Power(dBm) 9.00 Icc (mA) Icc(mA) 11.00 35.00 8.00 7.00 30.00 9.00 6.00 25.00 5.00 ICC (mA) RF P O (dBm) ICC (mA) 10.00 4.00 8.00 20.00 3.00 2.00 7.00 15.00 1.00 6.00 2.50 2.75 3.00 3.25 3.50 3.75 4.00 4.25 4.50 4.75 0.00 2.50 5.00 2.75 3.00 3.25 VCC (V) 30.0 10.0 4.75 10.00 5.00 30.0 0.0 20.0 -5.0 15.0 -5.0 15.0 11 -10.0 10.0 -10.0 10.0 -15.0 1.5 2.0 2.5 3.0 3.5 5.0 -15.0 4.0 ICC (mA) 25.0 ICC (mA) 5.0 RF P O (dBm) 20.0 RF P O (dBm) 0.0 5.0 0.0 LVL ADJ (V) 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 LVL ADJ (V) TX Power Output and ICC versus Level Adjust at 905 MHz, 3.6 V VCC 10.0 4.50 Icc (mA) 25.0 TRANSCEIVERS Icc (mA) 1.0 4.25 P out (dB) 5.0 0.5 4.00 TX Power Output and ICC versus Level Adjust at 868 MHz, 3.6 V VCC P out (dB) 0.0 3.75 VCC, LVL ADJ (V) TX Power Output and ICC versus Level Adjust at 433 MHz, 3.6 V VCC 10.0 3.50 30.0 P out (dB) Icc (mA) RF P O (dBM) 5.0 25.0 20.0 -5.0 15.0 -10.0 10.0 ICC (mA) 0.0 -15.0 5.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 LVL ADJ (V) 11-74 Rev B11 010516