RF2919 11 433/868/915MHZ ASK/OOK RECEIVER Typical Applications • Wireless Meter Reading • Remote Data Transfers • Keyless Entry Systems • Wireless Security Systems • 433/868/915MHz ISM Bands Systems Product Description The RF2919 is a monolithic integrated circuit intended for use as a low cost ASK/OOK receiver. The device is provided in 32-lead plastic packaging and is designed to provide a fully functional AM receiver. The chip is intended for applications in the North American 915MHz ISM band and European 433MHz and 868MHz ISM bands. The integrated VCO, +64 prescaler, and reference oscillator require only the addition of an external crystal to provide a complete phase-locked oscillator for single channel applications. A data comparator is included to provide logic level outputs. .284 .268 .006 .002 .020 .201 .193 .284 .268 .011 .007 .057 .053 .201 .193 7°MAX 0°MIN .030 .020 SiGe HBT Si CMOS LOOP FLT Si Bi-CMOS RESNTR+ GaAs MESFET RESNTR- GaAs HBT PD ! Si BJT 32 25 26 29 Package Style: LQFP-32 • Fully Monolithic Integrated Receiver • 2.7V to 5.0V Supply Voltage • Up to 256kbps Data Rates DC BIAS Phase Detector & Charge Pump 2 OSC E 30 OSC B 21 RSSI 20 MUTE 23 DATA OUT • 300MHz to 1000MHz Frequency Range • Power Down Capability • Analog or Digital Output 11 12 13 16 17 18 22 24 14 DATA IN- VREF IF 10 DATA IN+ 9 IF2 BP- Linear RSSI IF2 BP+ 8 IF2 IN MIX OUT IF1 BP- 6 IF1 OUT MIX IN 31 Prescaler ÷64 IF1 BP+ 4 IF1 IN- LNA OUT IF1 IN+ RX IN 11 Features Functional Block Diagram Rev A12 001113 Ordering Information RF2919 RF2919 PCBA-L RF2919 PCBA-M RF2919 PCBA-H 433/868/915MHz ASK/OOK Receiver Fully Assembled Evaluation Board, 433MHz Fully Assembled Evaluation Board, 868MHz Fully Assembled Evaluation Board, 915MHz RF Micro Devices, Inc. 7625 Thorndike Road Greensboro, NC 27409, USA Tel (336) 664 1233 Fax (336) 664 0454 http://www.rfmd.com 11-143 TRANSCEIVERS Optimum Technology Matching® Applied .005 RF2919 Absolute Maximum Ratings Parameter Ratings Unit Supply Voltage Control Voltages Input RF Level Output Load VSWR Operating Ambient Temperature Storage Temperature -0.5 to +5.5 -0.5 to +5.0 +10 50:1 -40 to +85 -40 to +150 VDC VDC dBm Parameter °C °C Caution! ESD sensitive device. RF Micro Devices believes the furnished information is correct and accurate at the time of this printing. However, RF Micro Devices reserves the right to make changes to its products without notice. RF Micro Devices does not assume responsibility for the use of the described product(s). Specification Min. Typ. Max. Unit 300 to 1000 MHz 300 to 1000 10 MHz ms -74 -98 dBc/Hz dBc/Hz MHz Ω µA Condition T=25 °C, VCC =3.6V, Freq=915MHz Overall RF Frequency Range VCO and PLL Section VCO Frequency Range PLL Lock Time PLL Phase Noise Reference Frequency Crystal RS Charge Pump Current 0.5 50 40 17 100 The PLL lock time is set externally by the bandwidth of the loop filter and start-up of the crystal. 915MHz, 5kHz loop BW, 10kHz offset 915 MHz, 5kHz loop BW, 100kHz offset Sink and source current Overall Receive Section Frequency Range RX Sensitivity LO Leakage RSSI DC Output Range RSSI Sensitivity RSSI Dynamic Range TRANSCEIVERS 11 -100 300 to 1000 -104 0.4 to 1.5 13 60 MHz dBm dBm V mV/dB dB 18 16 3.6 3.7 -8 -15 82-j86 77-j43 Open Collector dB dB dB dB dBm dBm Ω Ω Ω 15 7.5 17 17 -20 -15 -30 -26 dB dB dB dB dBm dBm dBm dBm -70 IF BW =150kHz, Freq=915MHz, S/N =8dB RL =24kΩ MUTE = 0 MUTE = 0 LNA Power Gain Noise Figure Input IP3 Input P1dB RX IN Impedance Output Impedance Mixer Conversion Power Gain Noise Figure (SSB) Input IP3 Input IP3 Input P1dB Input P1dB 433MHz, Matched to 50Ω 915MHz, Matched to 50Ω 433MHz 915MHz 915 MHz 915 MHz 433MHz (see Plots) 915MHz (see Plots) Single-ended configuration 433MHz, Matched to 50Ω 915MHz, Matched to 50Ω 433MHz, SSB Measurement 915MHz, SSB Measurement 433MHz 915MHz 433MHz 915MHz First IF Section IF Frequency Range Voltage Gain Noise Figure IF1 Input Impedance IF1 Output Impedance 11-144 0.1 10.7 34 13 330 330 25 MHz dB dB Ω Ω IF=10.7MHz, ZL =330Ω Rev A12 001113 RF2919 Parameter Specification Min. Typ. Max. Unit Condition Second IF Section IF Frequency Range Voltage Gain Noise Figure Input IP3 IF2 Input Impedance Data Output Impedance Data Output Rise/Fall Time Data Output Level 0.1 10.7 60 13 25 330 6.3 - j25.7 150 0.3 VCC -0.3 MHz dB dB mVPP Ω kΩ ns V IF=10.7MHz, internal to demod ZLOAD=1MΩ || 3pF ZLOAD=1MΩ || 3pF Power Down Control Logical Controls “ON” Logical Controls “OFF” Control Input Impedance Turn On Time 2.0 4 V V kΩ ms 4 ms 3.6 2.7 to 5.0 10 V V mA µA 1.0 25 Turn Off Time Voltage supplied to the input Voltage supplied to the input fXTAL =14.318MHz. Dependent on configuration. Power Supply Voltage Current Consumption 8 12 1 Specifications Operating limits RX Mode Power Down Mode TRANSCEIVERS 11 Rev A12 001113 11-145 RF2919 Pin 1 Function VCC1 2 RX IN 3 GND1 4 LNA OUT 5 GND2 6 MIX IN 7 8 GND3 MIX OUT 9 IF1 IN- Description Interface Schematic This pin is used to supply DC bias to the receiver RF circuits. An RF bypass capacitor should be connected directly to this pin and returned to ground. A 100pF capacitor is recommended for 915MHz applications. A 220pF capacitor is recommended for 433MHz applications. RF input pin for the receiver electronics. RX IN input impedance is a low impedance when enabled. RX IN is a high impedance when the receiver is disabled. RX IN Ground connection for RF receiver functions. Keep traces physically short and connect immediately to ground plane for best performance. Output pin for the receiver RF low noise amplifier. This pin is an open collector output and requires an external pull up coil to provide bias and tune the LNA output. LNA OUT GND2 is connection for the 40 dB IF limiting amplifier. Keep traces physically short and connect immediately to ground plane for best performance. RF input to the RF Mixer. An LC matching network between LNA OUT and MIX IN can be used to connect the LNA output to the RF mixer input in applications where an image filter is not needed or desired. MIX IN GND3 is the ground connection for the receiver RF mixer. IF output from the RF mixer. Interfaces directly to 10.7MHz ceramic IF filters as shown in the application schematic. A pull-up inductor and series matching capacitor should be used to present a 330Ω termination impedance to the ceramic filter. Alternately, an IF tank can be used to tailor the IF frequency and bandwidth to meet the needs of a given application. In addition to the matching components, a 15pF capacitor should be placed from this pin to ground. Balanced IF input to the 40dB limiting amplifier strip. A DC blocking capacitor is required on this input, 10nF is recommended. MIX OUT+ IF1 BP+ 60 kΩ VCC IF1 BP60 kΩ 330 Ω 11 TRANSCEIVERS 330 Ω IF1 IN+ 10 IF1 IN+ 11 IF1 BP+ 12 13 IF1 BPIF1 OUT 14 VREF IF 15 GND5 11-146 Functionally the same as pin 9 except non-inverting node amplifier input. In single-ended applications, this input should be bypassed directly to ground through a 10 nF capacitor. DC feedback node for the 40dB limiting amplifier strip. A 10nF bypass capacitor from this pin to ground is recommended. See pin 11. IF output from the 40dB limiting amplifier. The IF1 OUT output presents a nominal 330Ω output resistance and interfaces directly to 10.7MHz ceramic filters. IF1 IN- See pin 9. See pin 9. See pin 9. IF1 OUT DC voltage reference for the IF limiting amplifiers (typically 1.1V). A 10nF capacitor from this pin to ground is recommended. Ground connection for 60dB IF limiting amplifier. Keep traces physically short and connect immediately to ground plane for best performance. Rev A12 001113 RF2919 Pin 16 Function IF2 IN Description Interface Schematic Inverting input to the 60dB limiting amplifier strip. A 10 nF DC blocking capacitor is required on this input. The IF2 IN input presents a nominal 330Ω input resistance and interfaces directly to 10.7MHz ceramic filters. IF2 BP60 kΩ IF2 BP+ 60 kΩ 330 Ω IF2 IN 17 IF2 BP+ 18 19 IF2 BPVCC3 20 MUTE DC feedback node for the 60dB limiting amplifier strip. A 10nF bypass capacitor from this pin to ground is required. See pin 17. See pin 16. See pin 16. This pin is used is supply DC bias to the 60dB IF limiting amplifier. An IF bypass capacitor should be connected directly to this pin and returned to ground. A 10 nF capacitor is recommended for 10.7MHz IF applications. This pin is used to mute the data output (DATA OUT). MUTE>2.0V turns the DATA OUT signal on. MUTE<1.0V turns the DATA OUT signal off. 75 kΩ MUTE 25 kΩ 21 RSSI A DC voltage proportional to the received signal strength is output from this pin. The output voltage increases with increasing signal strength. VCC RSSI 23 DATA IN- DATA OUT 24 DATA IN+ 25 RESNTR- 26 27 RESNTR+ VCC2 28 GND4 Rev A12 001113 The inverting input of the data comparator. The RSSI is fed to this pin via a 50kΩ resistor. This input is available for a data filtering capacitor that provides noise and 2x IF rejection. The value of the capacitor can be calculated by C= 1/(2πF*50kΩ) where F is the desired 3dB bandwidth. DATA IN50 kΩ RSSI 11 The data comparator output which contains the modulating data recovered from the RSSI signal. Hysteresis can be added to the comparator by placing a very large (<1MΩ) resistor between pins 23 and 24.The magnitude of the load impedance is intended to be 1MΩ or greater. DATA OUT The non-inverting input of the data comparator. The RSSI is fed to this See pin 22. pin via a 50kΩ resistor. This input is available for a large filtering capacitor such that the modulation signal can be filtered out leaving a DC reference signal for the comparator. This port is used to supply DC voltage to the VCO as well as to tune the RESNTR+ center frequency of the VCO. Equal value inductors should be connected to this pin and pin 26. See pin 25. DATA IN+ 50 kΩ TRANSCEIVERS 22 RESNTR- See pin 25. This pin is used is supply DC bias to the VCO, prescaler, and PLL. An IF bypass capacitor should be connected directly to this pin and returned to ground. A 10nF capacitor is recommended for 10.7MHz IF applications. GND4 is the ground shared on chip by the VCO, prescaler, and PLL electronics. 11-147 RF2919 Pin 29 Function LOOP FLT Description Output of the charge pump, and input to the VCO control. An RC network from this pin to ground is used to establish the PLL bandwidth. Interface Schematic VCC LOOP FLT 30 OSC B 31 OSC E 32 PD ESD This pin is connected directly to the reference oscillator transistor base. The intended reference oscillator configuration is a modified Colpitts. A 100pF capacitor should be connected between pin 30 and pin 31. This pin is connected directly to the emitter of the reference oscillator transistor. A 100pF capacitor should be connected from this pin to ground. This pin is used to power up or down the RF2919. A logic high (PWR DWN >2.0 V) powers up the receiver and PLL. A logic low (PWR DWN <1.0 V) powers down circuit to standby mode. This diode structure is used to provide electrostatic discharge protection to 3kV using the Human body model. The following pins are protected: 1, 3, 5, 7-19, 21-24, 27-31. OSC B OSC E See pin 30. VCC TRANSCEIVERS 11 11-148 Rev A12 001113 RF2919 RF2919 Theory of Operation and Application Information OPERATION The ASK/OOK demodulation is accomplished by an on-chip data comparator. The RSSI output is internally routed through 50kΩ resistors to provide the inputs (DATA IN+ and DATA IN-) to the data comparator. Either input may be used as the data input with the other input used as the reference. A shunt capacitor can be added to the data input to provide filtering of noise and the second IF harmonic. The value of the data filtering capacitor is calculated by 1 = --------------------------------2πF ⋅ 16.7kΩ where F is the desired 3dB bandwidth. The factor of 16.7kΩ is the net internal impedance (50kΩ in parallel with a 25kΩ comparator input impedance). A large filtering capacitor may be used on the reference input to remove the modulation signal, leaving a DC reference for the comparator. Because this reference filter may have a long time constant, a longer preamble may be required to allow the DC reference to stabilize. The data pattern also affects the stability of the DC reference and the reliability of the received data. Since a string of consecutive data 'ones' (or 'zeroes') will result in a change to the DC reference, a coding scheme such as Manchester should be used to Rev A12 001113 improve data integrity. Hysteresis can be added by placing a resistor between the input and the output. The DATA OUT pin is only capable of driving rail-to-rail output into a very high impedance and small capacitance, with the amount of capacitance affecting the DATA OUT bandwidth. For a 3pF load, the bandwidth is in excess of 500kHz. The rise and fall times of the RSSI are limited by the bandwidth of the IF filters, thereby limiting the effective data rate. The RSSI output signal is supplied from a current source and therefore requires a resistor to convert it to a voltage. For a 24kΩ resistive load, the RSSI will typically range from 0.4V to 1.5V (3.6V supply). A small parallel capacitor is suggested to limit the bandwidth and filter noise. APPLICATION AND LAYOUT CONSIDERATIONS The RX IN pin is DC biased, requiring a DC blocking capacitor. If the RF filter has DC blocking characteristics, such as a ceramic dielectric filter, then a DC blocking capacitor is not necessary. When in power down mode, the RX IN impedance increases. Therefore in a half-duplex application, the RF2919 RX IN may share the RF filter with a transmitter output having a similar high impedance power down characteristic. Care must be taken in this case to account for loading effects of the transmitter on the receiver and vice versa in matching the filter to both the transmitter and receiver. The VCO is a very sensitive block in this system. RF signals feeding back into the VCO by either radiation or coupling of traces may cause the PLL to become unlocked. The trace(s) for the anode of the tuning varactor should also be kept short. The layout of the resonators and varactor are very important. The capacitor and varactor should be closest to the RF2919 pins and the trace length should be as short as possible. The inductors can be placed further away and any trace inductance can be compensated by reducing the value of the inductors. Printed inductors may also be used with careful design. For best results, the physical layout should be as symmetrical as possible. When using loop bandwidths lower than the 5kHz shown on the evaluation board, better supply filtering at the resonators (and lower VCC noise as well) will help reduce phase noise of the VCO; a series resistor of 100Ω to 200Ω and a 1µF or larger capacitor can be used. Phase noise is generally more critical in narrowband applications where adjacent channel selectivity is 11-149 11 TRANSCEIVERS The RF2919 is a part of a family of low-power RF transceiver IC's that was developed for wireless data communication devices operating in the European 433MHz/868MHz ISM bands or U.S. 915MHz ISM band. This IC has been implemented in a 15GHz silicon bipolar process technology that allows low-power transceiver operation in a variety of commercial wireless products. The RF2919 realizes a highly integrated, single-conversion ASK/OOK receiver with the addition of a reference crystal, intermediate frequency (IF) filtering, and a few passive components. The LNA (low-noise amplifier) input of the RF2919 is easily matched to a front-end filter or antenna by means of a DC blocking capacitor and reactive components. The receiver local oscillator (LO) is generated by an internalized VCO, PLL and phase discriminator in conjunction with the external reference crystal, loop filter and VCO resonator components. The receiver IF section is optimized to interface with low cost 10.7MHz ceramic filters, and its -3dB bandwidth of 25MHz also allows it to be used (with lower gain) at higher frequencies with other types of filters. RF2919 a concern, but it can also contribute to raising the noise floor of the receiver, thereby degrading sensitivity. For the interface between the LNA and mixer, the coupling capacitor should be as close to the RF2919 pins as possible with the bias inductor being further away. Once again, the value of the inductor can be changed to compensate for trace inductance. The output impedance of the LNA is on the order of several kΩ which makes matching to 50Ω difficult. If image filtering is desired, a high impedance filter is recommended. If no filtering is used, the match to the mixer input need not be a good conjugate match due to the high gain of the IF amplifier stages. In fact, a conjugate match between the LNA and mixer will not significantly improve sensitivity, but will have an adverse effect on system IIP3 and increase the likelihood of IF instability. TRANSCEIVERS 11 To lock faster, C needs to be minimized. 1. Design the loop filter for the minimum phase margin possible without causing loop instability problems; this allows C to be kept at a minimum. 2. Design the loop filter for the highest loop cut frequency possible without distorting low frequency modulation components; this also allows C to be kept at a minimum. For additional applications information, refer to the following technical articles. TA0031 "Frequency Synthesis Using the RF2510" DK1000 "ASK Transmit and Receive Chip Set" Predicting and Minimizing PLL Lock Time The RF2919 implements a conventional PLL on chip. The VCO is followed by a prescaler, which divides down the output frequency for comparison with the reference oscillator frequency. The output of the phase discriminator is a sequence of pulse width modulated current pulses in the required direction to steer the VCO's control voltage to maintain phase lock, with a loop filter integrating the current pulses. The lock time of this PLL is a combination of the loop transient response time and the slew rate set by the phase discriminator output current combined with the magnitude of the loop filter capacitance. A good approximation for total lock time of the RF2919 is: D LockTime = ------- + 35000 ⋅ C ⋅ dV FC where D is a factor to account for the loop damping, FC is the loop cut frequency, C is the sum of all shunt capacitors in the loop filter, and dV is the required step voltage change to produce the desired frequency change during the transient. For loops with low phase margin (30° to 40°), use D=2 whereas for loops with better phase margin (50° to 60°), use D=1. 11-150 Rev A12 001113 RF2919 PD OSC E OSC B LOOP FLT GND4 VCC2 RESNTR+ RESNTR- Pin Out 32 31 30 29 28 27 26 25 VCC1 1 24 DATA IN+ RX IN 2 23 DATA OUT GND1 3 22 DATA IN21 RSSI LNA OUT 4 9 10 11 12 13 14 15 16 IF2 IN 17 IF2 BP+ GND5 MIX OUT 8 VREF IF 18 IF2 BP- IF1OUT GND3 7 IF1 BP- 19 VCC3 IF1 BP+ MIX IN 6 IF1 IN+ 20 MUTE IF1 IN- GND2 5 TRANSCEIVERS 11 Rev A12 001113 11-151 RF2919 Application Schematic 433MHz VCC 10 Ω 10 nF 47 pF 18 nH 9.0 pF PD 2.2 nF 18 nH 2.7 kΩ 3.9 kΩ *** 22 nF VCC VCC 10 Ω 10 nF 47 pF 32 4.7 µF 1 50 Ω µstrip J1 RF IN 2.0 pF 100 pF 26 25 29 DC BIAS 28 30 Phase Detector & Charge Pump 2 6.612813 MHz 27 27 nH 100 pF 100 pF 31 3 VCC 21 RSSI 10 pF 24 kΩ 39 nH 4 10 Ω 10 nF VCC 47 pF 100 Ω 9.0 pF Prescaler Β64 20 6 10 Ω 10 Ω 50 kΩ 47 pF 50 kΩ 8 10 nF 47 pF 15 pF J2 IF OUT 50 Ω µstrip 22 pF 120 pF 2.2 µH ** 11 12 13 14 15 16 17 18 22 10 nF 10 nF 10 nF 10 nF 10 nF 10 nF ** 24 Filter 10 nF 10 nF J3 ASK OUT 23 9 10 510 Ω VCC 19 Linear RSSI 7 6.8 µH MUTE 5 ** 0 Filter ** Components not normally populated. *** SMV1233-011 TRANSCEIVERS 11 11-152 Rev A12 001113 RF2919 Application Schematic 868MHz VCC 10 Ω 10 nF 47 pF PD 6.8 nH 2.2 nF 6.8 nH 3.9 kΩ *** 3.0 pF 2.7 kΩ 22 nF VCC VCC 10 Ω 10 nF 47 pF 32 4.7 µF 1 50 Ω µstrip J1 RF IN 1.5 pF 100 pF 26 25 29 DC BIAS 28 30 Phase Detector & Charge Pump 2 13.41015 MHz 27 8.2 nH 100 pF 100 pF 31 3 VCC 21 RSSI 10 pF 24 kΩ 12 nH 4 10 Ω 10 nF VCC 47 pF ** 1.0 pF Prescaler Β64 20 6 10 Ω 10 Ω 50 kΩ 47 pF 50 kΩ 8 10 nF 47 pF 15 pF 11 12 13 14 15 16 17 18 22 10 nF ASK OUT 23 9 10 VCC 19 Linear RSSI 7 6.8 µH MUTE 5 ** 24 1.8 kΩ J2 IF OUT 50 Ω µstrip 22 pF 120 pF 2.2 µH ** Filter 10 nF 10 nF 10 nF 10 nF 10 nF 10 nF 10 nF ** 0 Filter ** Components not normally populated. *** SMV1233-011 TRANSCEIVERS 11 Rev A12 001113 11-153 RF2919 Application Schematic 915MHz VCC 10 Ω 10 nF 47 pF 6.8 nH 3.0 pF PD 2.2 nF 6.8 nH 2.7 kΩ 3.9 kΩ *** 22 nF VCC VCC 10 Ω 10 nF 47 pF 32 4.7 µF 1 50 Ω µstrip J1 RF IN 2.0 pF 26 25 29 DC BIAS 14.15099 MHz 27 30 Phase Detector & Charge Pump 2 6.8 nH 28 100 pF 100 pF 100 pF 31 3 VCC 21 RSSI 10 pF 24 kΩ 12 nH 4 10 Ω 10 nF VCC 47 pF ** 1.0 pF Prescaler Β64 20 6 10 Ω 10 Ω 50 kΩ 47 pF 50 kΩ 8 10 nF 47 pF 15 pF 11 12 13 14 15 16 17 18 22 10 nF J3 ASK OUT 23 9 10 VCC 19 Linear RSSI 7 6.8 µH MUTE 5 ** 24 1.8 kΩ J2 IF OUT 50 Ω µstrip 22 pF 120 pF 2.2 µH ** Filter 10 nF 10 nF 10 nF 10 nF 10 nF 10 nF 10 nF ** 0 Filter ** Components not normally populated. *** SMV1233-011 TRANSCEIVERS 11 11-154 Rev A12 001113 RF2919 Evaluation Board Schematic H (915MHz), M (868MHz), L (433MHz) Boards (Download Bill of Materials from www.rfmd.com.) VCC R9 10 Ω C27 47 pF L7* R11 2.7 kΩ R10 3.9 kΩ D1*** C28* R1 10 Ω C29 2.2 nF L6* C30 22 nF VCC VCC C1 10 nF C2 47 pF C3 4.7 µF 32 J1 RF IN 26 25 29 DC BIAS 1 50 Ω µstrip 30 C5 100 pF 21 L2* VCC 4 C6 10 nF C7 47 pF C8* R3* VCC C32 100 pF L4 6.8 µH RSSI C23 10 pF R7 24 kΩ Prescaler Β64 MUTE 5 R6 10 Ω 20 6 R4 10 Ω C31 100 pF 31 3 R2 10 Ω X1* 27 Phase Detector & Charge Pump 2 C4* L1* 28 C33 3 to 10 pF 19 Linear RSSI 7 50 kΩ VCC C21 47 pF 50 kΩ C22 10 nF 8 C11 10 nF C12 47 pF C9 15 pF 10 J2 IF OUT 50 Ω µstrip C14 120 pF L5 2.2 µH R5* C13 22 pF RSW2** C15 10 nF 11 12 C16 10 nF 13 C17 10 nF 14 15 16 17 18 C19 C18 10 nF 10 nF 22 C20 10 nF C25** 24 C24 10 nF R8** RSW1 0Ω F1 SFECV10.7MS3S-A-TC fO=10.7 MHz BW=180 kHz P1 P1-1 F2 SFECV10.7MS3S-A-TC fO=10.7 MHz BW=180 kHz Drawing 2919400-, 401-, 402*See table for values. P1-3 **Components not normally populated. ***D1 : SMV1233-011 Rev A12 001113 J3 ASK OUT 23 9 P2 1 PD 2 GND 3 VCC P2-1 P2-3 1 RSSI 2 GND 3 MUTE Board C4 (pF) L1 (nH) L2 (nH) C8 (pF) L6 (nH) L7 (nH) C28 (pF) X1 (MHz) R3 (Ω) R5 (Ω) L (433MHz) 2.0 27 39 9.0 18 18 9.0 6.612813 100 510 M (868MHz) 1.5 8.2 12 1.0 6.8 6.8 3.0 13.41015 ** 1.8 k H (915MHz) 2.0 6.8 12 1.0 6.8 6.8 3.0 14.15099 ** 1.8 k 11 TRANSCEIVERS PD C26 10 nF 11-155 RF2919 Evaluation Board Layout - 433MHz Board Size 2.0” x 2.0” Board Thickness 0.040”, Board Material FR-4, Multi-Layer TRANSCEIVERS 11 11-156 Rev A12 001113 RF2919 Evaluation Board Layout - 868MHz TRANSCEIVERS 11 Rev A12 001113 11-157 RF2919 Evaluation Board Layout - 915MHz TRANSCEIVERS 11 11-158 Rev A12 001113 RF2919 1.4 RSSI Freq = 915MHz, VCC = 2.7V, Mute = High 1.4 RSSI, -40°C RSSI, 22.5°C RSSI, -40°C RSSI, 22.5°C 1.2 RSSI Freq = 915MHz, VCC = 2.7V, Mute = Low 1.2 RSSI, 85°C RSSI, 85°C 1.0 RSSI Output (V) RSSI Output (V) 1.0 0.8 0.8 0.6 0.6 0.4 0.4 0.2 0.2 -125.0 1.6 0.0 -105.0 -85.0 -65.0 -45.0 -25.0 -125.0 -85.0 -65.0 -45.0 Power In (dBm) RSSI Freq = 915MHz, VCC = 3.6V, Mute = High RSSI Freq = 915MHz, VCC = 3.6V, Mute = Low 1.6 RSSI, -40°C RSSI, 22.5°C 1.4 -105.0 Power In (dBm) 1.4 RSSI, 85°C -25.0 RSSI, -40°C RSSI, 22.5°C RSSI, 85°C 1.2 RSSI Output (V) RSSI Output (V) 1.2 1.0 0.8 1.0 0.8 0.6 0.6 0.4 0.2 -125.0 1.8 0.0 -105.0 -85.0 -65.0 -45.0 -25.0 -125.0 -65.0 -45.0 RSSI Freq = 915MHz, VCC = 5.0V, Mute = High RSSI Freq = 915MHz, VCC = 5.0V, Mute = Low 1.8 -25.0 RSSI, -40°C RSSI, 22.5°C 1.6 RSSI, 85°C RSSI, 22.5°C RSSI, 85°C 1.4 RSSI Output (V) RSSI Output (V) -85.0 Power In (dBm) 1.4 1.2 1.0 0.8 1.2 1.0 0.8 0.6 0.6 0.4 0.4 0.2 -125.0 -105.0 Power In (dBm) RSSI, -40°C 1.6 11 0.2 0.2 -105.0 -85.0 -65.0 Power In (dBm) Rev A12 001113 -45.0 -25.0 -125.0 -105.0 -85.0 -65.0 -45.0 -25.0 Power In (dBm) 11-159 TRANSCEIVERS 0.4 RF2919 Current versus Temperature RX Frequency = 915MHz 12.0 Sensitivity versus Temperature RX Frequency = 915MHz -90.0 Vcc=2.70 Vcc=2.70 Vcc=3.60 Vcc=3.60 11.0 -95.0 Sensitivity (dBm) Current (mA) 10.0 9.0 -100.0 8.0 -105.0 7.0 -110.0 -40.0 -30.0 -20.0 -10.0 0.0 10.0 20.0 30.0 40.0 50.0 60.0 70.0 80.0 -40.0 -30.0 -20.0 -10.0 0.0 Temperature (°C) Data Output Level versus Temperature RX Frequency = 915MHz LNA Impedance 0.8 Swp Max 1GHz 6 0. Vcc=2.70 2. 0 4.0 10.0 20.0 30.0 40.0 50.0 60.0 70.0 80.0 Temperature (°C) 1.0 6.0 Vcc=3.60 0. 4 0 3. 0 4. 5.0 0.2 LNA Input (RX on) 11 LNA Input (RX off) -3 .0 LNA Output 11-160 .0 -2 -1.0 10.0 20.0 30.0 40.0 50.0 60.0 70.0 80.0 Temperature (°C) -0.8 -40.0 -30.0 -20.0 -10.0 0.0 -0 .6 .4 -0 2.0 -4 .0 -5. 0 2 -0. 2.5 TRANSCEIVERS 10.0 4.0 5.0 3.0 2.0 1.0 0.8 0.6 0.2 0 0.4 10.0 3.0 -10.0 Data Output Level (V P-P) 3.5 Swp Min 0.3GHz Rev A12 001113