LH540205 FEATURES • Fast Access Times: 20/25/35/50 ns • Fast-Fall-Through Time Architecture Based on CMOS Dual-Port SRAM Technology • Input Port and Output Port Have Entirely Independent Timing • Expandable in Width and Depth • Full, Half-Full, and Empty Status Flags • Data Retransmission Capability • TTL-Compatible I/O • Pin and Functionally Compatible with Am/IDT7205 • Control Signals Assertive-LOW for Noise Immunity • Package: 28-Pin, 300-mil PDIP FUNCTIONAL DESCRIPTION The LH540205 is a FIFO (First-In, First-Out) memory device, based on fully-static CMOS dual-port SRAM technology, capable of storing up to 8192 nine-bit words. It follows the industry-standard architecture and package pinouts for nine-bit asynchronous FIFOs. Each nine-bit LH540205 word may consist of a standard eight-bit byte, together with a parity bit or a block-marking/framing bit. The input and output ports operate entirely independently of each other, unless the LH540205 becomes either totally full or else totally empty. Data flow at a port is initiated by asserting either of two asynchronous, assertive-LOW control inputs: Write (W) for data entry at the input port, or Read (R) for data retrieval at the output port. Full, Half-Full, and Empty status flags monitor the extent to which the internal memory has been filled. The system may make use of these status outputs to avoid the risk of data loss, which otherwise might occur either by attempting to write additional words into an already-full LH540205, or by attempting to read additional words from an already-empty LH540205. When an LH540205 is operating in a depth-cascaded configuration, the Half-Full Flag is not available. CMOS 8192 × 9 Asynchronous FIFO Data words are read out from the LH540205’s output port in precisely the same order that they were written in at its input port; that is, according to a First-In, First Out (FIFO) queue discipline. Since the addressing sequence for a FIFO device’s memory is internally predefined, no external addressing information is required for the operation of the LH540205 device. Drop-in-replacement compatibility is maintained with both larger sizes and smaller sizes of industry-standard nine-bit asynchronous FIFOs. The only change is in the number of internally-stored data words implied by the states of the Full Flag and the Half-Full Flag. The Retransmit (RT) control signal causes the internal FIFO-memory-array read-address pointer to be set back to zero, to point to the LH540205’s first physical memory location, without affecting the internal FIFO-memoryarray write-address pointer. Thus, the Retransmit control signal provides a mechanism whereby a block of data, delimited by the zero physical address and the current write-address-pointer value, may be read out repeatedly an arbitrary number of times. The only restrictions are that neither the read-address pointer nor the write-address pointer may ‘wrap around’ during this entire process, i.e., advance past physical location zero after traversing the entire memory. The retransmit facility is not available when an LH540205 is operating in a depth-expanded configuration. PIN CONNECTIONS 28-PIN PDIP TOP VIEW W 1 28 VCC D8 2 27 D4 D3 3 26 D5 D2 4 25 D6 D1 5 24 D7 D0 6 23 FL/RT XI 7 22 RS FF 8 21 EF Q0 9 20 XO/HF Q1 10 19 Q7 Q2 11 18 Q6 Q3 12 17 Q5 Q8 13 16 Q4 VSS 14 15 R 540205-2D Figure 1. Pin Connections for PDIP Packages 1 CMOS 8192 × 9 Asynchronous FIFO LH540205 allows a deeper ‘effective FIFO’ to be implemented by using two or more individual LH540205 devices, without incurring additional latency (‘fallthrough’ or ‘bubblethrough’) delays, and without the necessity of storing and retrieving any given data word more than once. In this cascaded operating mode, one LH540205 device must be designated as the ‘first-load’ or ‘master’ device, by grounding its First-Load (FL/RT) control input; the remaining LH540205 devices are designated as ‘slaves,’ by tying their FL/RT inputs HIGH. Because of the need to share control signals on pins, the Half-Full Flag and the retransmission capability are not available for either ‘master’ or ‘slave’ LH540205 devices operating in cascaded mode. FUNCTIONAL DESCRIPTION (cont’d) The Reset (RS) control signal returns the LH540205 to an initial state, empty and ready to be filled. An LH540205 should be reset during every system power-up sequence. A reset operation causes the internal FIFOmemory-array write-address pointer, as well as the readaddress pointer, to be set back to zero, to point to the LH540205’s first physical memory location. Any information which previously had been stored within the LH540205 is not recoverable after a reset operation. A cascading (depth-expansion) scheme may be implemented by using the Expansion In (XI) input signal and the Expansion Out (XO/HF) output signal. This scheme RS W DATA INPUTS D 0 - D8 RESET LOGIC INPUT PORT CONTROL WRITE POINTER DUAL-PORT RAM ARRAY OUTPUT PORT CONTROL R READ POINTER 8192 x 9 ... DATA OUTPUTS Q0 - Q8 FLAG LOGIC FL/RT XI EXPANSION LOGIC EF FF XO/HF 540205-1 Figure 2. LH540205 Block Diagram 2 CMOS 8192 × 9 Asynchronous FIFO LH540205 PIN DESCRIPTIONS PIN PIN TYPE D0 – D8 I Q0 – Q8 O/Z 1 DESCRIPTION PIN PIN TYPE 1 DESCRIPTION Input Data Bus XO/HF O Expansion Out/Half-Full Flag Output Data Bus XI I Expansion In W I Write Request FL/RT I First Load/Retransmit R I Read Request RS I Reset EF O Empty Flag VCC V Positive Power Supply FF O Full Flag VSS V Ground NOTE: 1. I = Input, O = Output, Z = High-Impedance, V = Power Voltage Level OPERATIONAL DESCRIPTION Reset The LH540205 is reset whenever the Reset input (RS) is taken LOW. A reset operation initializes both the readaddress pointer and the write-address pointer to point to location zero, the first physical memory location. During a reset operation, the state of the XI and FL/RT inputs determines whether the device is in standalone mode or in depth-cascaded mode. (See Tables 1 and 2.) The reset operation forces the Empty Flag EF to be asserted (EF = LOW), and the Half-Full Flag HF and the Full Flag FF to be deasserted (HF = FF = HIGH); the Data Out pins (D0 – D8) are forced into a high-impedance state. A reset operation is required whenever the LH540205 first is powered up. The Read (R) and Write (W) inputs may be in any state when the reset operation is initiated; but they must be HIGH, before the reset operation is terminated by a rising edge of RS, by a time tRRSS (for Read) or tWRSS (for Write) respectively. (See Figure 9.) Write A write cycle is initiated by a falling edge of the Write (W) control input. Data setup times and hold times must be observed for the data inputs (D0 – D 8). Write operations may occur independently of any ongoing read operations. However, a write operation is possible only if the FIFO is not full, (i.e., if the Full Flag FF is HIGH). At the falling edge of W for the first write operation after the memory is half filled, the Half-Full Flag is asserted (HF = LOW). It remains asserted until the difference between the write pointer and the read pointer indicates that the data words remaining in the LH540205 are filling the FIFO memory to less than or equal to one-half of its total capacity. The Half-Full Flag is deasserted (HF = HIGH) by the appropriate rising edge of R. (See Table 3.) The Full Flag is asserted (FF = LOW) at the falling edge of W for the write operation which fills the last available location in the FIFO memory array. FF = LOW inhibits further write operations until FF is cleared by a valid read operation. The Full Flag is deasserted (FF = HIGH) after the next rising edge of R releases another memory location. (See Table 3.) Read A read cycle is initiated by a falling edge of the Read (R) control input. Read data becomes valid at the data outputs (Q0 – Q8) after a time tA from the falling edge of R. After R goes HIGH, the data outputs return to a high-impedance state. Read operations may occur independently of any ongoing write operations. However, a read operation is possible only if the FIFO is not empty (i.e., if the Empty Flag EF is HIGH). The LH540205’s internal read-address and writeaddress pointers operate in such a way that consecutive read operations always access data words in the same order that they were written. The Empty Flag is asserted (EF = LOW) after that falling edge of R which accesses the last available data word in the FIFO memory. EF is deasserted (EF = HIGH) after the next rising edge of W loads another valid data word. (See Table 3.) Data Flow-Through Read-data flow-through mode occurs when the Read (R) control input is brought LOW while the FIFO is empty, and is held LOW in anticipation of a write cycle. At the end of the next write cycle, the Empty Flag EF momentarily is deasserted, and the data word just written becomes available at the data outputs (Q0 – Q8) after a maximum time of tWEF + tA. Additional write operations may occur while the R input remains LOW; but only data from the first write operation flows through to the data outputs. Additional data words, if any, may be accessed only by toggling R. Write-data flow-through mode occurs when the Write (W) input is brought LOW while the FIFO is full, and is held LOW in anticipation of a read cycle. At the end of the read cycle, the Full Flag momentarily is deasserted, but then immediately is reasserted in response to W being held LOW. A data word is written into the FIFO on the rising edge of W, which may occur no sooner than tRFF + tWPW after the read operation. 3 CMOS 8192 × 9 Asynchronous FIFO LH540205 Table 2. Expansion-Pin Usage According to Grouping Mode OPERATIONAL DESCRIPTION (cont’d) Retransmit The FIFO can be made to reread previously-read data by means of the Retransmit function. A retransmit operation is initiated by pulsing the RT input LOW. Both R and W must be deasserted (HIGH) for the duration of the retransmit pulse. The FIFO’s internal read-address pointer is reset to point to location zero, the first physical memory location, while the internal write-address pointer remains unchanged. After a retransmit operation, those data words in the region in between the read-address pointer and the write-address pointer may be reaccessed by subsequent read operations. A retransmit operation may affect the state of the status flags FF, HF, and EF, depending on the relocation of the read-address pointer. There is no restriction on the number of times that a block of data within an LH540205 may be read out, by repeating the retransmit operation and the subsequent read operations. The maximum length of a data block which may be retransmitted is 8192 words. Note that if the write-address pointer ever ‘wraps around’ (i.e., passes location zero more than once) during a sequence of retransmit operations, some data words will be lost. The Retransmit function is not available when the LH540205 is operating in depth-cascaded mode, because the FL/RT control pin must be used for first-load selection rather than for retransmission control. Table 1. Grouping-Mode Determination During a Reset Operation XI FL/ RT MODE XO/HF XI FL/RT USAGE USAGE USAGE H1 H Cascaded Slave 2 XO XI FL H1 L Cascaded Master 2 XO XI FL L X Standalone HF (none) RT NOTES: 1. A reset operation forces XO HIGH for the nth FIFO, thus forcing XI HIGH for the (n+1)st FIFO. 2. The terms ‘master’ and ‘slave’ refer to operation in depth-cascaded grouping mode. 3. H = HIGH; L = LOW; X = Don’t Care. 4 I/O PIN STANDALONE CASCADED CASCADED MASTER SLAVE I XI Grounded From XO (n-1st FIFO) From XO (n-1st FIFO) O XO/HF Becomes HF To XI (n+1st FIFO) To XI (n+1st FIFO) I FL/RT Becomes RT Grounded Logic (Logic HIGH LOW) Table 3. Status Flags NUMBER OF UNREAD DATA WORDS PRESENT WITHIN 8192 × 9 FIFO FF HF EF 0 H H L 1 to 4096 H H H 4097 to 8191 H L H 8192 L L H CMOS 8192 × 9 Asynchronous FIFO LH540205 OPERATIONAL MODES Width Expansion Standalone Configuration Word-width expansion is implemented by placing multiple LH540205 devices in parallel. Each LH540205 should be configured for standalone mode. In this arrangement, the behavior of the status flags is identical for all devices; so, in principle, a representative value for each of these flags could be derived from any one device. In practice, it is better to derive ‘composite’ flag values using external logic, since there may be minor speed variations between different actual devices. (See Figures 3 and 4.) When depth cascading is not required for a given application, the LH540205 is placed in standalone mode by tying the Expansion In input (XI) to ground. This input is internally sampled during a reset operation. (See Table 1.) HF DATA IN D0 - D8 R W WRITE 9 READ 9 DATA OUT Q0 - Q8 LH540205 FULL FLAG RESET FF EF RS RT EMPTY FLAG RETRANSMIT XI 540205-17 Figure 3. Standalone FIFO (8192 × 9) DATA IN D0 - D17 18 HF HF 9 9 WRITE FULL FLAG RESET W W R FF EF LH540205 R LH540205 EMPTY FLAG READ RS RS RT RT 9 XI RETRANSMIT 9 XI 18 DATA OUT Q0 - Q17 540205-18 Figure 4. FIFO Word-Width Expansion (8192 × 18) 5 CMOS 8192 × 9 Asynchronous FIFO LH540205 all devices are tied together. Likewise, only one LH540205 is enabled during any given read cycle; thus, the common Data Out outputs of all devices are wireORed together OPERATIONAL MODES (cont’d) Depth Cascading Depth cascading is implemented by configuring the required number of LH540205s in depth-cascaded mode. In this arrangement, the FIFOs are connected in a circular fashion, with the Expansion Out output (XO) of each device tied to the Expansion In input (XI) of the next device. One FIFO in the cascade must be designated as the ‘first-load’ device, by tying its First Load input (FL/RT) to ground. All other devices must have their FL/RT inputs tied HIGH. In this mode, W and R signals are shared by all devices, while logic within each LH540205 controls the steering of data. Only one LH540205 is enabled during any given write cycle; thus, the common Data In inputs of In depth-cascaded mode, external logic should be used to generate a composite Full Flag and a composite Empty Flag, by ANDing the FF outputs of all LH540205 devices together and ANDing the EF outputs of all devices together. Since FF and EF are assertive-LOW signals, this ‘ANDing’ actually is implemented using an assertiveHIGH physical OR gate. The Half-Full Flag and the Retransmit function are not available in depth-cascaded mode. XO W DATA IN D0 - D8 R 9 FF LH540205 RS EF FL XI FF Vcc 9 LH540205 RS EF FL XI EMPTY Vcc XO 9 9 FF RS DATA OUT Q0 - Q8 XO 9 FULL 9 9 9 LH540205 RS EF FL XI 540205-19 Figure 5. FIFO Depth Cascading (24576 × 9) 6 CMOS 8192 × 9 Asynchronous FIFO LH540205 of another LH540205, which is operating in the opposite direction, to form a single bidirectional bus interface. Care must be taken to assure that the appropriate read, write, and flag signals are routed to each system. Both wordwidth expansion and depth cascading may be used in bidirectional applications. OPERATIONAL MODES (cont’d) Compound FIFO Expansion A combination of word-width expansion and depth cascading may be implemented easily by operating groups of depth-cascaded FIFOs in parallel. Bidirectional FIFO Operation Bidirectional data buffering between two systems may be implemented by operating LH540205 devices in parallel, but in opposite directions. The Data In inputs of each LH540205 are tied to the corresponding Data Out outputs Q0 - Q17 Q0 - Q8 R W RS DATA IN LH540205 DEPTH EXPANSION BLOCK Q0 - QN-10 LH540205 DEPTH EXPANSION BLOCK Q0 - QN-1 DATA OUT LH540205 DEPTH EXPANSION BLOCK ARRAY STORES N-BIT WORDS. D9 - DN-1 D0 - DN-1 DN-9 - DN-1 D18 - DN-1 540205-20 Figure 6. Compound FIFO Expansion Wa Rb FFa EFb LH540205 HFb RS RTb Da0 - 8 Qb0 - 8 XI SYSTEM A SYSTEM B Qa0 - 8 Db0 - 8 Ra EFa Wb LH540205 FFb HFa RTa RS XI 540205-21 Figure 7. Bidirectional FIFO Operation (8192 × 9 × 2) 7 CMOS 8192 × 9 Asynchronous FIFO LH540205 ABSOLUTE MAXIMUM RATINGS 1 PARAMETER RATING Supply Voltage to VSS Potential –0.5 V to 7 V Signal Pin Voltage to VSS Potential 2 –0.5 V to VCC + 0.5 V (not to exceed 7 V) DC Output Current ±50 mA 3 Storage Temperature Range –65oC to 150oC Power Dissipation (Package Limit) 1.0 W DC Voltage Applied to Outputs In High-Z State –0.5 V to VCC + 0.5 V (not to exceed 7 V) NOTES: 1. Stresses greater than those listed under ‘Absolute Maximum Ratings’ may cause permanent damage to the device. This is a stress rating for transient conditions only. Functional operation of the device at these or any other conditions outside of those indicated in the ‘Operating Range’ of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. Negative undershoots of 1.5 V in amplitude are permitted for up to 10 ns once per cycle. 3. Outputs should not be shorted for more than 30 seconds. No more than one output should be shorted at any time. OPERATING RANGE SYMBOL PARAMETER TA Temperature, Ambient VCC Supply Voltage VSS Supply Voltage VIL Logic LOW Input Voltage VIH Logic HIGH Input Voltage 1 MIN MAX UNIT 0 70 °C 4.5 5.5 V 0 0 V –0.5 0.8 V 2.0 V CC + 0.5 V NOTE: 1. Negative undershoots of 1.5 V in amplitude are permitted for up to 10 ns once per cycle. DC ELECTRICAL CHARACTERISTICS (Over Operating Range) SYMBOL PARAMETER TEST CONDITIONS MIN MAX UNIT ILI Input Leakage Current VCC = 5.5 V, VIN = 0 V to VCC –10 10 µA ILO Output Leakage Current R ≥ VIH, 0 V ≤ VOUT ≤ V CC –10 10 µA VOH Output HIGH Voltage IOH = –2.0 mA 2.4 VOL Output LOW Voltage 1 ICC Average Supply Current ICC2 Average Standby Current 1 ICC3 Power Down Current 1 V IOL = 8.0 mA 0.4 V Measured at f = 33 MHz 110 mA All Inputs = VIH 15 mA All Inputs = VCC – 0.2 V 8 mA NOTE: 1. I CC, ICC2, and ICC3 are dependent upon actual output loading and cycle rates. Specified values are with outputs open. 8 CMOS 8192 × 9 Asynchronous FIFO LH540205 AC TEST CONDITIONS PARAMETER Input Pulse Levels VSS to 3 V Input Rise and Fall Times (10% to 90%) 5 ns Input Timing Reference Levels 1.5 V Output Reference Levels 1.5 V Output Load, Timing Tests Figure 8 CAPACITANCE 1,2 PARAMETER +5 V RATING 1.1k Ω DEVICE UNDER TEST 680 Ω 30 pF * * INCLUDES JIG AND SCOPE CAPACITANCES 540205-4 RATING CIN (Input Capacitance) 5 pF COUT (Output Capacitance) 7 pF Figure 8. Output Load Circuit NOTES: 1. Sample tested only. 2. Capacitances are maximum values at 25oC, measured at 1.0 MHz, with VIN = 0 V. 9 CMOS 8192 × 9 Asynchronous FIFO LH540205 AC ELECTRICAL CHARACTERISTICS 1 (Over Operating Range) SYMBOL PARAMETER tA = 20 ns MIN MAX tA = 25 ns MIN tA = 35 ns tA = 50 ns MAX MIN MAX MIN MAX UNIT READ CYCLE TIMING tRC Read Cycle Time 30 – 35 – 45 – 65 – ns tA Access Time – 20 – 25 – 35 – 50 ns tRR Read Recovery Time 10 – 10 – 10 – 15 – ns tRPW Read Pulse Width 2 20 – 25 – 35 – 50 – ns tRLZ Data Bus Active from Read LOW 3 5 – 5 – 5 – 5 – ns tWLZ Data Bus Active from Write HIGH 3,4 10 – 10 – 10 – 10 – ns tDV Data Held Valid from Read Pulse HIGH 5 – 5 – 5 – 5 – ns tRHZ Data Bus High-Z from Read HIGH 3 – 15 – 15 – 15 – 20 ns WRITE CYCLE TIMING tWC Write Cycle Time 30 – 35 – 45 – 65 – ns tWPW Write Pulse Width 2 20 – 25 – 35 – 50 – ns tWR Write Recovery Time 10 – 10 – 10 – 15 – ns tDS Data Setup Time 12 – 15 – 18 – 30 – ns tDH Data Hold Time 0 – 0 – 0 – 0 – ns RESET TIMING tRSC Reset Cycle Time 2 30 – 35 – 45 – 65 – ns tRS Reset Pulse Width 20 – 25 – 35 – 50 – ns tRSR Reset Recovery Time 10 – 10 – 10 – 15 – ns tRRSS Read HIGH to RS HIGH 20 – 25 – 35 – 50 – ns tWRSS Write HIGH to RS HIGH 20 – 25 – 35 – 50 – ns – 45 – 65 – ns RETRANSMIT TIMING 5 tRTC Retransmit Cycle Time tRT Retransmit Pulse Width 2 20 – 25 – 35 – 50 – ns tRTR Retransmit Recovery Time 10 – 10 – 10 – 15 – ns 30 – 35 FLAG TIMING tEFL Reset LOW to Empty Flag LOW – 30 – 35 – 45 – 65 ns tHFH,FFH Reset LOW to Half-Full and Full Flags HIGH – 30 – 35 – 45 – 65 ns tREF Read LOW to Empty Flag LOW – 20 – 25 – 35 – 45 ns tRFF Read HIGH to Full Flag HIGH – 20 – 25 – 35 – 45 ns tWEF Write HIGH to Empty Flag HIGH – 20 – 25 – 35 – 45 ns tWFF Write LOW to Full Flag LOW – 20 – 25 – 35 – 45 ns tWHF Write LOW to Half-Full Flag LOW – 20 – 25 – 35 – 45 ns tRHF Read HIGH to Half-Full Flag HIGH – 20 – 25 – 35 – 45 ns tXOL Expansion Out LOW – 25 – 35 – 50 ns tXOH tXI EXPANSION TIMING – 20 Expansion Out HIGH – 20 – 25 – 35 – 50 ns Expansion In Pulse Width 20 – 25 – 35 – 50 – ns tXIR Expansion In Recovery Time 10 – 10 – 10 – 10 – ns tXIS Expansion in Setup Time 10 – 10 – 15 – 15 – ns NOTES: 1. All timing measurements are performed at ‘AC Test Condition’ levels. 2. Pulse widths less than minimum value are not allowed. 10 CMOS 8192 × 9 Asynchronous FIFO LH540205 TIMING DIAGRAMS t RSC t RS RS R,W t RRSS t WRSS t RSR tEFL EF t FFH , t HFH FF,HF NOTES: 1. tRSC = tRS + tRSR. 2. W and R ≥ VIH around the rising edge of RS. 3. The Data Out pins (D0 - D8) are forced into a high-impedance state whenever EF = LOW. 540205-14 Figure 9. Reset Timing t RPW t RC t RR tA tA R t RLZ t RHZ t DV Q0 - Q8 VALID DATA OUT VALID DATA OUT t WC t WR t WPW W t DS D0 - D8 t DH VALID DATA IN VALID DATA IN 540205-5 Figure 10. Asynchronous Write and Read Operation 11 CMOS 8192 × 9 Asynchronous FIFO LH540205 TIMING DIAGRAMS (cont’d) LAST WRITE FIRST READ R W t RFF t WFF FF 540205-6 Figure 11. Full Flag From Last Write to First Read LAST READ FIRST WRITE W R t REF t WEF EF NOTE: The Data Out pins (D0 - D8) are forced into a high-impedance state whenever EF = LOW. Figure 12. Empty Flag From Last Read to First Write 12 540205-7 CMOS 8192 × 9 Asynchronous FIFO LH540205 TIMING DIAGRAMS (cont’d) VALID DATA IN D0 - D8 W tRPE R EF t REF t WEF t WLZ tA Q0 - Q8 VALID DATA OUT NOTES: 1. tRPE = tRPW 2. tRPE: Effective Read Pulse Width after Empty Flag HIGH. 3. The Data Out pins (D0 - D8) are forced into a high-impedance state whenever EF = LOW. 540205-8 Figure 13. Read Data Flow-Through R tWPF W t RFF FF t WFF t DS t DH VALID DATA IN D0 - D8 tA Q0 - Q8 VALID DATA OUT NOTES: 1. tWPF = tWPW. 2. tWPF: Effective Write Pulse Width after Full Flag HIGH. 540205-9 Figure 14. Write Data Flow-Through 13 CMOS 8192 × 9 Asynchronous FIFO LH540205 TIMING DIAGRAMS (cont’d) W t WEF EF t RPE R NOTES: 1. tRPE = tRPW 2. tRPE: Effective Read Pulse Width after Empty Flag HIGH. 3. The Data Out pins (D0 - D8) are forced into a high-impedance state whenever EF = LOW. 540205-10 Figure 15. Empty Flag Timing R t RFF FF t WPF W NOTES: 1. tWPF = tWPW. 2. tWPF: Effective Write Pulse Width after Full Flag HIGH. 540205-11 Figure 16. Full Flag Timing 14 CMOS 8192 × 9 Asynchronous FIFO LH540205 TIMING DIAGRAMS (cont’d) MORE THAN HALF-FULL HALF-FULL OR LESS HALF-FULL OR LESS W R t WHF tRHF HF 540205-12 Figure 17. Half-Full Flag Timing t RT RT t RTR R,W NOTES: 1. tRTC = tRT + tRTR. 2. FF, HF, and EF may change state during retransmit; but they will become valid by tRTC. 540205-13 Figure 18. Retransmit Timing 15 CMOS 8192 × 9 Asynchronous FIFO LH540205 TIMING DIAGRAMS (cont’d) W WRITE TO LAST AVAILABLE LOCATION READ FROM LAST VALID LOCATION R t XOL t XOH t XOL t XOH XO 540205-15 Figure 19. Expansion-Out Timing t XI t XIR XI t XIS W WRITE TO FIRST AVAILABLE LOCATION t XIS READ FROM FIRST VALID LOCATION R 540205-16 Figure 20. Expansion-In Timing 16 CMOS 8192 × 9 Asynchronous FIFO LH540205 PACKAGE DIAGRAMS 28DIP (DIP28-W-300) DETAIL 7.49 [0.295] 7.11 [0.280] 0° TO 15° 0.30 [0.012] 0.20 [0.008] 34.80 [1.370] 34.54 [1.360] 7.62 [0.300] TYP. 3.30 [0.130] 4.57 [0.180] MAX 3.43 [0.135] 3.18 [0.125] 2.54 [0.100] TYP. DIMENSIONS IN MM [INCHES] 0.53 [0.021] 0.38 [0.015] 0.51 [0.020] MIN MAXIMUM LIMIT MINIMUM LIMIT 28DIP-3 28-pin, 300-mil PDIP ORDERING INFORMATION LH540205 Device Type D Package - ## Speed 20 25 35 50 Access Time (ns) 28-pin, 300-mil Plastic DIP (DIP28-W-300) CMOS 8192 x 9 FIFO Example: LH540205D-25 (CMOS 8192 x 9 FIFO, 28-pin, 600-mil DIP, 25 ns) 540205MD 17