LH540203 CMOS 2048 × 9 Asynchronous FIFO FEATURES FUNCTIONAL DESCRIPTION • Fast Access Times: 15/20/25/35/50 ns The LH540203 is a FIFO (First-In, First-Out) memory device, based on fully-static CMOS dual-port SRAM technology, capable of storing up to 2048 nine-bit words. It follows the industry-standard architecture and package pinouts for nine-bit asynchronous FIFOs. Each nine-bit LH540203 word may consist of a standard eight-bit byte, together with a parity bit or a block-marking/framing bit. • Fast-Fall-Through Time Architecture Based on CMOS Dual-Port SRAM Technology • Input Port and Output Port Have Entirely Independent Timing • Expandable in Width and Depth The input and output ports operate entirely independently of each other, unless the LH540203 becomes either totally full or else totally empty. Data flow at a port is initiated by asserting either of two asynchronous, assertive-LOW control inputs: Write (W) for data entry at the input port, or Read (R) for data retrieval at the output port. • Full, Half-Full, and Empty Status Flags • Data Retransmission Capability • TTL-Compatible I/O • Pin and Functionally Compatible with Sharp LH5498 and with Am/IDT/MS7203 • Control Signals Assertive-LOW for Noise Immunity • Packages: 28-Pin, 300-mil PDIP 28-Pin, 300-mil SOJ * 32-Pin PLCC Full, Half-Full, and Empty status flags monitor the extent to which the internal memory has been filled. The system may make use of these status outputs to avoid the risk of data loss, which otherwise might occur either by attempting to write additional words into an already-full LH540203, or by attempting to read additional words from an already-empty LH540203. When an LH540203 is operating in a depth-cascaded configuration, the Half-Full Flag is not available. D4 26 D5 D2 4 25 D6 D1 5 24 D7 D0 6 23 FL/RT XI 7 22 RS FF 8 21 EF Q0 9 20 XO/HF 4 3 2 1 32 31 30 D5 27 3 D4 2 D3 VCC D8 32-PIN PLCC NC* VCC W 28 D8 TOP VIEW 1 W TOP VIEW D2 5 29 D1 6 28 D7 D0 7 27 NC XI 8 26 FL/RT FF 9 25 RS Q0 10 24 EF Q1 11 23 XO/HF D6 Q1 10 19 Q7 NC 12 22 11 18 Q6 Q7 Q2 Q2 13 21 Q3 12 17 Q5 Q6 Q8 13 16 Q4 VSS 14 15 R 540203-2D Figure 1. Pin Connections for PDIP and SOJ * Packages Q4 Q5 R NC* VSS Q3 14 15 16 17 18 19 20 Q8 28-PIN PDIP 28-PIN SOJ * D3 PIN CONNECTIONS NOTE: * = No external electrical connections are allowed. 540203-3D Figure 2. Pin Connections for PLCC Package * This is a final data sheet; except that all references to the SOJ package have Advance Information status. 1 CMOS 2048 × 9 Asynchronous FIFO LH540203 The Reset (RS) control signal returns the LH540203 to an initial state, empty and ready to be filled. An LH540203 should be reset during every system power-up sequence. A reset operation causes the internal FIFOmemory-array write-address pointer, as well as the readaddress pointer, to be set back to zero, to point to the LH540203’s first physical memory location. Any information which previously had been stored within the LH540203 is not recoverable after a reset operation. FUNCTIONAL DESCRIPTION (cont’d) Data words are read out from the LH540203’s output port in precisely the same order that they were written in at its input port; that is, according to a First-In, First Out (FIFO) queue discipline. Since the addressing sequence for a FIFO device’s memory is internally predefined, no external addressing information is required for the operation of the LH540203 device. Drop-in-replacement compatibility is maintained with both larger sizes and smaller sizes of industry-standard nine-bit asynchronous FIFOs. The only change is in the number of internally-stored data words implied by the states of the Full Flag and the Half-Full Flag. A cascading (depth-expansion) scheme may be implemented by using the Expansion In (XI) input signal and the Expansion Out (XO/HF) output signal. This allows a deeper ‘effective FIFO’ to be implemented by using two or more LH540203 devices, without incurring additional latency (‘fallthrough’ or ‘bubblethrough’) delays, and without the necessity of storing and retrieving any given data word more than once. In this cascaded operating mode, one LH540203 device must be designated as the ‘firstload’ or ‘master’ device, by grounding its First-Load (FL/RT) control input; the remaining LH540203 devices are designated as ‘slaves,’ by tying their FL/RT inputs HIGH. Because of the need to share control signals on pins, the Half-Full Flag and the retransmission capability are not available for either ‘master’ or ‘slave’ LH540203 devices operating in cascaded mode. The Retransmit (RT) control signal causes the internal FIFO-memory-array read-address pointer to be set back to zero, to point to the LH540203’s first physical memory location, without affecting the internal FIFO-memoryarray write-address pointer. Thus, the Retransmit control signal provides a mechanism whereby a block of data, delimited by the zero physical address and the current write-address-pointer value, may be read out repeatedly an arbitrary number of times. The only restrictions are that neither the read-address pointer nor the write-address pointer may ‘wrap around’ during this entire process, i.e., advance past physical location zero after traversing the entire memory. The retransmit facility is not available when an LH540203 is operating in a depth-expanded configuration. RS RESET LOGIC W INPUT PORT CONTROL DATA INPUTS D0 - D8 WRITE POINTER DUAL-PORT RAM ARRAY OUTPUT PORT CONTROL R READ POINTER 2048 x 9 ... DATA OUTPUTS Q0 - Q8 FLAG LOGIC FL/RT XI EXPANSION LOGIC EF FF XO/HF 540203-1 Figure 3. LH540203 Block Diagram 2 CMOS 2048 × 9 Asynchronous FIFO LH540203 PIN DESCRIPTIONS PIN PIN TYPE 1 D0 – D8 I Q0 – Q8 O/Z DESCRIPTION PIN PIN TYPE 1 DESCRIPTION Input Data Bus XO/HF O Expansion Out/Half-Full Flag Output Data Bus XI I Expansion In W I Write Request FL/RT I First Load/Retransmit R I Read Request RS I Reset EF O Empty Flag VCC V Positive Power Supply FF O Full Flag VSS V Ground NOTE: 1. I = Input, O = Output, Z = High-Impedance, V = Power Voltage Level OPERATIONAL DESCRIPTION Reset The LH540203 is reset whenever the Reset input (RS) is taken LOW. A reset operation initializes both the readaddress pointer and the write-address pointer to point to location zero, the first physical memory location. During a reset operation, the state of the XI and FL/RT inputs determines whether the device is in standalone mode or in depth-cascaded mode. (See Tables 1 and 2.) The reset operation forces the Empty Flag EF to be asserted (EF = LOW), and the Half-Full Flag HF and the Full Flag FF to be deasserted (HF = FF = HIGH); the Data Out pins (D0 – D8) are forced into a high-impedance state. A reset operation is required whenever the LH540203 first is powered up. The Read (R) and Write (W) inputs may be in any state when the reset operation is initiated; but they must be HIGH, before the reset operation is terminated by a rising edge of RS, by a time tRRSS (for Read) or tWRSS (for Write) respectively. (See Figure 10.) Write A write cycle is initiated by a falling edge of the Write (W) control input. Data setup times and hold times must be observed for the data inputs (D0 – D 8). Write operations may occur independently of any ongoing read operations. However, a write operation is possible only if the FIFO is not full, (i.e., if the Full Flag FF is HIGH). At the falling edge of W for the first write operation after the memory is half filled, the Half-Full Flag is asserted (HF = LOW). It remains asserted until the difference between the write pointer and the read pointer indicates that the data words remaining in the LH540203 are filling the FIFO memory to less than or equal to one-half of its total capacity. The Half-Full Flag is deasserted (HF = HIGH) by the appropriate rising edge of R. (See Table 3.) The Full Flag is asserted (FF = LOW) at the falling edge of W for the write operation which fills the last available location in the FIFO memory array. FF = LOW inhibits further write operations until FF is cleared by a valid read operation. The Full Flag is deasserted (FF = HIGH) after the next rising edge of R releases another memory location. (See Table 3.) Read A read cycle is initiated by a falling edge of the Read (R) control input. Read data becomes valid at the data outputs (Q0 – Q8) after a time tA from the falling edge of R. After R goes HIGH, the data outputs return to a high-impedance state. Read operations may occur independently of any ongoing write operations. However, a read operation is possible only if the FIFO is not empty (i.e., if the Empty Flag EF is HIGH). The LH540203’s internal read-address and writeaddress pointers operate in such a way that consecutive read operations always access data words in the same order that they were written. The Empty Flag is asserted (EF = LOW) after that falling edge of R which accesses the last available data word in the FIFO memory. EF is deasserted (EF = HIGH) after the next rising edge of W loads another valid data word. (See Table 3.) Data Flow-Through Read-data flow-through mode occurs when the Read (R) control input is brought LOW while the FIFO is empty, and is held LOW in anticipation of a write cycle. At the end of the next write cycle, the Empty Flag EF momentarily is deasserted, and the data word just written becomes available at the data outputs (Q0 – Q8) after a maximum time of tWEF + tA. Additional write operations may occur while the R input remains LOW; but only data from the first write operation flows through to the data outputs. Additional data words, if any, may be accessed only by toggling R. Write-data flow-through mode occurs when the Write (W) input is brought LOW while the FIFO is full, and is held LOW in anticipation of a read cycle. At the end of the read cycle, the Full Flag momentarily is deasserted, but then immediately is reasserted in response to W being held LOW. A data word is written into the FIFO on the rising edge of W, which may occur no sooner than tRFF + tWPW after the read operation. 3 CMOS 2048 × 9 Asynchronous FIFO LH540203 Table 2. Expansion-Pin Usage According to Grouping Mode OPERATIONAL DESCRIPTION (cont’d) Retransmit The FIFO can be made to reread previously-read data by means of the Retransmit function. A retransmit operation is initiated by pulsing the RT input LOW. Both R and W must be deasserted (HIGH) for the duration of the retransmit pulse. The FIFO’s internal read-address pointer is reset to point to location zero, the first physical memory location, while the internal write-address pointer remains unchanged. After a retransmit operation, those data words in the region in between the read-address pointer and the write-address pointer may be reaccessed by subsequent read operations. A retransmit operation may affect the state of the status flags FF, HF, and EF, depending on the relocation of the read-address pointer. There is no restriction on the number of times that a block of data within an LH540203 may be read out, by repeating the retransmit operation and the subsequent read operations. The maximum length of a data block which may be retransmitted is 2048 words. Note that if the write-address pointer ever ‘wraps around’ (i.e., passes location zero more than once) during a sequence of retransmit operations, some data words will be lost. The Retransmit function is not available when the LH540203 is operating in depth-cascaded mode, because the FL/RT control pin must be used for first-load selection rather than for retransmission control. Table 1. Grouping-Mode Determination During a Reset Operation XI FL/ RT MODE XO/HF XI FL/RT USAGE USAGE USAGE H1 H Cascaded Slave 2 XO XI FL H1 L Cascaded Master 2 XO XI FL L X Standalone HF (none) RT NOTES: 1. A reset operation forces XO HIGH for the nth FIFO, thus forcing XI HIGH for the (n+1)st FIFO. 2. The terms ‘master’ and ‘slave’ refer to operation in depth-cascaded grouping mode. 3. H = HIGH; L = LOW; X = Don’t Care. 4 I/O PIN STANDALONE CASCADED CASCADED MASTER SLAVE I XI Grounded From XO (n-1st FIFO) From XO (n-1st FIFO) O XO/HF Becomes HF To XI (n+1st FIFO) To XI (n+1st FIFO) I FL/RT Becomes RT Grounded (Logic LOW) Logic HIGH Table 3. Status Flags NUMBER OF UNREAD DATA WORDS PRESENT WITHIN 2048 × 9 FIFO FF HF EF 0 H H L 1 to 1024 H H H 1025 to 2047 H L H 2048 L L H CMOS 2048 × 9 Asynchronous FIFO LH540203 OPERATIONAL MODES Width Expansion Standalone Configuration Word-width expansion is implemented by placing multiple LH540203 devices in parallel. Each LH540203 should be configured for standalone mode. In this arrangement, the behavior of the status flags is identical for all devices; so, in principle, a representative value for each of these flags could be derived from any one device. In practice, it is better to derive ‘composite’ flag values using external logic, since there may be minor speed variations between different actual devices. (See Figures 4, 5, and 6.) When depth cascading is not required for a given application, the LH540203 is placed in standalone mode by tying the Expansion In input (XI) to ground. This input is internally sampled during a reset operation. (See Table 1.) HF DATA IN D0 - D8 R W WRITE 9 READ 9 DATA OUT Q0 - Q8 LH540203 FULL FLAG RESET FF EF RS RT EMPTY FLAG RETRANSMIT XI 540203-17 Figure 4. Standalone FIFO (2048 × 9) DATA IN D0 - D17 18 HF HF 9 9 WRITE FULL FLAG RESET W W R FF EF LH540203 R LH540203 EMPTY FLAG READ RS RS RT RT 9 XI RETRANSMIT 9 XI 18 DATA OUT Q0 - Q17 540203-18 Figure 5. FIFO Word-Width Expansion (2048 × 18) 5 CMOS 2048 × 9 Asynchronous FIFO LH540203 all devices are tied together. Likewise, only one LH540203 is enabled during any given read cycle; thus, the common Data Out outputs of all devices are wireORed together. OPERATIONAL MODES (cont’d) Depth Cascading Depth cascading is implemented by configuring the required number of LH540203s in depth-cascaded mode. In this arrangement, the FIFOs are connected in a circular fashion, with the Expansion Out output (XO) of each device tied to the Expansion In input (XI) of the next device. One FIFO in the cascade must be designated as the ‘first-load’ device, by tying its First Load input (FL/RT) to ground. All other devices must have their FL/RT inputs tied HIGH. In this mode, W and R signals are shared by all devices, while logic within each LH540203 controls the steering of data. Only one LH540203 is enabled during any given write cycle; thus, the common Data In inputs of In depth-cascaded mode, external logic should be used to generate a composite Full Flag and a composite Empty Flag, by ANDing the FF outputs of all LH540203 devices together and ANDing the EF outputs of all devices together. Since FF and EF are assertive-LOW signals, this ‘ANDing’ actually is implemented using an assertive-HIGH physical OR gate. The Half-Full Flag and the Retransmit function are not available in depth-cascaded mode. XO W DATA IN D0 - D8 R 9 FF LH540203 RS EF FL XI FF Vcc 9 LH540203 RS EF FL XI EMPTY Vcc XO 9 9 FF RS DATA OUT Q0 - Q8 XO 9 FULL 9 9 9 LH540203 RS EF FL XI 540203-19 Figure 6. FIFO Depth Cascading (6144 × 9) 6 CMOS 2048 × 9 Asynchronous FIFO LH540203 LH540203 are tied to the corresponding Data Out outputs of another LH540203, which is operating in the opposite direction, to form a single bidirectional bus interface. Care must be taken to assure that the appropriate read, write, and flag signals are routed to each system. Both wordwidth expansion and depth cascading may be used in bidirectional applications. OPERATIONAL MODES (cont’d) Compound FIFO Expansion A combination of word-width expansion and depth cascading may be implemented easily by operating groups of depth-cascaded FIFOs in parallel. Bidirectional FIFO Operation Bidirectional data buffering between two systems may be implemented by operating LH540203 devices in parallel, but in opposite directions. The Data In inputs of each Q0 - Q17 Q0 - Q8 R W RS DATA IN LH540203 DEPTH EXPANSION BLOCK Q0 - QN-10 LH540203 DEPTH EXPANSION BLOCK Q0 - QN-1 DATA OUT LH540203 DEPTH EXPANSION BLOCK ARRAY STORES N-BIT WORDS. D9 - DN-1 D0 - DN-1 DN-9 - DN-1 D18 - DN-1 540203-20 Figure 7. Compound FIFO Expansion Wa Rb FFa EFb LH540203 HFb RS RTb Da0 - 8 Qb0 - 8 XI SYSTEM A SYSTEM B Qa0 - 8 Db0 - 8 Ra EFa Wb LH540203 FFb HFa RTa RS XI 540203-21 Figure 8. Bidirectional FIFO Operation (2048 × 9 × 2) 7 CMOS 2048 × 9 Asynchronous FIFO LH540203 ABSOLUTE MAXIMUM RATINGS 1 PARAMETER RATING Supply Voltage to VSS Potential –0.5 V to 7 V Signal Pin Voltage to VSS Potential 2 –0.5 V to VCC + 0.5 V (not to exceed 7 V) DC Output Current ± 50 mA 3 Storage Temperature Range –65oC to 150oC Power Dissipation (Package Limit) 1.0 W DC Voltage Applied to Outputs In High-Z State –0.5 V to VCC + 0.5 V (not to exceed 7 V) NOTES: 1. Stresses greater than those listed under ‘Absolute Maximum Ratings’ may cause permanent damage to the device. This is a stress rating for transient conditions only. Functional operation of the device at these or any other conditions outside of those indicated in the ‘Operating Range’ of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. Negative undershoots of 1.5 V in amplitude are permitted for up to 10 ns once per cycle. 3. Outputs should not be shorted for more than 30 seconds. No more than one output should be shorted at any time. OPERATING RANGE SYMBOL PARAMETER TA Temperature, Ambient VCC Supply Voltage VSS Supply Voltage VIL Logic LOW Input Voltage VIH Logic HIGH Input Voltage 1 MIN MAX UNIT 0 70 °C 4.5 5.5 V 0 0 V –0.5 0.8 V 2.0 V CC + 0.5 V NOTE: 1. Negative undershoots of 1.5 V in amplitude are permitted for up to 10 ns once per cycle. DC ELECTRICAL CHARACTERISTICS (Over Operating Range) SYMBOL PARAMETER TEST CONDITIONS MIN MAX UNIT ILI Input Leakage Current VCC = 5.5 V, VIN = 0 V to VCC –10 10 µA ILO Output Leakage Current R ≥ VIH, 0 V ≤ VOUT ≤ V CC –10 10 µA VOH Output HIGH Voltage IOH = –2.0 mA 2.4 VOL Output LOW Voltage 1 ICC Average Supply Current ICC2 Average Standby Current 1 ICC3 Power Down Current 1 V IOL = 8.0 mA 0.4 V Measured at f = 40 MHz 100 mA All Inputs = VIH 15 mA All Inputs = VCC – 0.2 V 5 mA NOTE: 1. I CC, ICC2, and ICC3 are dependent upon actual output loading and cycle rates. Specified values are with outputs open. 8 CMOS 2048 × 9 Asynchronous FIFO LH540203 AC TEST CONDITIONS PARAMETER Input Pulse Levels VSS to 3 V Input Rise and Fall Times (10% to 90%) 5 ns Input Timing Reference Levels 1.5 V Output Reference Levels 1.5 V Output Load, Timing Tests Figure 9 CAPACITANCE 1,2 PARAMETER +5 V RATING 1.1 k Ω DEVICE UNDER TEST 680 Ω 30 pF* * INCLUDES JIG AND SCOPE CAPACITANCES 540203-4 RATING CIN (Input Capacitance) 5 pF COUT (Output Capacitance) 7 pF Figure 9. Output Load Circuit NOTES: 1. Sample tested only. 2. Capacitances are maximum values at 25oC, measured at 1.0 MHz, with VIN = 0 V. 9 CMOS 2048 × 9 Asynchronous FIFO LH540203 AC ELECTRICAL CHARACTERISTICS 1 (Over Operating Range) SYMBOL tA = 15 ns PARAMETER MIN MAX tA = 20 ns MIN MAX tA = 25 ns MIN tA = 35 ns MAX MIN tA = 50 ns MAX MIN UNIT MAX READ CYCLE TIMING tRC Read Cycle Time 25 – 30 – 35 – 45 – 65 – ns tA Access Time – 15 – 20 – 25 – 35 – 50 ns tRR Read Recovery Time 10 – 10 – 10 – 10 – 15 – ns 2 tRPW Read Pulse Width 15 – 20 – 25 – 35 – 50 – ns tRLZ Data Bus Active from Read LOW 3 5 – 5 – 5 – 5 – 5 – ns tWLZ Data Bus Active from Write HIGH 3,4 10 – 10 – 10 – 10 – 10 – ns tDV Data Valid from Read Pulse HIGH 5 – 5 – 5 – 5 – 5 – ns – 15 – 15 – 15 – 15 – 20 ns tRHZ Data Bus High-Z from Read HIGH tWC Write Cycle Time 3 WRITE CYCLE TIMING tWPW Write Pulse Width 2 25 – 30 – 35 – 45 – 65 – ns 15 – 20 – 25 – 35 – 50 – ns tWR Write Recovery Time 10 – 10 – 10 – 10 – 15 – ns tDS Data Setup Time 12 – 12 – 12 – 15 – 20 – ns tDH Data Hold Time 0 – 0 – 0 – 0 – 0 – ns RESET TIMING tRSC Reset Cycle Time 25 – 30 – 35 – 45 – 65 – ns tRS Reset Pulse Width 2 15 – 20 – 25 – 35 – 50 – ns tRSR Reset Recovery Time 10 – 10 – 10 – 10 – 15 – ns tRRSS Read HIGH to RS HIGH 15 – 20 – 25 – 35 – 50 – ns tWRSS Write HIGH to RS HIGH 15 – 20 – 25 – 35 – 50 – ns RETRANSMIT TIMING 5 tRTC Retransmit Cycle Time 2 tRT Retransmit Pulse Width tRTR Retransmit Recovery Time 25 – 30 – 35 – 45 – 65 – ns 15 – 20 – 25 – 35 – 50 – ns – 10 – 10 – 10 – 15 – ns 10 FLAG TIMING tEFL Reset LOW to Empty Flag LOW – 25 – 30 – 35 – 45 – 65 ns tHFH,FFH Reset LOW to Half-Full and Full Flags HIGH – 25 – 30 – 35 – 45 – 65 ns tREF Read LOW to Empty Flag LOW – 15 – 20 – 25 – 35 – 45 ns tRFF Read HIGH to Full Flag HIGH – 15 – 20 – 25 – 35 – 45 ns tWEF Write HIGH to Empty Flag HIGH – 15 – 20 – 25 – 35 – 45 ns tWFF Write LOW to Full Flag LOW – 15 – 20 – 25 – 35 – 45 ns tWHF Write LOW to Half-Full Flag LOW – 15 – 20 – 25 – 35 – 45 ns tRHF Read HIGH to Half-Full Flag HIGH – 15 – 20 – 25 – 35 – 45 ns tXOL Expansion Out LOW – 18 – 20 – 25 – 35 – 50 ns tXOH Expansion Out HIGH – 18 – 20 – 25 – 35 – 50 ns tXI Expansion In Pulse Width 15 – 20 – 25 – 35 – 50 – ns tXIR Expansion In Recovery Time 10 – 10 – 10 – 10 – 10 – ns tXIS Expansion in Setup Time 7 – 10 – 10 – 15 – 15 – ns EXPANSION TIMING NOTES: 1. All timing measurements are performed at ‘AC Test Condition’ levels. 2. Pulse widths less than minimum value are not allowed. 10 CMOS 2048 × 9 Asynchronous FIFO LH540203 TIMING DIAGRAMS t RSC t RS RS R,W t RRSS t WRSS t RSR tEFL EF t FFH , t HFH FF,HF NOTES: 1. tRSC = tRS + tRSR. 2. W and R ≥ VIH around the rising edge of RS. 3. The Data Out pins (D0 - D8) are forced into a high-impedance state whenever EF = LOW. 540203-14 Figure 10. Reset Timing t RPW t RC t RR tA tA R t RLZ t RHZ t DV Q0 - Q8 VALID DATA OUT VALID DATA OUT t WC t WR t WPW W t DS D0 - D8 t DH VALID DATA IN VALID DATA IN 540203-5 Figure 11. Asynchronous Write and Read Operation 11 CMOS 2048 × 9 Asynchronous FIFO LH540203 TIMING DIAGRAMS (cont’d) LAST WRITE FIRST READ R W t RFF t WFF FF 540204-6 Figure 12. Full Flag From Last Write to First Read LAST READ FIRST WRITE W R t REF t WEF EF NOTE: The Data Out pins (D0 - D8) are forced into a high-impedance state whenever EF = LOW. Figure 13. Empty Flag From Last Read to First Write 12 540203-7 CMOS 2048 × 9 Asynchronous FIFO LH540203 TIMING DIAGRAMS (cont’d) VALID DATA IN D0 - D8 W tRPE R EF t REF t WEF t WLZ tA Q0 - Q8 VALID DATA OUT NOTES: 1. tRPE = tRPW 2. tRPE: Effective Read Pulse Width after Empty Flag HIGH. 3. The Data Out pins (D0 - D8) are forced into a high-impedance state whenever EF = LOW. 540203-8 Figure 14. Read Data Flow-Through R tWPF W t RFF FF t WFF t DS t DH VALID DATA IN D0 - D8 tA Q0 - Q8 VALID DATA OUT NOTES: 1. tWPF = tWPW. 2. tWPF: Effective Write Pulse Width after Full Flag HIGH. 540203-9 Figure 15. Write Data Flow-Through 13 CMOS 2048 × 9 Asynchronous FIFO LH540203 TIMING DIAGRAMS (cont’d) W t WEF EF t RPE R NOTES: 1. tRPE = tRPW 2. tRPE: Effective Read Pulse Width after Empty Flag HIGH. 3. The Data Out pins (D0 - D8) are forced into a high-impedance state whenever EF = LOW. 540203-10 Figure 16. Empty Flag Timing R t RFF FF t WPF W NOTES: 1. tWPF = tWPW. 2. tWPF: Effective Write Pulse Width after Full Flag HIGH. 540203-11 Figure 17. Full Flag Timing MORE THAN HALF-FULL HALF-FULL OR LESS HALF-FULL OR LESS W R t WHF tRHF HF 540203-12 Figure 18. Half-Full Flag Timing 14 CMOS 2048 × 9 Asynchronous FIFO LH540203 TIMING DIAGRAMS (cont’d) t RT RT t RTR R,W NOTES: 1. tRTC = tRT + tRTR. 2. FF, HF, and EF may change state during retransmit; but they will become valid by tRTC. 540203-13 Figure 19. Retransmit Timing W WRITE TO LAST AVAILABLE LOCATION READ FROM LAST VALID LOCATION R t XOL t XOH t XOL t XOH XO 540203-15 Figure 20. Expansion-Out Timing t XI t XIR XI t XIS W WRITE TO FIRST AVAILABLE LOCATION t XIS READ FROM FIRST VALID LOCATION R 540203-16 Figure 21. Expansion-In Timing 15 CMOS 2048 × 9 Asynchronous FIFO LH540203 PACKAGE DIAGRAMS 28DIP (DIP28-W-300) DETAIL 7.49 [0.295] 7.11 [0.280] 0° TO 15° 0.30 [0.012] 0.20 [0.008] 34.80 [1.370] 34.54 [1.360] 3.30 [0.130] 7.62 [0.300] TYP. 4.57 [0.180] MAX 3.43 [0.135] 3.18 [0.125] 2.54 [0.100] TYP. DIMENSIONS IN MM [INCHES] 0.51 [0.020] MIN 0.53 [0.021] 0.38 [0.015] MAXIMUM LIMIT MINIMUM LIMIT 28DIP-3 28-pin, 300-mil PDIP 28SOJ (SOJ28-P-300) 28 DETAIL 15 7.9 [0.311] 7.5 [0.295] 1 8.63 [0.340] 8.23 [0.324] 14 3.7 [0.146] 3.3 [0.130] 2.6 [0.102] 2.2 [0.087] 0.64 [0.025] MIN 18.7 [0.736] 18.3 [0.720] 0.8 [0.031] 0.6 [0.024] 0.102 [0.004] 0.20 [0.008] 1.27 [0.050] TYP. DIMENSIONS IN MM [INCHES] 0.53 [0.021] 0.33 [0.013] 1.15 [0.045] 0.85 [0.033] MAXIMUM LIMIT MINIMUM LIMIT 28SOJ300 28-pin, 300-mil SOJ 16 7.0 [0.276] 6.6 [0.260] CMOS 2048 × 9 Asynchronous FIFO LH540203 32PLCC (PLCC32-P-R450) 1.27 [0.050] 4 SIDES BSC 15.11 [0.595] 14.86 [0.585] 13.46 [0.530] 12.45 [0.490] 14.05 [0.553] 13.89 [0.547] 11.51 [0.453] 11.35 [0.447] DETAIL 12.57 [0.495] 12.32 [0.485] 0.10 [0.004] 0.81 [0.032] 0.66 [0.026] 3.56 [0.140] 3.12 [0.123] 2.41 [0.095] 1.52 [0.060] 10.92 [0.430] 9.91 [0.390] 0.38 [0.015] MIN MAXIMUM LIMIT DIMENSIONS IN MM (INCHES) MINIMUM LIMIT 0.53 [0.021] 0.33 [0.013] 32PLCC 32-pin, 450-mil PLCC ORDERING INFORMATION LH540203 Device Type X Package - ## Speed 15 20 25 35 50 Access Time (ns) D 28-pin, 300-mil Plastic DIP (DIP28-W-300) K 28-pin, 300-mil SOJ * (SOJ28-P-300) U 32-pin Plastic Leaded Chip Carrier (PLCC32-P-R450) CMOS 2048 x 9 FIFO * Contact a Sharp representative for availability of SOJ package. Example: LH540203U-25 (CMOS 2048 x 9 FIFO, 32-pin PLCC, 25 ns) 540203MD 17