SIPEX SP774BT

®
SP574B/674B/1674B/774B
12–Bit Sampling A/D Converters
■ Complete Monolithic 12–Bit A/D Converters
■
■
■
■
■
■
with Sample–Hold, Reference, Clock and Tri–
state Outputs
Full Nyquist Sampling at All Sample Rates
Choice of Sampling Rates — 40kHz, 66kHz,
100kHz or 125kHz
Low Power Dissipation — 110mW
12–Bit Linearity Over Temperature
Commercial, Industrial and Military Temperature Ranges
Next–Generation Replacement for 574A, 674A,
1674A, 774A Devices
DESCRIPTION…
The SP574B/674B/1674B/774B (SPx74B) Series are complete 12–bit successive–approximation A/D converters integrated on a single die with tri-state output latches, an internal
reference, clock and a sample–hold. The new “B–Series” features true Nyquist sampling while
maintaining compatibility with prior versions. They are drop–in replacements for the older 574A/
674A/1674A/774A type devices.
STS
28
DB11
27
DB10
DB9
25
26
DB8
24
DB7
23
DB6
DB5
22
NIBBLE A
21
DB4
20
DB3
19
DB2
18
NIBBLE B
DB1
17
DB0
16
DGND
15
NIBBLE C
THREE–STATE BUFFERS AND CONTROL
12–BIT SAR
12–BIT
CAPACITANCE
DAC
COMP
OSC
OFFSET/GAIN
TRIM
REF
CONTROL LOGIC
7.5K
15K
7.5K
N/C
1
VLOGIC
SP574B/674B/1674B/774B
2
12/8
3
CS
4
5
A0
R/C
6
7
8
CE
VCC
REF
OUT
9
AGND
10
REF
IN
12–Bit Sampling A/D Converters
1
11
VEE
15K
7.5K
12
BIP
OFF
13
10V
IN
14
20V
IN
© Copyright 2000 Sipex Corporation
ABSOLUTE MAXIMUM RATINGS
VCC to Digital Common .................................................. 0 to +16.5V
VLOGIC to Digital Common ................................................... 0 to +7V
Analog Common to Digital Common ......................................... ±1V
Control Inputs to Digital Common ................. –0.5V to VLOGIC +0.5V
(CE, CS, A0, 12/8, R/C)
Analog Input Voltage Range ........................................... ±FS ±30%
Analog Inputs to Analog Common ...................................... ±16.5V
(REF IN, BIP OFF, 10VIN)
20VIN to Analog Common ........................................................ ±24V
REF OUT ............................................... Indefinite short to common
................................................................... Momentary short to VCC
Power Dissipation ............................................................. 1000mW
Lead Temperature, Soldering .................................. 300˚C, 10Sec
J/C ..................................................................................... 45˚C/W
MTBF–25˚C Ground Base ................................ 2.915 million hours
MTBF–125˚C Missile Launch ...................... 10.16 thousand hours
•
CAUTION:
ESD (ElectroStatic Discharge) sensitive
device. Permanent damage may occur on
unconnected devices subject to high energy
electrostatic fields. Unused devices must be
stored in conductive foam or shunts.
Personnel should be properly grounded prior
to handling this device. The protective foam
should be discharged to the destination
socket before devices are removed.
Inputs exceeding +30% or –30% of FS will cause erratic performance.
SPECIFICATIONS
(Typical @ 25°C with VCC = +15V, VEE = 0V, VLOGIC = +5V unless otherwise noted.)
PARAMETER
MIN.
TYP.
MAX.
UNIT
RESOLUTION
All models
12
Bits
ANALOG INPUTS
Input Ranges
Bipolar
±5, ±10
V
Unipolar
0 to +10, 0 to +20
V
Input Impedance
SP574B/SP674B
10 Volt Input
3.75
6.25
kΩ
20 Volt Input
15
25
kΩ
SP1674B/SP774B
10 Volt Input
1.875
3.125
kΩ
20 Volt Input
7.45
12.42
kΩ
Nyquist Frequency
SP574B
20
kHz
SP674B
33
kHz
SP1674B
50
kHz
SP774B
62.5
kHz
DIGITAL INPUTS
Logic Inputs CE, CS R/C, AO, 12/8
Logic 1
+2.4
+5.5
V
Logic 0
–0.3
+0.8
V
Current
±0.1
±50
µA
±5
µA
Capacitance
5
pF
12/8 Control Input
Hardwire to VLOGIC or DIGITAL COMMON
DIGITAL OUTPUTS
Logic Outputs DB11–DB0, STS
Logic 1
+2.4
V
Logic 0
+0.4
V
Leakage (High Z State)
±40
µA
Capacitance
5
pF
Parallel Data Output Codes
Unipolar
Positive true binary
Bipolar
Positive true offset binary
INTERNAL REFERENCE
Output Voltage
10.00 ±0.1
V
Output Current
2
mA
SP574B/674B/1674B/774B
12–Bit Sampling A/D Converters
2
CONDITIONS
–0.3V to +5.5V Input
0V to +5.5V Input
ISOURCE ≤ 500µA
ISINK ≤ 1.6mA
Data bits only
Note 1
© Copyright 2000 Sipex Corporation
SPECIFICATIONS (continued)
(Typical @ 25°C with VCC = +15V, VEE = 0V, VLOGIC = +5V unless otherwise noted.)
PARAMETER
CONVERSION TIME
SP574B
12–Bit Conversion
8–Bit Conversion
SP674B
12–Bit Conversion
8–Bit Conversion
SP1674B
12–Bit Conversion
8–Bit Conversion
SP774B
12–Bit Conversion
8–Bit Conversion
ACCURACY
Linearity Error
–A, –J, –S
–B, –K, –T
Differential Linearity Error
–A, –J, –S
–B, –K, –T
Offset
Unipolar
Bipolar
–A, –J, –S
–B, –K, –T
Full Scale (Gain) Error
–A
–B
–J
–K
–S
–T
STABILITY
Unipolar Offset
–J
–K, –A, –S
–B, –T
Bipolar Offset
–J, –A, –S
–K, –B, –T
Gain (Scale Factor)
–J, –A, –S
–K, –B, –T
SP574B/674B/1674B/774B
MIN.
TYP.
MAX.
UNIT
13
10
25
19
µs
µs
9
6
15
11.2
µs
µs
5
4
10
7.6
µs
µs
4
3
8
6
µs
µs
±1.0
±0.5
LSB
LSB
11
11
12
12
Bits
Bits
Bits
Bits
±3
LSB
±10
±4
LSB
LSB
CONDITIONS
@ 25°C and TMIN to TMAX
@ 25°C and TMIN to TMAX
Note 2
@ 25°C
TMIN to TMAX
@ 25°C
TMIN to TMAX
Note 3
% of full scale; TMIN to TMAX
Note 4
No adjustment @ 25°C
With adjustment @ 25°C
No adjustment @ 25°C
With adjustment @ 25°C
No adjustment @ 25°C
With adjustment @ 25°C
No adjustment @ 25°C
With adjustment @ 25°C
No adjustment @ 25°C
With adjustment @ 25°C
No adjustment @ 25°C
With adjustment @ 25°C
±0.3
±0.6
±0.3
±0.45
±0.15
±0.5
±0.22
±0.4
±0.12
±0.8
±0.5
±0.6
±0.25
%FS
%FS
%FS
%FS
%FS
%FS
%FS
%FS
%FS
%FS
%FS
%FS
%FS
±10
±5
±2.5
ppm/°C
ppm/°C
ppm/°C
TMIN to TMAX
TMIN to TMAX
TMIN to TMAX
±10
±5
ppm/°C
ppm/°C
TMIN to TMAX
TMIN to TMAX
±50
±25
ppm/°C
ppm/°C
TMIN to TMAX
TMIN to TMAX
12–Bit Sampling A/D Converters
3
© Copyright 2000 Sipex Corporation
SPECIFICATIONS (continued)
(Typical @ 25°C with VCC = +15V, VEE = 0V, VLOGIC = +5V unless otherwise noted.)
PARAMETER
MIN.
POWER REQUIREMENTS
+4.5
VLOGIC
ILOGIC
SP574B
SP674B
SP1674B
SP774B
VCC
+11.4
ICC
SP574B
SP674B
SP1674B
SP774B
POWER DISSIPATION
SP574B
SP674B
SP1674B
SP774B
ENVIRONMENTAL
Operating Temperature Range
–J, –K
0
–A, –B
–40
–S, –T
–55
Storage Temperature Range
–J, –K
–40
–A, –B, –S, –T
–65
TYP.
MAX.
UNIT
+5.5
V
1
1
1
1
3
3
3
3
+16.5
mA
mA
mA
mA
V
7
7
10
10
9
9
12.5
12.5
mA
mA
mA
mA
110
110
155
155
150
150
200
200
mW
mW
mW
mW
+70
+85
+125
°C
°C
°C
+85
+150
°C
°C
CONDITIONS
Notes:
1.
Available for external loads. External load should not change during conversion. When supplying an
external load and operating on a +12V supply, a buffer amplifier must be provided for the reference
output.
2.
Minimum resolution for which no missing codes are guaranteed.
3.
Externally adjustable to zero. See Calibration information.
4.
Fixed 50Ω resistor between REF OUT and REF IN.
5.
Specifications are identical for all models unless otherwise noted.
TYPICAL AC DYNAMICS
Measurement/Model
SP574B
Test Conditions:
Sampling Rate
40
Input Frequency (FIN )
19
SP674B
SP1674B
SP774B
Unit
67
31
100
49
125
61
kHz
kHz
SFDR
90
85
80
77
dB
THD
-80
-80
-77
-76
dB
SINAD
SNR
72
72
71
71
dB
72.5
72.5
72.5
72.5
dB
Note:
1.
Refer to Figure 10, for typical FFT at Nyquist sampling rate.
SP574B/674B/1674B/774B
12–Bit Sampling A/D Converters
4
© Copyright 2000 Sipex Corporation
PIN ASSIGNMENTS…
PIN
FUNCTION
PIN
FUNCTION
1
VLOGIC
28
STS
2
12/8
27
DB11(MSB)
3
CS
26
DB10
4
A0
25
DB9
5
R/C
24
DB8
6
CE
23
DB7
7
VCC
22
DB6
8
REF OUT
21
DB5
9
ANA GND(AC)
20
DB4
10
REF IN
19
DB3
11
N/C*
18
DB2
12
BIP OFF
17
DB1
13
10VIN
16
DB0(LSB)
CIRCUIT OPERATION…
The SPx74B are complete monolithic capacitor
DAC–based 12–bit analog-to-digital converters with integral voltage reference, comparator,
successive–approximation register (SAR),
sample–and–hold, clock, output buffers and
control circuitry. The high level of integration
of the SPx74B Series means they require few
external components.
When the control section of the SPx74B initiates
a conversion command, the clock is enabled and
the successive–approximation register is reset to
all zeros. Once the conversion cycle begins, it can
not be stopped or restarted and data is not available
from the output buffers. The SAR, timed by the
clock, sequences through the conversion cycle and
returns an end–of–convert flag to the control section of the ADC. The clock is then disabled by the
control section, the output status goes low, and the
control section is enabled to allow the data to be
read by external command.
14
20VIN
15
DIG. GND
*This pin is not connected inside the device so it can
be tied to –15V, ground, or left floating.
The internal SPx74B 12–bit CDAC is sequenced
by the SAR starting from the MSB to the LSB at
the beginning of the conversion cycle to provide
an output voltage from the CDAC that is equal
to the input signal voltage (which is divided by
the input voltage divider network). The comparator determines whether the addition of each
successively–weighted bit voltage causes the
CDAC output voltage summation to be greater
or less than the input voltage; if the sum is less,
the bit is left on; if more, the bit is turned off.
After testing all the bits, the SAR contains a 12–
bit binary code which accurately represents the
input signal to within ±1⁄2 LSB.
FEATURES…
The SPx74B Series feature standard bipolar
and unipolar input ranges of 10V and 20V. Input
ranges are controlled by a bipolar offset pin and
laser-trimmed for specified linearity, gain and
offset accuracy. Power requirements are +5V
and +12V to +15V with a maximum dissipation
of 150mW at the specified voltages. Conversion
times of 8µs, 10µs, 15µs and 25µs are available,
as are units with 10, 25 or 50ppm/°C temperature coefficients for flexible matching to specific application requirements.
The internal reference provides the voltage reference to the CDAC with excellent stability over
temperature and time. The reference is trimmed
to 10.00 Volts ±1% and can supply up to 2mA to
an external load in addition to that required to
drive the reference input resistor (1mA) and
offset resistor (1mA) when operating with ±15V
supplies. If the SPx74B is used with ±12V
supplies, or if external current must be supplied
over the full temperature range, an external
buffer amplifier is recommended. Any external
load on the SPx74B reference must remain
constant during conversion.
The SPx74B Series are available in nine product grades for each conversion time. The –J
and –K models are specified over 0˚C to +
70˚C commercial temperature range; the –A
and –B models are specified over the –40˚C
to +85˚C industrial temperature range; the –S
and –T models are specified over the –55˚C to
+125˚C military temperature range. Package
options include 28–pin CDIP, 28–pin plastic
DIP (both narrow and wide), 28-pin PLCC
and 28–pin SOIC.
SP574B/674B/1674B/774B
12–Bit Sampling A/D Converters
5
© Copyright 2000 Sipex Corporation
controlled through the normal R/C control line
(refer to Figure 1). When the R/C line makes a
negative transition, the SPx74B starts the timing
of the sampling and conversion. The first two
clock cycles are allocated to signal acquisition of
the input by the CDAC (this time is defined as
tACQ). Following these two cycles, the input sample
is taken and held. The A/D conversion follows this
cycle with the duration controlled by the internal
clock cycle, which is determined by the specific
product model. Note that because the sample is
taken relative to the R/C transition, tACQ is also the
traditional “aperture delay” of this internal sample
and hold. Since tACQ is measured in clock cycles,
its duration will vary with the internal clock frequency.
SAMPLE–AND–HOLD FUNCTION
Although there is no sample–and–hold circuit in
the classical sense, the sampling nature of the
capacitive DAC makes the SPx74B appear to have
a built–in sample–and–hold. The sample–and–
hold function of the CDAC architecture is optimized to provide full Nyquist sampling at any
maximum sampling rate. Because the S/H function is included in the ADC circuitry, the majority
of the S/H specifications are included within the A/
D specifications.
Note that some system architectures may use an
external sample–and–hold. The built–in S/H function of the SPx74B will provide additional isolation. Once the internal sample is taken by the
CDAC capacitance, the input of the SPx74B is
disconnected from the input. This prevents transients occurring during conversion from being
inflicted upon the attached buffer. All other 574/
674–type circuits will cause a transient load current on the input which will upset the buffer output
and may add error to the conversion itself. In
addition, the isolation of the input after the acquisition time in the SPx74B allows you the opportunity to release the HOLD on an external sample–
and–hold and start it tracking the next sample. This
will increase system throughput with your existing
components.
Offset, gain and linearity errors of the S/H circuit,
as well as the effects of its droop rate, are included
in the overall specs for the SPx74B.
USING THE SPX74B SERIES
Typical Interface Circuit
The SPx74B is a complete A/D converter that is
fully operational when powered up and issued a
Start Convert Signal. Only a few external components are necessary. The SPx74B Series have four
standard input ranges: 0V to +10V, 0V to +20V,
±5V and ±10V. Figure 2 depicts a typical interface
circuit for operating the SPx74B in a unipolar
input mode. Figure 3 depicts a typical interface
circuit for operating the SPx74B in a bipolar input
mode. Further information is given in the following sections on these connections, but first a few
considerations concerning board layout to achieve
the best operation.
When using an external S/H, the SPx74B acts as
any other 574–type device because the internal S/
H is transparent. The sample/hold function in the
SPx74B is inherent to the capacitor DAC structure, and its timing characteristics are determined
by the internally generated clock. However, for
multiplexer operation, the internal S/H may eliminate the need for an external S/H. The operation of
the S/H function is internal to the SPx74B and is
For each application of this device, strict attention
must be given to power supply decoupling, board
layout (to reduce pickup between analog and digital sections), and grounding. Digital timing, calibration and the analog signal source must be
considered for correct operation.
CE
R/C
t(ACQ)
To achieve specified accuracy, a double–sided
printed circuit board with a copper ground plane
on the component side is recommended. Keep
analog signal traces away from digital lines. It is
best to lay the PC board out such that there is an
analog section and a digital section with a single
point ground connection between the two through
an RF bead. If this is not possible, run analog
ACQUISITION
TIME
WAIT FOR
CONVERT SIGNAL
CONVERSION
WAIT FOR
BUS READ
VIN
CDAC VOLTAGE
0 VOLTS
ACQUISITION TIME =
APERTURE DELAY TIME =
0.12 x tCONVERT
Figure 1. Sample–and–Hold Function
SP574B/674B/1674B/774B
12–Bit Sampling A/D Converters
6
© Copyright 2000 Sipex Corporation
OUTPUT BITS
MSB
27
26
25 24 23
22
21 20 19 18 17 16
LSB
2
12/8
NIBBLE A
3
CS
A0
4
5
R/C
CONTROL
LOGIC
NIBBLE B
NIBBLE C
THREE–STATE BUFFERS AND CONTROL
6
CE
12–BITS
OSCILLATOR
28
12–BIT SAR
R1
100KΩ
-15V
1
+
+15V
0 TO 10V 10V
IN 13
100KΩ
ANALOG
INPUTS
STROBE
12–BITS
SAMPLE/HOLD
20V
IN 14
CDAC
STS
VLOGIC
10µF
COMP
15
+5V
0.1µF
DGND
LSB
MSB
BIP
0 TO 20V OFF
12
100Ω
VREF
OUT 8
OFFSET/GAIN
TRIM NETWORK
REF
REF
AMP
R2
100Ω
10
VREF
IN
VCC 7
+
VEE 11
10µF
0.1µF
N.C.
9
+15V
AGND
Figure 2. Unipolar Input Connections
signals between ground traces and cross digital
lines at right angles only.
Capacitor bypass pairs are needed from each supply pin to its respective ground to filter noise and
counter the problems caused by the variations in
supply current. A 10µF tantalum and a 0.1µF
ceramic type in parallel between VLOGIC (pin 1) and
digital common (pin15), and VCC (pin 7) and
analog common (pin 9) is sufficient. VEE is generated internally so pin 11 may be grounded or
connected to a negative supply if the SPx74B is
being used to upgrade an already existing design.
Grounding Considerations
Any ground path from the analog and digital
ground should be as low resistance as possible to
accommodate the ground currents present with
this device.
The analog ground current is approximately
6mA DC while the digital ground is 3mA DC.
The analog and digital common pins should be
tied together as close to the package as possible
to guarantee best performance. The code–dependent currents flow through the VLOGIC and
VCC terminals and not through the analog and
digital common pins.
CALIBRATION AND CONNECTION
PROCEDURES
Unipolar
The calibration procedure consists of adjusting the
converter’s most negative output to its ideal value for
offset adjustment, and then adjusting the most positive
output to its ideal value for gain adjustment.
Power Supplies
The supply voltages for the SPx74B must be kept
as quiet as possible from noise pickup and also
regulated from transients or drops. Because the
part has 12–bit accuracy, voltage spikes on the
supply lines can cause several LSB deviations on
the output. Switching power supply noise can be a
problem. Careful filtering and shielding should be
employed to prevent the noise from being picked
up by the converter.
SP574B/674B/1674B/774B
Starting with offset adjustment and referring to
Figure 2, the midpoint of the first LSB increment
should be positioned at the origin to get an output
code of all 0s. To do this, an input of +1⁄2 LSB or
+1.22mV for the 10V range and +2.44mV for the
20V range should be applied to the SPx74B.
Adjust the offset potentiometer R1 for code transition flickers between 0000 0000 0000 and 0000
0000 0001.
12–Bit Sampling A/D Converters
7
© Copyright 2000 Sipex Corporation
+9.9927V for the ±10V range. Adjust the gain
potentiometer R2 for flicker between codes 1111
1110 and 1111 1111 1111.
The gain adjustment should be done at positive full
scale. The ideal input corresponding to the last
code change is applied. This is 11⁄2LSB below the
nominal full scale which is +9.9963V for the 10V
range and +19.9927V for the 20V range. Adjust
the gain potentiometer R2 for flicker between
codes 1111 1111 1110 and 1111 1111 1111. If
calibration is not necessary for the intended application, replace R2 with a 50Ω, 1% metal film
resistor and remove the network analog input to
pin 13 for the 0V to 10V range or to pin 14 for the
0V to 20V range.
Alternative
The 100Ω potentiometer R2 provides gain adjust
for 10V and 20V ranges. In some applications, a
full scale of 10.24V (for and LSB of 2.5mV) or
20.48 (for an LSB of 5.0mV) is more convenient.
For these, replace R2 by a 50Ω, 1% metal film
resistor. Then to provide gain adjust for the 10.24
range, add a 200Ω potentiometer in series with pin
13. For the 20.48V range, add a 1000Ω potentiometer in series with pin 14.
Bipolar
The gain and offset errors listed in the specifications may be adjusted to zero using the potentiometers R1 and R2 (See Figure 3). If adjustment is not
needed, either or both pots may be replaced by a
50Ω, 1% metal film resistor.
CONTROLLING THE SPx74B
The SPx74B can be operated by most microprocessor systems due to the control input pins and
on–chip logic. It may also be operated in the
“stand–alone” mode and enabled by the R/C
input pin. Full microprocessor control consists
of selecting an 8– or 12–bit conversion cycle,
initiating the conversion, and reading the output
data when ready. The output read has the options
of choosing either 12–bits at once or 8–bits followed by 4–bits in a left–justified format. All five
control inputs are TTL/CMOS compatible and
include 12/8, CS, A0, R/C and CE. The use of these
inputs in controlling the converter’s operation is
To calibrate, connect the analog input signal to pin
13 for a ±5V range or to pin 14 for a ±10V range.
First apply a DC input voltage 1⁄2 LSB above
negative full scale which is –4.9988V for the ±5V
range or –9.9976V for the ±10V range. Adjust the
offset potentiometer R1 for flicker between output
codes 0000 0000 0000 and 0000 0000 0001. Next,
apply a DC input voltage 11⁄2 LSB below positive
full scale which is +4.9963V for the ±5 range or
OUTPUT BITS
MSB
12/8
CS
A0
R/C
CE
27
26
25 24 23
22
21 20 19 18 17 16
LSB
2
NIBBLE A
3
4
CONTROL
LOGIC
5
NIBBLE B
NIBBLE C
THREE–STATE BUFFERS AND CONTROL
6
12–BITS
OSCILLATOR
28
12–BIT SAR
1
+
ANALOG
INPUTS
10V
IN 13
SAMPLE/HOLD
±10V
20V
IN 14
MSB
10µF
STROBE
12–BITS
±5V
CDAC
STS
VLOGIC
COMP
15
+5V
0.1µF
DGND
LSB
BIP
OFF 12
100Ω
R1
VREF
OUT 8
100Ω
R2
OFFSET/GAIN
TRIM NETWORK
REF
REF
AMP
10
VREF
IN
VCC 7
+
VEE 11
10µF
0.1µF
9
+15V
N.C.
AGND
Figure 3. Bipolar Input Connections
SP574B/674B/1674B/774B
12–Bit Sampling A/D Converters
8
© Copyright 2000 Sipex Corporation
Conversion Length
A conversion start transition latches the state of A0
as shown in Figure 4 and Table 1. The latched state
determines if the conversion stops with 8–bits (A0
high) or continues for 12–bits (A0 low). If all 12–
bits are read following an 8–bit conversion, the
three LSB’s will be a logic “0” and DB3 will be a
logic “1”. A0 is latched because it is also involved
in enabling the output buffers as explained elsewhere. No other control inputs are latched.
shown in Table 1, and the internal control logic is
shown in a simplified schematic in Figure 4.
Conversion Start
A conversion may be initiated by a logic transition
on any of the three inputs: CE, CS R/C, as shown
in Table 1. The last of the three to reach the correct
state starts the conversion, so one, two or all three
may be dynamically controlled. The nominal delay from each is the same and all three may change
state simultaneously. In order to assure that a
particular input controls the start of conversion, the
other two should be setup at least 50ns earlier.
Refer to the convert mode timing specifications.
The Convert Start timing diagram is shown in
Figure 6.
Stand–Alone Operation
The simplest interface is a control line connected
to R/C. The other controls must be tied to known
states as follows: CE and 12/8 are wired high, A0
and CS are wired low. The output data arrives in
words of 12–bits each. The limits on R/C duty
cycle are shown in Figures 8 and 9. The duty cycle
may be within and including the extremes shown
in the specifications. In general, data may be read
when R/C is high unless STS is also high, indicating a conversion is in progress.
The output signal STS is the status flag and goes
high only when a conversion is in progress.
While STS is high, the output buffers remain in
a high impedance state so that data can not be
read. Also, when STS is high, an additional Start
Convert will not reset the converter or reinitiate
a conversion. Note, if A0 changes state after a
conversion begins, an additional Start Convert
command will latch the new state of A0 and
possibly cause a wrong cycle length for that
conversion (8–versus 12–bits).
CE CS R/C 12/8 A0
Reading Output Data
The output data buffers remain in a high impedance state until the following four conditions are
met: R/C is high, STS is low, CE is high and CS is
low. The data lines become active in response to
these four conditions, and output data according to
the conditions of the control lines 12/8 and A0. The
timing diagram for this process is shown in Figure
7. When 12/8 is high, all 12 data outputs become
active simultaneously and the A0 input is ignored.
The 12/8 input is usually tied high or low; it is TTL/
CMOS compatible. When 12/8 is low, the output
is separated into two 8–bit bytes as shown below:
BYTE 1
BYTE2
xxxx xxxx
xxxx 0000
OPERATION
0
x
x
x
x
None
x
1
x
x
x
None
0
0
x
0
Initiate 12–Bit Conversion
0
0
x
1
Initiate 8–Bit Conversion
1
0
x
0
Initiate 12–Bit Conversion
1
0
x
1
Initiate 8–Bit Conversion
1
0
x
0
Initiate 12–Bit Conversion
1
0
x
1
Initiate 8–Bit Conversion
1
0
1
1
x
Enable 12–Bit Output
1
0
1
0
0
Enable 8 MSB's Only
1
0
1
0
1
Enable 4 LSB's plus 4
Trailing Zeroes
MSB
LSB
This configuration makes it easy to connect to an
8–bit data bus as shown in Figure 5. The A0 control
can be connected to the least significant bit of the
address bus in order to store the output data into
two consecutive memory locations. When A0 is
pulled low, the 8 MSB’s are enabled only. When
A0 is high, the 8 MSB’s are disabled, bits 4 through
7 are forced to a zero and the four LSB’s are
enabled. The two byte format is “left justified data”
as shown above and can be considered to have a
decimal point or binary to the left of byte 1.
Table 1. SPx74B Control Input Truth Table
SP574B/674B/1674B/774B
12–Bit Sampling A/D Converters
9
© Copyright 2000 Sipex Corporation
A0 may be toggled without damage to the converter at any time. Break–before–make action is
guaranteed between the two data bytes. This assures that the outputs which are strapped together
in Figure 5 will never be enabled at the same time.
"NYQUIST" SAMPLING
Each of the SPx74B analog-to-digital converters has been designed to provide Nyquist sampling (highest input frequency is 1/2 of the
sampling rate) data conversion with no degradation in DC performance. This is shown in
Figure 10. Note that the Differential Linearity
and Integral Linearity min/max values are well
within the ± 1/2 LSB limits of a K-version
Converter. Also, the Typical FFT at Nyquist
rates shown on Figure 10 reflect the values
listed in the Typical AC Dynamics table.
In Figure 7, it can be seen that a read operation
usually begins after the conversion is complete and
STS is low. If earlier access is needed, the read can
begin no later than the addition of times tDD and tHS
before STS goes low.
NIBBLE B ZERO
OVERRIDE
NIBBLE A, B
INPUT BUFFERS
NIBBLE C
12/8
READ CONTROL
CS
A0
R/C
H
CE
D Q
CK
R
EOC8
CK
Q
D
DELAY
STS
Q
A0 LATCH
EOC12
Figure 4. SPx74B Control Logic
A0
ADDRESS BUS
28
STS
2
12/8
DB11 (MSB)
4
27
26
A0
25
24
23
DATA
BUS
22
SPx74B
21
20
19
18
17
DB0 (LSB)
DIG
COM
16
15
Figure 5. Interfacing SPx74B to 8–Bit Interface Bus
SP574B/674B/1674B/774B
12–Bit Sampling A/D Converters
10
© Copyright 2000 Sipex Corporation
CONVERT MODE TIMING
tHEC
CE
CS
R/C
tSSC
tSRC
tHRC
A0
tSAC
tHAC
STS
tDSC
tC
HIGH IMPEDANCE
DB11–
DB0
CHARACTERISTICS
Typical @ 25˚C, VCC = +15V or +10V, VLOGIC = +5V, VEE = 0V, unless otherwise specified.
PARAMETER
tDSC STS Delay from CE
MIN.
TYP.
MAX.
200
UNITS
ns
tHEC CE Pulse Width
50
ns
tSSC CS to CE Setup
50
ns
tHSC CS Low during CE High
50
ns
tSRC R/C to CE Setup
50
ns
tHRC R/C Low during CE High
50
ns
tSAC A0 to CE Setup
0
ns
tHAC A0 Valid during CE High
50
tC
Conversion Time1, 3, 4
CONDITIONS
ns
See specifications
NOTES:
1.
Parameters guaranteed by design and sample tested.
2.
Parameters 100% tested @ 25˚C on special orders.
3.
100% tested.
4.
TMIN to TMAX.
Figure 6. Convert Mode Timing
SP574B/674B/1674B/774B
12–Bit Sampling A/D Converters
11
© Copyright 2000 Sipex Corporation
READ MODE TIMING
CE
CS
tSSR
tHSR
tHRR
R/C
tSRR
A0
tSAR
tHAR
STS
tHD
HIGH
DB11–
DB0
IMPEDANCE
DATA
VALID
tDD
tHL
CHARACTERISTICS
Typical @ 25˚C, VCC = +15V or +12V, VLOGIC = +5V, VEE = 0V, unless otherwise specified.
tDD
PARAMETER
Access Time From CE2
tHD
Data Valid After CE Low2
tHL
Output Float Delay2
MIN.
TYP.
MAX.
150
25
UNITS
ns
ns
150
ns
tSSR CS to CE Setup
50
0
ns
tSRR R/C to CE Setup
0
0
ns
tSAR A0 to CE Setup
50
tHSR CS Valid After CE Low
0
0
ns
tHRR R/C High After CE Low
0
50
ns
tHAR A0 Valid After CE Low
50
tHS
300
STS Delay After Data Valid
CONDITIONS
ns
ns
1000
ns
NOTES:
1.
Parameters guaranteed by design and sample tested.
2.
Parameters 100% tested @ 25˚C on special orders.
Figure 7. Read Mode Timing
SP574B/674B/1674B/774B
12–Bit Sampling A/D Converters
12
© Copyright 2000 Sipex Corporation
STAND–ALONE MODE TIMING CHARACTERISTICS
Typical @ 25˚C, VCC= +15V or +12V, VLOGIC = +5V, VEE =0V, unless otherwise specified.
PARAMETER
tHRL Low R/C Pulse Width 2
tDS
MIN.
50
TYP .
UNITS
ns
200
ns
STS Delay from R/C 2
tHDR Data Valid After R/C Low 2
tHS
MAX.
25
STS Delay After Data Valid 2
tHRH High R/C Pulse Width
CONDITIONS
ns
300
1000
ns
150
ns
tDDR Data Access Time
150
ns
NOTES:
1.
Parameters guaranteed by design and sample tested.
2.
Parameters 100% tested @ 25˚C on special orders.
tHRL
R/C
tDS
tC
STS
tHDR
tHS
DB11–DB0
DATA VALID
DATA VALID
Figure 8. Low Pulse for R/C — Outputs Enabled After Conversion
R/C
tDS
tHRH
tC
STS
tDDR
DB11–DB0
HIGH–Z
tHDR
DATA VALID
HIGH–Z
Figure 9. High Pulse For R/C — Outputs Enabled While R/C is High, Otherwise High Impedance
SP574B/674B/1674B/774B
12–Bit Sampling A/D Converters
13
© Copyright 2000 Sipex Corporation
Figure 10. Typical FFT at Nyquist Sampling Rates
ORDERING INFORMATION
Model
Monotonicity
Linearity
Gain TC
Temperature Range
Package Types
25µs Conversion Time
SP574BJ ............... 11 Bits .............................. ±1.0
SP574BK .............. 12 Bits .............................. ±0.5
SP574BA .............. 11 Bits .............................. ±1.0
SP574BB .............. 12 Bits .............................. ±0.5
SP574BS .............. 11 Bits .............................. ±1.0
SP574BT ............... 12 Bits .............................. ±0.5
LSB ...................... 50ppm/°C ....................... 0°C to +70°C ................................. L, N, P, S
LSB ...................... 25ppm/°C ....................... 0°C to +70°C ................................. L, N, P, S
LSB ...................... 50ppm/°C ....................... –40°C to +85°C ............................. L, N, P, S
LSB ...................... 25ppm/°C ....................... –40°C to +85°C ............................. L, N, P, S
LSB ...................... 50ppm/°C ....................... –55°C to +125°C ........................................ Q
LSB ...................... 25ppm/°C ....................... –55°C to +125°C ........................................ Q
15µs Conversion Time
SP674BJ ............... 11 Bits .............................. ±1.0
SP674BK .............. 12 Bits .............................. ±0.5
SP674BA .............. 11 Bits .............................. ±1.0
SP674BB .............. 12 Bits .............................. ±0.5
SP674BS .............. 11 Bits .............................. ±1.0
SP674BT ............... 12 Bits .............................. ±0.5
LSB ...................... 50ppm/°C ....................... 0°C to +70°C ................................. L, N, P, S
LSB ...................... 25ppm/°C ....................... 0°C to +70°C ................................. L, N, P, S
LSB ...................... 50ppm/°C ....................... –40°C to +85°C ............................. L, N, P, S
LSB ...................... 25ppm/°C ....................... –40°C to +85°C ............................. L, N, P, S
LSB ...................... 50ppm/°C ....................... –55°C to +125°C ........................................ Q
LSB ...................... 25ppm/°C ....................... –55°C to +125°C ........................................ Q
10µs Conversion Time
SP1674BJ ............. 11 Bits .............................. ±1.0
SP1674BK ............ 12 Bits .............................. ±0.5
SP1674BA ............ 11 Bits .............................. ±1.0
SP1674BB ............ 12 Bits .............................. ±0.5
SP1674BS ............ 11 Bits .............................. ±1.0
SP1674BT ............. 12 Bits .............................. ±0.5
LSB ...................... 50ppm/°C ....................... 0°C to +70°C ................................. L, N, P, S
LSB ...................... 25ppm/°C ....................... 0°C to +70°C ................................. L, N, P, S
LSB ...................... 50ppm/°C ....................... –40°C to +85°C ............................. L, N, P, S
LSB ...................... 25ppm/°C ....................... –40°C to +85°C ............................. L, N, P, S
LSB ...................... 50ppm/°C ....................... –55°C to +125°C ........................................ Q
LSB ...................... 25ppm/°C ....................... –55°C to +125°C ........................................ Q
8µs Conversion Time
SP774BJ ............... 11 Bits .............................. ±1.0
SP774BK .............. 12 Bits .............................. ±0.5
SP774BA .............. 11 Bits .............................. ±1.0
SP774BB .............. 12 Bits .............................. ±0.5
SP774BS .............. 11 Bits .............................. ±1.0
SP774BT ............... 12 Bits .............................. ±0.5
LSB ...................... 50ppm/°C ....................... 0°C to +70°C ................................. L, N, P, S
LSB ...................... 25ppm/°C ....................... 0°C to +70°C ................................. L, N, P, S
LSB ...................... 50ppm/°C ....................... –40°C to +85°C ............................. L, N, P, S
LSB ...................... 25ppm/°C ....................... –40°C to +85°C ............................. L, N, P, S
LSB ...................... 50ppm/°C ....................... –55°C to +125°C ........................................ Q
LSB ...................... 25ppm/°C ....................... –55°C to +125°C ........................................ Q
N — 28–pin, 0.3" wide plastic DIP .................. L — 28-pin, PLCC ....... S — 28–pin, 0.3" SOIC
P — 28–pin, 0.6" wide plastic DIP ......................................................... Q — 28–pin, 0.6" Ceramic DIP (consult factory)
SP574B/674B/1674B/774B
12–Bit Sampling A/D Converters
14
© Copyright 2000 Sipex Corporation
Corporation
SIGNAL PROCESSING EXCELLENCE
Sipex Corporation
Headquarters and
Sales Office
22 Linnell Circle
Billerica, MA 01821
TEL: (978) 667-8700
FAX: (978) 670-9001
e-mail: [email protected]
Sales Office
233 South Hillview Drive
Milpitas, CA 95035
TEL: (408) 934-7500
FAX: (408) 935-7600
Sipex Corporation reserves the right to make changes to any products described herein. Sipex does not assume any liability arising out of the
application or use of any product or circuit described hereing; neither does it convey any license under its patent rights nor the rights of others.
SP574B/674B/1674B/774B
12–Bit Sampling A/D Converters
15
© Copyright 2000 Sipex Corporation