MURATA-PS OKLP-X25-W12-C

OKLP-X/25-W12-C
www.murata-ps.com
25A Po
Power Block Non-Isolated DC-DC Converter
Typical unit
FEATURES
PRODUCT OVERVIEW

High efficiency (91% @12Vin, 1.8Vout)
The “25A Power Block” is a non-isolated switching power converter, providing up to 49.5W with
an input range of 7-13.2V DC, a regulated output
of 0.8-3.6V DC, and load current up to 25A at 1V
output voltage. The Power Block is a synchronous

Power Block (25A, 7-13Vin, 0.8-3.6Vout, SMT)

Input under-voltage lockout

Small footprint (0.5” [12.7] x 0.67” [17] x 0.42”
[10.7])

No minimum load required
buck converter. It has been implemented using a
synchronous buck gate driver IC with co-packed
control and synchronous MOSFETs and Schottky
diode. The output filter consists of 375nH inductance and 20μf capacitance.

Low Output Ripple

-20°C to 70°C operating temperature
+5V
VIN
PWM
VOUT
Output
Filter
GND
GND
Thermal Sensor
TEMP
2.15KΩ
+CS
-CS
Figure 1. Block Diagram
For full details go to
www.murata-ps.com/rohs
(pending)
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OKLP-X/25-W12-C.A01.D22 Page 1 of 20
OKLP-X/25-W12-C
25A Power Block Non-Isolated DC-DC Converter
PERFORMANCE SPECIFICATIONS SUMMARY AND ORDERING GUIDE
Input ➁
Output
Root Model
OKLP-X/25-W12-C ➀
Efficiency ➂
Vout
(Volts)
Iout (Amps,
max.)
Power
(Watts)
Vin nom.
(Volts)
Range
(Volts)
Iin, full load
(Amps)
Min.
Typ.
0.8-3.3
25
49.5
12
7-13.2
7.56
92%
93.5%
Dimensions
Inches (mm)
0.5 x 0.67 x 0.42
(12.7 x 17.02 x 10.7)
➀ Typical at Ta=+25°C
➁ @Vin=7V, Vout=3.3V, Iout=15A
➂ @Vin=12V, Vout=3.3V, Iout=15A
PART NUMBER STRUCTURE
OK L P - X / 25 - W12 - C
Okami Non-isolated PoL
RoHS Hazardous Substance Compliance
C = RoHS-6 (does not claim EU RoHS exemption
LGA Surface Mount
Power Block
Output Voltage Range
0.8-3.3Vdc
Input Voltage Range
7-13.2Vdc
Maximum Rated Output
Current in Amps
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OKLP-X/25-W12-C.A01.D22 Page 2 of 20
OKLP-X/25-W12-C
25A Power Block Non-Isolated DC-DC Converter
1. Input Requirements
Table 1.1. Voltage:
Parameter
Notes
Min
Nom
Max
Units
Enable (Pin 2) Turn-on Module
2.0
V
Turn-off Module
0.8
Vin (Pin 1):
Operating
7
12
13.2
V
Absolute max
16.5
+5V (Pin 10): Operating
4.5
5
6
Under-voltage lockout, rising
4.1
V
Under-voltage lockout, falling
3.0
PWM (Pin 8): High
2.5
V pin 10 +0.3V
1
V
Low
0.8
1. Before the PWM signal is applied to pin #8 (PWM), ensure that +5V is applied to the gate driver IC supply (pin 10).
Otherwise, permanent damage may result to the unit.
Table 1.2. Current:
Parameter
Vin=7V, Vout=3.3V, Iout=15A (Pin 1)
Vin=7V, Vout=1.8V, Iout=20A
Vin=12V, Vout=1.8V, Iout=20A
+5V (Pin 10) (Switching at 500 KHz)
Notes
Min
Nom
30
Max
7.56
6.335
3.37
40
Units
A
A
A
mA
2. Output Requirements
Table 2.1. Voltage:
Parameter
Notes
Min
0.8
Nom
1.8
Max
3.6
Units
V
Notes
Min
Nom
Max
Units
1
1
1
0
0
0
25
20
15
A
A
A
Operating Range
Table 2.2. Current per Phase:
Parameter
Operating Range
1.0Vout
1.8Vout
3.3Vout
1. 7V to 12V input, switching at 500KHz.
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OKLP-X/25-W12-C.A01.D22 Page 3 of 20
OKLP-X/25-W12-C
25A Power Block Non-Isolated DC-DC Converter
Table 2.3. Power/Efficiency
Parameter
Notes
Min
Nom
1, 2
88
86.5
90.5
89
93.5
92
90
89
93
91
95.5
93.5
Output Power
Efficiency:
1.0V output at 25A, Vin=7V
1.0V output at 25A, Vin=12V
1.8V output at 20A, Vin=7V
1.8V output at 20A, Vin=12V
3.3V output at 15A,Vin=7V
3.3V output at 15A, Vin=12V
Max
49.5
Units
W
%
%
%
%
%
%
1. 7V to 12V input, switching at 400KHz, with 200 LFM at 55C
2. Gate drive and controller losses are included. For the purpose of this calculation, controller loss is assumed to be 0.2W.
Table 2.4. Capacitor
Parameter
Input Capacitance
Output Capacitance
Notes
1
2, 3
Min
Nom
60
20.1
Max
Units
μF
μF
1. 6*10μf/16V/X7R
2. 2 X 10μf, 0805, 6.3V, X7R + 1 X 0402, 0.1μf, 16V, X7R
3. Additional input and output capacitors are to be added externally as part of the buck regulator design.
Table 2.5. Resistor
Parameter
Output-to-GND Resistor
Notes
Min
Nom
301
Max
Units
Ω
Notes
1
Min
323
0.665
Nom
380
0.7
35
Max
437
0.735
Units
nH
mΩ
A
Notes
Min
Nom
495
1.35
-4.4
Max
Units
uA
V
mV / C
Table 2.6. Inductor
Parameter
Inductance
DCR (25C)
Isat (125C)
1. See Block Diagram for DCR sense requirements.
Table 3. Temperature Sense
Parameter
Bias current sourced from controller (into Pin 7)
Voltage at 25C (Pin 7)
Temperature coefficient (0 to 130 C)
1.34
1.36
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OKLP-X/25-W12-C.A01.D22 Page 4 of 20
OKLP-X/25-W12-C
25A Power Block Non-Isolated DC-DC Converter
4. Dynamic Load Response: Iout 50-100-50% nom
Settling time to within 2% of Vout (See Dynamic Load Response plots)
5. Mechanical
5.1. General
Single-board, designed for machine pick-N-place. Footprint is 0.5” x 0.67”. Maximum height is 0.48”.
Table 5.2.
Parameter
Dimensions
Weight
Notes
Nom
0.5x 0.67 X 0.42
12.7x 17.02 X 10.7
0.179
5.09
Units
inches
mm
ounces
grams
Table 5.3. Pinout
Pin #
1
2
3
4
5
6,9
7
8
10
Name
Vin
Enable
+Cs
-Cs
Vo
GND
Temperature
PWM
+5V
Function
Input voltage for the MOSFET
Turn Off Module (Enable < 0.8V), Turn On Module (Enable > 2.0V)
Positive DCR sense
Negative DCR sense
Output voltage
Ground for both input and output
From temperature sense device on the power block for temperature sensing.
3.3V compliant PWM signal to the gate driver
Bias voltage for gate driver
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OKLP-X/25-W12-C.A01.D22 Page 5 of 20
OKLP-X/25-W12-C
25A Power Block Non-Isolated DC-DC Converter
5.4. Mechanical Specifications
[17.52]
0.690
[13.41]
0.528
[2.06]
0.081
[1.52]
0.060
[3.35]
0.132
1
[10.16]
0.400
2
3
4
5
[6.604]
0.260
[5.08]
0.200
CL
CL
10
9
8
7
[8.76]
0.345
[13.21]
0.520
6
10x
[2.74]
0.108
CL
RECOMMENDED FOOTPRINT
(VIEWED THROUGH POWER BLOCK)
10x
[1.96]
0.077
Figure 2. Recommended Footprint
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OKLP-X/25-W12-C.A01.D22 Page 6 of 20
OKLP-X/25-W12-C
25A Power Block Non-Isolated DC-DC Converter
5.4. Mechanical Specifications, cont.
.025 X 45°
(PIN #1
INDICATOR)
17.0
.67
10.7
.42
4.00
.157
12.7
.50
CL
0.25
.010
MIN
11.9±2.2
.47±.09
ALL PINS COPLANAR
WITHIN .004"
13.40
.528
K1*
3.35
.132
10
9
8
7
6
K6*
K5*
10.16
.400
1
2
3
4
5
PIN #1
1.60
10x .063
2.29
10x .090
DIMENSIONS ARE IN INCHES [mm]
TOLERANCES:
2 PLACE .02
3 PLACE .010
ANGLES:
1
INPUT/OUTPUT CONNECTIONS
COMPONENTS SHOWN ARE FOR REFERENCE ONLY
MATERIAL:
PINS: COPPER ALLOY
THIRD ANGLE PROJECTION
FINISH: (ALL PINS)
GOLD (5u"MIN) OVER NICKEL (50u" MIN)
Figure 3. Mechanical Dimensions
Pin
1
2
3
4
5
6
7
8
9
10
Function
Vin
K Point
*
Enable
CS+
CSVout
*
Gnd
*
Temp
PWM
Gnd
5v
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OKLP-X/25-W12-C.A01.D22 Page 7 of 20
OKLP-X/25-W12-C
25A Power Block Non-Isolated DC-DC Converter
Tape and Reel Information (MSL Rating 2)
TAPE AND REEL
7770235 SHIPPING KIT
TAPE AND REEL WITH MSL2
PACKAGING (NOT SHOWN)
200 UNITS PER REEL
.025 X 45°
(PIN #1
INDICATOR)
11.9±2.2
.47±.09
330.2
13.00
PICKUP
POINT
4.00
.157
6.4
.25
FEED (UNWIND) DIRECTION
PICK-UP NOZZLE
LOCATION
4.0-6.0mm
PIN #1 TYP
(ORIENTATION)
1.50
.059 (ROUND) SPROCKET
HOLES ALONG THIS EDGE
40.4
1.59
23.8
.94
REF
4.00
.157
OBLONG HOLES
ALONG THIS EDGE
2.00
.079
REF
44.0
1.73
POCKET TAPE
DETAIL
20.00
.787
PITCH
Figure 4. Tape and Reel
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OKLP-X/25-W12-C.A01.D22 Page 8 of 20
OKLP-X/25-W12-C
25A Power Block Non-Isolated DC-DC Converter
6. Block Diagram
+5V
VIN
PWM
VOUT
Output
Filter
GND
GND
Thermal Sensor
TEMP
2.15KΩ
+CS
-CS
Figure 5. Block Diagram
For DCR sensing, there is a 2.15KΩ resistor on the power block (between CS+ and output inductor as shown) to work
with an external 0.22μf capacitor (not supplied with the power block). The external C shown as across CS+ and CS- pins
should be installed on the PCB. The R value in the RC network is the inductor DCR, used in the relation L/(DCR+PCB
trace)=RC. (PCB trace equal 0.1mΩ.)
7. Miscellaneous
Table 7.1. Environmental
Parameter
Notes
Min
Nom
Max
Units
Temperature, Operating, Long-Term
1
-5
55
°C
Temperature, Operating, Short-Term (72 hours)
2, 3
-20
70
°C
Temperature, Storage
-40
125
°C
Available airflow (along either long or short side)
200
LFM
Altitude, Operating
4
-500
10,000
Feet
Relative Humidity, Operating, Non-Condensing
10
90
%
MSL Rating 2
1. Unit’s component temperatures will not exceed vendor’s derating guidelines with up to 3 units operating side by side
spaced 0.1” apart.
2. For single unit operation, component temperatures can exceed vendor’s derating guidelines, but will not exceed component max temperature ratings.
3. With up to 3 units operating side by side spaced 0.1” apart, component temperatures will not activate OTP, and will not
compromise reliability.
4. Derate operating temperature 1°C per 1000 Feet of altitude above sea level.
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OKLP-X/25-W12-C.A01.D22 Page 9 of 20
OKLP-X/25-W12-C
25A Power Block Non-Isolated DC-DC Converter
Table 7.2. Reliability
Parameter
Calculated MTBF
Service Life
Notes
1
2
Min
-
Nom
7.683
7
Max
-
Units
MHrs
Years
1. Calculated according to Bellcore or Telcordia TR-NTW-000332 at 40C full-load.
2. Calculated at 30 °C.
7.3. Parallel Operation
2 or more units will be operated in parallel. Current sharing function will be performed by the external PWM controller.
7.4. Use of Ceramic Capacitors
Unit does not use any SMT ceramic capacitors larger than 1210.
7.5. SMT Reflow Soldering Guidelines
The surface-mount reflow solder profile shown below is
suitable for SAC305 type lead-free solders. This graph should
be used only as a guideline. Many other factors influence
the success of SMT reflow soldering. Since your production environment may differ, please thoroughly review these
guidelines with your process engineers.
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OKLP-X/25-W12-C.A01.D22 Page 10 of 20
OKLP-X/25-W12-C
25A Power Block Non-Isolated DC-DC Converter
TYPICAL PERFORMANCE DATA
Efficiency vs. Line Voltage and Load Current @ +55˚C., 200 LFM (Vout = 1.0V)
95
95
90
90
85
85
VIN = 7V
VIN = 12V
80
Efficiency (%)
Efficiency (%)
Efficiency vs. Line Voltage and Load Current @ +55˚C., 200 LFM (Vout = 1.8V)
75
70
65
VIN = 7V
VIN = 12V
80
75
70
65
60
60
55
55
50
50
0
5
10
15
20
0
25
5
10
15
20
25
Load Curre nt (Amps)
Load Curre nt (Amps)
Efficiency vs. Line Voltage and Load Current @ +55˚C., 200 LFM (Vout = 3.3V)
Maximum Current Temperature Derating at Sea Level
Vout = 1V; Vin = 7-13.2V
100
95
30
90
80
Output Current (Amps)
Efficiency (%)
25
VIN = 7V
VIN = 12V
85
75
70
65
60
Natural Convection
20
1.0 m/s (200 LFM)
15
10
5
55
0
50
0
5
10
-5
15
0
5
10
15
20
25
30
35
40
45
50
55
60
65
70
75
80
85
90
75
80
85
90
Ambient Temperature (°C)
Load Curre nt (Amps)
Maximum Current Temperature Derating at Sea Level
Vout = 3.3V; Vin = 7-13.2V
30
30
25
25
Output Current (Amps)
Output Current (Amps)
Maximum Current Temperature Derating at Sea Level
Vout = 1.8V; Vin = 7-13.2V
20
Natural Convection
15
1.0 m/s (200 LFM)
10
5
20
Natural Convection
15
1.0 m/s (200 LFM)
10
5
0
0
-5
0
5
10
15
20
25
30
35
40
45
50
55
Ambient Temperature (°C)
60
65
70
75
80
85
90
-5
0
5
10
15
20
25
30
35
40
45
50
55
60
65
70
Ambient Temperature (°C)
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OKLP-X/25-W12-C.A01.D22 Page 11 of 20
OKLP-X/25-W12-C
25A Power Block Non-Isolated DC-DC Converter
TYPICAL PERFORMANCE DATA
Efficiency vs. Load Current (Vo=1V, Vin=12Vin, 25°C, 0LFM)
Efficiency vs. Load Current (Vo=1V, Vin=12Vin, 25°C, 100LFM)
95
95
90
90
Efficiency (%)
100
Efficiency (%)
100
85
80
400KHZ
75
500KHZ
70
85
80
400KHZ
75
500KHZ
70
600KHZ
600KHZ
65
65
60
0
5
10
15
Load Curre nt (Amps)
20
60
25
0
Efficiency vs. Load Current (Vo=1V, Vin=12Vin, 25°C, 200LFM)
95
90
90
Efficiency (%)
95
Efficiency (%)
100
85
80
400KHZ
400KHZ
75
500KHZ
600KHZ
65
65
0
5
10
15
Load Curre nt (Amps)
20
60
25
0
Efficiency vs. Load Current (Vo=1.8V, Vin=12Vin, 25°C, 100LFM)
95
95
90
90
Efficiency (%)
100
85
80
400KHZ
75
500KHZ
70
5
10
Load Curre nt (Amps)
15
20
Efficiency vs. Load Current (Vo=1.8V, Vin=12Vin, 25°C, 200LFM)
100
Efficiency (%)
25
80
70
600KHZ
85
80
400KHZ
75
500KHZ
70
600KHZ
600KHZ
65
65
60
20
85
500KHZ
70
60
10
15
Load Curre nt (Amps)
Efficiency vs. Load Current (Vo=1.8V, Vin=12Vin, 25°C, 0LFM)
100
75
5
0
5
10
Load Curre nt (Amps)
15
20
60
0
5
10
Load Curre nt (Amps)
15
20
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OKLP-X/25-W12-C.A01.D22 Page 12 of 20
OKLP-X/25-W12-C
25A Power Block Non-Isolated DC-DC Converter
TYPICAL PERFORMANCE DATA
Efficiency vs. Load Current (Vo=3.3V, Vin=12Vin, 25°C, 0LFM)
Efficiency vs. Load Current (Vo=3.3V, Vin=12Vin, 25°C, 100LFM)
95
95
90
90
Efficiency (%)
100
Efficiency (%)
100
85
80
400KHZ
75
500KHZ
70
85
80
400KHZ
75
500KHZ
70
600KHZ
600KHZ
65
65
60
0
5
Load Curre nt (Amps)
10
15
60
0
5
Load Curre nt (Amps)
10
15
Efficiency vs. Load Current (Vo=3.3V, Vin=12Vin, 25°C, 200LFM)
100
95
Efficiency (%)
90
85
80
400KHZ
75
500KHZ
70
600KHZ
65
60
0
5
Load Curre nt (Amps)
10
15
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OKLP-X/25-W12-C.A01.D22 Page 13 of 20
OKLP-X/25-W12-C
25A Power Block Non-Isolated DC-DC Converter
TYPICAL PERFORMANCE DATA
Dynamic load Transient Response: @25C, natural airflow, Vin=12V; Input/Output capacitance (see table 2.4), data based on the ZMDI ZSPM1000 evaluation board.
12.5A to 25A (slew rate 1.0A/μs)
3.3Vout
1.8Vout
1.0Vout
0A to 12.5A (slew rate 1.0A/μs)
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OKLP-X/25-W12-C.A01.D22 Page 14 of 20
OKLP-X/25-W12-C
25A Power Block Non-Isolated DC-DC Converter
TECHNICAL NOTES
Overview
* The “Power Stage” of a Non-isolated PoL:
The Murata Power Solutions OKLP-X/25 Power Block is a non-isolated,
switching power converter. It is capable of providing a 49.5W, regulated
output of 0.8-3.6V DC, with load currents up to 25A at 1V output voltage.
The Power Block has an input range of 7-13.2V DC. The Power Block is a
synchronous buck converter and has been implemented using a synchronous buck gate driver IC with co-packed control and synchronous MOSFETs
and Schottky diode. The output filter consists of 375nH inductance and
20μf capacitance. A regulated +5V supply is required for the gate driver IC
within the OKLP-X/25 Power Block.
• Does “the heavy lifting”—FETs, output inductor, gate drive circuitry
• Synchronous buck converter topology (evaluated at 400-600 KHz)
• Requires external parts for a complete POL solution (PWM, etc.)
• Can accommodate analog or digital controllers
In order to implement a complete POL solution, external circuitry must be
added in the form of a PWM controller, gate drive voltage, as well as input
and output capacitors. The Power Blocks are designed to accommodate
either analog or digital PWM controllers, affording customers a wide range
of performance features and functionality, according to their needs. For
dense PCB circuit implementations, the PWM controller can be mounted on
the underside the PCB, resulting in a very dense PCB layout.
Compelling advantages
Murata Power Solutions’ Power Blocks offer compelling advantages to
users seeking flexibility and ease-of-use, including the following:
• High efficiency, high power density (352 W/in³) in a compact footprint
(0.5in. x 0.67in.)
• Accurate DCR, ±5 % tolerance
• Accurate temperature sense via precision temp reference
• Ease of use; Simpler pcb layout; Noise/EMI contained within Power Block
• PMBus option (depending on PWM IC used)
• Current sharing options (depending on PWM IC used)
• Cost between down-solutions and integrated PoL modules
• PCB area/BOM reduction vs. fully discrete solutions
• Compatible with multiple PWM IC suppliers (e.g., IR, Linear Tech,
Powervation, TI, ZMDI)
The ease-of-use aspect of the Power Blocks enables users to reduce the
design cycle to improve time-to-market. The Power Blocks are a high
reliability solution with a calculated MTBF of 3 MH (min.) and Service Life
of 6 years. Controlled variances and tight control over the inductor DCR,
for example, ±5 % tolerance vs. ±10%, typically, enables more accurate
current sense. In all these variables and features, “Knowing what you get”
is important to realizing a successful and reliable design.
The OKLP-X/25 Power Block can be used with any analog or digital PWM
controller IC. By simplifying the design task and providing for a high-density
layout, including a reduced BOM (e.g., output capacitance), depending on
transient performance vs. output capacitance, the OKLP-X/25 Power Block
enables a robust design, reduced total cost of ownership and higher energy
efficiency across all output load conditions. Basic information, including
efficiency, thermal derating, etc, for the Power Block alone, not including
controller losses, has been characterized.
25A Power Block:
+5V
VIN
PWM
Output
Filter
VOUT
GND
GND
Thermal
Sensor
TEMP
2.15KΩ
+CS
C*
-CS
Figure 6. 25A Power Block
* 0.22μf external capacitor must be used for accurate current sense
INPUT/OUTPUT CONNECTIONS
Contact Murata Power Solutions for further information.
Each pin of the Power Block and related functional information for the
controller (PWM) are described.
Pin # Name
Function
1
Vin
Input voltage for the MOSFET
2
Enable
Turn Off Module (Enable < 0.8V), Turn On Module (Enable > 2.0V)
Discussion
3
+Cs
Positive DCR sense
The OKLP-X/25 Power Block is not a completely integrated point-of-load
(PoL) solution. Power Blocks comprise the Power Stage* of a non-isolated
converter, integrating the power FETs, output inductor, current sense, temperature sense, and gate drive circuitry of a synchronous buck converter.
This is the part of a PoL that performs the “heavy lifting” in the conversion
process.
4
-Cs
Negative DCR sense
5
Vo
Output voltage
6,9
GND
Ground for both input and output
7
Temperature From temperature sense device on the power block for temperature sensing
8
PWM
3.3V compliant PWM signal to the gate driver
10
+5V
Bias voltage for gate driver
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OKLP-X/25-W12-C.A01.D22 Page 15 of 20
OKLP-X/25-W12-C
25A Power Block Non-Isolated DC-DC Converter
PCB Design Guidelines
Guidelines for proper conductor (surface and buried traces, vias, etc.)
copper plating, pad sizes, trace widths, spacing, etc., can be found in IPC2221A, “Generic Standard on Printed Circuit Board Design.” Please consult
this or similar standards when designing PCB layouts for the high-current
output from the OLKP Power Blocks or any high-current power supply,
taking into consideration, maximum currents, temperature rise and convection and/or conduction cooling of the end-user application.
Powerblock Power Pins
Placing larger vias close to the power pins will improve thermal performance. Connecting each group of power and ground vias together on all
inner layers where possible with a copper area will improve heat dissipation.
Via Construction and Sizing
• Via diameter and copper plating thickness affect current carrying capacity.
• Increasing outer layer copper thickness will allow thicker via plating
thickness. MPS uses 3 Oz outer layers for 1 Oz via plating.
• Increased via plating thickness will prevent barrel cracking when board
temperature changes to extremes, including reflow, resulting in improved
reliability.
The following chart shows that larger diameter vias or thicker copper
plating will improve the current carrying capacity.
ΔT
k
A = (Diameter * PI * Plating)
I = (k * (T ^ 0.44)) * (A ^ 0.725)
Via wall plating thickness (oz)
1.00
0.50
0.25
10
1.54 A
0.93 A
0.56 A
15
2.06 A
1.25 A
0.75 A
20
2.54 A
1.54 A
0.93 A
25
2.99 A
1.81 A
1.09 A
30
3.41 A
2.06 A
1.25 A
35
3.81 A
2.31 A
1.40 A
40
4.20 A
2.54 A
1.54 A
50
4.94 A
2.99 A
1.81 A
60
5.63 A
3.41 A
2.06 A
ΔT = Max temperature rise above ambient (25°C)
k = Derating constant (.024)
A = Area in square mils
I = Current in Amps
Via Diameter (mils)
For optimum performance, heavy copper (2 Oz or greater) or use of multiple
copper layers should be used for all power connections.
For higher currents, improved thermal performance and increased reliability of the power converter, the following suggestions are recommended:
• Multiple vias capable of carrying the current required should be used.
Two adequately sized vias per amp. is not uncommon.
• Vias should be placed as close to power pins as permissible.
• Use of thermal reliefs for vias and power pads should be avoided.
• Unused inner layer via pads should not be removed. This annular ring
reduces the resistance and increases the copper area of the via. Connecting these vias together on as many inner layers as possible using
copper fills will also improve via performance.
• It is important to note that hole plating thickness and circumference
must be used to determine the cross section when calculating the current carrying capacity of vias. Hole plating thickness will be much thinner
than the copper weight of the printed circuit board.
IPC-2221A Formula for Calculating Trace Width and Vias
I = kΔT0.44A0.725
WHERE:
I = current in amperes
A = cross section in sq mils
ΔT = temperature rise in °C
k is a derating constant such that:
k = .048 for outer layers
k = .024 for inner layers
Input/Output Capacitor Selection
The required amount of input and output capacitance will be determined
on an application by application basis. However, there are guidelines
common to every design which can be identified and following is a very
brief overview.
For instance, ceramic capacitors with very low ESR (and ESL, if published) should be selected to reduce input and output ripple voltages. These
should be placed as close to the power supply input as practical. External
input bypass “bulk” capacitance should then be determined in order to
stabilize the input voltage during large load transients and supply extra current to the load during a step load change. The maximum output capacitive
loading specified in the datasheet should be observed. Consideration must
also be given to ripple voltage and currents and the impact on capacitor
lifetime and system reliability. Note that both input and output capacitors
should be placed close to the load.
Also, as some systems are difficult to fully characterize analytically,
some empirical testing may be necessary to assure successful operation.
Input Capacitor Selection
Reduce Input Ripple Voltage: The first step is to reduce ripple voltage
amplitude at the input of the converter. For this purpose, ceramic capacitors
with very low ESR should be selected; large, bulk capacitors do not reduce
ripple voltage, as the ESR of aluminum electrolytics and most tantalums are
too high to allow for effective ripple reduction. Therefore, to reduce the rms
current in the bulk capacitors the ripple voltage amplitude must be reduced
using ceramic capacitors. From the literature, “as a general rule of thumb,
keeping the peak to peak ripple amplitude below 75 mV keeps the rms
currents in the bulk capacitors within acceptable limits.
Load current, duty cycle, and switching frequency are several factors
which determine the magnitude of the input ripple voltage. The input ripple
voltage amplitude is directly proportional to the output load current. The
maximum input ripple amplitude occurs at maximum output load. Also, the
amplitude of the voltage ripple varies with the duty cycle of the converter.
For a single phase buck regulator, the duty cycle is approximately the ratio
of output to input dc voltage. A single phase buck regulator reaches its
maximum ripple at 50% duty cycle.” Further detail can be found in the
literature.
The following equation can be used to determine the amount of ceramic
capacitance required to reduce the ripple voltage amplitude to acceptable
levels:
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OKLP-X/25-W12-C
25A Power Block Non-Isolated DC-DC Converter
CMIN = (Iout x DC X (1-DC) x 1000)/(FSW x Vpmax), DC=Vout/(Vin x );
=Efficiency
Where
FSW is the switching frequency in KHz
Iout is the steady state output load current
CMIN is the minimum required ceramic input capacitance in μF ➀
VP(MAX) is the maximum allowed peak-peak ripple voltage ➁
Example Ceramic Calculation
Given:
• VIN = 12 V
• VOUT = 3.3 V
• IOUT = 10 A
  =
90%
• FSW =
333 kHz
• DC =
0.3
The minimum ceramic capacitance required to reduce the ripple voltage to
75 mVpp is calculated to be:
CMIN=(10A x 0.3 x (1-0.3) x 1000)/333 x 75mV = 84μF
➀ The actual capacitance of a ceramic is less than the stated nominal value at a given DC voltage. Make sure
the actual value is equal to or greater than the calculated value.
➁ 75 mVpp is recommended Vpmax. This will yield approximately 22 mVrms of ripple voltage.
Transients and Bulk Capacitors
Bulk capacitors control the voltage deviation at the input when the converter is responding to an output load transient. The higher the capacitance,
the lower the deviation. Therefore, the size of the input bulk capacitor is
determined by the size of the output current transient and the allowable
input voltage deviation. The amplitude of the input voltage deviation during
a transient is directly proportional to the load current change. If the magnitude of the transient load current is doubled, the input voltage disturbance
is doubled also.
Lower input voltage means higher input currents. The input current
scales directly by duty cycle. At lower input voltages the input transient
currents will also be higher. To comply with output voltage deviation limits,
more input capacitance is required.
Consider a 2.5V output regulator with a 10A transient load. With a 12V
input, the ideal duty cycle is 2.5/12 = 0.208. The 10 A load transient on
the output transforms to a 2.08A transient on the input. With a 3.3 V input
regulator, the duty cycle is now 2.5/3.3=0.758. The 10 A load transient is
now a 7.58A input transient. This will cause a larger voltage deviation on
the lower voltage supply where the voltage limits are probably tighter.
During a transient, input inductance slows the current slew rate seen by
the host supply. The use of a filter inductor places more demands on the
input bulk capacitors since more of the initial current demand must come
from the input capacitors rather than the host supply. The input voltage at
the regulator input now sees a much higher voltage deviation. In the end,
both the input and output capacitors have to be recharged, causing higher
peak currents to be demanded from the host supply.
Bulk input capacitance calculation example
When designing a system consisting of a single POL module, the first step
is to calculate the magnitude of the input transient current. This is done
by calculating the reflected input transient for each POL module’s output
transient. When calculating, you must determine the worst case transient
combination of all modules and proceed accordingly.
The magnitude of the input current transient is calculated from the following equation:
Delta IIN=VOUT/(VIN x ) x delta IOUT, where
  is efficiency
• ΔIOUT is the output transient current
• ΔIIN is the input transient current
• VOUT is the nominal output voltage
• VIN is the nominal input voltage
The efficiency value  is obtained from the regulator data sheet. Use a
value from the efficiency curve for the particular output voltage and the
highest expected output current.
Next, determine the maximum allowable voltage deviation on the
bulk capacitors. This is the maximum allowable dip during the peak
transient step that was calculated in step one. The smaller the voltage
deviation, the higher the required amount of bulk capacitance.
The following equation calculates the minimum required bulk capacitance.
C = (1.21 x ΔI2IN x L)/ΔV2
Where:
ΔIIN is the change in input current in response to the output step load
transient
L is stray inductance in the host supply path and/or any series inductor ➂
ΔV is the allowable input voltage dip following the output step load transient
Note that this equation is an approximation. The value it produces should
be considered to be an absolute minimum amount. The exact value will
have to be determined through experimentation depending on how well
regulated your host supply is.
Example
• Assume filter L = 560 nH
• Assume allowable ΔV is 100 mV
• Assume input transient current (ΔIIN) was calculated to be 2.774A
C = (1.21 x ΔI2IN x L)/ΔV2 = (1.21 x (2.774)2 x 560 x 10-9)/(-.100)2 = 521 μF
According to the calculation, a minimum 521μF of bulk capacitance is
needed. Use the nearest standard value of 560 μF.
➂ The user needs to decide if a series filter inductor is going to be used. If using an inductor, pick a value no
greater than 560 nH. If not using one, use a value of 50 nH in the calculation to account for stray inductance
in the host supply path and its finite bandwidth.
Detailed discussion of the use of an input inductor is beyond the scope of these guidelines, however; if
reflected ripple is a concern, a small (560 nH or less) input inductor can be used. At lower currents, this input
inductor can take the form of a power ferrite bead. This is an effective way to confine ripple currents to the
local input bypass caps. An input inductor can reduce the reflected ripple current by an order of magnitude.
During transient conditions, the use of an input inductor puts larger demands on input bulk capacitors. Take
care when using input inductors as they will affect input capacitor selection.
Output Capacitor Selection
There are numerous factors to consider when adding external capacitors to
switched-mode power supplies (SMPS), including noise, startup, ESR, stability, pre-bias applications, Sense inputs, On/Off (remote enable) controls
and other topics.
Most DC-DC applications require external bypass “bulk” capacitors as
part of the output load. These capacitors supply extra current during a step
load change. Lower DC voltages used in newer logic devices mean that the
voltage margin difference between logic ZERO and logic ONE is reduced to
hundreds or even tens of millivolts. Thus, since even modest power supply
noise can cause data errors by exceeding this threshold, these bypass caps
are necessary to reduce this DC-DC noise.
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OKLP-X/25-W12-C.A01.D22 Page 17 of 20
OKLP-X/25-W12-C
25A Power Block Non-Isolated DC-DC Converter
In addition to the possibility of failed or delayed startup, increasing
external capacitance can cause sluggish transient response, possible
ringing and instability. The maximum output capacitive load specification is
really an indication of acceptable and stable startup performance but with
moderated transient response.
Designing for Transient Performance
When designing for a load transient, the output bulk capacitors and high
frequency bypass capacitors determine the response performance and
voltage deviation of the regulator. The most important parameters are the
magnitude of the load transient (ΔI) and the distributed bus impedance to
the load. The selection of the output capacitors is determined by the
allowable peak voltage deviation (ΔV). This limit should reflect the actual
requirements, and should not be specified lower than needed.
Data sheet tables give the maximum allowable output capacitance
for each module. If external capacitance is required for stable operation,
the minimum value will be listed in the datasheet. Recommended capacitance is also listed in the datasheet for improved transient performance.
The recommended capacitance value will meet a typical ΔV spec at a 50%
transient load step.
Detailed analysis has been performed to allow capacitor limits to be
accurately defined. By following the capacitor recommendations in the data
sheet and selecting capacitors based on your actual operating conditions, a
reliable, low-cost power system can be designed.
Additional explanation can be found at the Murata Power Solutions web
page at www.murata-ps.com/data/apnotes/dcan-58.pdf, Application Note
D-CAN-58, Output Capacitive Load Considerations.
The distribution bus impedance seen by the load is the parameter that
determines the peak voltage deviation during a fast transient. The system
requires a low impedance bus over all frequencies with adequate bypass
capacitors to achieve fast slew rates. If the impedance of the network
that supplies the load remains below a maximum impedance, the voltage
deviation due to the transient will remain within allowable voltage deviation
requirements. It is simply Ohm’s Law: ΔV= ΔI x Z. Keep the magnitude of
Z below the maximum limit, and the transient voltage deviation will stay
within its limits.
Power Block Performance
Divide ΔV by the ΔI to determine the maximum allowable impedance,
Zmax. This is the impedance limit which must be maintained by the output
capacitor network for frequencies above which the regulator is effective. To
maintain low impedance from the regulator to the load, high frequency, low
value ceramic capacitors must be placed very close to the load to minimize
the effects of trace inductance while larger value ceramic capacitors can
be placed closer to the regulator.
Pin #2 (Enable):
This provides the host or system controller to the option turn-on/off the
module. Alternatively, this input can also be tied to Vin or the +5V supply to
the gate driver, Pin 10 (up to 15V).
Transient Design Example
Calculating the maximum allowable output impedance, given the following
requirements:
• VO = 2.5 V
• Output current step from 0.8 A to 12.5 A (ΔI = 11.7 A)
• Maximum allowable voltage deviation (ΔV) is 100 mV
• 20 A/μsec slew rate.
ΔV/ΔI = Maximum impedance
ΔV/ΔI = 100 mV/11.7 A = 8.55 mΩ
Selecting four 330 μF capacitors with an ESR of 25 mΩ would provide
an effective ESR of 6.25 mΩ and 1320 μF of total capacitance. Using these
capacitors, the actual amplitude of the transient deviation would be about
±73 mV (11.7 A × 6.25 mΩ). By maintaining the low impedance over the
complete frequency range, any high slew rate transient will be achieved.
Absolute Maximum Capacitor Limits
All regulators have an absolute maximum capacitance limit. MPS DC-DC
converter modules incorporate output short-circuit protection. During
startup, the regulator must charge the output capacitance in order to raise
the output voltage to its set-point and this current flow is in addition to any
load current that may be drawn by the application circuit. If there is too
much output capacitance, the current demanded from the regulator trips its
over-current protection circuit. Furthermore, each over-current trip will be
followed by further attempts by the regulator to restart. This can result in
the regulator entering a perpetual cycle of over-current shutdown.
The OKLP-X/25 Power Block modules have been tested using controller
(PWM) IC’s under various transient load conditions. Contact Murata Power
Solutions for further details.
Power Block Pin Functional Descriptions
Pin #1 (Vin):
Input supply pin, with a range of 7 – 13.2Vin (see Table 1.1).
Pin #3 (+Cs), Positive DCR (current) sense and Pin #4 (-Cs), Negative DCR
(current) sense: For additional information, please reference the relevant
applications notes (www.zmdi.com/zspm1000) for the specific controller
(PWM) IC to be used. Contact Murata Power Solutions for further information. A brief description of using current sense with the Power Block
follows.
Current Sensing
Many controller (PWM) IC’s implement average current sensing to provide
accurate current information over the switching period. A generated
schematic of the required current sensing circuitry is shown in figure 7
for the widely used DCR current-sensing method, which uses the parasitic
resistance of the inductor to acquire the current information. The principle
is based on a matched time-constant (i.e., RC=L/R (DCR) between the
inductor and the low-pass filter built from the 2.15KΩ resistor and an external capacitor (not supplied with the OKLP-X/25 Power Block) across +Cs
and –Cs (220μf), where the inductor L and DCR (+5%) values are used.
Pin #5 (Vout): Output voltage supplied to the load. Note: There is minimal
input/output capacitance incorporated in the Power Block. Approximately
600μf is “typical” at 25A output current level, depending on the application.
Ref. to paragraph 2.4. Capacitor (OKLP-X25 datasheet). The user needs to
determine the appropriate amount of external capacitance for energy storage, ripple voltage requirements, etc.
Pin #6 (Gnd)
Pin #7 (Temperature): Temperature Measurement
The OKLP-X/25 includes a Thermal Sensor in the module for temperature
sensing of the inductor. This element is used by the controller for temperature compensation, measuring the inductor temperature. This information
www.murata-ps.com/support
OKLP-X/25-W12-C.A01.D22 Page 18 of 20
OKLP-X/25-W12-C
25A Power Block Non-Isolated DC-DC Converter
can be used to adapt the gain of the current sense path to compensate for
the increase in actual DCR.
+5V
Pin #8 (PWM):
This is a 3.3V logic level tri-state PWM input and 7V tolerant. “High” turns
the control MOSFET on, and “Low” turns the synchronous MOSFET on.
“Tri-state” turns both MOSFETs off. In diode emulation mode, “Tri-state”
activates internal diode emulation control.
VIN
PWM
Pin #10 (+5V): Supply to the gate driver IC (4.5V to 7V). This can be supplied via another +5V power rail, or a linear regulator or an LDO (e.g.,
LM317 or LP2992).
C
GND
GND
TEMP
Power Block Design Process
The design process begins with selecting a PWM controller for use with
the OKLP-X/25-W12 Power Block. As each controller (PWM) IC differs in
configuration and performance, the user needs to ensure that adequate
technical support is available from the supplier of choice (e.g., datasheets,
application notes, and configuration tools). For details concerning usage
with a Power Block (i.e., the “power stage”) to implement a point-of-load
solution, including regulation, transient performance, protection, and
sequencing, please consult the supplier’s web page. Contact Murata-PS
Technical Support (www.murata-ps.com/support), as well as the websites
below, for further information.
VOUT
L
+Sense
- Sense
+CS
Thermal
Sensor
2.15KΩ
0.22μF
-CS
Figure 7. Inductor Current Sensing Using the DCR Method
www.zmdi.com/Murata_Power_Block
www.powervation.com/products/single-phase-controllers
www.murata-ps.com/support
OKLP-X/25-W12-C.A01.D22 Page 19 of 20
OKLP-X/25-W12-C
25A Power Block Non-Isolated DC-DC Converter
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Murata Power Solutions, Inc.
11 Cabot Boulevard, Mansfield, MA 02048-1151 U.S.A.
ISO 9001 and 14001 REGISTERED
This product is subject to the following operating requirements
and the Life and Safety Critical Application Sales Policy:
Refer to: http://www.murata-ps.com/requirements/
Murata Power Solutions, Inc. makes no representation that the use of its products in the circuits described herein, or the use of other
technical information contained herein, will not infringe upon existing or future patent rights. The descriptions contained herein do not imply
the granting of licenses to make, use, or sell equipment constructed in accordance therewith. Specifications are subject to change without
notice.
© 2013 Murata Power Solutions, Inc.
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