® SP8530 S2ADC™ - Simultaneous Sampling Analog to Digital Converter ■ Patented Simultaneous Sampling of 2 channels (Patent # 5,638,072) ■ 12 Bit Resolution ■ Single +5Volt Supply ■ Internal Reference, 1.25V ■ Unipolar 0 to +2.5 Volt Input Range ■ Fast, 7.75 µs Conversion Time Both Channels ■ Fast Power Shutdown/Turn-On Mode ■ 3-Wire Synchronous Serial High Speed Interface ■ True Differential Measurements ■ 2µA Shutdown Mode (10µW) ■ Low Power CMOS 60mW typical DESCRIPTION The SP8530 is a two channel simultaneous sampling, 12-Bit serial out data acquisition system. The device contains a high speed 12-Bit analog to digital converter, internal reference, and sample/hold circuitry for both channels. The 8530 is available in 16-pin PDIP and SOIC packages, specified over Commercial and Industrial temperature ranges. CS CONTROL LOGIC STATUS COUNTER SCLK SAR VIN A VIN B OFFSET ADJUST DAC DOUT LATCHED COMPARATOR RTRIM BUFFER PD REF. GAIN ADJUST REF OUT ™-S2ADC is a TRADEMARK OF SIPEX CORPORATION Patent Pending SP8530DS/01 SP8530 S2ADC - Simultaneous Sampling Analog to Digital Converter TM 1 © Copyright 2000 Sipex Corporation ABSOLUTE MAXIMUM RATINGS (TA=+25˚C unless otherwise noted) .............................................. VDD to DGND ............................................................. -0.3V to +7V VDA to AGND .............................................................. -0.3V to +7V Vin to AGND .................................................... -0.3V to VDA +0.3V Digital Input to VSS ........................................... -0.3V to VDD+0.3V Digital Output to VSS ........................................ -0.3V to VDD+0.3V Operating Temp. Range Commercial (J,K Version) ............................... 0˚C to 70˚C Industrial (A,B Version) .............................. -40˚C to +85˚C Storage Temperature ............................................... -65˚C to 150˚C Lead Temperature(Solder 10sec) ........................................ +300˚C Power Dissipation to +70˚C ................................................ 500mW Derate Above 70˚C ......................................................... 10mW/ ˚C SPECIFICATIONS Unless otherwise noted the following specifications apply for VDD = 5V with limits applicable for TA = 25oC. PARAMETER DC Accuracy Resolution Integral Linearity J, A K ,B MIN. TYP. MAX. 12 UNIT CONDITIONS Bits +0.6 +0.4 +1.0 +0.75 LSB LSB Differential Linearity Error J, A K ,B +0.5 +0.5 +1.0 +1.0 LSB LSB Gain Error J, A K,B +0.2 +0.1 +1.0 +0.5 %FSR %FSR Externally Trimmable to Zero Externally Trimmable to Zero Offset Error J, A K,B +4 +3 +7 +5 LSB LSB Externally Trimmable to Zero Externally Trimmable to Zero Gain Match J, A K,B +2 +2 LSB LSB Offset Match J, A K,B +1.0 +0.5 LSB LSB 0 to 2.5 Volts Analog Input Conversion Speed Sample Time Conversion Time Complete Cycle Simultaneous Convert Rate: Clock Speed Data Rate: SP8530DS/01 400 7.75 8.25 No Missing Codes No Missing Codes Externally Trimmable to Zero Externally Trimmable to Zero ns µs 121 4 242 KHz MHz KHz SP8530 S2ADC - Simultaneous Sampling Analog to Digital Converter TM 2 Simultaneous Pair Total Data Conversion Rate © Copyright 2000 Sipex Corporation SPECIFICATIONS (continued) Unless otherwise noted the following specifications apply for VDD = 5V with limits applicable for TA = 25oC. PARAMETER Reference Output Ref. Out Temp. Coef. J, A K,B MIN. TYP. 1.25 15 10 Ref.Out Error Output Current +2 1 Digital Inputs Input Low Voltage , VIL Input High Voltage , VIH MAX. UNIT CONDITIONS Volt.Nom. ppm/˚C ppm/˚C +25 mV mA 0.8 Volt Max. VDD= 5V +5% Volt Min. VDD= 5V +5% 2.0 Input Current IIN +1 µA Input Capacitance 3 pF Max. Digital Outputs Data Format 12-Bit Serial See Timing diagram Data Coding Binary See Timing Diagram VOH 4.0 VOL 0.4 Volt. Min. VDD=5V+5%, IOH=-0.4mA Volt Max. VDD=5V+5%, IOL=-1.6mA AC Accuracy fin=47KHz,VDD=5.0V @ 25˚C, SCLK=4MHz Spurious Free Dynamic Range (SFDR) 83 dB Total Harmonic Distortion (THD) -80 dB Signal to Noise & Distortion (SINAD) 71 dB Signal to Noise (SNR) 72 dB Acquisition Time to 0.01% 200 ns -3db Small Signal BW 13 MHz Aperture Delay 35 ns Aperture Jitter 150 ps RMS Aperture Delay Matching 400 ps Sampling Dynamics Power Supplies VDD SP8530DS/01 4.75 5.25 Volts SP8530 S2ADC - Simultaneous Sampling Analog to Digital Converter TM 3 For a +FS step change at input © Copyright 2000 Sipex Corporation SPECIFICATIONS (continued) Unless otherwise noted the following specifications apply for VDD = 5V with limits applicable for TA = 25oC. PARAMETER MIN. TYP. MAX. UNIT CONDITIONS Supply Current Operating Mode 11.5 17 mA SD=0, VDD=+5.0V Shutdown Mode 0.01 2 µA SD=1 Power Dissipation Operating Mode Shutdown Mode 60 .05 85 10 mW µW SD=0 SD=1 20 µS Via Shutdown Control to 1 LSB settling error. Power Supplies Cont. Power Turn On Temperature Range Commercial 0 to +70 ˚C Industrial -40 to +85 ˚C Storage -65 to +150 ˚C SP8530DS/01 SP8530 S2ADC - Simultaneous Sampling Analog to Digital Converter TM 4 © Copyright 2000 Sipex Corporation time, thus preserving the relevant temporal information of the applied signals, precisely. This unique feature permits the SP8530 to ideally fit applications where the information content is carried on dual carriers, such as in-phase and quadrature phase systems. Further, S2ADC™ architecture permits the sampling of such signals without the necessity of demodulating or further conditioning of the carrier prior to conversion, potentially saving significant amounts of other support electronics. It is also suited to measure instantaneous transfer functions between input signals and their corresponding output signal. PIN ASSIGNMENTS Pin 1-N.C.-No Connection Pin 2-VIN B-Analog Input B Pin 3-VIN A- Analog Input A Pin 4-AGND-Analog Ground Pin 5-VSS-Digital Ground Pin 6-SCLK-Serial Clock Input Pin 7-DOUT Digital Data Output Pin 8-STATUS- High During Conversion Pin 9-CS-Chip Select Bar Input High Deselects chip Low Selects chip Pin 10-SD-Shutdown Input, logic low power up, logic high = powerdown Pin 11-VDD Digital +5V supply Pin 12-VDA Analog +5V supply Pin 13-OffADJ-A External Offset Adjust A Pin 14-OffADJ-B External Offset Adjust B Pin 15-REFOUT-Voltage Reference Output Pin 16-GAINADJ-External Gain Adjustment N.C. 1 16 GAIN ADJUST VIN B 2 15 REF OUT VIN A 3 14 OFFSET ADJ. B AGND 4 13 OFFSET ADJ. A VSS 5 12 VDA SCLK 6 11 VDD DOUT 7 10 PD STATUS 8 9 CS SP8530 Such measurements are commonly made in test equipment and PIN electronics as well as in many other systems where instantaneous cause and effect relationships are monitored. The SP8530 permits the user to convert each channel and digitally subtract the result in external logic to produce a precise digital differential result. The SP8530 is fabricated in Sipex' Bipolar Enhanced CMOS Process that permits state-ofthe-art design using bipolar devices in the analog/linear section and extremely low power CMOS in digital/logic section. CIRCUIT OPERATION The operating circuit in Figure 1 shows a simple circuit required to operate the SP8530. The conversion is controlled by the user supplied signal Chip Select Bar (CS) which selects and deselects the device, and a system clock (SCLK). A high level applied to CS asynchronously clears the internal logic, puts the sample & hold (CDAC) into sample mode and places the DOUT (Data Output) pin in a high impedance state. FEATURES The SP8530 is a two channel simultaneous sampling, 12-Bit serial out data acquisition system. The device contains a high speed 12-bit analog to digital converter, internal reference, and sample and hold circuitry for both channels. The patented, simultaneous sampling feature of this monolithic integrated circuit, permits the user to measure and convert the analog information on each of two channels at the same SP8530DS/01 Conversion is initiated by falling edge on CS in slave mode at which point the selected input voltages are held and a conversion is started. A delay of 90ns is required between the falling edge of CS and the first rising of SCLK. SP8530 S2ADC - Simultaneous Sampling Analog to Digital Converter TM 5 © Copyright 2000 Sipex Corporation 10kOhms 0.01µF* 1 N.C. GAIN ADJUST 16 VB 2 VIN B REF OUT 15 VA 3 VIN A OFFSET ADJ. B 14 4 AGND OFFSET ADJ. A 13 5 VSS 6 SP8530 VDA 12 SCLK VDD 11 7 DOUT SHUTDOWN 10 8 STATUS CS 9 5kOhms 2kOhms 5kOhms +5V 2kOhms 0.1µF 6.8µF 0.1µF CLOCK IN DATA OUT STATUS OUT CHIP SELECT SHUTDOWN * Optional filter capacitor is helpful in a noisy pc board application. Figure 1. Operating Circuit The device responds to the shut down signal asynchronously so that a conversion in progress will be interrupted and the resulting data will be erroneous. A 20 µSec delay is required between the falling edge of power down and initiation of a conversion. Layout Considerations Because of the high resolution and linearity of the SP8530 system design considerations such as ground path impedance and contact resistance become very important. Data Format 32 bits of data are sent for each conversion. The first 16 bits are the conversion A result, which is shipped with 4 leading "0"s, and then 12 bits of data, MSB first. The second 16 bits are the conversion B result, which are also shipped with 4 leading "0"s, and then 12 bits of data, MSB first. Data changes on the falling edge of SCLK and is stable on the rising edge of SCLK. To avoid introducing distortion when driving the analog inputs of these devices, the source resistance must be very low, or constant with signal level. Note that in the operating circuit there is no connection made between VDA (Pin 12) and the system power supply. This is because the analog supply pin (VDA) is connected internally to the digital supply pin (VDD) through a ten ohm resistor. Continuous stand alone operation is obtained by holding CS low. In this mode an oscillator is connected directly to SCLK pin. The SCLK signal along with the STATUS output Signal are used to synchronize the host system with the converter's data. In this mode there is a single dead SCLK cycle between the 32nd clock of one conversion and the first clock of the following conversion for the SP8530. A clock frequency of 4 MHz the SP8530 provides a throughput rate of 121KHz. This connection when combined with parallel combination of 6.8µF tantalum and 0.1µF ceramic capacitor between VDA and analog ground, will provide some immunity to noise which resides on the system supply. To maintain maximum system accuracy, the supply connected to the VDD pin should be well isolated from digital supplies and wide load variations. To limit effects of digital switching elsewhere in a system, it often makes sense to run a separate +5V supply conductor from the supply regulator to any analog components requiring +5V including the SP8530. Noise on the power In slave mode operation, CS is brought high on each conversion so that all conversions are initiated by falling edge on CS. SP8530DS/01 SP8530 S2ADC - Simultaneous Sampling Analog to Digital Converter TM 6 © Copyright 2000 Sipex Corporation Minimizing “Glitches” Layout Considerations (cont.) supply lines can degrade the converters performance, especially corrupting are noise and spikes from a switching power supply. Coupling of external transients into an analog to digital converter can cause errors which are difficult to debug. In addition to the above discussions on layout considerations, bypassing and grounding, there are several other useful steps that can be taken to get the best analog performance from a system using the SP8530 converters. These potential system problem sources are particularly important to consider when developing a new system, and looking for causes of errors in breadboards. The ground pins (AGND and VSS) on the SP8530 are separated internally and should be connected to each other under the converter. Applying the technique of using separate analog and digital ground planes is usually the best way to preserve dynamic performance and reduce noise coupling into sensitive converter circuits. Where any compromise must be made the common return of the analog input signal should be referenced to the AGND pin of the converter. This prevents any voltage drops that might occur in the power supply's common return from appearing in series with the input signal. First, care should be taken to avoid transients during critical times in the sampling and conversion process. Since the SP8530 has a internal sample/hold function, the signal that puts the device into hold state (CS going low) is critical, as it would be on any sample/hold amplifier. The CS falling edge should have a 5 to 10 ns transition time, low jitter, and have minimal ringing, especially during the first 20ns after it falls. Coupling between analog and digital lines should be minimized by careful layout. For instance, if analog and digital lines must cross they should do so at right angles. Parallel analog and digital lines should be separated from each other by a trace connected to common. If external gain and offset potentiometers are used, the potentiometers and related resistors should be located as close to the SP8530 as possible. SP8530DS/01 SP8530 S2ADC - Simultaneous Sampling Analog to Digital Converter TM 7 © Copyright 2000 Sipex Corporation TIMING CHARACTERISTICS (Typical @ 25°C with VDD = +5V, unless otherwise noted) PARAMETER MIN. Thoughput Time (tTP=tA+tC) 8.25 TYP. MAX .UNIT Acquisition Time (tA) (2 SCLK Periods) 400 Conversion Time (tC) (31 SCLK Periods) 7.75 SCLK Low Pulse Width (tSKL) 110 125 ns SCLK High Pulse Width (tSKH) 110 125 ns SCLK Period (tSKT) 250 500 ns µs ns Buss Access Time (tCBA) 51 ns Buss Relinquish Time (tBR) 45 ns Setup Time -SCLK Falling to CSN Falling (tCSSU) 0 ns CSN Low Before SCLK Rises (tCS) 90 ns SCLK Falling to Data Valid (tSD) 50 ns CSN Falling to status Rising (tDCS) 69 ns SCLK 33 Falling to Status Rising Free Run (tDSS) 70 ns SCLK32 Falling to Status Falling ( tDSE) 45 ns Delay SD Low to initiate Conversion (tpu) 5 µs Aperture Delay Slave-Mode (tAPC) 30 ns Aperture Delay Free-Running Mode (tAPS) 35 ns SP8530DS/01 SP8530 S2ADC - Simultaneous Sampling Analog to Digital Converter TM 8 COND. µs © Copyright 2000 Sipex Corporation TIMING DIAGRAMS 31 tskt tcssu 32 2 1 3 4 x SCLK 5 31 32 x tskl tcs tskh tpu CS tdcs STATUS DATA tcba Hi-Z B0 tbr tdse tsd A11 "0" B1 Hi-Z B0 tapc ACQUIRE CONVERT ta ACQUIRE tc SD Slave Mode 31 32 1 33 2 3 4 5 31 32 33 1 SCLK "0" CS tdss tdse STATUS tsd DATA "0" B0 A11 B1 B0 "0" tAPS CONVERT AQUIRE ta ACQUIRE tc Free Running Mode SP8530DS/01 SP8530 S2ADC - Simultaneous Sampling Analog to Digital Converter TM 9 © Copyright 2000 Sipex Corporation PACKAGE: PLASTIC DUAL–IN–LINE (NARROW) E1 E D1 = 0.005" min. (0.127 min.) A1 = 0.015" min. (0.381min.) D A = 0.210" max. (5.334 max). C A2 L B1 B e = 0.100 BSC (2.540 BSC) Ø eA = 0.300 BSC (7.620 BSC) ALTERNATE END PINS (BOTH ENDS) DIMENSIONS (Inches) Minimum/Maximum (mm) 8–PIN 14–PIN 16–PIN 18–PIN 20–PIN 22–PIN A2 0.115/0.195 (2.921/4.953) 0.115/0.195 (2.921/4.953) 0.115/0.195 (2.921/4.953) 0.115/0.195 (2.921/4.953) 0.115/0.195 (2.921/4.953) 0.115/0.195 (2.921/4.953) B 0.014/0.022 (0.356/0.559) 0.014/0.022 (0.356/0.559) 0.014/0.022 (0.356/0.559) 0.014/0.022 (0.356/0.559) 0.014/0.022 (0.356/0.559) 0.014/0.022 (0.356/0.559) B1 0.045/0.070 (1.143/1.778) 0.045/0.070 (1.143/1.778) 0.045/0.070 (1.143/1.778) 0.045/0.070 (1.143/1.778) 0.045/0.070 (1.143/1.778) 0.045/0.070 (1.143/1.778) C 0.008/0.014 (0.203/0.356) 0.008/0.014 (0.203/0.356) 0.008/0.014 (0.203/0.356) 0.008/0.014 (0.203/0.356) 0.008/0.014 (0.203/0.356) 0.008/0.014 (0.203/0.356) D 0.355/0.400 0.735/0.775 0.780/0.800 0.880/0.920 0.980/1.060 1.145/1.155 (9.017/10.160) (18.669/19.685) (19.812/20.320) (22.352/23.368) (24.892/26.924) (29.083/29.337) E 0.300/0.325 (7.620/8.255) 0.300/0.325 (7.620/8.255) 0.300/0.325 (7.620/8.255) 0.300/0.325 (7.620/8.255) 0.300/0.325 (7.620/8.255) 0.300/0.325 (7.620/8.255) E1 0.240/0.280 (6.096/7.112) 0.240/0.280 (6.096/7.112) 0.240/0.280 (6.096/7.112) 0.240/0.280 (6.096/7.112) 0.240/0.280 (6.096/7.112) 0.240/0.280 (6.096/7.112) L 0.115/0.150 (2.921/3.810) 0.115/0.150 (2.921/3.810) 0.115/0.150 (2.921/3.810) 0.115/0.150 (2.921/3.810) 0.115/0.150 (2.921/3.810) 0.115/0.150 (2.921/3.810) Ø 0°/ 15° (0°/15°) 0°/ 15° (0°/15°) 0°/ 15° (0°/15°) 0°/ 15° (0°/15°) 0°/ 15° (0°/15°) 0°/ 15° (0°/15°) SP8530DS/01 SP8530 S2ADC - Simultaneous Sampling Analog to Digital Converter TM 10 © Copyright 2000 Sipex Corporation PACKAGE: PLASTIC SMALL OUTLINE (SOIC) E H D A Ø e B DIMENSIONS (Inches) Minimum/Maximum (mm) SP8530DS/01 A1 L 14–PIN 16–PIN 18–PIN 20–PIN 24–PIN 28–PIN A 0.090/0.104 (2.29/2.649)) 0.090/0.104 (2.29/2.649) 0.090/0.104 (2.29/2.649)) 0.090/0.104 (2.29/2.649) 0.090/0.104 (2.29/2.649) 0.090/0.104 (2.29/2.649) A1 0.004/0.012 (0.102/0.300) 0.004/0.012 (0.102/0.300) 0.004/0.012 (0.102/0.300) 0.004/0.012 (0.102/0.300) 0.004/0.012 (0.102/0.300) 0.004/0.012 (0.102/0.300) B 0.013/0.020 (0.330/0.508) 0.013/0.020 (0.330/0.508) 0.013/0.020 (0.330/0.508) 0.013/0.020 (0.330/0.508) 0.013/0.020 (0.330/0.508) 0.013/0.020 (0.330/0.508) D 0.348/0.363 (8.83/9.22) 0.398/0.413 (10.10/10.49) 0.447/0.463 (11.35/11.74) 0.496/0.512 (12.60/13.00) 0.599/0.614 (15.20/15.59) 0.697/0.713 (17.70/18.09) E 0.291/0.299 (7.402/7.600) 0.291/0.299 (7.402/7.600) 0.291/0.299 (7.402/7.600) 0.291/0.299 (7.402/7.600) 0.291/0.299 (7.402/7.600) 0.291/0.299 (7.402/7.600) e 0.050 BSC (1.270 BSC) 0.050 BSC (1.270 BSC) 0.050 BSC (1.270 BSC) 0.050 BSC (1.270 BSC)) 0.050 BSC (1.270 BSC) 0.050 BSC (1.270 BSC) H 0.394/0.419 (10.00/10.64) 0.394/0.419 (10.00/10.64) 0.394/0.419 (10.00/10.64) 0.394/0.419 (10.00/10.64) 0.394/0.419 (10.00/10.64) 0.394/0.419 (10.00/10.64) L 0.016/0.050 (0.406/1.270) 0.016/0.050 (0.406/1.270) 0.016/0.050 (0.406/1.270) 0.016/0.050 (0.406/1.270) 0.016/0.050 (0.406/1.270) 0.016/0.050 (0.406/1.270) Ø 0°/8° (0°/8°) 0°/8° (0°/8°) 0°/8° (0°/8°) 0°/8° (0°/8°) 0°/8° (0°/8°) 0°/8° (0°/8°) SP8530 S2ADC - Simultaneous Sampling Analog to Digital Converter TM 11 © Copyright 2000 Sipex Corporation ORDERING INFORMATION Model segment Model ..................................................... INL Linearity (LSB) ....... Temperature Range ............................................... Package Types SP8530JN ........................................................... ±1.0 ........................... 0˚C to +70˚C .......................................... 16-pin, 0.3" Plastic DIP SP8530JS ........................................................... ±1.0 ........................... 0˚C to +70˚C .................................................... 16-pin, 0.3" SOIC SP8530KN ......................................................... ±0.75 .......................... 0˚C to +70˚C .......................................... 16-pin, 0.3" Plastic DIP SP8530KS ......................................................... ±0.75 .......................... 0˚C to +70˚C .................................................... 16-pin, 0.3" SOIC SP8530AN .......................................................... ±1.0 ......................... -40˚C to +85˚C ........................................ 16-pin, 0.3" Plastic DIP SP8530AS .......................................................... ±1.0 ......................... -40˚C to +85˚C .................................................. 16-pin, 0.3" SOIC SP8530BN ......................................................... ±0.75 ........................ -40˚C to +85˚C ........................................ 16-pin, 0.3" Plastic DIP SP8530BS ......................................................... ±0.75 ........................ -40˚C to +85˚C .................................................. 16-pin, 0.3" SOIC Please consult the factory for pricing and availability on a Tape-On-Reel option. Corporation SIGNAL PROCESSING EXCELLENCE Sipex Corporation Headquarters and Sales Office 22 Linnell Circle Billerica, MA 01821 TEL: (978) 667-8700 FAX: (978) 670-9001 e-mail: [email protected] Sales Office 233 South Hillview Drive Milpitas, CA 95035 TEL: (408) 934-7500 FAX: (408) 935-7600 Sipex Corporation reserves the right to make changes to any products described herein. Sipex does not assume any liability arising out of the application or use of any product or circuit described hereing; neither does it convey any license under its patent rights nor the rights of others. SP8530DS/01 SP8530 S2ADC - Simultaneous Sampling Analog to Digital Converter TM 12 © Copyright 2000 Sipex Corporation