® SP8542/SP8544 Two and Four Channel 12-Bit Multiplexed Sampling ADCs ■ ■ ■ ■ ■ ■ ■ ■ Two or Four Channel Input Mux 12 Bit Resolution Single +5Volt Supply Internal 1.25 Volt Reference Unipolar 0 to +2.5 Volt Input Range Fast, 3.75 µs Conversion Time per Channel Fast Power Shutdown/Turn-On Mode 3-Wire Synchronous Serial High Speed Interface ■ 2µA Shutdown Mode (10µW) ■ Low Power CMOS 42mW typical DESCRIPTION The SP8542 (2 channel) and SP8544 (4 channel) are 12-Bit serial in/out data acquisition systems with a bi-directional serial interface. The devices contain a high speed 12-Bit analog to digital converter, internal reference, and a 2 or 4 channel input mux which drives the internal sample/ hold circuitry. The SP8542 is available in 16-pin PDIP and SOIC packages, and the SP8544 is available in 18-pin PDIP and SOIC packages, specified over Commercial and Industrial temperature ranges. CS SCLK CONTROL LOGIC STATUS COUNTER MUX DIN CH0 Register CH1 MUX SAR *CH2 *CH3 CDAC OFFSET ADJUST DOUT LATCHED COMPARATOR RTRIM BUFFER SHUTDOWN REF. GAIN ADJUST SP8542 - 2 CHANNEL MUX *SP8544 - 4 CHANNEL MUX REF OUT SP8542/8544DS/01 SP8542/8544 Two and Four Channel 12-Bit Multiplexed Sampling ADC's 1 © Copyright 2000 Sipex Corporation ABSOLUTE MAXIMUM RATINGS (TA=+25˚C unless otherwise noted) .............................................. VDD to DGND ............................................................. -0.3V to +7V VDA to AGND .............................................................. -0.3V to +7V Vin to AGND .................................................... -0.3V to VDA +0.3V Digital Input to VSS ........................................... -0.3V to VDD+0.3V Digital Output to VSS ........................................ -0.3V to VDD+0.3V Operating Temp. Range Commercial (J,K Version) ............................... 0˚C to 70˚C Industrial (A,B Version) ............................. -40˚C to +85˚C Storage Temperature ............................................... -65˚C to 150˚C Lead Temperature(Solder 10sec) ...................................... +300˚C Power Dissipation to +70˚C ............................................... 500mW Derate Power Dissipation Above 70˚C ......................... 10mW/ ˚C SPECIFICATIONS Unless otherwise noted the following specifications apply for VDD = 5V with limits applicable for TA = 25˚C. PARAMETER DC Accuracy Resolution Integral Linearity J, A K ,B MIN. TYP. MAX. 12 UNIT CONDITIONS Bits +0.6 +0.4 +1.0 +0.75 LSB LSB Differential Linearity Error J, A K ,B +0.5 +0.5 +1.0 +1.0 LSB LSB Gain Error J, A K,B +0.2 +0.1 +1.0 +0.5 %FSR %FSR Externally Trimmable to Zero Externally Trimmable to Zero Offset Error J, A K,B +4 +3 +7 +5 LSB LSB Externally Trimmable to Zero Externally Trimmable to Zero Analog Input Input Impedance On Channel Off Channel (2) Input Bias Current Channel to Channel Crosstalk Off to On Channel Conversion Speed Sample Time (1) Conversion Time (1) Complete Cycle (1) Convert Rate (1) Clock Speed Date Rate (1) Convert Rate (1) SP8542/8544DS/01 0 to 2.5 Volts 8 1.0 1.0 -90 No Missing Codes No Missing Codes pF GΩ nA -80 400 3.75 4.25 117.6 4 235 58.8 dB ns µs µs KHz MHz KHz KHz SP8542/8544 Two and Four Channel 12-Bit Multiplexed Sampling ADC's 2 In series with 1.4KΩ note 2 @ 10KHz Full Scale sine wave 2 Channels Total Conversion Rate 4 Channels © Copyright 2000 Sipex Corporation SPECIFICATIONS (continued) Unless otherwise noted the following specifications apply for VDD = 5V with limits applicable for TA = 25˚C. PARAMETER Reference Output Ref. Out Temp. Coef. J, A K,B MIN. TYP. 1.25 30 20 Ref.Out Error +4 Output Current 1 Digital Inputs Input Low Voltage , VIL Input High Voltage , VIH MAX. +25 mV mA 2.0 Input Capacitance Digital Outputs CONDITIONS ppm/˚C ppm/˚C 0.8 Input Current IIN UNIT Volt Volt VDD= 5V ±5% Volt VDD= 5V ±5% +1 µA 3 pF Data Format (3) Data Coding (4) VOH 4.0 VOL 0.4 Volt VDD=5V±5%, IOH=-0.4mA Volt VDD=5V±5%, IOL=+1.6mA AC Accuracy Spurious Free Dynamic Range (SFDR) 78 dB fin=47KHz Total Harmonic Distortion (THD) -74 dB fin=47KHz Signal to Noise & Distortion (SINAD) 70 dB fin=47KHz Signal to Noise (SNR) 71 dB fin=47KHz Acquisition Time to 0.01% 250 ns -3dB Small Signal BW 13 MHz Aperture Delay 35 ns Aperture Jitter 10 ps RMS Sampling Dynamics SP8542/8544DS/01 SP8542/8544 Two and Four Channel 12-Bit Multiplexed Sampling ADC's 3 © Copyright 2000 Sipex Corporation SPECIFICATIONS (continued) Unless otherwise noted the following specifications apply for VDD = 5V with limits applicable for TA = 25˚C. PARAMETER Power Supplies MIN. TYP. MAX. +4.75 +5 +5.25 Supply Current Operating Mode 8.4 14 mA SD=0 Shutdown Mode .01 2 µA SD=1 Power Dissipation Operating Mode Shutdown Mode 42 0.05 70 10 mW µW SD=0 SD=1 20 µS VDD Power Turn On UNIT CONDITIONS V Via Shutdown Control to 1 LSB settling error. Temperature Range Commercial 0 to +70 ˚C Industrial -40 to +85 ˚C Storage -65 to +150 ˚C (1) Free Running Mode (2) Note that the transition from off to on causes charging currents that increase the average input current (3) Data Format is 12-Bit Serial (4) Data Coding is binary (see Timing Diagram) SP8542/8544DS/01 SP8542/8544 Two and Four Channel 12-Bit Multiplexed Sampling ADC's 4 © Copyright 2000 Sipex Corporation SP8542 PIN ASSIGNMENTS SP8544 PIN ASSIGNMENTS Pin 1-N.C.-No Connection Pin 2-CH0-Analog Mux Input 0 Pin 3-CH1-Analog Mux Input 1 Pin 4-AGND-Analog Ground Pin 5-VSS Digital Ground Pin 6-SCLK-Serial Clock Input Pin 7-DOUT Digital Data Output Pin 8-DIN Mux Channel Selection Input Pin 9-Status Pin 10-CS-Chip Select Bar Input, High Deselects chip, Low Selects chip Pin 11-SD-Shutdown Input, logic low = power up, logic high = powerdown Pin 12-VDD Digital +5V supply Pin 13-VDA Analog +5V supply Pin 14-OffADJ External Offset Adjust Pin 15-Refout-Voltage Reference Output Pin 16-GAINADJ-External Gain Adjustment Pin 1-N.C.-No Connection Pin 2-CH0-Analog Mux Input 0 Pin 3-CH1-Analog Mux Input 1 Pin 4-CH2-Analog Mux Input 2 Pin 5-CH3-Analog Mux Input 3 Pin 6-AGND-Analog Ground Pin 7-VSS Digital Ground Pin 8-SCLK-Serial Clock Input Pin 9-DOUT Digital Data Output Pin 10-DIN Mux Channel Selection Input Pin 11-Status Pin 12-CS-Chip Select Bar Input, High Deselects chip, Low Selects chip Pin 13-SD-Shutdown Input, logic low = power up, logic high = powerdown Pin 14-VDD Digital +5V supply Pin 15-VDA Analog +5V supply Pin 16-OffADJ External Offset Adjust Pin 17-Refout-Voltage Reference Output Pin 18-GAINADJ-External Gain Adjustment N.C. 1 16 GAIN ADJUST N.C. 1 18 GAIN ADJUST CH0 2 15 REF OUT CH0 2 17 REF OUT CH1 3 14 OFFSET ADJ. CH1 3 16 OFFSET ADJ. CH2 4 15 VDA AGND 4 13 VDA CH3 5 14 VDD VSS 5 12 VDD AGND 6 13 SD SCLK 6 11 SD VSS 7 12 CS DOUT 7 10 CS SCLK 8 11 STATUS DIN 8 9 STATUS DOUT 9 10 DIN SP8542 SP 8542 Channel Selection Truth Table MA0 0 1 SP8542/8544DS/01 SP8544 SP 8544 Channel Selection Truth Table Channel Selection CH0 CH1 MA1 0 0 1 1 MA0 0 1 0 1 SP8542/8544 Two and Four Channel 12-Bit Multiplexed Sampling ADC's 5 Channel Selection CH0 CH1 CH2 CH3 © Copyright 2000 Sipex Corporation 10kOhms 0.01µF* 1 N.C. GAIN ADJUST 16 CH0 2 CH0 REF OUT 15 CH1 3 CH1 OFFSET ADJ. 14 4 AGND 5 VSS 6 SCLK 7 DOUT 8 DIN 5kOhms VDA 13 SP8542 VDD 12 SD 11 CS 10 STATUS + +5V 0.1µF 2kOhms 6.8µF 0.1µF 9 CLOCK IN DATA OUT DATA IN STATUS OUT CHIP SELECT SHUT DOWN * Optional filter capacitor is helpful in a noisy pc board application. Figure 1. Operating Circuit FEATURES The SP8542 and SP8544 are two and four channel 12-Bit serial In/Out data acquisition system. The device contains a high speed 12-bit analog to digital converter, internal reference, and a two or four channel input Mux which drives the internal sample and hold circuit. Conversion is initiated by falling edge on CS in slave mode at which point the selected input voltage is held and a conversion is started. A delay tCS of 90ns is required between the falling edge of CS and the first rising of SCLK. The device responds to the shut down signal asynchronously so that a conversion in progress will be interrupted and the resulting data will be erroneous. A 20 µSec delay is required between the falling edge of shutdown and initiation of a conversion. The SP8542 and SP8544 are fabricated in Sipex' Bipolar Enhanced CMOS Process that permits state-of-the-art design using bipolar devices in the analog/linear section and extremely low power CMOS in digital/logic section. Input Data Format The SP8542 requires, in addition to the Chip Select Bar (CS) and System Clock (SCLK) signals, one multiplexer configuration bit (MA0). The SP8544 requires, in addition to the Chip Select Bar (CS) and System Clock (SCLK) signals, two multiplexer configuration bits (MA1 and MA0). These bits are shifted into the DIN pin, MSB first, during the first two clocks of the 16 clock conversion cycle and configure the input multiplexer to select the desired input channel. CIRCUIT OPERATION Figure 1 and 2 shows a simple circuit required to operate the SP8542 and SP8544. Please refer to the free running mode timing diagram or the slave mode timing diagram. The conversion is controlled by the user supplied signals Chip Select Bar (CS) which selects and deselects the device, and a system clock (SCLK). A high level applied to CS asynchronously clears the internal logic, puts the sample & hold (CDAC) into sample mode and places the DOUT (Data Output) pin in a high impedance state. SP8542/8544DS/01 SP8542/8544 Two and Four Channel 12-Bit Multiplexed Sampling ADC's 6 © Copyright 2000 Sipex Corporation 10kOhms 0.01µF* 1 N.C. CH0 2 CH0 GAIN ADJUST 18 REF OUT 17 CH1 3 CH1 OFFSET ADJ. 16 CH2 4 CH2 VDA 15 CH3 5 CH3 VDD 14 6 AGND SP8544 7 VSS 8 SCLK 9 DOUT SD 13 CS 12 5kOhms + +5V 0.1µF 2kOhms 6.8µF 0.1µF STATUS 11 DIN 10 CLOCK IN DATA OUT DATA IN STATUS OUT CHIP SELECT SHUT DOWN * Optional filter capacitor is helpful in a noisy pc board application. Figure 2. Operating Circuit These bits, if shifted in during the nth conversion, will determine the input configuation for the (n+1) conversion (see timing diagram). The input range is 0 to 2.5V. The serial output is Hi-Z unless conversion data is being shifted out. It is therefore possible to tie the DIN pin to the DOUT pin for a 3-wire interface or leave them seperate for a 4-wire interface. The output is compatible with SPI, QSPI and MICROWIRE serial communication protocols. data. In this mode there is a single dead SCLK cycle between the 16th clock of one conversion and the first clock of the following conversion for both the SP8542 and SP8544. At a clock frequency of 4 MHz the SP8542 provides a throughput rate of 117.6KHz for both channels and the SP8544 provides a throughput rate of 58.8KHz for all four channels. Both devices provide a throughput rate of 235KHz for one channel in Free Running Mode. 0utput Data Format In slave mode operation, CS is brought high between each conversion so that all conversions are initiated by falling edge on CS. 12 Bits of data are sent in 16 clock cycles for each conversion. Dout is in high impedance state during the first four clock cycles of the conversion and sends the 12 bits of data MSB first, in the succeeding 12 clock cycles. Output data changes on the falling edge of SCLK and is stable on the rising edge of SCLK. Layout Considerations Because of the high resolution and linearity of the SP8542 and SP8544 system design considerations such as ground path impedance and contact resistance become very important. Free Running operation is obtained by holding CS low. In this mode an oscillator is connected directly to SCLK pin. The SCLK signal along with the STATUS output Signal are used to synchronize the host system with the converter's SP8542/8544DS/01 To avoid introducing distortion when driving the analog inputs of these devices, the source resistance must be very low, or constant with signal level. Note that in the operating circuit SP8542/8544 Two and Four Channel 12-Bit Multiplexed Sampling ADC's 7 © Copyright 2000 Sipex Corporation there is no connection made between VDA and the system power supply. This is because the analog supply pin (VDA) is connected internally to the digital supply pin (VDD) through a ten ohm resistor. Minimizing "Glitches" Coupling of external transients into an analog to digital converter can cause errors which are difficult to debug. In addition to the above discussions on layout considerations, bypassing and grounding, there are several other useful steps that can be taken to get the best analog performance from a system using the SP8542 or SP8544 converter. These potential system problem sources are particularly important to consider when developing a new system, and looking for causes of errors in breadboards. This connection when combined with a parallel combination of 6.8µF tantalum and 0.1µF ceramic capacitor between VDA and analog ground, will provide some immunity to noise which resides on the system supply. To maintain maximum system accuracy, the supply connected to the VDD pin should be well isolated from digital supplies and wide load variations. First, care should be taken to avoid transients during critical times in the sampling and conversion process. Since the SP8542 and SP0544 have internal sample/hold function the signal that puts the device into hold state (CS) going low is critical, as it would be on any sample/hold amplfier. The CS falling edge should have 5 to 10 ns transition time, low jitter, and have a minimal ringing, especially during the first 35 ns after it falls. To limit effects of digital switching elsewherein a system, it often makes sense to run a seperate +5Vsupply conductor from the supply requlator to any analog components requiring +5V including the SP8542 and SP8544. Noise on the power supply lines can degrade the converters performance, especially corrupting are noise and spikes from a switching power supply. The ground pins (AGND and VSS) on the SP8542 and SP8544 are separated internally and should be connected to each other under the converter. The use of separate Analog & Digital ground planes is usually the best technique for preserving dynamic performance and reducing noise coupling into sensitive converter circuits. Where any compromise must be made the common return of the analog input signal should be referenced to the AGND pin of the converter. This prevents any voltage drops that might occur in the power supply common returns from appearing in series with the input signal. Coupling between analog and digital lines should be minimized by careful layout. For instance, if analog and digital lines must cross they should do so at right angles. Parallel analog and digital lines should be separated from each other by a trace connected to common. If external gain and offset potentiometers are used, the potentiometers and related resistors should be located as close to the SP8542 and SP8544 as possible. SP8542/8544DS/01 SP8542/8544 Two and Four Channel 12-Bit Multiplexed Sampling ADC's 8 © Copyright 2000 Sipex Corporation TIMING CHARACTERISTICS (Typical @ 25°C with VDD = +5V, unless otherwise noted) PARAMETER MIN. Thoughput Time (tTP=tA+tC) 4.25 Acquisition Time (tA) (2 SCLK Periods) 400 Conversion Time (tC) (15 SCLK Periods) 3.75 SCLKLow Pulse Width (tSKL) 110 125 ns SCLK High Pulse Width (tSKH) 110 125 ns SCLK Period (tSKT) 250 ns Setup Time DIN to SCLK Rising (tDISU) 0 ns Hold Time from SCLK Rising to DIN (tDIH). 5 ns Buss Relinquish Time (tBR) TYP. MAX. UNIT 500 ns µs 45 ns Setup Time -SCLK Falling to CSN Falling (tCSSU) 10 ns CSN Low Before SCLK Rises (tCS) 90 ns SCLK Falling to Data Valid (tSD) 50 ns CSN Falling to STATUS Rising (tDCS) 69 ns SCLK 17Falling to Status Rising Free Run (tDSS) 70 ns SCLK16 Falling to Status Falling ( tDSE) 45 ns Delay SD Low to initiate Conversion (tPU) 5 µs Aperture Delay Slave-Mode (tAPC) 30 ns Aperture Delay Free-Running Mode (tAPS) 35 ns SP8542/8544DS/01 SP8542/8544 Two and Four Channel 12-Bit Multiplexed Sampling ADC's 9 COND. µs © Copyright 2000 Sipex Corporation 2 3 4 5 6 15 16 1 2 3 4 5 6 15 Timing Diagrams Slave Mode SP8542 SP8542/8544DS/01 1 16 SCLK CSN 10 SP8542/8544 Two and Four Channel 12-Bit Multiplexed Sampling ADC's STATUS DIN DATA WORD (N+1) DATA WORD N DATA D1 D11 D10 D11 D10 D0 MA0 D1 D0 MA0 PROGRAM BIT FOR WORD (N + 1) tCSSU PROGRAM BIT FOR WORD (N + 2) tDIH tCS tDISU tSKH 1 SCLK 2 tSKL tSKT 3 tBR 4 tDSE tSD 5 15 16 D1 D0 tAPC CS tPU tDCS STATUS HI-Z DATA D11 D10 HI-Z © Copyright 2000 Sipex Corporation MA0 tC MODE SD AQUIRE CONVERT tA AQUIRE 16 17 1 2 3 4 5 6 15 16 17 1 2 3 4 5 6 15 16 17 1 2 CS = 0 STATUS HI-Z DATA D1 HI-Z DATA WORD N D0 D1 D11 D10 tDSS tAPS SCLK 17 tDIH 1 D1 D0 MA0 tSKL tSKH 2 tDSE tSD tSKT 3 MA1 MA0 PROGRAM BIT FOR WORD (N + 2) PROGRAM BIT FOR WORD (N + 1) tDISU D11 D10 D0 MA0 DIN DATA WORD (N+1) 4 5 tBR 6 15 16 17 1 CS = 0 STATUS D11 DATA © Copyright 2000 Sipex Corporation DIN MODE AQUIRE D10 D1 D0 MA1 MA0 tC CONVERT tA AQUIRE CONVERT Timing Diagrams 11 SP8542/8544 Two and Four Channel 12-Bit Multiplexed Sampling ADC's Free Running Mode SP8542 SP8542/8544DS/01 15 SCLK 2 3 4 5 6 15 16 1 2 3 4 5 6 15 Timing Diagrams Slave Mode SP8544 SP8542/8544DS/01 1 16 SCLK CSN 12 SP8542/8544 Two and Four Channel 12-Bit Multiplexed Sampling ADC's STATUS DIN DATA WORD (N+1) DATA WORD N DATA D1 D11 D10 D11 D10 D0 MA1 MA0 D0 MA1 MA0 PROGRAM BIT FOR WORD (N + 1) tCSSU D1 PROGRAM BIT FOR WORD (N + 2) tDIH tCS tDISU tSKH 1 SCLK 2 tSKL tSKT 3 tBR 4 tDSE tSD 5 15 16 D1 D0 tAPC CS tPU tDCS STATUS HI-Z DATA © Copyright 2000 Sipex Corporation MA1 D11 D10 MA0 tC MODE SD AQUIRE HI-Z CONVERT tA AQUIRE 16 17 1 2 3 4 5 6 15 16 17 1 2 3 4 5 6 15 16 17 1 2 CS = 0 STATUS HI-Z DATA D1 HI-Z DATA WORD N D1 D11 D10 D0 D0 MA1 MA0 DIN tDSS tAPS SCLK 17 tSKL tSKH tDIH 1 D11 D10 D1 D0 MA1 MA0 2 tDSE tSD tSKT 3 MA1 MA0 PROGRAM BIT FOR WORD (N + 2) PROGRAM BIT FOR WORD (N + 1) tDISU DATA WORD (N+1) 4 5 tBR 6 15 16 17 1 CS = 0 STATUS © Copyright 2000 Sipex Corporation D11 DATA DIN MODE AQUIRE MA1 D10 D1 D0 MA0 MA1 tC CONVERT tA AQUIRE CONVERT Timing Diagrams 13 SP8542/8544 Two and Four Channel 12-Bit Multiplexed Sampling ADC's Free Running Mode SP8544 SP8542/8544DS/01 15 SCLK PACKAGE: PLASTIC DUAL–IN–LINE (NARROW) E1 E D1 = 0.005" min. (0.127 min.) A1 = 0.015" min. (0.381min.) D A = 0.210" max. (5.334 max). C A2 B1 B e = 0.100 BSC (2.540 BSC) Ø L eA = 0.300 BSC (7.620 BSC) ALTERNATE END PINS (BOTH ENDS) DIMENSIONS (Inches) Minimum/Maximum (mm) 8–PIN 14–PIN 16–PIN 18–PIN 20–PIN 22–PIN A2 0.115/0.195 (2.921/4.953) 0.115/0.195 (2.921/4.953) 0.115/0.195 (2.921/4.953) 0.115/0.195 (2.921/4.953) 0.115/0.195 (2.921/4.953) 0.115/0.195 (2.921/4.953) B 0.014/0.022 (0.356/0.559) 0.014/0.022 (0.356/0.559) 0.014/0.022 (0.356/0.559) 0.014/0.022 (0.356/0.559) 0.014/0.022 (0.356/0.559) 0.014/0.022 (0.356/0.559) B1 0.045/0.070 (1.143/1.778) 0.045/0.070 (1.143/1.778) 0.045/0.070 (1.143/1.778) 0.045/0.070 (1.143/1.778) 0.045/0.070 (1.143/1.778) 0.045/0.070 (1.143/1.778) C 0.008/0.014 (0.203/0.356) 0.008/0.014 (0.203/0.356) 0.008/0.014 (0.203/0.356) 0.008/0.014 (0.203/0.356) 0.008/0.014 (0.203/0.356) 0.008/0.014 (0.203/0.356) D 0.355/0.400 0.735/0.775 0.780/0.800 0.880/0.920 0.980/1.060 1.145/1.155 (9.017/10.160) (18.669/19.685) (19.812/20.320) (22.352/23.368) (24.892/26.924) (29.083/29.337) E 0.300/0.325 (7.620/8.255) 0.300/0.325 (7.620/8.255) 0.300/0.325 (7.620/8.255) 0.300/0.325 (7.620/8.255) 0.300/0.325 (7.620/8.255) 0.300/0.325 (7.620/8.255) E1 0.240/0.280 (6.096/7.112) 0.240/0.280 (6.096/7.112) 0.240/0.280 (6.096/7.112) 0.240/0.280 (6.096/7.112) 0.240/0.280 (6.096/7.112) 0.240/0.280 (6.096/7.112) L 0.115/0.150 (2.921/3.810) 0.115/0.150 (2.921/3.810) 0.115/0.150 (2.921/3.810) 0.115/0.150 (2.921/3.810) 0.115/0.150 (2.921/3.810) 0.115/0.150 (2.921/3.810) Ø 0°/ 15° (0°/15°) 0°/ 15° (0°/15°) 0°/ 15° (0°/15°) 0°/ 15° (0°/15°) 0°/ 15° (0°/15°) 0°/ 15° (0°/15°) SP8542/8544DS/01 SP8542/8544 Two and Four Channel 12-Bit Multiplexed Sampling ADC's 14 © Copyright 2000 Sipex Corporation PACKAGE: PLASTIC SMALL OUTLINE (SOIC) E H D A Ø e A1 B DIMENSIONS (Inches) Minimum/Maximum (mm) L 14–PIN 16–PIN 18–PIN 20–PIN 24–PIN 28–PIN A 0.090/0.104 (2.29/2.649)) 0.090/0.104 (2.29/2.649) 0.090/0.104 (2.29/2.649)) 0.090/0.104 (2.29/2.649) 0.090/0.104 (2.29/2.649) 0.090/0.104 (2.29/2.649) A1 0.004/0.012 (0.102/0.300) 0.004/0.012 (0.102/0.300) 0.004/0.012 (0.102/0.300) 0.004/0.012 (0.102/0.300) 0.004/0.012 (0.102/0.300) 0.004/0.012 (0.102/0.300) B 0.013/0.020 (0.330/0.508) 0.013/0.020 (0.330/0.508) 0.013/0.020 (0.330/0.508) 0.013/0.020 (0.330/0.508) 0.013/0.020 (0.330/0.508) 0.013/0.020 (0.330/0.508) D 0.348/0.363 (8.83/9.22) 0.398/0.413 (10.10/10.49) 0.447/0.463 (11.35/11.74) 0.496/0.512 (12.60/13.00) 0.599/0.614 (15.20/15.59) 0.697/0.713 (17.70/18.09) E 0.291/0.299 (7.402/7.600) 0.291/0.299 (7.402/7.600) 0.291/0.299 (7.402/7.600) 0.291/0.299 (7.402/7.600) 0.291/0.299 (7.402/7.600) 0.291/0.299 (7.402/7.600) e 0.050 BSC (1.270 BSC) 0.050 BSC (1.270 BSC) 0.050 BSC (1.270 BSC) 0.050 BSC (1.270 BSC)) 0.050 BSC (1.270 BSC) 0.050 BSC (1.270 BSC) H 0.394/0.419 (10.00/10.64) 0.394/0.419 (10.00/10.64) 0.394/0.419 (10.00/10.64) 0.394/0.419 (10.00/10.64) 0.394/0.419 (10.00/10.64) 0.394/0.419 (10.00/10.64) L 0.016/0.050 (0.406/1.270) 0.016/0.050 (0.406/1.270) 0.016/0.050 (0.406/1.270) 0.016/0.050 (0.406/1.270) 0.016/0.050 (0.406/1.270) 0.016/0.050 (0.406/1.270) Ø 0°/8° (0°/8°) 0°/8° (0°/8°) 0°/8° (0°/8°) 0°/8° (0°/8°) 0°/8° (0°/8°) 0°/8° (0°/8°) SP8542/8544DS/01 SP8542/8544 Two and Four Channel 12-Bit Multiplexed Sampling ADC's 15 © Copyright 2000 Sipex Corporation ORDERING INFORMATION Model ..................................................... INL Linearity (LSB) ............................. Temperature Range ..................................... Package Types SP8542JN ........................................................... ±1.0 ................................................ 0˚C to +70˚C ................................. 16-pin, 0.3" Plastic DIP SP8542JS ........................................................... ±1.0 ................................................ 0˚C to +70˚C .......................................... 16-pin, 0.3" SOIC SP8542KN ......................................................... ±0.75 ............................................... 0˚C to +70˚C ................................. 16-pin, 0.3" Plastic DIP SP8542KS ......................................................... ±0.75 ............................................... 0˚C to +70˚C .......................................... 16-pin, 0.3" SOIC SP8542AN .......................................................... ±1.0 ............................................... -40˚C to +85˚C ............................... 16-pin, 0.3" Plastic DIP SP8542AS .......................................................... ±1.0 ............................................... -40˚C to +85˚C ........................................ 16-pin, 0.3" SOIC SP8542BN ......................................................... ±0.75 .............................................. -40˚C to +85˚C ............................... 16-pin, 0.3" Plastic DIP SP8542BS ......................................................... ±0.75 .............................................. -40˚C to +85˚C ........................................ 16-pin, 0.3" SOIC Model ..................................................... INL Linearity (LSB) ............................. Temperature Range ..................................... Package Types SP8544JN ........................................................... ±1.0 ................................................ 0˚C to +70˚C ................................. 18-pin, 0.3" Plastic DIP SP8544JS ........................................................... ±1.0 ................................................ 0˚C to +70˚C .......................................... 18-pin, 0.3" SOIC SP8544KN ......................................................... ±0.75 ............................................... 0˚C to +70˚C ................................. 18-pin, 0.3" Plastic DIP SP8544KS ......................................................... ±0.75 ............................................... 0˚C to +70˚C .......................................... 18-pin, 0.3" SOIC SP8544AN .......................................................... ±1.0 ............................................... -40˚C to +85˚C ............................... 18-pin, 0.3" Plastic DIP SP8544AS .......................................................... ±1.0 ............................................... -40˚C to +85˚C ........................................ 18-pin, 0.3" SOIC SP8544BN ......................................................... ±0.75 .............................................. -40˚C to +85˚C ............................... 18-pin, 0.3" Plastic DIP SP8544BS ......................................................... ±0.75 .............................................. -40˚C to +85˚C ........................................ 18-pin, 0.3" SOIC Please consult the factory for pricing and availability on a Tape-On-Reel option. Corporation SIGNAL PROCESSING EXCELLENCE Sipex Corporation Headquarters and Sales Office 22 Linnell Circle Billerica, MA 01821 TEL: (978) 667-8700 FAX: (978) 670-9001 e-mail: [email protected] Sales Office 233 South Hillview Drive Milpitas, CA 95035 TEL: (408) 934-7500 FAX: (408) 935-7600 Sipex Corporation reserves the right to make changes to any products described herein. Sipex does not assume any liability arising out of the application or use of any product or circuit described hereing; neither does it convey any license under its patent rights nor the rights of others. SP8542/8544DS/01 SP8542/8544 Two and Four Channel 12-Bit Multiplexed Sampling ADC's 16 © Copyright 2000 Sipex Corporation