SL74HC251 8-Input Data Selector/Multiplexer with 3-State Outputs High-Performance Silicon-Gate CMOS The SL74HC251 is identical in pinout to the LS/ALS251. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LS/ALSTTL outputs. The device selects one of the eight binary Data Inputs, as determined by the Address Inputs. The Output Enable pin must be at a low level for the selected data to appear at the outputs. If Output Enable is high, the Y and the Y outputs are in the high-impedance state. This 3-State feature allows the IN74HC251 to be used in bus-oriented systems. • Outputs Directly Interface to CMOS, NMOS, and TTL • Operating Voltage Range: 2.0 to 6.0 V • Low Input Current: 1.0 µA • High Noise Immunity Characteristic of CMOS Devices ORDERING INFORMATION SL74HC251N Plastic SL74HC251D SOIC TA = -55° to 125° C for all packages PIN ASSIGNMENT LOGIC DIAGRAM FUNCTION TABLE Inputs PIN 16 =VCC PIN 8 = GND Outputs A2 A1 A0 OE Y Y X X X H Z Z L L L L D0 D0 L L H L D1 D1 L H L L D2 D2 L H H L D3 D3 H L L L D4 D4 H L H L D5 D5 H H L L D6 D6 H H H L D7 D7 D0,D1...D7=the level of the respective D input Z = high-impedance state X = don’t care SLS System Logic Semiconductor SL74HC251 MAXIMUM RATINGS * Symbol Parameter Value Unit -0.5 to +7.0 V VCC DC Supply Voltage (Referenced to GND) VIN DC Input Voltage (Referenced to GND) -1.5 to VCC +1.5 V DC Output Voltage (Referenced to GND) -0.5 to VCC +0.5 V DC Input Current, per Pin ±25 mA DC Output Current, per Pin ±50 mA ICC DC Supply Current, VCC and GND Pins ±75 mA PD Power Dissipation in Still Air, Plastic DIP+ SOIC Package+ 750 500 mW -65 to +150 °C 260 °C VOUT IIN IOUT Tstg TL Storage Temperature Lead Temperature, 1 mm from Case for 10 Seconds (Plastic DIP or SOIC Package) * Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. +Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C SOIC Package: : - 7 mW/°C from 65° to 125°C RECOMMENDED OPERATING CONDITIONS Symbol VCC VIN, VOUT Parameter DC Supply Voltage (Referenced to GND) DC Input Voltage, Output Voltage (Referenced to GND) TA Operating Temperature, All Package Types tr, t f Input Rise and Fall Time (Figure 1) VCC =2.0 V VCC =4.5 V VCC =6.0 V Min Max Unit 2.0 6.0 V 0 VCC V -55 +125 °C 0 0 0 1000 500 400 ns This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, VIN and VOUT should be constrained to the range GND≤(VIN or VOUT)≤VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open. SLS System Logic Semiconductor SL74HC251 DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND) VCC Guaranteed Limit Test Conditions V 25 °C to -55°C ≤85 °C ≤125 °C Unit Minimum High-Level Input Voltage VOUT=0.1 V or VCC-0.1 V IOUT≤ 20 µA 2.0 4.5 6.0 1.5 3.15 4.2 1.5 3.15 4.2 1.5 3.15 4.2 V VIL Maximum Low -Level Input Voltage VOUT=0.1 V or VCC-0.1 V IOUT ≤ 20 µA 2.0 4.5 6.0 0.3 0.9 1.2 0.3 0.9 1.2 0.3 0.9 1.2 V VOH Minimum High-Level Output Voltage VIN=VIH or VIL IOUT ≤ 20 µA 2.0 4.5 6.0 1.9 4.4 5.9 1.9 4.4 5.9 1.9 4.4 5.9 V VIN=VIH or VIL IOUT ≤ 4.0 mA IOUT ≤ 5.2 mA 4.5 6.0 3.98 5.48 3.84 5.34 3.7 5.2 VIN=VIH or VIL IOUT ≤ 20 µA 2.0 4.5 6.0 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 VIN=VIH or VIL IOUT ≤ 4.0 mA IOUT ≤ 5.2 mA 4.5 6.0 0.26 0.26 0.33 0.33 0.4 0.4 Symbol Parameter VIH VOL Maximum Low-Level Output Voltage V IIN Maximum Input Leakage Current VIN=VCC or GND 6.0 ±0.1 ±1.0 ±1.0 µA IOZ Maximum Three-State Leakage Current Output in High-Impedance State VIN= VIL or VIH VOUT=VCC or GND 6.0 ±0.5 ±5.0 ±10 µA ICC Maximum Quiescent Supply Current (per Package) VIN=VCC or GND IOUT=0µA 6.0 8.0 80 160 µA SLS System Logic Semiconductor SL74HC251 AC ELECTRICAL CHARACTERISTICS(CL=50pF,Input t r=t f=6.0 ns) VCC Symbol Parameter Guaranteed Limit V 25 °C to -55°C ≤85°C ≤125°C Unit tPLH, t PHL Maximum Propagation Delay, Input D to Output Y or Y (Figures 1,2 and 5) 2.0 4.5 6.0 185 37 31 230 46 39 280 56 48 ns tPLH, t PHL Maximum Propagation Delay , Input A to Output Y or Y (Figures 3 and 5) 2.0 4.5 6.0 205 41 35 255 51 43 310 62 53 ns tPLZ, t PHZ Maximum Propagation Delay , Output Enable to Output Y (Figures 4 and 6) 2.0 4.5 6.0 195 39 33 245 48 42 295 59 50 ns tPZL, t PZH Maximum Propagation Delay , Output Enable to Output Y (Figures 4 and 6) 2.0 4.5 6.0 145 29 25 180 36 31 220 44 38 ns tPLZ, t PHZ Maximum Propagation Delay , Output Enable to Output Y (Figures 4 and 6) 2.0 4.5 6.0 220 44 37 275 55 47 330 66 56 ns tPZL, t PZH Maximum Propagation Delay , Output Enable to Output Y (Figures 4 and 6) 2.0 4.5 6.0 150 30 26 190 38 33 225 45 38 ns tTLH, t THL Maximum Output Transition Time, Any Output (Figures 1 and 6) 2.0 4.5 6.0 75 15 13 95 19 16 110 22 19 ns Maximum Input Capacitance - 10 10 10 pF Maximum Three-State Output Capacitance (Output in High-Impedance State) - 15 15 15 pF CIN COUT CPD Power Dissipation Capacitance (Per Package) Typical @25°C,VCC=5.0 V Used to determine the no-load dynamic power consumption: PD=CPDVCC2f+ICCVCC 36 Figure 1. Switching Waveforms pF Figure 2. Switching Waveforms SLS System Logic Semiconductor SL74HC251 Figure 3. Switching Waveforms Figure 5. Test Circuit Figure 4. Switching Waveforms Figure 6.Test Circuit EXPANDED LOGIC DIAGRAM SLS System Logic Semiconductor