SL74HCT157 Quad 2-Input Data Selectors/Multiplexer High-Performance Silicon-Gate CMOS The SL74HCT157 is identical in pinout to the LS/ALS157. This device may be used as a level converter for interfacing TTL or NMOS outputs to High Speed CMOS inputs. This device routes 2 nibbles (A or B) to a single port (Y) as determined by the Select input. The data is presented at the outputs in noninvertered form. A high level on the Output Enable input sets all four Y outputs to a low level. • TTL/NMOS Compatible Input Levels • Outputs Directly Interface to CMOS, NMOS, and TTL • Operating Voltage Range: 4.5 to 5.5 V • Low Input Current: 1.0 µA ORDERING INFORMATION SL74HCT157N Plastic SL74HCT157D SOIC TA = -55° to 125° C for all packages PIN ASSIGNMENT LOGIC DIAGRAM FUNCTION TABLE Inputs PIN 16 =VCC PIN 8 = GND Outputs Output Enable Select Y0-Y3 H X L L L A0-A3 L H B0-B3 X=don’t care A0-A3,B0-B3=the levels of the respective Data-Word Inputs SLS System Logic Semiconductor SL74HCT157 MAXIMUM RATINGS * Symbol Parameter Value Unit -0.5 to +7.0 V VCC DC Supply Voltage (Referenced to GND) VIN DC Input Voltage (Referenced to GND) -1.5 to VCC +1.5 V DC Output Voltage (Referenced to GND) -0.5 to VCC +0.5 V DC Input Current, per Pin ±20 mA DC Output Current, per Pin ±25 mA ICC DC Supply Current, VCC and GND Pins ±50 mA PD Power Dissipation in Still Air, Plastic DIP+ SOIC Package+ 750 500 mW -65 to +150 °C 260 °C VOUT IIN IOUT Tstg TL Storage Temperature Lead Temperature, 1 mm from Case for 10 Seconds (Plastic DIP or SOIC Package) * Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. +Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C SOIC Package: : - 7 mW/°C from 65° to 125°C RECOMMENDED OPERATING CONDITIONS Symbol VCC VIN, VOUT Parameter DC Supply Voltage (Referenced to GND) DC Input Voltage, Output Voltage (Referenced to GND) TA Operating Temperature, All Package Types tr, t f Input Rise and Fall Time (Figure 1 Min Max Unit 4.5 5.5 V 0 VCC V -55 +125 °C 0 500 ns This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, VIN and VOUT should be constrained to the range GND≤(VIN or VOUT)≤VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open. SLS System Logic Semiconductor SL74HCT157 DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND) VCC Guaranteed Limit Test Conditions V 25 °C to -55°C ≤85 °C ≤125 °C Unit Minimum High-Level Input Voltage VOUT=0.1 V or VCC-0.1 V IOUT≤ 20 µA 4.5 5.5 2.0 2.0 2.0 2.0 2.0 2.0 V VIL Maximum Low -Level Input Voltage VOUT=0.1 V or VCC-0.1 V IOUT ≤ 20 µA 4.5 5.5 0.8 0.8 0.8 0.8 0.8 0.8 V VOH Minimum High-Level Output Voltage VIN=VIH or VIL IOUT ≤ 20 µA 4.5 5.5 4.4 5.4 4.4 5.4 4.4 5.4 V VIN=VIH or VIL IOUT ≤ 4.0 mA 4.5 3.98 3.84 3.7 VIN=VIH or VIL IOUT ≤ 20 µA 4.5 5.5 0.1 0.1 0.1 0.1 0.1 0.1 VIN=VIH or VIL IOUT ≤ 4.0 mA 4.5 0.26 0.33 0.4 Symbol Parameter VIH VOL Maximum Low-Level Output Voltage V IIN Maximum Input Leakage Current VIN=VCC or GND 5.5 ±0.1 ±1.0 ±1.0 µA ICC Maximum Quiescent Supply Current (per Package) VIN=VCC or GND IOUT=0µA 5.5 4.0 40 160 µA ∆ICC Additional Quiescent Supply Current VIN=2.4 V, Any One Input VIN=VCC or GND, Other Inputs IOUT=0µA SLS System Logic Semiconductor 5.5 -55°C 25°C to 125°C 2.9 2.4 mA SL74HCT157 AC ELECTRICAL CHARACTERISTICS (VCC =5.0 V ± 10%, CL=50pF,Input t r=t f=6.0 ns) Guaranteed Limit Symbol Parameter 25 °C to -55°C ≤85°C ≤125°C Unit tPLH, t PHL Maximum Propagation Delay, Input A or B to Output Y (Figures 1and 4) 27 34 41 ns tPLH, t PHL Maximum Propagation Delay , Select to Output Y (Figures 2 and 4) 37 46 56 ns tPLH, t PHL Maximum Propagation Delay , Output Enable to Output Y (Figures 3 and 4) 30 38 45 ns tTLH, t THL Maximum Output Transition Time, Any Output (Figures 1 and 4) 15 19 22 ns Maximum Input Capacitance 10 10 10 pF CIN Power Dissipation Capacitance (Per Transceiver Channel) CPD Used to determine the no-load dynamic power consumption: PD=CPDVCC2f+ICCVCC Typical @25°C,VCC=5.0 V 64 pF Figure 1. Switching Waveforms Figure 2. Switching Waveforms Figure 3. Switching Waveforms Figure 4. Test Circuit SLS System Logic Semiconductor SL74HCT157 EXPANDED LOGIC DIAGRAM SLS System Logic Semiconductor