SL74HCT241 Octal 3-State Noninverting Buffer/Line Driver/Line Receiver High-Performance Silicon-Gate CMOS The SL74HCT241 is identical in pinout to the LS/ALS241. The SL74HCT241 may be used as a level converter for interfacing TTL or NMOS outputs to High Speed CMOS inputs. This octal noninverting buffer/line driver/line receiver is designed to be used with 3-state memory address drivers, clock drivers, and other bus-oriented systems. The device has noninverting outputs and two output enables. Enable A is active-low and Enable B is active-high. • TTL/NMOS Compatible Input Levels • Outputs Directly Interface to CMOS, NMOS, and TTL • Operating Voltage Range: 4.5 to 5.5 V • Low Input Current: 1.0 µA ORDERING INFORMATION SL74HCT241N Plastic SL74HCT241D SOIC TA = -55° to 125° C for all packages PIN ASSIGNMENT LOGIC DIAGRAM FUNCTION TABLE Inputs PIN 20=VCC PIN 10 = GND Output Inputs Output Enable A A YA Enable B B YB L L L H L L L H H H H H H X Z L X Z X = don’t care Z = high impedance SLS System Logic Semiconductor SL74HCT241 MAXIMUM RATINGS * Symbol Parameter Value Unit -0.5 to +7.0 V VCC DC Supply Voltage (Referenced to GND) VIN DC Input Voltage (Referenced to GND) -1.5 to VCC +1.5 V DC Output Voltage (Referenced to GND) -0.5 to VCC +0.5 V DC Input Current, per Pin ±20 mA DC Output Current, per Pin ±35 mA ICC DC Supply Current, VCC and GND Pins ±75 mA PD Power Dissipation in Still Air, Plastic DIP+ SOIC Package+ 750 500 mW -65 to +150 °C 260 °C VOUT IIN IOUT Tstg Storage Temperature TL Lead Temperature, 1 mm from Case for 10 Seconds (Plastic DIP or SOIC Package) * Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. +Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C SOIC Package: : - 7 mW/°C from 65° to 125°C RECOMMENDED OPERATING CONDITIONS Symbol VCC VIN, VOUT Parameter DC Supply Voltage (Referenced to GND) DC Input Voltage, Output Voltage (Referenced to GND) TA Operating Temperature, All Package Types tr, t f Input Rise and Fall Time (Figure 1) Min Max Unit 4.5 5.5 V 0 VCC V -55 +125 °C 0 500 ns This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, VIN and VOUT should be constrained to the range GND≤(VIN or VOUT)≤VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open. SLS System Logic Semiconductor SL74HCT241 DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND) VCC Symbol Parameter Test Conditions Guaranteed Limit V 25 °C to -55°C ≤85 °C ≤125 °C Unit VIH Minimum HighLevel Input Voltage VOUT= VCC-0.1 V IOUT≤ 20 µA 4.5 5.5 2.0 2.0 2.0 2.0 2.0 2.0 V VIL Maximum Low Level Input Voltage VOUT= 0.1 V IOUT ≤ 20 µA 4.5 5.5 0.8 0.8 0.8 0.8 0.8 0.8 V VOH Minimum HighLevel Output Voltage VIN= VIH IOUT ≤ 20 µA 4.5 5.5 4.4 5.4 4.4 5.4 4.4 5.4 V VIN= VIH IOUT ≤ 6.0 mA 4.5 3.98 3.84 3.7 VIN = VIL IOUT ≤ 20 µA 4.5 5.5 0.1 0.1 0.1 0.1 0.1 0.1 VIN= VIL IOUT ≤ 6.0 mA 4.5 0.26 0.33 0.4 VOL Maximum LowLevel Output Voltage V IIN Maximum Input Leakage Current VIN=VCC or GND 5.5 ±0.1 ±1.0 ±1.0 µA IOZ Maximum three State Leakage Current Output in High-Impedance State VIN = VIL or VIH VOUT=VCC or GND 5.5 ±0.5 ±5.0 ±10.0 µA ICC Maximum Quiescent Supply Current (per Package) VIN=VCC or GND IOUT=0µA 5.5 4.0 40 160 µA Additional Quiescent VIN = 2.4 V, Any One Input VIN=VCC or GND, Other Inputs ≥-55°C 25°C to 125°C mA Supply Current IOUT=0µA 2.9 2.4 ∆ICC 5.5 NOTE: Total Supply Current = ICC + ∑∆ICC SLS System Logic Semiconductor SL74HCT241 AC ELECTRICAL CHARACTERISTICS (VCC=5.0 V ± 10%, CL=50pF,Input t r=t f=6.0 ns) Guaranteed Limit Symbol Parameter 25 °C to -55°C ≤85°C ≤125°C Unit tPLH, t PHL Maximum Propagation Delay, A to YA or B to YB (Figures 1 and 3) 23 29 35 ns tPLZ, t PHZ Maximum Propagation Delay, Output Enable to YA or YB (Figures 2 and 4) 30 38 45 ns tPZH, t PZL Maximum Propagation Delay, Output Enable to YA or YB (Figures 2 and 4) 26 33 39 ns tTLH, t THL Maximum Output Transition Time, Any Output (Figures 1 and 3) 12 15 18 ns Maximum Input Capacitance 10 10 10 pF Maximum Three-State Output Capacitance (Output in High-Impedance State) 15 15 15 pF CIN COUT Power Dissipation Capacitance (Per Enable Output) CPD Used to determine the no-load dynamic power consump tion: PD=CPDVCC2f+ICCVCC Figure 1. Switching Waveforms SLS System Logic Semiconductor Typical @25°C,VCC=5.0 V 55 pF Figure 2. Switching Waveforms SL74HCT241 Figure 3. Test Circuit Figure 4. Test Circuit EXPANDED LOGIC DIAGRAM (1/4 of the Device) SLS System Logic Semiconductor