SLS SL74LS164

SL74LS164
8-Bit Serial-Input/Parallel-Output
Shift Register
This 8-bit shift register features gated serial inputs and an
asynchronous reset. The gated serial inputs (A and B) permit complete
control over incoming data as a low at either (or both) input(s) inhibits
entry of the new data and resets the first flip flop to the low level at the
next clock pulse. A high level input enables the other input which will
then determine the state of the first flip-flop. Data at the serial inputs
may be changed while the clock is high or low, but only information
meeting the setup requirements will be entered clocking occurs or the
low-to-high level transition of the clock input. All inputs are diodeclamped to minimize transmission-line effects.
• Gated (Enable/Disable) Serial Inputs
• Fully Buffered Clock and Serial Inputs
• Asynchronous Clear
ORDERING INFORMATION
SL74LS164N Plastic
SL74LS164D SOIC
TA =0° to 70°C
for all packages
PIN ASSIGNMENT
LOGIC DIAGRAM
FUNCTION TABLE
Inputs
PIN 14 =VCC
PIN 7 = GND
Outputs
Reset
Clock
A1 A2
L
X
X X
QA QB ... QH
L
L ... L
H
X X
no change
H
H D
D QAn ... QGn
H
D H
D QAn ... QGn
H
L L
L QAn ... QGn
D = data input
X = don’t care
QAn - QGn = data shifted from the previous stage on a
rising edge at the clock input.
SLS
System Logic
Semiconductor
SL74LS164
MAXIMUM RATINGS *
Symbol
Parameter
Value
Unit
VCC
Supply Voltage
7.0
V
VIN
Input Voltage
7.0
V
VOUT
Output Voltage
5.5
V
Tstg
Storage Temperature Range
-65 to +150
°C
*
Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
Max
Unit
5.25
V
VCC
Supply Voltage
4.75
VIH
High Level Input Voltage
2.0
VIL
Low Level Input Voltage
0.8
V
IOH
High Level Output Current
-0.4
mA
IOL
Low Level Output Current
8.0
mA
TA
Ambient Temperature Range
0
+70
°C
Clock Frequency
0
25
MHz
tsu
Setup Time, A1 or A2 to Clock
15
ns
th
Hold Time, Clock to A1 or A2
5
ns
tw
Pulse Width, Clock
20
ns
tw
Pulse Width, Reset
20
ns
trec
Recovery Time
5
ns
fclock
V
DC ELECTRICAL CHARACTERISTICS over full operating conditions
Guaranteed Limit
Symbol
Parameter
Test Conditions
Min
Max
Unit
-1.5
V
VIK
Input Clamp Voltage
VCC = min, IIN = -18 mA
VOH
High Level Output Voltage
VCC = min, IOH = -0.4 mA
VOL
Low Level Output Voltage
VCC = min, IOL = 4 mA
0.4
VCC = min, IOL = 8 mA
0.5
VCC = max, VIN = 2.7 V
20
mA
VCC = max, VIN = 7.0 V
0.1
mA
-0.4
mA
-100
mA
27
mA
IIH
High Level Input Current
IIL
Low Level Input Current
VCC = max, VIN = 0.4 V
IO
Output Short Circuit Current
VCC = max, VO = 0 V
(Noote 1)
ICC
Supply Current
VCC = max (Note 2)
2.7
-20
V
V
Note 1: Not more than one output should be shorted at a time, and duration should not exceed one second.
SLS
System Logic
Semiconductor
SL74LS164
Note 2: ICC is measured with outputs open, serial inputs grouned, the clock input at 2.4 V, and a momentary
ground, then 4.5 V applied.
AC ELECTRICAL CHARACTERISTICS (TA=25°C, VCC = 5.0 V, CL = 15 pF, RL = 2 kΩ, t r =15
ns, tf = 6.0 ns)
Symbol
Parameter
Min
Max
Unit
tPLH
Propagation Delay Time, Clock to Q
27
ns
tPHL
Propagation Delay Time, Clock to Q
32
ns
tPHL
Propagation Delay Time, Reset to Q
36
ns
tsu
Setup Time, A1 or A2 to Clock
15
ns
th
Hold Time, Clock to A1 or A2
5
ns
tw
Pulse Width, Clock
20
ns
tw
Pulse Width, Reset
20
ns
Figure 1. Switching Waveforms
Figure 2. Switching Waveforms
NOTES A. CL includes probe and jig capacitance.
B. All diodes are 1N916 or 1N3064.
Figure 3. Switching Waveform
SLS
System Logic
Semiconductor
Figure 4. Test Circuit
SL74LS164
TIMING DIAGRAM
SLS
System Logic
Semiconductor