TECHNICAL DATA IN74LV164 8-BIT SERIAL-IN/PARALLEL-OUT SHIFT REGISTER The IN74LV164 is a low-voltage Si-gate CMOS device and is pin and function compatible with the IN74HC/HCT164. The IN74LV164 is an 8-bit edge-triggered shift register with serial data entry and an output from each of the eight stages. Data is entered serially through one of two inputs (DSA or DSB); either input can be used as an active HIGH enable for data entry through the other input. Both inputs must be connected together or an unused input must be tied HIGH. Data shifts one place to the right on each LOW-to-HIGH transition of the clock (CP) input and enters into Q0, which is the logical AND of the two data inputs (DSA, DSB ) that existed one set-up time prior to the rising clock edge. A LOW on the master reset (MR) input overrides all other inputs and clears the register asynchronously, forcing all outputs LOW. • • • • • N SUFFIX PLASTIC DIP 14 1 14 1 ORDERING INFORMATION IN74LV164N IN74LV164D IZ74LV164 PIN ASSIGNMENT DSA 1 14 V CC DSB 2 13 Q7 Q0 3 12 Q6 Q1 4 11 Q5 Q2 5 10 Q4 Q3 6 9 MR GND 7 8 CP LOGIC DIAGRAM 2 Q0 DATA 4 Plastic DIP SOIC chip TA = -40° to 125° C for all packages Outputs Directly Interface to CMOS, NMOS, and TTL Operating Voltage Range: 1.2 to 5.5 V Low Input Current: 1.0 µA, 0.1 µÀ at Ò = 25 °Ñ Output Current: 6 mA at VCC = 3.0 V; 12 mA at VCC = 4.5 V High Noise Immunity Characteristic of CMOS Devices 1 SERIAL DSA DATA 2 INPUTS DSB D SUFFIX SO Q1 5 Q2 6 Q3 10 Q 4 PARALLEL DATA OUTPUTS 11 Q 5 12 Q 6 CP 8 FUNCTION TABLE 13 Q 7 Inputs MR 9 PIN 14=VCC PIN 7 = GND Outputs MR CP DSA DSB Q0 Q1 ... Q7 L X X X L L … L H L L L Q0 ... Q6 H L H L Q0 ... Q6 H H L L Q0 ... Q6 H H H H Q0 ... Q6 H = high voltage level L = low voltage level X = don’t care INTEGRAL 1 IN74LV164 MAXIMUM RATINGS * Symbol VCC IIK * DC supply voltage Value Unit -0.5 to + 7.0 V 1 DC Input diode current ±20 mA 2 DC Output diode current ±50 mA DC Output source or sink current ±25 mA VCC current ±50 mA ±50 mA IOK * IO * Parameter 3 ICC IGND GND current PD Power dissipation per package: * Plastic DIP SO Tstg 4 mW 750 500 Storage Temperature TL -65 to +150 °C 260 °C Lead Temperature, 1.5 mm (Plastic DIP Package), 0.3 mm (SO Package) from Case for 4 Seconds * Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. * 1 VI < -0.5 V or VI > VCC + 0.5 V. * 2 VO < -0.5 V or VO > VCC + 0.5 V. * 3 -0.5 V < VO < VCC + 0.5 V. * 4 Derating - Plastic DIP: - 12 mW/°C from 70° to 125°C SO Package: : - 8 mW/°C from 70° to 125°C RECOMMENDED OPERATING CONDITIONS Symbol Parameter Min Max Unit 1.2 5.5 V VCC DC Supply Voltage VI Input Voltage 0 VCC V VO Output Voltage 0 VCC V TA Operating Temperature, All Package Types -40 +125 °C tr, t f Input Rise and Fall Time (Figure 1) 0 0 0 0 500 200 100 50 ns 1.0 V ≤ VCC < 2.0 V 2.0 V ≤ VCC < 2.7 V 2.7 V ≤ VCC < 3.6 V 3.6 V ≤ VCC ≤ 5.5 V This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, VIN and VOUT should be constrained to the range GND≤(VIN or VOUT)≤VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open. INTEGRAL 2 IN74LV164 DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND) Symbol Parameter Test VCC conditions V Guaranteed Limit 25°C to -40°C 85°C 125°C Unit min max min max min max VIH HIGH level input voltage 1.2 2.0 2.7 3.0 3.6 4.5 5.5 0.9 1.4 2.0 2.0 2.0 3.15 3.85 - 0.9 1.4 2.0 2.0 2.0 3.15 3.85 - 0.9 1.4 2.0 2.0 2.0 3.15 3.85 - V VIL LOW level input voltage 1.2 2.0 2.7 3.0 3.6 4.5 5.5 - 0.3 0.6 0.8 0.8 0.8 1.35 1.65 - 0.3 0.6 0.8 0.8 0.8 1.35 1.65 - 0.3 0.6 0.8 0.8 0.8 1.35 1.65 V VOH HIGH level output voltage VI = VIH or VIL IO = -100 µÀ 1.2 2.0 2.7 3.0 3.6 4.5 5.5 1.05 1.85 2.55 2.85 3.45 4.35 5.35 - 1.0 1.8 2.5 2.8 3.4 4.3 5.3 - 1.0 1.8 2.5 2.8 3.4 4.3 5.3 - V VI = VIH or VIL IO = -6.0 mÀ 3.0 2.48 - 2.40 - 2.20 - V VI = VIH or VIL IO = -12.0 mÀ 4.5 3.70 - 3.60 - 3.50 - V VI = VIH or VIL IO = 100 µÀ 1.2 2.0 2.7 3.0 3.6 4.5 5.5 - 0.15 0.15 0.15 0.15 0.15 0.15 0.15 - 0.2 0.2 0.2 0.2 0.2 0.2 0.2 - 0.2 0.2 0.2 0.2 0.2 0.2 0.2 V VI = VIH or VIL IO = 6.0 mÀ 3.0 - 0.33 - 0.4 - 0.5 V VI = VIH or VIL IO = 12.0 mÀ 4.5 - 0.40 - 0.55 - 0.65 V Input current VI = VCC or 0 V 5.5 - ±0.1 - ±1.0 - ±1.0 µÀ ICC Supply current VI =VCC or 0 V IO = 0 µÀ 5.5 - 8.0 - 80 - 160 µÀ ICC1 Supply current VI =VCC – 0.6 V 2.7 3.6 - 0.2 - 0.5 - 0.85 mÀ VOL II LOW level output voltage INTEGRAL 3 IN74LV164 AC ELECTRICAL CHARACTERISTICS (CL=50 pF, t r=t f= 2.5 ns, RL = 1 kΩ) Symbol Parameter tPHL, tPLH Propagation delay , CP to Qn Test VCC conditions V Guaranteed Limit 25°C to -40°C 85°C 125°C min max min max min max Unit VI = 0 V or V1 Figure 1 and 4 1.2 2.0 2.7 3.0 4.5 - 150 30 23 18 15 - 180 39 29 23 19 - 210 49 36 29 24 ns Propagation delay , MR to VI = 0 V or V1 Qn Figure 1 and 4 1.2 2.0 2.7 3.0 4.5 - 150 30 23 18 15 - 180 39 29 23 19 - 210 49 36 29 24 ns tw Pulse Width, CP or MR VI = 0 V or V1 Figure 1 1.2 2.0 2.7 3.0 4.5 100 28 21 17 14 - 130 34 25 20 17 - 160 41 30 24 20 - ns tsu Setup Time, DSA or DSB to CP VI = 0 V or V1 Figure 3 1.2 2.0 2.7 3.0 4.5 60 19 13 11 9 - 80 22 16 13 11 - 100 26 19 15 13 - ns th Hold Time, DSA or DSB to VI = 0 V or V1 CP Figure 3 1.2 2.0 2.7 3.0 4.5 50 5 5 5 5 - 50 5 5 5 5 - 50 5 5 5 5 - ns trec Recovery Time, MR to CP VI = 0 V or V1 Figure 2 1.2 2.0 2.7 3.0 4.5 70 15 11 9 8 - 100 19 14 11 10 - 130 24 18 14 12 - ns fmax Clock Frequency VI = 0 V or V1 Figure 1 and 4 1.2 2.0 2.7 3.0 4.5 - 2 16 22 27 32 - 1 14 19 24 27 - 1 12 16 20 24 MHz CI Input capacitance 5.0 - 7.0 - - - - pF CPD Power dissipation capacitance 5.5 - 80 - - - - pF tPHL INTEGRAL VI = 0 V or VCC 4 IN74LV164 tw tr CP tf 90% (1 ) 10% (2) VM MR V1 GND VM V1 (1) GND t PHL tw 1/fmax Q VOH ( 1) VM Q tPLH VOL t PHL V OH (1 ) (2) t rec VM V OL CP Figure 1. Switching Waveforms (2) V1 (1) VM GND Figure 2. Switching Waveforms TEST POINT VALID VM DSA or DSB (2 ) V1 (1 ) DEVICE UNDER TEST GND t su th RL (2 ) V1 CP VM OUTPUT * CL ( 1) GND * Includes all probe and jig capacitance Figure 3. Switching Waveforms Figure 4. Test Circuit Note: (1) (2) VM = 1.5 V at VCC = 2.7 V VM = 0.5 ⋅VCC at VCC =1.2 V, 2.0 V, 3.0 V, 4.5 V V1 = VCC at VCC =1.2 V, 2.0 V, 2.7 V, 4.5 V V1 = 2.7 V at VCC = 3.0 V TIMING DIAGRAM CP DSA DSB MR Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 INTEGRAL 5 IN74LV164 CHIP PAD DIAGRAM 06 08 1.1+ 0.03 09 07 10 05 11 04 12 03 14 01 02 13 Y (0,0) Chip marking LV164 1.71 + 0.03 X Location of marking (mm): left lower corner x= 0.960, y= 0.130. Chip thickness: 0.46 ± 0.02 (0.35 ± 0.02) mm. PAD LOCATION Location (left lower corner), mm Pad No Symbol 01 02 03 04 05 06 07 08 09 10 11 12 13 14 DSA DSB Q0 Q1 Q2 Q3 GND CP MR Q4 Q5 Q6 Q7 VCC X 1.172 1.486 1.486 1.486 1.486 1.486 0.978 0.440 0.127 0.127 0.127 0.127 0.127 0.635 Y 0.131 0.131 0.363 0.531 0.689 0.885 0.885 0.885 0.885 0.653 0.485 0.326 0.131 0.131 Pad size, mm 0.100 õ 0.100 0.100 õ 0.100 0.100 õ 0.100 0.100 õ 0.100 0.100 õ 0.100 0.100 õ 0.100 0.100 õ 0.100 0.100 õ 0.100 0.100 õ 0.100 0.100 õ 0.100 0.100 õ 0.100 0.100 õ 0.100 0.100 õ 0.100 0.100 õ 0.100 Note: Pad location is given as per passivation layer INTEGRAL 6