CXA1622M/P
Stereo Power Amplifier/Monaural BTL Power Amplifier
Description
The CXA1622M/P is a bipolar IC developed as
power amplifier for compact radio cassettes with
built-in pre-amplifier and power amplifier electrical
volume.
Features
• Use one channel in stereo mode
· EIAJ output=110 mW (Typ.), VCC=3
(CXA1622M)
· EIAJ output=450 mW (Typ.), VCC=6
(CXA1622P)
• BTL mode
· EIAJ output=320 mW (Typ.), VCC=3
(CXA1622M)
· EIAJ output=360 mW (Typ.), VCC=3
CXA1622M
16 pin SOP (Plastic)
CXA1622P
16 pin DIP (Plastic)
V, RL=8 Ω
V, RL=8 Ω
V, RL=8 Ω
V, RL=8 Ω
(CXA1622P)
• Built-in electrical volume
• Built-in ripple filter (ripple rejection 34.5 dB typ.)
• Selection between stereo power amplifier and
monaural BTL power amplifier is possible by
switching Pin 2.
Applications
Suitable for audio power amplifier for stereo and
monaural radios and power amplifier for radio
cassette and Walkman.
Structure
Bipolar silicon monolithic IC
Absolute Maximum Ratings (Ta=25 °C)
• Supply voltage
VCC
8
V
• Operating temperature Topr
–10 to +60
°C
• Storage temperature Tstg –65 to +150
°C
• Allowable power dissipation
PD 410 (CXA1622M) mW
1200 (CXA1622P) mW
Operating Conditions (Ta=25 °C)
• Supply voltage
• Stereo mode
1.8 V to 4.5 V (CXA1622M)
1.8 V to 7.0 V (CXA1622P)
• Monaural BTL mode 1.8 V to 4.5 V
(3 V recommended)
{
Power dissipation curve
PD-Power dissipation (mW)
Free air
CXA1622P
1000
500
CXA1622M
–30
–20
–10
0
10
20
30
40
50
60
70
Ta-Ambient temperature (°C)
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
—1—
E92121B79-TE
CXA1622M/P
Pin Description
Pin
No.
Symbol
Pin voltage
3V
6V
Equivalent circuit
Description
VCC
16
1, 16
IN1
IN2
1
11k
0
0
Input
—
—
1.5
3
Power amplifier NF.
Connected to time constant 4.7 µF.
0
0
Pre-amplifier GND
0
0
Power amplifier GND
1.5
3
Power amplifier output
2.72
5.43
3
6
7.5k
GND
3
NC
VCC
4
4, 13
NF1
NF2
13
4.7k
100k
GND
5, 12
6, 11
GND1
GND2
P-GND1
P-GND2
VCC
7, 10
OUT1
OUT2
7
10
100k
GND
VCC
8.5k
8
9
RIPPLE
8
73k
73k
90k
90k
VCC
—2—
Connected to time constant 10 µF
for ripple filter.
VCC
CXA1622M/P
Pin
No.
Symbol
Pin voltage
3V
6V
Equivalent circuit
Description
VCC
14
14
VOL
20k
0 to
1.25
0 to
1.25
Control gain with change in voltage
(0 to 1.25 V) to electrical volume
control pin.
1.25
1.25
Regulator pin
1.25
Mode selection SW
• BTL mode when open
• Stereo mode when connected to
GND
80k
GND
VCC
24k
15
REG
15
4k
VCC
REG
15k
2
SW
1.25
2
15k
Block Diagram, Pin Configuration, and Application Circuit
1) Stereo mode
GND
C3
10µ
+
C7
0.1µ
C5
3.3µ
+
C9
0.1µ
V1
3V
C10
220µ
+
16
15
14
13
12
11
10
OUT1
C12
220µ
VCC
OUT1
P GND1
GND
NF1
VOL
REG
IN1
+
IN1
C2
10µ
+
R1
50k
SP1
8
9
PRE+POWER1
REG
VOL
PRE+POWER2
RIPPLE
8
+
OUT2
7
P GND2
NC
C1
10µ
6
GND
5
NF2
4
+
IN2
3
SW
2
IN2
1
+
C4
3.3µ
C5
0.1µ
+
OUT2
C11
220µ
C8
10µ
SP2
8
GND
GND
—3—
CXA1622M/P
2) BTL mode
C2
10µ
+
C6
0.1µ
C4
3.3µ
+
C8
0.1µ
V1
3V
C9
220µ
+
16
15
14
12
11
VCC
OUT1
GND
NF1
13
P GND1
OUT+
VOL
IN1
REG
R1
50k
10
9
PRE+POWER1
IN
+
REG
VOL
C1
10µ
SP2
8
PRE+POWER2
+
C3
3.3µ
C5
0.1µ
RIPPLE
8
OUT2
7
P GND2
6
GND
5
NF2
4
NC
3
SW
2
IN2
1
+
OUT–
C7
10µ
GND
∗ The input signal enters the pre-amplifier with attenuation controlled with DC at Pin 14 and then it is amplified
by the approximately 30 dB (fixed) power amplifier.
∗ The state of Pin 2 can be used to select between stereo mode and monaural BTL mode.
The pre-power 1 and pre-power 2 output are positive phase output when Pin 2 is GND. Pre-power 2 is
inverse output of pre-power 1 output when Pin 2 is open.
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for
any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
—4—
No.
Test
—5—
Crosstalk L → R
Crosstalk R → L
14
level Rch
Residual noise
level Lch
Residual noise
factor Rch
Audio distortion
13
12
11
10
factor Lch
OFF ON
ON ON
OFF OFF OFF
OFF ON
ON OFF
OFF ON
EIAJ output Rch
8
Audio distortion
ON OFF
EIAJ output Lch
7
9
OFF ON
ON OFF
OFF ON
ON ON OFF
Attenuation Rch
Attenuation Lch
5
S3
S4
S5
S6
S7
S8
S9
S10 S11 S12 S13 S14
OFF OFF
ON
ON
ON OFF
OFF ON
ON OFF
OFF ON
ON OFF
OFF ON
ON OFF
OFF ON
ON OFF
OFF ON
ON
OFF OFF OFF ON OFF OFF ON OFF OFF OFF OFF OFF OFF OFF
S2
6
Channel balance
gain Rch
Audio voltage
gain Lch
Audio voltage
during no signal
Circuit current
4
3
2
1
S1
BIAS SW conditions
Upper : CXA1622M (VCC=3 V)
Lower : CXA1622P (VCC=6 V)
Test item
{
Typical conditions for each bias
Function block
Stereo mode
bias description
Input waveform and
Test point
V5
V4
V5
V4
V5
V4
V5
V4
V5
V4
V5
V4
I1
Output waveform and
350
90
V1=–20 dBm 1 kHz, RL=8 Ω
Output level where THD=10 %
Lch output level when Rch is input
V1=–40 dBm 1 kHz
Rch output level when Lch is input
V1=–40 dBm 1 kHz
max volume
Noise level during no signal at
max volume
Noise level during no signal at
Distortion factor when output is 50 mW
V1=–20 dBm 1 kHz, RL=8 Ω
Distortion factor when output is 50 mW
–60
–60
–65
–65
0.7
0.7
450
110
90
V1=–20 dBm 1 kHz, RL=8 Ω
450
110
350
4.3
V1=–20 dBm 1 kHz, RL=8 Ω
5.8
1.0
4.3
1.5
5.8
1.0
0
32.6
33.7
32.6
33.7
3.0
3.0
Typ.
1.5
–3
27
28
27
28
1.0
1.0
Min.
Output level where THD=10 %
max volume and half volume
Output level difference between
V1=–40 dBm 1 kHz
max volume and half volume
Output level difference between
V1=–40 dBm 1 kHz
L and R channel balance
V1=–40 dBm 1 kHz
V1=–40 dBm 1 kHz
Circuit current during no signal
description of test method
–56
–56
–60
–60
2.5
2.5
12
12
12
12
3
36
38
36
38
7.7
8.2
Max.
dBm
dBm
dBm
dBm
%
%
mW
mW
dB
dB
dB
dB
dB
mA
Unit
CXA1622M/P
Input point
No.
Test
Test item
EIAJ output
5
—6—
7
Residual noise level
factor
Audio distortion
Attenuation
4
6
Audio voltage gain
DC bias lag
Output
during no signal
Circuit current
3
2
1
S2
S3
S4
S5
S6
S7
S8
S9
BIAS SW conditions
S10 S11 S12 S13 S14
ON
OFF OFF
ON
ON
ON
OFF ON ON OFF OFF OFF ON OFF ON ON OFF ON ON OFF
S1
Upper : CXA1622M
Lower : CXA1622P
Typical conditions for each bias
Function block
BTL mode VCC=3 V
bias description
Input waveform and
Test point
Circuit current during no signal
V3
V3
V3
V3
V3
max volume
Noise level during no signal at
Distortion factor when output is 50 mW
–65
320
220
V1=–20 dBm 1 kHz, RL=8 Ω
360
260
5.0
1.0
Output level where THD=10 %
6.0
1.5
38
37
34
0
3
Typ.
30
Min.
V1=–20 dBm 1 kHz, RL=8 Ω
max volume and half volume
Output level difference between
V1=–40 dBm 1 kHz
V1=–40 dBm 1 kHz
|V3| Output DC bias lag
I1
Output waveform and
description of test method
–62
2.5
12
12
43
42
30
7
Max.
dBm
%
mW
dB
dB
mV
mA
Unit
CXA1622M/P
Input point
CXA1622M/P
Electrical Characteristics Test Circuit
C4
10µ
+
R2
25k
C3
10µ
+
R3
50k
V2
3V
C8
0.1µ
S7
+
S6
C6
3.3µ
C10 C11
0.1µ 220µ
+
V
C13
220µ
I1 A
R6
8
V4
S12
+
R1
25k
S8
S5
16
15
14
13
12
11
10
9
IN1
REG
VOL
NF1
GND
P GND1
OUT1
VCC
S9
S2
S11
R5
8
NC
NF2
GND
P GND2
OUT2
RIPPLE
S3
SW
C1
10µ
+
IN2
CXA1622M/P
1
2
3
4
5
6
7
8
Y3 Y
S18
+
V1
RC
+
C2
10µ
+
S4
C5
3.3µ
C7
0.1µ
+
+
S1
C12
220µ
C9
10µ
R4
8
V5 V
S13
S14
V6 V
GND
Notes on Operation
• Set print pattern to low impedance because Pins 6 and 11 are GND of power amplifier output stage.
• The value of the phase correction capacitance attached to Pins 7 and 10 varies slightly according to the
print pattern.
• Provide a large land for DIP type Pin 5 because it also serves as heat dissipation pin.
• Place the by-pass capacitor of VCC (Pin 9) as close to the pin as possible.
—7—
CXA1622M/P
Stereo output single mode
∗ Keep the by-pass capacitor close to the IC pins
C3
10µ +
C7
0.1µ
R1
50k
C5
3.3µ
+
∗ C9
C10
0.1µ 220µ
+
V1
3V
R3
8
C2
10µ
11
10
C12
220µ
9
VCC
VOL
12
OUT1
REG
13
P GND1
14
GND
15
NF1
16
IN1
+
+
IN1
NC
NF2
GND
P GND2
OUT2
RIPPLE
1
2
3
4
5
6
7
8
+
+
SW
C1
10µ
IN2
IN2
CXA1622M/P
+
C4
3.3µ
+
C5
0.1µ
C11
220µ
C8
10µ
R2
8
GND
Monaural output BTL mode
∗ Keep the by-pass capacitor close to the IC pins
REG
VOL
13
12
11
10
9
VCC
IN1
C4
3.3µ
OUT1
14
+
∗ C8
C9
0.1µ 220µ
+
V1
3V
P GND1
15
C5
0.1µ
GND
16
C1
10µ
R2
8
CXA1622M/P
IN2
SW
NC
NF2
GND
P GND2
OUT2
RIPPLE
+
IN
R1
50k
NF1
C2
10µ +
1
2
3
4
5
6
7
8
+
C3
3.3µ
C5
0.1µ
+
C7
10µ
GND
—8—
CXA1622M/P
When using internal IC electrical volume in BTL mode
VOL
11
10
9
VCC
REG
12
OUT1
IN1
13
P GND1
14
GND
15
C8
C9
0.1µ 220µ
+
V1
3V
C4
+ 3.3µ
R2
8
CXA1622M/P
IN2
SW
NC
NF2
GND
P GND2
OUT2
RIPPLE
+
IN
16
C1
10µ
C5
0.1µ
R1
50k
NF1
C2
10µ +
1
2
3
4
5
6
7
8
+
C3
3.3µ
+
C5
0.1µ
s.p
C7
10µ
GND
When using IC as fixed gain amplifier in BTL mode
Pin14 → GND (IC Gain MAX)
11
10
9
OUT1
VCC
VOL
12
P GND1
REG
13
GND
14
NF1
15
C1
10µ
R2
8
CXA1622M/P
IN2
SW
NC
NF2
GND
P GND2
OUT2
RIPPLE
+
+
16
C8
C9
0.1µ 220µ
+
V1
3V
C4
+ 3.3µ
IN1
+
IN
C5
0.1µ
C2
10µ
1
2
3
4
5
6
7
8
+
C3
3.3µ
C5
0.1µ
+
C7
10µ
GND
—9—
s.p
CXA1622M/P
BTL, Stereo Application Circuit
When using internal IC electrical volume
VOL
13
12
11
10
9
VCC
REG
C4
+ 3.3µ
OUT1
14
C8
C9
0.1µ 220µ
+
P GND1
15
C5
0.1µ
GND
16
IN1
R1
50k
NF1
C2
10µ +
IN Lch
+
CXA1622M/P
IN2
SW
NC
NF2
GND
P GND2
OUT2
RIPPLE
C1
10µ
1
2
3
4
5
6
7
8
+
C3
3.3µ
+
C5
0.1µ
R2
8
s.p
R2
8
s.p
C7
10µ
LINKAGE VOL.
VOL
12
11
10
9
VCC
REG
13
OUT1
14
C8
C9
0.1µ 220µ
+
V1
3V
P GND1
15
C5
0.1µ
C4
+ 3.3µ
GND
16
IN1
R1
50k
NF1
C2
10µ +
IN Rch
+
CXA1622M/P
IN2
SW
NC
NF2
GND
P GND2
OUT2
RIPPLE
C1
10µ
1
2
3
4
5
6
7
8
+
C3
3.3µ
C5
0.1µ
+
C7
10µ
GND
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for
any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
—10—
CXA1622M/P
BTL, Stereo Application Circuit
When using IC as fixed gain amplifier
Pin14 → GND (IC Gain Max)
11
10
9
VCC
VOL
12
OUT1
REG
13
P GND1
14
GND
15
NF1
16
C1
10µ
C9
220µ
+
CXA1622M/P
IN2
SW
NC
NF2
GND
P GND2
OUT2
RIPPLE
+
+
C8
0.1µ
C4
+ 3.3µ
IN1
+
IN Lch
C5
0.1µ
C2
10µ
1
2
3
4
5
6
7
8
+
C3
3.3µ
+
C5
0.1µ
R2
8
s.p
R2
8
s.p
C7
10µ
LINKAGE
C2
10µ
C8 C9
0.1µ 220µ
+
V1
3V
+
11
10
9
OUT1
VCC
VOL
12
P GND1
REG
13
GND
14
NF1
15
+
16
IN1
+
IN Rch
C5
0.1µ
C4
3.3µ
+
CXA1622M/P
IN2
SW
NC
NF2
GND
P GND2
OUT2
RIPPLE
C1
10µ
1
2
3
4
5
6
7
8
+
C3
3.3µ
C5
0.1µ
+
C7
10µ
GND
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for
any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
—11—
CXA1622M/P
Output vs Distortion 1 CXA1622P
Output vs Distortion 2 CXA1622M
stereo mode single-channel input
stereo mode single-channel input
10
VCC=1.8V
VCC=3V
Distortion factor [%]
Distortion factor [%]
10
VIN=–26dBm
fIN=1kHz
RL=8Ω
5
IN=–26dBm
VCC=4.5V
VCC=3V
VIN=–26dBm
fIN=1kHz
RL=8Ω
5
IN=–20dBm
IN=–26dBm
IN=–20dBm
0
10
100
VCC=1.8V
VCC=4.5V
0
1000
10
100
Output [mV]
1000
Output [mV]
Output vs Distortion factor 3
Output vs Distortion 4 CXA1622M BTL mode
CXA1622P BTL mode
10
VCC=1.8V
Distortion factor [%]
Distortion factor [%]
10
VCC=3V
VIN=–26dBm
fIN=1kHz
RL=8Ω
5
VCC=1.8V
VCC=3V
VIN=–26dBm
fIN=1kHz
RL=8Ω
5
IN=–20dBm
IN=–26dBm
0
0
10
100
1000
10
1000
Output [mV]
Output [mV]
Stereo mode frequency characteristics
BTL mode frequency characteristics
VIN=–40dBm VOL MAX VCC=3V
VIN=–40dBm VOL MAX VCC=3V
0
Output [dB]
0
Output [dB]
100
–10
output C=220µF
RL=8Ω
IN=–40dBm,1kHz is
assumed as 0dB
–20
10
100
1k
–10
IN=–40dBm,1kHz is
assumed as 0dB
–20
10k
10
100k
Input signal frequency [Hz]
100
1k
10k
Input signal frequency [Hz]
—12—
100k
CXA1622M/P
Package Outline
Unit : mm
CXA1622M
16PIN SOP (PLASTIC)
+ 0.4
1.85 – 0.15
+ 0.4
9.9 – 0.1
16
9
6.9
8
+ 0.1
0.2 – 0.05
1.27
0.45 ± 0.1
0.5 ± 0.2
1
7.9 ± 0.4
+ 0.3
5.3 – 0.1
0.15
+ 0.2
0.1 – 0.05
0.24 M
PACKAGE STRUCTURE
PACKAGE MATERIAL
SONY CODE
SOP-16P-L01
EIAJ CODE
SOP016-P-0300
EPOXY RESIN
LEAD TREATMENT
SOLDER PLATING
LEAD MATERIAL
COPPER ALLOY
PACKAGE MASS
0.2g
JEDEC CODE
16PIN DIP (PLASTIC)
16
+ 0.3
6.4 – 0.1
+ 0.4
19.2 – 0.1
+ 0.1
0.05
0.25 –
CXA1622P
7.62
9
1
0° to 15°
8
+ 0.4
3.7 – 0.1
Two kinds of package surface:
1.All mat surface type.
2.All mirror surface type.
3.0 MIN
0.5 MIN
2.54
0.5 ± 0.1
1.2 ± 0.15
PACKAGE STRUCTURE
PACKAGE MATERIAL
EPOXY RESIN
DIP-16P-01
LEAD TREATMENT
SOLDER PLATING
EIAJ CODE
DIP016-P-0300
LEAD MATERIAL
COPPER ALLOY
JEDEC CODE
Similar to MO-001-AE
PACKAGE MASS
1.0 g
SONY CODE
—13—