SONY CXA1875AM

CXA1875AP/AM
8-bit D/A Converter Compatible with I2C Bus
Description
The CXA1875AP/AM is developed as a 8-bit 5 ch
D/A converter compatible with I2C bus.
Features
• Serial control through I2C bus
• 4 built-in general purpose I/O ports (Digital I/O)
• I/O can be specified to respective ports
independently
• Selection of 8 slave addresses possible through
address select pins (3 pins)
Applications
I2C bus can control ICs that do not correspond to
I2C bus by connecting the DC control pins of them.
Structure
Bipolar silicon monolithic IC
16 pin DIP (Plastic)
16 pin SOP (Plastic)
Absolute Maximum Ratings (Ta=25°C)
• Supply voltage
VCC
7
• Operating temperature Topr –20 to +75
• Storage temperature Tstg –65 to +150
• Allowable power dissipation
PD
960
Operating Conditions
• Supply voltage
VCC
• Operating temperature Topr
5±0.5
–20 to +75
V
°C
°C
mW
V
°C
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
—1—
E94X27-TE
CXA1875AP/AM
Pin Configuration (Top View)
I2C bus
Slave address select pin
SW I/O
VCC
SCL
SDA
SAD2
SAD1
SAD0
SW3
SW2
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
SW1
SW0
DAC3
DAC2
DAC1
DAC0
GND
DAC4
SW I/O
DAC output
Block Diagram
SAD2 SAD1 SAD0
SW0-3
Open collector
Level
Conversion
Level
Conversion
LATCH
I2C BUS
SDA
SCL
Level
Conversion
I2C Decoder
Power
on
Reset
VCC
REG
GND
LATCH
LATCH
LATCH
LATCH
LATCH
DAC
DAC
DAC
DAC
DAC
AMP
AMP
AMP
AMP
AMP
DAC4
DAC3
DAC2
DAC1
DAC0
VCC
—2—
CXA1875AP/AM
Pin Description
No.
1
2
9
10
Symbol
SW1
SW0
SW2
SW3
14
15
SDA
SCL
Equivalent circuit
Description
I/O pin for general purpose I/O port
VILmax: 1.5 V
VIHmin: 3 V
VOLmax: 0.4 V
VCC
150
SDA I/O pin for I2C bus
4.5k
VCC
3
4
5
6
7
DAC4
DAC3
DAC2
DAC1
DAC0
8
GND
VCC
56
22k
D/A converter output pin
20k
20k
GND pin
VCC
11
12
13
SAD0
SAD1
SAD2
Slave address input pin
Input at positive logic
VILmax: 1.5 V
VIHmin: 3 V
VCC
150
4.5k
16
Power supply pin
VCC
Electrical Characteristics (Ta=25 °C, VCC=5 V)
D/A Converter Block
Test
No.
Item
Symbol
Test contents
circuit
1
Circuit current
ICC
1
DAC 0 to 4=127
2
3
4
Differential
linearity
Minimum output
voltage
Maximum
output voltage
5
Output current
6
Output
impedance
Min. Typ. Max. Unit
6
9
12
mA
–1
0
+1
LSB
DLE
1
V(DAC0 to 4=n+1)–V(DAC0 to 4=N)
×128–1
V(DAC0 to 4=191)–V(DAC0 to 4=63)
n=0 to 127
Vmin
1
DAC 0 to 4=0
0.1
0.4
0.7
V
Vmax
1
DAC 0 to 4=255
4.3
4.6
4.9
V
Iout
2
+1
mA
Z0
2
6
Ω
Current that can be flowed from Pins 3
to 7
V(–1 mA) –V(1 mA)
DAC 0 to 4=127,
2 mA
—3—
–1
0
3
CXA1875AP/AM
SW, SAD Pins
No.
7
8
9
10
11
Item
Low level input
voltage
High level input
voltage
Low level input
current
High level input
current
Low level input
voltage
Symbol
Text
circuit
Test contents
VIL
3
ST 0 to 3 an input voltage that turns to ‘0’
—
—
1.5
V
VIH
3
ST 0 to 3 an input voltage that turns to ‘1’
3.0
—
—
V
IIL
3
Input current when 0.4 V is applied
–10
0
+10
µA
IIH
3
Input current when 4.5 V is applied
–10
0
+10
µA
VOL
4
SW 0 to 3=1, Output voltage when 1 mA
flows in
0
0.2
0.4
V
Min. Typ. Max. Unit
I2C Bus Block Items (SDA, SCL)
No.
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
Item
High level input voltage
Low level input voltage
High level input current
Low level input current
Low level output voltage
At 3 mA flow to SDA (Pin 14)
Maximum flowing current
Input capacitance
Maximum clock frequency
Data change minimum waiting time
Data transfer start minimum waiting time
Low level clock pulse width
High level clock pulse width
Minimum start preparation waiting time
Minimum data hold time
Minimum data preparation time
Rise time
Fall time
Minimum stop preparation waiting time
Symbol
Min. Typ. Max. Unit
VIH
VIL
IIH
IIL
3.0
0
—
—
—
—
—
—
5.0
1.5
10
10
V
V
µA
µA
VOL
0
—
0.4
V
3
—
0
4.7
4.0
4.7
4.0
4.7
5
250
—
—
4.7
—
—
—
—
—
—
—
—
—
—
—
—
—
—
10
100
—
—
—
—
—
—
—
1
300
—
mA
pF
kHz
µs
µs
µs
µs
µs
µs
ns
µs
ns
µs
IOL
CI
fSCL
tBUF
tHD:STA
tLOW
tHIGH
tSU:STA
tHD:DAT
tSU:DAT
tR
tF
tSU:STO
I2C bus load conditions: Pull up resistance 4 kΩ (Connected to +5 V)
Load capacitance 200 pF (Connected to GND)
—4—
CXA1875AP/AM
I2C Bus Control Signal
SDA
tR
tBUF
tHD:STA
tF
SCL
tHD:STA
tLOW
tHD:DAT
S
P
tSU:STO
tSU:STA
tHIGH
tSU:DAT
P
Sr
Electrical Characteristics Test Circuit
Test circuit 1
Test circuit 2
I2C BUS
+5V
A
10µ
I2C BUS
5V
0.022µ
+5V
A
10µ
0.022µ
16
15
14
13
12
11
10
9
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
100p
100p 100p 100p
100p
100p
100p 100p 100p
V
Test circuit 4
I2C BUS
+5V
±1mA
V
Test circuit 3
100p
I2C BUS
0.022µ
A
10µ
V4
16
1
15
2
14
3
13
4
12
5
11
6
V4=
10
7
9
+5V
0.022µ
1mA
10µ
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
8
1.5 V (No. 7)
3.0 V (No. 8)
0.4 V (No. 9)
4.5 V (No. 10)
—5—
V
CXA1875AP/AM
Definition of I2C Register
<Slave address>
MSB
0
LSB
1
0
0
SAD2 SAD1 SAD0
R/W
0: SLAVE RECEIVER
R/W
1: SLAVE TRANSMITTER
SAD 0 to 2: 11 to 13 pin
0: "LOW"
1: "HIGH"
<Register table>
• With the IC reset all registers are reset to 0
• ∗: Not defined
• ×: Don’t care
• Sub address is auto incremented
• It can be used as a 6-bit D/A converter by setting the lower two bits of DAC 0-4 registors to 0, but take care
that the max. voltage of DA output will lower about 100 mV compared with the use of 8 bits.
Control Register
Sub address
BIT7
BIT6
BIT5
BIT4
BIT3
BIT2
BIT1
BIT0
× × × × × 000
REF
∗
∗
∗
SW3
SW2
SW1
SW0
× × × × × 001
DAC0 (8)
× × × × × 010
DAC1 (8)
× × × × × 011
DAC2 (8)
× × × × × 100
DAC3 (8)
× × × × × 101
DAC4 (8)
Status Register
BIT7
BIT6
BIT5
BIT4
BIT3
BIT2
BIT1
BIT0
PONRES
0
0
0
ST3
ST2
ST1
ST0
—6—
CXA1875AP/AM
<Registers>
REF
(1):
In brackets ( ) number of bits
Switches D/A converter reference voltage
0:Standardizes the inner regulator
1:Standardizes voltage resistance divided from VCC
SW0 to 3 (1):
Selects ON/OFF of Pins 1, 2, 9 and 10
(Each pin is the open collector output of NPN transistor)
0:OFF
1:ON
DAC0 to 4 (8):
Digital data input register of D/A converter
0:Output voltage turns to minimum
255:Output voltage turns to maximum
PONRES (1):
Detects POWER ON RESET
0:Master passes from the bus and is reset to 0 after having read this status
1:Set to 1 when power supply is turned on or when there has been a power dip
ST0 to 3
Detects and registers the voltage condition of Pins 1, 2, 9 and 10
0:1.5 V and below
1:3.0 V and above
Note) SW0 to 3 effective during 0
(1):
I2C Bus Signal
There are 2 signals in I2C bus. SDA (Serial DAta) and SCL (Serial Clock).
SDA is double-way.
• As SDA is double-way it has 3 state outputs, H, L and HIZ.
H
L
HIZ
L
• I2C transfer begins with Start Condition and ends with Stop Condition.
Stop Condition P
Start Condition S
SDA
SCL
—7—
CXA1875AP/AM
• I2C data write (Write from I2C controller to IC)
AT L during write
MSB
MSB
HIZ
LSB
HIZ
SDA
SCL
1
2
3
4
5
6
7
8
9
1
8
9
S
Address
MSB
LSB
1
8
DATA (n)
HIZ
9
1
ACK
9
8
ACK
9
DATA (n+1)
ACK
DATA (n+2)
HIZ
1
8
∗ The number of data that can be
transferred at a time is confined
to units of 8-bit that can be set
as required.
Sub Address is incremented
automatically.
9
P
DATA
Sub Address
HIZ
HIZ
8
ACK
ACK
DATA
ACK
• I2C data read (Read from IC to I2C controller)
At H during read
HIZ
SDA
SCL
1
6
7
8
9
7
1
8
9
P
S
Address
ACK
DATA
ACK
• Read timing
MSB
LSB
IC output SDA
SCL
9
1
2
3
4
5
6
7
8
9
Read timing
ACK
DATA
ACK
∗ Data read is performed with SCL rise.
—8—
CXA1875AP/AM
Application Circuit
I2C BUS
0.022µ
+5V
10k
10k
10µ
General purpose
output port
16
15
14
13
12
11
10
9
6
7
8
CXA1875AP/AM
1
2
3
4
5
10k
10k
2SC2785
D/A converter output
10k
General purpose
input port
10k
10k
2SC2785
Slave address for 4 CH and 4 DH
10k
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for
any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
—9—
CXA1875AP/AM
Unit : mm
CXA1875AP
16PIN DIP (PLASTIC)
16
+ 0.3
6.4 – 0.1
+ 0.4
19.2 – 0.1
+ 0.1
0.05
0.25 –
Package Outline
7.62
9
1
0° to 15°
8
Two kinds of package surface:
1.All mat surface type.
2.All mirror surface type.
3.0 MIN
0.5 MIN
+ 0.4
3.7 – 0.1
2.54
0.5 ± 0.1
1.2 ± 0.15
PACKAGE STRUCTURE
PACKAGE MATERIAL
EPOXY RESIN
DIP-16P-01
LEAD TREATMENT
SOLDER PLATING
EIAJ CODE
DIP016-P-0300
LEAD MATERIAL
COPPER ALLOY
JEDEC CODE
Similar to MO-001-AE
PACKAGE MASS
1.0 g
SONY CODE
CXA1875AM
16PIN SOP (PLASTIC)
+ 0.4
1.85 – 0.15
+ 0.4
9.9 – 0.1
16
9
6.9
+ 0.2
0.1 – 0.05
8
+ 0.1
0.2 – 0.05
1.27
0.45 ± 0.1
0.5 ± 0.2
1
7.9 ± 0.4
+ 0.3
5.3 – 0.1
0.15
0.24 M
PACKAGE STRUCTURE
PACKAGE MATERIAL
SONY CODE
SOP-16P-L01
EIAJ CODE
SOP016-P-0300
EPOXY RESIN
LEAD TREATMENT
SOLDER PLATING
LEAD MATERIAL
COPPER ALLOY
PACKAGE MASS
0.2g
JEDEC CODE
Purchase of Sony’s I2C components conveys a license under the Philips I2C Patent Rights to use these components in an I2C
system, provided that the system conforms to the I2C Standard Specifications as defined by Philips.
—10—