TI UCC38085

 SLUS488B − SEPTEMBER 2002 − REVISED MAY 2003
FEATURES
APPLICATIONS
D
D
D
D
D
D
D
D
D
D
D
D
D
Programmable Slope Compensation
Internal Soft-Start on the UCC38083/4
Cycle-by-Cycle Current Limiting
Low Start-Up Current of 120 µA and 1.5 mA
Typical Run Current
Single External Component Oscillator
Programmable from 50 kHz to 1 MHz
High-Current Totem-Pole Dual Output Stage
Drives Push-Pull Configuration with 1-A Sink
and 0.5-A Source Capability
Current Sense Discharge Transistor to
Improve Dynamic Response
Internally Trimmed Bandgap Reference
Undervoltage Lockout with Hysteresis
BASIC APPLICATION
V IN
POWER
TRANSFORMER
VDD
UCC3808x
CTRL
OUTA
RT
OUTB
CS
R SET
CF
The UCC38083/4/5/6 is a family of BiCMOS pulse width
modulation (PWM) controllers for dc-to-dc or off-line
fixed-frequency current-mode switching power
supplies. The dual output stages are configured for the
push-pull topology. Both outputs switch at half the
oscillator frequency using a toggle flip-flop. The dead
time between the two outputs is typically 110 ns, limiting
each output’s duty cycle to less than 50%.
The new UCC3808x family is based on the UCC3808A
architecture. The major differences include the addition
of a programmable slope compensation ramp to the CS
signal and the removal of the error amplifier. The current
flowing out of the ISET pin through an external resistor
is monitored internally to set the magnitude of the slope
V OUT compensation function. This device also includes an
internal discharge transistor from the CS pin to ground,
which is activated at each clock cycle after the pulse is
terminated. This discharges any filter capacitance on
the CS pin during each cycle and helps minimize filter
capacitor values and current sense delay.
The UCC38083 and the UCC38085 devices have the
turn-on/off thresholds of 12.5 V / 8.3 V, while the
UCC38084 and the UCC38086 has the turn-on/off
thresholds of 4.3 V / 4.1 V. Each device is offered in 8-pin
TSSOP (PW), 8-pin SOIC (D) and 8-pin PDIP (P)
packages.
GND
RT
DESCRIPTION
The UCC38083 and the UCC38084 devices have a
typical soft-start interval time of 3.5 ms while the
UCC38085 and the UCC38086 has less than 100 µs for
applications where internal soft-start is not desired.
RF
ISET
High-Efficiency Switch-Mode Power Supplies
Telecom dc-to-dc Converters
Point-of-Load or Point-of-Use Power Modules
Low-Cost Push-Pull and Half-Bridge
Applications
RS
FEEDBACK
UDG−01080
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
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Copyright  2002−2003, Texas Instruments Incorporated
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1
SLUS488B − SEPTEMBER 2002 − REVISED MAY 2003
ORDERING INFORMATION
THERMAL RESISTANCE TABLE
PACKAGE
θjc(°C/W)
SOIC−8 (D)
42
PDIP−8 (P)
50
32(2)
θja(°C/W)
84 to 160(1)
110(1)
232 to 257(2)
NOTES: (1) Specified θja (junction to ambient) is for devices mounted to 5-inch2 FR4 PC board
with one ounce copper where noted. When resistance range is given, lower values
are for 5 inch2 aluminum PC board. Test PWB was 0.062 inch thick and typically
used 0.635-mm trace widths for power packages and 1.3-mm trace widths for
non-power packages with a 100-mil x 100-mil probe land area at the end of each
trace.
(2). Modeled data. If value range given for θja, lower value is for 3x3 inch. 1 oz internal
copper ground plane, higher value is for 1x1-inch. ground plane. All model data
assumes only one trace for each non-fused lead.
TSSOP−8 (PW)
AVAILABLE OPTIONS
INTERNAL
SOFT START
TA
3.5 ms
−40°C to 85°C
75 µs
3.5 ms
0°C to 70°C
75 µs
UVLO
PACKAGES
ON
OFF
SOIC-8 (D)
PDIP-8 (P)
TSSOP-8 (PW)
12.5 V
8.3 V
UCC28083D
UCC28083P
UCC28083PW
4.3 V
4.1 V
UCC28084D
UCC28084P
UCC28084PW
12.5 V
8.3 V
UCC28085D
UCC28085P
UCC28085PW
4.3 V
4.1 V
UCC28086D
UCC28086P
UCC28086PW
12.5 V
8.3 V
UCC38083D
UCC38083P
UCC38083PW
4.3 V
4.1 V
UCC38084D
UCC38084P
UCC38084PW
12.5 V
8.3 V
UCC38085D
UCC38085P
UCC38085PW
4.3 V
4.1 V
UCC38086D
UCC38086P
UCC38086PW
† The D and PW packages are available taped and reeled. Add R suffix to device type, e.g. UCC28083DR (2500 devices
per reel) or UCC38083PWR (2000 devices per reel).
PW PACKAGE
(TOP VIEW)
D OR P PACKAGE
(TOP VIEW)
CTRL
ISET
CS
RT
2
1
8
2
7
3
6
4
5
VDD
OUTA
OUTB
GND
OUTA
VDD
CTRL
ISET
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1
2
3
4
8
7
6
5
OUTB
GND
RT
CS
SLUS488B − SEPTEMBER 2002 − REVISED MAY 2003
absolute maximum ratings over operating free-air temperature (unless otherwise noted)†
Supply voltage, VDD (IDD < 10 mA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 V
Supply current, IDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
Sink current (peak):
OUTA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0 A
OUTB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0 A
Source current (peak): OUTA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 A
OUTB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 A
Analog inputs:
CTRL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to VDD +0.3 V
CS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to VDD +0.3 V, not to exceed 6 V
RSET (minimum) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . >5 kΩ
RT (−100 µA < IRT < 100 µA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 2.0 V
Power dissipation at TA = 25°C (P package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 W
Power dissipation at TA = 25°C (D package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 650 mW
Power dissipation at TA = 25°C (PW package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400 mW
Junction operating temperature, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −55°C to 150°C
Storage temperature, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
Lead temperature (soldering 10 seconds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltages are with respect to GND.
Currents are positive into, and negative out of the specified terminal.
electrical characteristics over recommended operating virtual junction temperature range,
VDD = 10 V (See Note 1),1-µF capacitor from VDD to GND, RT = 165 kΩ, RF = 1 kΩ, CF = 220 pF,
RSET = 50 kΩ, TA = −40°C to 85°C for UCC2808x, TA = 0°C to 70°C for UCC3808x, TA = TJ
(unless otherwise noted)
overall
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
Start-up current
VDD < UVLO start threshold voltage
120
200
µA
Supply current
CTRL = 0 V,
See Note 1
1.5
2.5
mA
MIN
TYP
MAX
CS = 0 V,
undervoltage lockout
PARAMETER
TEST CONDITIONS
UCC38083/5
Start threshold voltage
Minimum operating voltage
after start
Hysteresis voltage
11.5
12.5
13.5
UCC38084/6
See Note 1
4.1
4.3
4.5
UCC38083/5
7.6
8.3
9.0
UCC38084/6
3.9
4.1
4.3
UCC38083/5
3.5
4.2
5.1
UCC38084/6
0.1
0.2
0.3
UNITS
V
oscillator
MIN
TYP
MAX
UNITS
Frequency
PARAMETER
2 x f(OUTA)
TEST CONDITIONS
180
200
220
kHz
Voltage amplitude
See Note 2
1.4
Oscillator fall time (dead time)
RT pin voltage
1.2
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1.5
1.6
V
110
220
ns
1.5
1.6
V
3
SLUS488B − SEPTEMBER 2002 − REVISED MAY 2003
electrical characteristics over recommended operating virtual junction temperature range,
VDD = 10 V (See Note 1),1-µF capacitor from VDD to GND, RT = 165 kΩ, RF = 1 kΩ, CF = 220 pF,
RSET = 50 kΩ, TA = −40°C to 85°C for UCC2808x, TA = 0°C to 70°C for UCC3808x, TA = TJ
(unless otherwise noted)
current sense
PARAMETER
TEST CONDITIONS
Gain
See Note 3
Maximum input signal voltage
CTRL = 5 V,
See Note 4
CS to output delay time
CTRL = 3.5 V,
0 mV ≤ CS ≤ 600 mV
CS = 0.5 V,
See Note 5
RT = 2.0 V,
Source current
MIN
TYP
MAX
1.9
2.2
2.5
0.47
0.52
0.57
V
100
200
ns
−200
Sink current
Overcurrent threshold voltage
CTRL to CS offset voltage
UNITS
V/V
nA
3
7
12
mA
0.70
0.75
0.80
V
CS = 0 V, 25°C
0.55
0.70
0.90
V
CS = 0 V
0.37
0.70
1.10
V
MIN
TYP
MAX
UNITS
48%
49%
50%
pulse width modulation
PARAMETER
TEST CONDITIONS
Maximum duty cycle
Measured at OUTA or OUTB
Minimum duty cycle
CTRL = 0 V
0%
output
PARAMETER
TEST CONDITIONS
Low-level output voltage (OUTA or OUTB)
MIN
TYP
MAX
0.5
1.0
0.5
1.0
High-level output voltage (OUTA or OUTB)
IOUT = 100 mA
IOUT = −50 mA,
Rise time
CLOAD = 1 nF
25
60
Fall time
CLOAD = 1 nF
25
60
MIN
TYP
MAX
(VDD − VOUT), See Note 6
UNITS
V
ns
soft-start
PARAMETER
TEST CONDITIONS
UNITS
OUTA/OUTB soft-start interval time,
UCC38083/4
CTRL = 1.8 V,
CS = 0 V,
Duty cycle from 0 to full
1.3
3.5
8.5
ms
OUTA/OUTB soft-start interval time,
UCC38085/6
CTRL = 1.8 V,
CS = 0 V,
Duty cycle from 0 to full
30
75
110
µs
TEST CONDITIONS
MIN
TYP
MAX
UNITS
IRAMP, peak
ISET, peak = 30 µA, Full duty cycle
NOTE 1: For UCCx8083/5, set VDD above the start threshold before setting to 10 V.
NOTE 2: Measured at ISET pin.
DV CTRL
NOTE 3: Gain is defined by A +
, 0 ≤ VCS ≤ 0.4 V.
DV
125
150
175
µA
slope compensation
PARAMETER
CS
NOTE 4: Measured at trip point of latch with CS ramped from 0.4 V to 0.6 V.
NOTE 5: This internal current sink on the CS pin is designed to discharge and external filter capacitor. It is not intended to be a dc sink path.
NOTE 6: Not 100% production tested. Ensured by design and also by the rise time test.
4
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SLUS488B − SEPTEMBER 2002 − REVISED MAY 2003
functional block diagram
Soft Start and Fault Latch
CTRL
1
S
Iss
Bias/UVLO
VREF
Q
0.5V
Slope Circuit
ISLOPE
8
R
Vdd−1
VDD
S
CT
+
R
Css
ISET
Q
I SLOPE =
5 x I SET
2
CS Circuitry
0.75V
PWM Comparator/Latch
Output Driver
7
OUTA
80 kΩ
S
60 kΩ
0.5V
CS
Q
Q
T
R
0.3 V
Q
3
6
OUTB
Oscillator
1.5V
1.5V
S
Q
I CT
R
RT
4
5
CT
0.2V
GND
UDG−01081
Terminal Functions
TERMINAL
NAME
PACKAGE
I/O
DESCRIPTION
D OR P
CS
3
I
The current-sense input to the PWM comparator, the cycle-by-cycle peak current comparator, and the
overcurrent comparator. The overcurrent comparator is only intended for fault sensing. Exceeding the
overcurrent threshold causes a soft-start cycle. An internal MOSFET discharges the current-sense filter
capacitor to improve dynamic performance of the power converter.
CTRL
1
I
Error voltage input to PWM comparator.
GND
5
−
Reference ground and power ground for all functions. Due to high currents, and high-frequency operation
of the IC, a low-impedance circuit board ground plane is highly recommended.
Current selection for slope compensation.
ISET
2
I
OUTA
7
O
OUTB
6
O
RT
4
I
Programs the oscillator.
VDD
8
I
Power input connection.
Alternating high-current output stages.
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5
SLUS488B − SEPTEMBER 2002 − REVISED MAY 2003
detailed pin descriptions
CTRL: The error voltage is typically generated by a secondary-side error amplifier and transmitted to the
primary-side referenced UCC3808x by means of an opto-coupler. CTRL has an internal divider ratio of 0.45 to
maintain a usable range with the minimum VDD of 4.1 V. The UCC38083/UCC38084 family features a built-in
full-cycle soft start while the UCC38085/6 does not.
For the UCC38083/4, soft-start is implemented as a clamp at the input to the PWM comparator. This causes
the output pulses to start near 0% duty cycle and increase until the clamp exceeds the CTRL voltage.
ISET: Program the slope compensation current ramp by connecting a resistor, RSET, from ISET to ground. The
voltage of the ISET pin tracks the 1.5-V internal oscillator ramp, as shown in Figure 1.
V(CS)
VDD
I RAMP, peak = 5 x ISET, peak
IRAMP
10k
I SET
RSET
UCC38083
VDD
1 CTRL
8
2 ISET
OUTA
7
3 CS
OUTB
6
4 RT
GND
5
ISET
1uF
OUTA
RF
1k
I RAMP
RT
220pF
165k
OUTB
Figure 1. Full Duty Cycle Output
The compensating current source, ISLOPE, at the CS pin is proportional to the ISET current, according to the
relation:
I
SLOPE
+5
I
SET
(1)
The ramping current due to ISLOPE develops a voltage across the effective filter impedance that is normally
connected from the current sense resistor to the CS input. In order to program a desired compensating slope
with a specific peak compensating ramp voltage at the CS pin, use the RSET value in the following equation:
RSET + V
Where V
OSC(peak)
OSC(peak)
5 RF
ǒRAMP VOLTAGE
Ǔ
HEIGHT
(2)
+ 1.5 V
Notice that the PWM Latch drives an internal MOSFET that will discharge an external filtering capacitor on the
CS pin. Thus, ISLOPE will appear to terminate when the PWM comparator or the cycle-by-cycle current limit
comparator sets the PWM latch. The actual compensating slope is not affected by premature termination of the
switching cycle.
6
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SLUS488B − SEPTEMBER 2002 − REVISED MAY 2003
detailed pin descriptions (continued)
OUTA and OUTB: Alternating high-current output stages. Both stages are capable of driving the gate of a power
MOSFET. Each stage is capable of 500-mA peak-source current, and 1-A peak-sink current.
The output stages switch at half the oscillator frequency, in a push-pull configuration. When the voltage on the
internal oscillator capacitor is rising, one of the two outputs is high, but during fall time, both outputs are off. This
dead time between the two outputs, along with a slower output rise time than fall time, ensures that the two
outputs cannot be on at the same time. This dead time is typically 110 ns.
The high-current output drivers consist of MOSFET output devices, which switch from VDD to GND. Each output
stage also provides a very low impedance to overshoot and undershoot. This means that in many cases,
external Schottky clamp diodes are not required.
RT: The oscillator programming pin. The oscillator features an internal timing capacitor. An external resistor,
RT, sets a current from the RT pin to ground. Due to variations in the internal CT, nominal VRT of 1.5 V can vary
from 1.2 V to 1.6 V
Selecting RT as shown programs the oscillator frequency:
RT +
1
28.7
ǒ
1 * 2.0
10 −12 f OSC
Ǔ
10 −7
(3)
where fOSC is in Hz, resistance in Ω. The recommended range of timing resistors is between 25 kΩ and 698 kΩ.
For best performance, keep the timing resistor lead from the RT pin to GND (pin 5) as short as possible.
1.5 V
I
1.5 V
I
RT
S
Q
CT
R
OSCILLATOR
4
0.2 V
CT
R
OUTPUT
T
Approximate Frequency +
28.7
10 −12
1
R T ) ǒ2.0
10 −7Ǔ
UDG−01083
Figure 2. Block Diagram for Oscillator
VDD: The power input connection for this device. Although quiescent VDD current is very low, total supply
current may be higher, depending on OUTA and OUTB current, and the programmed oscillator frequency. Total
VDD current is the sum of quiescent VDD current and the average OUT current. Knowing the operating
frequency and the MOSFET gate charge (QG), average OUT current can be calculated from:
I
OUT
+Q
G
f OSC
(4)
where f is the oscillator frequency.
To prevent noise problems, bypass VDD to GND with a ceramic capacitor as close to the chip as possible along
with an electrolytic capacitor. A 1-µF decoupling capacitor is recommended.
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7
SLUS488B − SEPTEMBER 2002 − REVISED MAY 2003
APPLICATION INFORMATION
The following application circuit shows an isolated 12-VIN to 2.5 VOUT push-pull converter with scalable output
power (20 W to 200 W). Note that the pinout shown is for SOIC-8 and PDIP-8 packages.
typical application
V O= 2.2 V TO 3.3 V
ADJUSTABLE
VIN = 12 V
+/−20%V
SR
DRIVE
1 µF
8
VDD
4.7Ω
7 OUTA
RT 4
UCC3808x
4.7Ω
6
6 OUTB
RF 1 kΩ
RS
3 CS
CTRL 1
GND
ISET
5
2
CF
220 pF
5
165
kΩ
4
1
2
3
TL431
RT
UDG−01084
8
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SLUS488B − SEPTEMBER 2002 − REVISED MAY 2003
APPLICATION INFORMATION
operational waveforms
Figure 3 illustrates how the voltage ramp is effectively added to the voltage across the current sense element
VCS, to implement slope compensation.
OUTA
OUTB
VRS
ADDED
RAMP
VOLTAGE
VCS, Pin 3
UDG−01085
Figure 3. Typical Slope Compensation Waveforms at 80% Duty Cycle
In Figure 3, OUTA and OUTB are shown at a duty cycle of 80%, with the associated voltage VRS across the
current sense resistor of the primary push-pull power MOSFETs. The current flowing out of CS generates the
ramp voltage across the filter resistor RF that is positioned between the power current sense resistor and the
CS pin. This voltage is effectively added to VRS to provide slope compensation at VCS, pin 3. A capacitor CF
is also recommended to filter the waveform at CS.
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9
SLUS488B − SEPTEMBER 2002 − REVISED MAY 2003
layout considerations
To prevent noise problems, bypass VDD to GND with a ceramic capacitor as close to the chip as possible along
with an electrolytic capacitor. A 1-µF decoupling capacitor is recommended.
Use a local ground plane near the small signal pins (CTRL, ISET, CS and RT) of the IC for shielding. Connect
the local ground plane to the GND pin with a single trace. Do not extend the local ground plane under the power
pins (VDD, OUTA, OUTB and GND). Instead, use signal return traces to the GND pin for ground returns on the
side of the integrated circuit with the power pins.
For best performance, keep the timing resistor lead from RT pin (pin 4) to GND (pin 5) as short as possible.
special layout considerations for the TSSOP package
Due to the different pinout and smaller lead pitch of the TSSOP package, special attention must be paid to
minimize noise problems. The pinout is different because the device had to be rotated 90° to fit into the smaller
TSSOP package.
For example, the two output pins are now on opposite sides of the package. The traces should not run under
the package together as they will couple switching noise into analog pins.
Another common problem is when RT and OUTB (pins 6 and 8) are routed together for some distance even
though they are not immediate side by side pins. Because of this, when OUTB rises, a voltage spike of upto
400 mV can couple into the RT. This spike causes the internal charge current into CT to be turned off
momentarily resulting in lower duty cycle. It is also important that note that the RT pin voltage cannot be
stabilized with a capacitor. The RT pin is just a dc voltage to program the internal CT. Instead, keep the OUTB
and RT runs short and far from each other and follow the printed wiring board layout suggestions above to fix
the problem.
reference design
A reference design is discussed in 50-W Push-Pull Converter Reference Design Using the UCC38083, TI
Literature Number SLUU135. This design controls a push-pull synchronous rectified topology with input range
of 18 V to 35 V (24 nominal) and 3.3-V output at 15 A. The schematic is shown in Figure 5 and the board layout
for the reference design is shown in Figure 4. Refer to the document for further details.
Figure 4. Reference Design Layout
10
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VCC
See Note 2
2OUT
1OUT
REG_OUT
2IN
1IN
GND
REG_IN
3
1
4
2
Note 1. C28, R25, and D12 accelerate the control to the secondary side feedback at start-up and prevent output voltage overshoot.
Note 2. Components used for the UCC38085 only.
+
5
7
8
6
+
+
SLUS488B − SEPTEMBER 2002 − REVISED MAY 2003
APPLICATION INFORMATION
Figure 5. Reference Design Schematic
11
SLUS488B − SEPTEMBER 2002 − REVISED MAY 2003
TYPICAL CHARACTERISTICS
OSCILLATOR FREQUENCY
vs
TEMPERATURE
OSCILLATOR FREQUENCY
vs
TIMING RESISTANCE
220
1200
215
T = 85°C
VDD = 15 V
1000
RT = 165 kΩ″
RF= 1 kΩ
CF = 220 kΩ
RSET = 50 kΩ
Frequency − kHz
800
Frequency − kHz
210
T = 25°C
VDD = 10 V
600
400
205
200
195
190
200
T = 40°C
VDD = 6 V
185
180
0
10
100
−50
1000
0
25
50
75
100
125
Temperature − °C
RT − Timing Resistance − kΩ
Figure 6
Figure 7
IDD
vs
OSCILLATOR FREQUENCY, (NO LOAD)
IDD
vs
OSCILLATOR FREQUENCY, 1 nF LOAD
25
12
VDD = 14 V
10
20
8
IDD − mA
15
IDD − mA
−25
VDD = 10 V
6
10
VDD = 14 V
VDD = 10 V
VDD = 6 V
4
VDD = 6 V
5
2
0
0
10
12
100
1000
10
100
Frequency − kHz
Frequency − kHz
Figure 8
Figure 9
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1000
SLUS488B − SEPTEMBER 2002 − REVISED MAY 2003
TYPICAL CHARACTERISTICS
DEAD TIME
vs
TIMING RESISTANCE OVER VDD
DEAD TIME
vs
TEMPERATURE
200
160
180
160
VDD = 6 V*
T = 85°C
T = 25°C
RT = 165 kΩ″
RF= 1 kΩ
CF = 220 kΩ
RSET = 50 kΩ
140
120
Dead Time − ns
VDD = 10 V
Dead Time − ns
VDD = 6 V*
140
120
100
VDD = 14 V
80
60
VDD = 14 V
T = −40°C
100
80
60
40
40
20
20
* UCCx8084/6, only
0
0
10
1000
100
−50
−25
0
25
Figure 10
100
125
Figure 11
CONTROL TO CS OFFSET
vs
TEMPERATURE
RAMP HEIGHT
vs
VDD
0.6
2.0
TA = 25°C
1.8
(OC Clamped)
RSET = 10 Ω
0.5
1.6
VCS = 0.40 V
1.4
RSET = 18 Ω
0.4
VPK(cs) − V
VCTRL − Control Voltage − V
75
50
Temperature − °C
RT − Timing Resistance − kΩ
1.2
1.0
0.8
0.3
0.2
0.6
RSET = 50 Ω
0.4
VCS = 0 V
0.1
RSET = 100 Ω
0.2
0
0.0
−50
−25
0
25
50
75
100
125
Temperature − °C
0
10
5
15
VDD − Volts
Figure 13
Figure 12
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13
SLUS488B − SEPTEMBER 2002 − REVISED MAY 2003
TYPICAL CHARACTERISTICS
RAMP HEIGHT
vs
RT
RAMP HEIGHT
vs
TEMPERATURE
0.7
0.6
RSET = 10 Ω
TA = 25°C
0.6
0.5
(OC Clamped)
VPK(cs) − V
0.4
VPK(cs) − V
RSET = 10 Ω
0.5
(OC Clamped)
RSET = 18 Ω
0.3
0.4
0.3
0.2
0.2
RSET = 50 Ω
RSET = 18 Ω
RSET = 50 Ω
0.1
0.1
RSET = 100 Ω
RSET = 100 Ω
0
0.0
100
10
1000
−50
−25
0
25
50
75
100
125
Temperature − °C
RT − kΩ
Figure 14
Figure 15
SOFT START
vs
TEMPERATURE
SOFT START
vs
TEMPERATURE
6
100
UCCx8085 AND UCCx8086
UCCx8083 AND UCCx8084
95
90
Soft Start Internal − µs
Soft Start Internal − ms
5
4
3
2
85
80
75
70
65
60
1
55
0
−50
50
−25
0
25
50
75
100
125
Temperature −°C
−25
0
25
50
Temperature − °C
Figure 16
14
−50
Figure 17
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75
100
125
SLUS488B − SEPTEMBER 2002 − REVISED MAY 2003
TYPICAL CHARACTERISTICS
CS TO OUTX DELAY TIME
vs
TEMPERATURE
150
140
CS Prop Delay − ns
130
120
110
100
90
80
70
60
50
−50
−25
0
25
50
75
100
125
Temperature − °C
Figure 18
RELATED PRODUCTS
UCC3808, 8-Pin Low Power Current Mode Push-Pull PWM, (SLUS168)
UCC3808A, 8-Pin Low-Power Current-Mode Push-Pull PWM, (SLUS456)
UCC3806, Low Power, Dual Output, Current Mode PWM Controller, (SLUS272)
Table 1. 8-Pin Push-Pull PWM Controller Family Feature Comparison
UVLO On
UVLO Off
CS
Discharge FET
Error
Amplifier
Programmable
Slope
Compensation
Internal
Softstart
12.5 V
8.3 V
Yes
No
Yes
Yes
UCC38084
4.3 V
4.1 V
Yes
No
Yes
Yes
UCC38085
12.5 V
8.3 V
Yes
No
Yes
No
UCC38086
4.3 V
4.1 V
Yes
No
Yes
No
UCC3808A−1
12.5 V
8.3 V
Yes
Yes
No
Yes
UCC3808A−2
4.3 V
4.1 V
Yes
Yes
No
Yes
UCC3808−1
12.5 V
8.3 V
No
Yes
No
Yes
UCC3808−2
4.3 V
4.1 V
No
Yes
No
Yes
Part Number
UCC38083
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15
SLUS488B − SEPTEMBER 2002 − REVISED MAY 2003
MECHANICAL DATA
D (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
8 PINS SHOWN
0.020 (0,51)
0.014 (0,35)
0.050 (1,27)
8
0.010 (0,25)
5
0.008 (0,20) NOM
0.244 (6,20)
0.228 (5,80)
0.157 (4,00)
0.150 (3,81)
Gage Plane
1
4
0.010 (0,25)
0°− 8°
A
0.044 (1,12)
0.016 (0,40)
Seating Plane
0.010 (0,25)
0.004 (0,10)
0.069 (1,75) MAX
PINS **
0.004 (0,10)
8
14
16
A MAX
0.197
(5,00)
0.344
(8,75)
0.394
(10,00)
A MIN
0.189
(4,80)
0.337
(8,55)
0.386
(9,80)
DIM
4040047/E 09/01
NOTES: A.
B.
C.
D.
16
All linear dimensions are in inches (millimeters).
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15).
Falls within JEDEC MS-012
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SLUS488B − SEPTEMBER 2002 − REVISED MAY 2003
MECHANICAL DATA
P (PDIP)
PLASTIC DUAL-IN-LINE
0.400 (10,60)
0.355 (9,02)
8
5
0.260 (6,60)
0.240 (6,10)
1
4
0.070 (1,78) MAX
0.325 (8,26)
0.300 (7,62)
0.020 (0,51) MIN
0.015 (0,38)
Gage Plane
0.200 (5,08) MAX
Seating Plane
0.010 (0,25) NOM
0.125 (3,18) MIN
0.100 (2,54)
0.021 (0,53)
0.015 (0,38)
0.430 (10,92)
MAX
0.010 (0,25) M
4040082/D 05/98
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-001
For the latest package information, go to http://www.ti.com/sc/docs/package/pkg_info.htm
www.ti.com
17
SLUS488B − SEPTEMBER 2002 − REVISED MAY 2003
MECHANICAL DATA
PW (R-PDSO-G**)
PACKAGE
PLASTIC SMALL-OUTLINE
14 PINS SHOWN
0,30
0,19
0,65
14
0,10 M
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°−ā 8°
A
0,75
0,50
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,10
8
14
16
20
24
28
A MAX
3,10
5,10
5,10
6,60
7,90
9,80
A MIN
2,90
4,90
4,90
6,40
7,70
9,60
DIM
4040064/F 01/97
NOTES:A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0,15.
Falls within JEDEC MO-153
For the latest package information, go to http://www.ti.com/sc/docs/package/pkg_info.htm
18
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