TI UCC2808-2

UCC1808-1/-2
UCC2808-1/-2
UCC3808-1/-2
Low Power Current Mode Push-Pull PWM
FEATURES
DESCRIPTION
• 130µA Typical Starting Current
The UCC3808 is a family of BiCMOS push-pull, high-speed, low power,
pulse width modulators. The UCC3808 contains all of the control and drive
circuitry required for off-line or DC-to-DC fixed frequency current-mode
switching power supplies with minimal external parts count.
• 1mA Typical Run Current
• Operation to 1MHz
• Internal Soft Start
The UCC3808 dual output drive stages are arranged in a push-pull configuration. Both outputs switch at half the oscillator frequency using a toggle
flip-flop. The dead time between the two outputs is typically 60ns to 200ns
depending on the values of the timing capacitor and resistors, thus limits
each output stage duty cycle to less than 50%.
• On Chip Error Amplifier With 2MHz
Gain Bandwidth Product
• On Chip VDD Clamping
• Dual Output Drive Stages In Push-Pull The UCC3808 family offers a variety of package options temperature range
options, and choice of undervoltage lockout levels. The family has UVLO
Configuration
thresholds and hysteresis options for off-line and battery powered systems.
• Output Drive Stages Capable Of
Thresholds are shown in the table below.
500mA Peak Source Current, 1A
Part Number
Turn on Threshold
Turn off Threshold
Peak Sink Current
UCCx808-1
UCCx808-2
12.5V
4.3V
8.3V
4.1V
BLOCK DIAGRAM
FB
COMP
CS
2
1
3
OVERCURRENT
COMPARATOR
PEAK CURRENT
COMPARATOR
8
VDD
7
OUTA
6
OUTB
5
GND
14V
0.75V
0.5V
2.0V
2.2V
VDD OK
OSCILLATOR
S
0.8V
PWM
COMPARATOR
Q
R
PWM
LATCH
1.2R
VDD–1V
Q
S
S
Q
Q
R
R
T
Q
VDD
0.5V
R
SOFT START
VOLTAGE
REFERENCE
SLOPE = 1V/ms
4
RC
UDG-99076
04/99
UCC1808-1/-2
UCC2808-1/-2
UCC3808-1/-2
ABSOLUTE MAXIMUM RATINGS
CONNECTION DIAGRAM
Supply Voltage (IDD ≤ 10mA) . . . . . . . . . . . . . . . . . . . . . . . 15V
Supply Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20mA
OUTA/OUTB Source Current (peak) . . . . . . . . . . . . . . . . –0.5A
OUTA/OUTB Sink Current (peak) . . . . . . . . . . . . . . . . . . . 1.0A
Analog Inputs (FB, CS) . –0.3V to VDD+0.3V, not to exceed 6V
Power Dissipation at TA = 25°C (N Package). . . . . . . . . . . . 1W
Power Dissipation at TA = 25°C (D Package) . . . . . . . . 650mW
Storage Temperature . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . –55°C to +150°C
Lead Temperature (Soldering, 10sec.) . . . . . . . . . . . . . +300°C
DIL-8, SOIC-8 (Top View)
J or N Package, D Package
Currents are positive into, negative out of the specified terminal.
Consult Packaging Section of Databook for thermal limitations
and considerations of package.
ORDER INFORMATION
ELECTRICAL CHARACTERISTICS: Unless otherwise specified,TA = 0°C to 70°C for the UCC3808-X, –40°C to 85°C for
the UCC2808-X and –55°C to 125°C for the UCC1808-X, VDD = 10V (Note 6), 1µF capacitor from VDD to GND, R = 22kΩ,
C = 330pF. TA = TJ.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNITS
Oscillator Section
Oscillator Frequency
175
194
213
kHz
Oscillator Amplitude/VDD
(Note 1)
0.44
0.5
0.56
V/V
Error Amplifier Section
Input Voltage
COMP = 2V
1.95
2
2.05
V
Input Bias Current
–1
1
µA
Open Loop Voltage Gain
60
80
dB
COMP Sink Current
FB = 2.2V, COMP = 1V
0.3
2.5
mA
COMP Source Current
FB = 1.3V, COMP = 3.5V
–0.2
–0.5
mA
PWM Section
Maximum Duty Cycle
Measured at OUTA or OUTB
48
49
50
%
Minimum Duty Cycle
COMP = 0V
0
%
Current Sense Section
Gain
(Note 2)
1.9
2.2
2.5
V/V
Maximum Input Signal
COMP = 5V (Note 3)
0.45
0.5
0.55
V
CS to Output Delay
COMP = 3.5V, CS from 0 to 600mV
100
200
ns
CS Source Current
–200
nA
CS Sink Current
CS = 0.5V, RC = 5.5V (Note 7)
5
10
mA
Over Current Threshold
0.7
0.75
0.8
V
COMP to CS Offset
CS = 0V
0.35
0.8
1.2
V
Output Section
OUT Low Level
I = 100mA
0.5
1
V
OUT High Level
I = –50mA, VDD – OUT
0.5
1
V
25
60
ns
Rise Time
CL = 1nF
Fall Time
CL = 1nF
25
60
ns
Undervoltage Lockout Section
Start Threshold
UCCx808-1 (Note 6)
11.5
12.5
13.5
V
UCCx808-2
4.1
4.3
4.5
V
2
UCC1808-1/-2
UCC2808-1/-2
UCC3808-1/-2
ELECTRICAL CHARACTERISTICS: Unless otherwise specified,TA = 0°C to 70°C for the UCC3808-X, –40°C to 85°C for
the UCC2808-X and –55°C to 125°C for the UCC1808-X, VDD = 10V (Note 6), 1µF capacitor from VDD to GND, R = 22kΩ,
C = 330pF. TA = TJ.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNITS
Undervoltage Lockout Section (cont.)
Minimum Operating Voltage After Start
UCCx808-1
7.6
8.3
9
V
UCCx808-2
3.9
4.1
4.3
V
Hysteresis
UCCx808-1
3.5
4.2
5.1
V
UCCx808-2
0.1
0.2
0.3
V
Soft Start Section
COMP Rise Time
FB = 1.8V, Rise from 0.5V to 4V
3.5
20
ms
Overall Section
Startup Current
VDD < Start Threshold
130
260
µA
Operating Supply Current
FB = 0V, CS = 0V (Note 5 and 6)
1
2
mA
VDD Zener Shunt Voltage
IDD = 10mA (Note 4)
13
14
15
V
Note 1: Measured at RC. Signal amplitude tracks VDD.
∆V
Note 2: Gain is defined by A = COMP , 0 VCS 0.4V.
∆VCS
Note 3: Parameter measured at trip point of latch with FB at 0V.
Note 4: Start threshold and Zener Shunt threshold track one another.
Note 5: Does not include current in the external oscillator network.
Note 6: For UCCx808-1, set VDD above the start threshold before setting at 10V.
Note 7: The internal current sink on the CS pin is designed to discharge an external filter capacitor. It is not intended to be a DC
sink path.
PIN DESCRIPTIONS
COMP: COMP is the output of the error amplifier and the
input of the PWM comparator. The error amplifier in the
UCC3808 is a true low-output impedance, 2MHz operational amplifier. As such, the COMP pin can both source
and sink current. However, the error amplifier is internally
current limited, so that zero duty cycle can be externally
forced by pulling COMP to GND.
stages. Both stages are capable of driving the gate of a
power MOSFET. Each stage is capable of 500mA peak
source current, and 1A peak sink current.
The output stages switch at half the oscillator frequency,
in a push/pull configuration. When the voltage on the RC
pin is rising, one of the two outputs is high, but during fall
time, both outputs are off. This “dead time” between the
two outputs, along with a slower output rise time than fall
time, insures that the two outputs can not be on at the
same time. This dead time is typically 60ns to 200ns and
depends upon the values of the timing capacitor and resistor.
The UCC3808 family features built-in full cycle soft start.
Soft start is implemented as a clamp on the maximum
COMP voltage.
CS: The input to the PWM,
peak current, and
overcurrent comparators. The overcurrent comparator is
only intended for fault sensing. Exceeding the
overcurrent threshold will cause a soft start cycle. An internal MOSFET discharges the current sense filter capacitor to improve dynamic performance of the power
converter.
The high-current output drivers consist of MOSFET output devices, which switch from VDD to GND. Each output stage also provides a very low impedance to
overshoot and undershoot. This means that in many
cases, external schottky clamp diodes are not required.
FB: The inverting input to the error amplifier. For best
stability, keep FB lead length as short as possible and FB
stray capacitance as small as possible.
RC: The oscillator programming pin. The UCC3808’s oscillator tracks VDD and GND internally, so that variations
in power supply rails minimally affect frequency stability.
Fig. 1 shows the oscillator block diagram.
GND: Reference ground and power ground for all functions. Due to high currents, and high frequency operation
of the UCC3808, a low impedance circuit board ground
plane is highly recommended.
Only two components are required to program the oscillator, a resistor (tied to the VDD and RC), and a capacitor (tied to the RC and GND). The approximate oscillator
frequency is determined by the simple formula:
OUTA and OUTB: Alternating high current output
3
UCC1808-1/-2
UCC2808-1/-2
UCC3808-1/-2
PIN DESCRIPTIONS (cont.)
fOSCILLATOR =
1. 41
RC
VDD: The power input connection for this device. Although quiescent VDD current is very low, total supply
current will be higher, depending on OUTA and OUTB
current, and the programmed oscillator frequency. Total
VDD current is the sum of quiescent VDD current and
the average OUT current. Knowing the operating frequency and the MOSFET gate charge (Qg), average
OUT current can be calculated from
where frequency is in Hertz, resistance in Ohms, and capacitance in Farads. The recommended range of timing
resistors is between 10kΩ and 200kΩ and range of timing capacitors is between 100pF and 1000pF. Timing resistors less than 10kΩ should be avoided.
For best performance, keep the timing capacitor lead to
GND as short as possible, the timing resistor lead from
VDD as short as possible, and the leads between timing
components and RC as short as possible. Separate
ground and VDD traces to the external timing network
are encouraged.
IOUT = Qg • F, where F is frequency.
To prevent noise problems, bypass VDD to GND with a
ceramic capacitor as close to the chip as possible along
with an electrolytic capacitor. A 1µF decoupling capacitor
is recommended.
UDG-97009
The oscillator generates a sawtooth waveform on RC. During the RC rise time, the output stages alternate on time, but both
stages are off during the RC fall time. The output stages switch a ½ the oscillator frequency, with guaranteed duty cycle of <
50% for both outputs.
Figure 1. Block diagram for oscillator.
APPLICATION INFORMATION
A 200kHz push-pull application circuit with a full wave rectifier is shown in Fig. 2. The output, VO, provides 5V at
75W maximum and is electrically isolated from the input.
Since the UCC3808 is a peak current mode controller the
2N2222A emitter following amplifier (buffers the CT waveform) provides slope compensation which is necessary
for duty ratios greater than 50%. Capacitor decoupling is
very important with a single ground IC controller and a
1µF is suggested as close to the IC as possible. The controller supply is a series RC for startup, paralleled with a
bias winding on the output inductor used in steady state
operation.
Isolation is provided by an optocoupler with regulation
done on the secondary side using the UC3965 Precision
Reference with Low Offset Error Amplifier. Small signal
compensation with tight voltage regulation is achieved
using this part on the secondary side. Many choices exist for the output inductor depending on cost, volume,
and mechanically strength. Several design options are
iron powder, molypermalloy (MPP), or a ferrite core with
an air gap as shown here. The main power transformer
is a low profile design, EFD size 25, using Magnetics
Inc. P material which is a good choice at this frequency
and temperature. The input voltage may range from 36V
dc to 72V dc. Refer to application note U-170 for addition design information.
4
–
VIN
36V TO 72V
+
47µF
4700µF
0.1µF
0.47µF
Figure 2. Typical application diagram.
5
97.6kΩ
0.05Ω
1
8
62Ω
7
62Ω
6
2
3
4
5
1000pF
330pF
20kΩ
2.2Ω
NS2
NS1
432Ω
4.99kΩ
1N4148
2.7Ω
(OPTIONAL)
301kΩ
1N4148 10Ω
32CTQ030
PRIMARY
GROUND
4.99kΩ
RC
IRF640
BYV
28-200
UCC3808D-1
2N2222A
2kΩ
BYV
28-200
IRF640
1000pF
CURRENT
SENSE
330pF
2kΩ
2.2Ω
1N5244
14V
56kΩ
NP1
NP2
EFD25
10:2
6
5
4
100pF
1
2
680µF
4
3
2
5
6
7
UC3965DP
U1
8
1
866Ω
0.01µF
1kV
1.0µF
MOC8102
U3
3
1N4148
1.0µF
EF25 8:24
LOOP A
LOOP B
1.0µF
10kΩ
26.1kΩ
26.1kΩ
49.9kΩ
SECONDARY
GROUND
CLOSED-LOOP
SOFT-START
390pF
4700pF 21.0kΩ
COMP
0.01µF
–
VO
5V 75W
+
UCC1808-1/-2
UCC2808-1/-2
UCC3808-1/-2
APPLICATION INFORMATION (cont.)
UDG-97010-1
UCC1808-1/-2
UCC2808-1/-2
UCC3808-1/-2
180
90
160
80
140
70
PHASE MARGIN (DEGREES)
FREQUENCY (kHz)
1000
100
120
CT=100pF
100
CT=220pF
CT=330pF
CT=560pF
CT=820pF
CT=1000pF
10
60
PHASE
50
80
40
60
30
GAIN
40
20
20
10
0
1
0
50
100
150
200
TIMING RESISTOR, RT (kOhms)
Figure 3. Typical oscillator frequency.
100
10000
FREQUENCY (Hz)
1000000
Figure 6. Typical error amplifier response.
120
14
VDD = 10v, T = +25°C
IDD
with 1nF load
12
DEAD TIME (ns)
8
6
IDD
without load
4
CT=1000pF
CT=820pF
100
10
IDD (mA)
0
1
250
AC GAIN (dB)
TYPICAL CHARACTERISTIC CURVES
2
80
CT=560pF
60
CT=330pF
CT=220pF
CT=100pF
40
20
0
0
200
400
600
800
1000
OSCILLATOR FREQUENCY (kHz)
0
1200
0
Figure 4. Typical IDD active current.
COMP – CS OFFSET (V)
1
0.8
0.6
0.4
0.2
0
-35
-15
5
25
45
100
Figure 7. Typical dead time between output stages.
1.2
-55
20
40
60
80
TIMING RESISTOR (RT) kOhms
65
85
105 125
TEMPERATURE (°C)
Figure 5. Typical COMP to CS offset vs. temperature.
UNITRODE CORPORATION
7 CONTINENTAL BLVD. • MERRIMACK, NH 03054
TEL. (603) 424-2410 FAX (603) 424-3460
6
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