1/4 Structure Silicon Monolithic Integrated Circuit Product Name Audio Interface for Cellular Phone Product No. BU7843AGU Features Audio Interface 6x6 keyscan circuit o ○Absolute Maximum Ratings(Ta=25 C） Parameter Analog supply voltage Digital supply voltage Power supply voltage Symbol AVDD DVDD PVDD Rating -0.3～4.5 -0.3～4.5 -0.3～4.5 Unit V V V Analog input voltage VAIN AVSS-0.3～AVDD+0.3 V Digital input voltage VDIN DVSS-0.3～DVDD+0.3 V IIN -10～+10 mA Pd 310(*1) mW TOPR -30～+85 o C -55～+125 o C Input current Allowable dissipation Operating temperature range Storage temperature range TSTG o Remarks o (*1) When Ta is above 25 C, reduce 3.1mW per 1 C. o ○Recommended operating conditions（Ta=25 C） Parameter Symbol Rating Typ. 2.8 Max. 3.1 Unit Analog operation voltage AVDD Min. 2.7 Digital operation voltage DVDD 1.65 1.8 3.1 V V Power operation voltage PVDD 2.7 2.8 3.1 V (*2) AVDD and PVDD are internally connected in the IC and use the same potential. This chip is not designed to protect itself against radioactive rays. REV. B Remarks (*2) 2/4 ○Electrical Characteristics (Unless otherwise noted, Ta = 25oC AVSS=DVSS=PVSS=0.0V Parameter Symbol ATT is set at 0) Min. Rating Typ. Max. 0.8 - - V DVDD=3.0V - - V DVDD=1.8V 0.2 V DVDD=3.0V Unit Condition Digital DC characteristics Digital high level input voltage 1 VIH1 Digital high level input voltage 2 VIH2 Digital low level input voltage 1 VIL1 Digital low level input voltage 2 Digital high level input current Digital low level input current Digital high level output voltage DVDD DVDD -0.4 - - DVDD VIL2 - - 0.4 V DVDD=1.8V IIH - - 1 μA VIH=DVDD IIL - - 1 μA VIL=DVSS DVDD - - V IOH=-1mA - - 0.5 V IOL=1mA VOH -0.5 Digital low level output voltage Digital AC characteristics SCL clock frequency fSCL - - 400 kHz Bus free time tBUF 1.3 - - μs tSU;STA 0.6 - - μs tHD;STA 0.6 - - μs SCL low time tLOW 1.3 - - μs SCL high time tHIGH 0.6 - - μs Data setup time tSU;DAT 100 - - ns Data hold time tHD;DAT 0 - - ns Stop condition setup time tSU;STO 0.6 - - μs (Iterative) start condition setup time (Iterative) start condition hold time VOL Current consumption AVDD=DVDD=PVDD=2.8V Standby current IST - input signal = no signal. 3 μA After a reset TX_OUT path current IDD1 - 1.3 2.2 mA MIC1_IN→MIX6→TX_OUT HF_OUT path current IDD2 - 1.4 2.4 mA RX_IN→MIX2→HF_OUT BT_OUT path current IDD3 - 1.3 2.2 mA RX_IN→MIX2→BT_OUT Reciever path current IDD4 - 2.5 4.2 mA Headphone path current IDD5 - 3.5 5.9 mA Speaker path current IDD6 - 1.9 3.2 mA Full operation current IDD9 - 8.5 13.5 mA All paths are ON Microphone bias current IDD8 - 250 430 μA BIAS_ON＝！ REV. B RX_IN→MIX2→RCVP_OUT､ RCVN_OUT DACL_IN→MIX2→HPL_OUT DACR_IN→MIX3→HPR_OUT DACL_IN→MIX4→SPL_OUT DACR_IN→MIX5→SPR_OUT 3/4 ○Pin layout diagram Pin CPOP C2 MIC2_IN G5 DVSS B8 N.C. D2 MIC3_IN F5 KB1 B7 N.C. C1 AUX1_IN H5 KB2 A8 N.C. D3 DACR_IN E5 KB3 A7 N.C. D1 AUX2_IN H6 KB4 C6 SPL_OUT E2 DACL_IN G6 KB5 B6 SPR_OUT E3 RX_IN H7 N.C. B5 HF_OUT E1 SDA G7 N.C. A6 BT_OUT E4 SDL H8 N.C. C5 TX_OUT F1 KBR0 G8 N.C. A5 COMOUT F2 KBR1 F6 IRQ B4 COMIN G1 N.C. F7 RSTB C4 AVDD G2 N.C. F8 HPR_OUT A4 AVSS H1 N.C. E6 HPL_OUT D4 CBIAS H2 N.C. E8 CHPL A3 MIC1_OUT F3 KBR2 D7 PVSS B3 MICB G3 KBR3 D6 PVDD A2 N.C. G4 KBR4 D8 RCVN_OUT B3 N.C. H3 KBR5 D5 CSTEP A1 AVDD / AVSS N.C. VREF + MIX6 SW + -26~ +12dB/2dB SPL_V -26~ +12dB/2dB SPR_V -26~ +4dB/2dB HF_V BT_V MIC_V -20~ +30dB/2dB -26~ +4dB/2dB TX_V SW C2 5 C8 32OBTL D5 44 D8 AUX1_V + -11~ +3dB/1dB D3 D1 + AUX2_V -11~ +3dB/1dB D6 AVDD / AVSS DACR_V -11~ +3dB/1dB 8 AUX2_IN D7 MIX2 DACL_V RCV_V -11~ +3dB/1dB -26~ +4dB/2dB E3 + MIX3 RX_V E8 40 HPL_V -11~ +3dB/1dB 16OSingle -26~ +4dB/2dB E6 E1 I2C BUS I/F HPR_V 12 E4 F7 30k F6 KEYSCAN KEYSCAN 6 6 G8 DVDD 16 DVDD 30k G2 DVDD 30k DVDD 30k H8 REV. B N.C. G7 32 31 H7 N.C. KB5 G6 30 29 H6 KB4 KB3 E5 28 H5 KB2 27 26 F5 KB1 DVSS G5 25 H4 24 DVDD KB0 F4 23 H3 22 N.C. N.C. 30k KBR5 KBR4 G4 21 20 19 G3 KBR3 KBR2 N.C. H2 18 H1 IRQ 34 DVDD / DVSS BU7843AGU N.C. RSTB 35 G1 17 CHPR 36 F2 6 N.C. E7 + MIX4 DVDD 15 N.C. HPR_OUT 38 37 F1 14 KBR1 F8 30k 13 KBR0 AVDD/PVDD is connected at internal, and they are connected analog portion. DVDD F3 SCL 16OSingle -26~ +4dB/2dB + MIX5 HPL_OUT 39 11 SDA PVSS 41 CHPL E2 10 RX_IN PVDD 42 9 DACL_IN RCVN_OUT 43 MIX1 7 DACR_IN RCVP_OUT CSTEP SW D2 C1 CPOP 45 6 AUX1_IN N.C. 46 4 MIC3_IN N.C. 47 C7 MIC AMP -26~ +4dB/2dB C3 B8 ANTI-POP MUTE 3 MIC2_IN 49 B7 48 MIC_BIAS MIC1_IN A8 SPL_OUT 50 A7 51 600OSingle C6 BT_OUT HF_OUT 52 55 1 N.C. N.C. RCVP_OUT C7 SPR_OUT C8 DVDD TX_OUT COMOUT KB0 H4 C5 COMIN 56 A5 AVDD 57 B4 58 C4 AVSS CBIAS 59 A4 MIC1_OUT 60 D4 A3 MICB 61 N.C. 62 B3 63 A2 B2 64 N.C. ○Block diagram F4 MIC1_IN B6 （Unit: mm） Pin name N.C. 54 VBGA063T050 Pin NO. C3 53 LOT No Pin name NO. A1 A6 BU78 43AGU Pin Pin name NO. B5 ○External measure and View 33 4/4 ○Cautions on use (1) Absolute Maximum Ratings An excess in the absolute maximum ratings, such as supply voltage, temperature range of operating conditions, etc., can break down devices, thus making impossible to identify breaking mode such as a short circuit or an open circuit. If any special mode exceeding the absolute maximum ratings is assumed, consideration should be given to take physical safety measures including the use of fuses, etc. (2) Operating conditions These conditions represent a range within which characteristics can be provided approximately as expected. The electrical characteristics are guaranteed under the conditions of each parameter. (3) Reverse connection of power supply connector The reverse connection of power supply connector can break down ICs. Take protective measures against the breakdown due to the reverse connection, such as mounting an external diode between the power supply and the IC’s power supply terminal. (4) Power supply line Design PCB pattern to provide low impedance for the wiring between the power supply and the GND lines.In this regard, for the digital block power supply and the analog block power supply, even though these power supplies has the same level of potential, separate the power supply pattern for the digital block from that for the analog block, thus suppressing the diffraction of digital noises to the analog block power supply resulting from impedance common to the wiring patterns. For the GND line, give consideration to design the patterns in a similar manner. Furthermore, for all power supply terminals to ICs, mount a capacitor between the power supply and the GND terminal. At the same time, in order to use an electrolytic capacitor, thoroughly check to be sure the characteristics of the capacitor to be used present no problem including the occurrence of capacity dropout at a low temperature, thus determining the constant. (5) GND voltage Make setting of the potential of the GND terminal so that it will be maintained at the minimum in any operating state. Furthermore, check to be sure no terminals are at a potential lower than the GND voltage including an actual electric transient. (6) Short circuit between terminals and erroneous mounting In order to mount ICs on a set PCB, pay thorough attention to the direction and offset of the ICs. Erroneous mounting can break down the ICs. Furthermore, if a short circuit occurs due to foreign matters entering between terminals or between the terminal and the power supply or the GND terminal, the ICs can break down. (7) Operation in strong electromagnetic field Be noted that using ICs in the strong electromagnetic field can malfunction them. (8) Inspection with set PCB On the inspection with the set PCB, if a capacitor is connected to a low-impedance IC terminal, the IC can suffer stress. Therefore, be sure to discharge from the set PCB by each process. Furthermore, in order to mount or dismount the set PCB to/from the jig for the inspection process, be sure to turn OFF the power supply and then mount the set PCB to the jig. After the completion of the inspection, be sure to turn OFF the power supply and then dismount it from the jig. In addition, for protection against static electricity, establish a ground for the assembly process and pay thorough attention to the transportation and the storage of the set PCB. (9) Input terminals In terms of the construction of IC, parasitic elements are inevitably formed in relation to potential. The operation of the parasitic element can cause interference with circuit operation, thus resulting in a malfunction and then breakdown of the input terminal. Therefore, pay thorough attention not to handle the input terminals, such as to apply to the input terminals a voltage lower than the GND respectively, so that any parasitic element will operate. Furthermore, do not apply a voltage to the input terminals when no power supply voltage is applied to the IC. In addition, even if the power supply voltage is applied, apply to the input terminals a voltage lower than the power supply voltage or within the guaranteed value of electrical characteristics. (10) Ground wiring pattern If small-signal GND and large-current GND are provided, It will be recommended to separate the large-current GND pattern from the small-signal GND pattern and establish a single ground at the reference point of the set PCB so that resistance to the wiring pattern and voltage fluctuations due to a large current will cause no fluctuations in voltages of the small-signal GND. Pay attention not to cause fluctuations in the GND wiring pattern of external parts as well. (11) External capacitor In order to use a ceramic capacitor as the external capacitor, determine the constant with consideration given to a degradation in the nominal capacitance due to DC bias and changes in the capacitance due to temperature, etc. (12) Others In case of use this LSI, please peruse some other detail documents, we called ,Technical note, Functinal description, Application note. REV. B Notice Notes No copying or reproduction of this document, in part or in whole, is permitted without the consent of ROHM Co.,Ltd. The content specified herein is subject to change for improvement without notice. The content specified herein is for the purpose of introducing ROHM's products (hereinafter "Products"). If you wish to use any such Product, please be sure to refer to the specifications, which can be obtained from ROHM upon request. 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