SONY CXD1852Q

CXD1852Q
MPEG1 Decoder
For the availability of this product, please contact the sales office.
Description
The CXD1852Q is a single-chip MPEG1 decoder
with a built-in CD-ROM decoder which allows
decoding of MPEG1 system, video and audio layers.
A built-in CD-ROM decoder enables direct connection
with a CD-DSP. Combining this chip with a control
microcomputer and 4-Mbit DRAM, etc. allows
configuration of a MPEG1 decoding system for video
CD players, etc.
Features
• Supply voltage: 3.3 ± 0.3V
• Input and output voltages: LVTTL compatible
• 5V can be applied as the input voltage (excluding
some pins)
• Allows decoding of MPEG1 system, video and
audio layers
• Built-in CD-ROM decoder allows direct connection
with a CD-DSP
• CD-ROM decoded output can be transferred to
and stored in an external DRAM
• RGB and YCbCr video data output allowed
• Built-in video sync generator
• Audio data output can support various DAC
• Supports various special playback modes
• Video CD PAL high resolution still picture can be
decoded with a single 4-Mbit DRAM
• 8-bit parallel and 4-line serial host interfaces
• CD-DA through operation allowed
120 pin QFP (Plastic)
Structure
Silicon gate CMOS IC
Applications
Video CD players, MPEG1 decoder boards, etc.
Block Diagram
CD-DSP
I/F
CD-ROM
Decoder
MPEG
System
Decoder
MPEG
Audio
Decoder
Audio
I/F
MPEG
Video
Decoder
DRAM
Controler
DRAM
I/F
Video Postprocessor
&
Sync Generator
Video
I/F
Video Sync
Signal
Host
interface
Host
I/F
To each circuit block
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E96656-PS
CXD1852Q
VSS
HSYNC
VSYNC
FID/FHREF
CBLNK/FSC
XSGRST
CSYNC
CLK0O
DOUT
DATO
BCKO
LRCO
FSXI
VDD
VSS
XTL2O
VDD
XTL2I
C2PO
LRCI
DATI
DOIN
BCKI
XHCS
XHDT
HRW
XHIRQ
HA0
XRST
HA1
1. Pin Configuration
120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91
VSS
1
90 VDD
XTL0O
2
89 DCLK
XTL0I
3
88 B/Cb7
VDD
4
87 B/Cb6
HA2
5
86 B/Cb5
HA3
6
85 B/Cb4
HD0
7
84 B/Cb3
HD1
8
83 B/Cb2
HD2
9
82 B/Cb1
HD3 10
81 B/Cb0
HD4 11
80 G/Y7
HD5 12
79 G/Y6
HD6 13
78 G/Y5
VDD 14
77 G/Y4
VSS 15
76
G/Y3
HD7 16
75 VSS
MA3 17
74 VDD
MA4 18
73 G/Y2
MA2 19
72 G/Y1
MA5 20
71 G/Y0
MA1 21
70 R/Cr7
VSS 22
69 R/Cr6
MA6 23
68 R/Cr5
MA0 24
67 R/Cr4
BC 25
66 R/Cr3
TCKI 26
65 R/Cr2
TDI 27
64 R/Cr1
TENA1 28
63 R/Cr0
TDO 29
62 XVOE
VST 30
61 VSS
–2–
VDD
OSDR
OSDG
OSDB
OSDEN
MD15
MD0
MD14
MD1
MD13
MD2
MD3
MD12
MD11
VSS
MD4
VDD
MD10
MD5
MD9
MD6
MD8
MD7
XCAS0
XCAS2/MA9
XRAS
XMWE
MA8
MA7
VSS
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60
CXD1852Q
2. Pin Description
Pin No.
Symbol
I/O
Description
VDD
+3.3V power supply
VSS
Connect to ground.
2
XTL0O
O
3
XTL0I
I
5, 6, 119,
HA0 to HA3
120
Video decoder master clock. Input the clock to XTL0I or connect an
oscillator between XTL0I and XTL0O. The recommended frequencies are
27MHz, 28.6363MHz (NTSC 8fsc) and 35.4686MHz (PAL 8fsc).
I
When the host interface operates in parallel mode, these pins are the
register address inputs. In serial mode, HA0 is the serial data input, and
HA1 to HA3 should be fixed to low level.
7 to 13,
16
HD0 to HD7
I/O
When the host interface operates in parallel mode, these pins are the
register data I/Os. In serial mode, HD0 is the serial data output, and HD1
to HD7 should be fixed to low level.
17 to 21,
23, 24,
32, 33
MA0 to MA8
O
DRAM address signal outputs. Connect to the DRAM address pins so that
the numbers match.
34
XRAS
O
Row address strobe signal output. Connect to the DRAM RAS signal pin.
35
XMWE
O
DRAM write enable signal output. Connect to the DRAM WE signal pin.
O
Used when connecting 8 Mbits of DRAM. Connect to the upper word
(256K to 512K-1) DRAM CAS signal pin (for both the upper and lower
bytes) when the DRAM configuration is 256 Kwords × 16 bits × 2, and to
the MA9 pin (for two DRAMs) when the DRAM configuration is 512 Kwords
× 8 bits × 2.
36
XCAS2/
MA9
37
XCAS0
O
DRAM column address strobe signal output. Connect to the lower word
(0 to 256K-1) DRAM CAS signal pin (for both the upper and lower bytes)
when the DRAM configuration is 256Kwords × 16 bits × 2, and to all
DRAM CAS signal pins in all other cases.
38 to 43,
46 to 55
MD0 to
MD15
I/O
DRAM data signal I/Os. Connect to the DRAM data pins so that the
numbers match.
56
OSDEN
I
OSD enable signal. The enabled polarity is changed by the register
settings.
57 to 59
OSDB,
OSDG,
OSDR
I
OSD data inputs. When the signal input to the OSDEN pin is enabled, the
color registered in the color table which is specified by these three inputs
(3 bits) is output as the image data.
I
Video output enable signal. Image data output and DCLK output are
enabled when this pin is low, and disabled when this pin is high (high
impedance). Note that the output control register must be set to output
enable for output to be enabled.
O
Image data outputs. The output data format (RGB, YCbCr, etc.) and the
correspondence between the pins and output data can be changed by
setting the registers.
I/O
Dot clock (DCLK) signal. The DCLK frequency is normally 13.5MHz.
DCLK can be input from this pin, or frequency divided from the clock input
and output from this pin.
62
XVOE
63 to 70
R/Cr0 to
R/Cr7
71 to 73,
76 to 88
G/Y0 to
G/Y7
81 to 88
B/Cb0 to
B/Cb7
89
DCLK
–3–
CXD1852Q
Pin No.
Symbol
I/O
Description
92
HSYNC
I/O
Horizontal sync signal. When using the built-in sync generator, the dot
clock (DCLK) is frequency divided and output. When not using the sync
generator, this pin is an input.
93
VSYNC
I/O
Vertical sync signal. When using the built-in sync generator, the dot clock
(DCLK) is frequency divided and output. When not using the built-in sync
generator, this pin is an input.
I/O
Field identification signal (FID) and horizontal sync phase reference signal
(FHREF). The signal to be used is set in the register. When set to FID, this
pin is an output if using the built-in sync generator, and an input if not
using the built-in sync generator. High corresponds to odd fields. When set
to FHREF, this pin outputs the signal obtained by frequency dividing XTL0.
When XTL0 is 8fsc, this signal is equivalent to the HSYNC cycle, and can
be used for phase comparison with the HSYNC signal.
94
FID/FHREF
95
CBLNK/
FSC
I/O
Composite blanking signal (CBLNK) and fsc signal. The signal to be used
is set in the register. When set to CBLNK, this pin is an output if using the
built-in sync generator, and an input if not using the built-in sync generator.
When set to fsc, this pin outputs the signal obtained by frequency dividing
XTL0. The frequency division ratio can be selected from 1/8 or 1/16.
96
CSYNC
O
Composite sync signal obtained by frequency dividing DCLK. This pin
cannot be input.
97
XSGRST
I
Sync generator reset signal input. The built-in sync generator is initialized
by setting this pin low.
98
CLK0O
O
Output for clock obtained by frequency dividing XTL0. The frequency
division ratio can be selected from 1, 1/2, 1/4 or 1/8.
99
DOUT
O
Audio digital output.
100
DATO
O
Audio serial data output to DAC.
101
LRCO
O
L/R clock output to DAC.
102
BCKO
O
Bit clock output to DAC.
103
FSXI
I
Audio interface clock input. Input 256fs (11.2896MHz), 384fs
(16.9344MHz), 512fs (22.5792MHz), or 768fs (33.8688MHz), etc.
106
XTL2O
O
107
XTL2I
I
109
C2PO
I
C2 pointer input from CD-DSP. Indicates that the DATI input contains an
error.
110
LRCI
I
LR clock input from CD-DSP. Indicates the L or R channel of DATI.
111
DATI
I
Serial data input from CD-DSP.
112
BCKI
I
Bit clock input from CD-DSP. This clock strobes the DATI input.
113
DOIN
I
Digital data input from CD-DSP.
114
XHCS
I
Chip select signal input during register access.
115
XHDT
I/O
Master clock for CD-ROM and audio decoders. Input the clock to XTL2I or
connect an oscillator between XTL2I and XTL2O. The recommended
frequency is 45MHz. Note that this clock is for the internal circuits, and the
input and output are not synchronized.
Wait signal output during register access. This pin is valid only when the
host interface operates in parallel mode. This pin functions as an open
drain, and should therefore be pulled up. It should be pulled up when the
host interface operates in serial mode as well.
–4–
CXD1852Q
Pin No.
Symbol
I/O
Description
116
HRW
I
R/W signal input when the host interface operates in parallel mode. Serial
clock input in serial mode.
117
XHIRQ
O
Interrupt request signal output. This pin functions as an open drain, and
should therefore be pulled up.
118
XRST
I
Hardware reset signal input. All operation is initialized by setting this pin
low.
25
BC
—
Test. Leave open.
26
TCKI
—
Test. Leave open.
27
TDI
—
Test. Leave open.
28
TENA1
—
Test. Leave open.
29
TDO
—
Test. Leave open.
30
VST
—
Test. Connect to ground.
–5–
CXD1852Q
3. Electrical Characteristics
3-1. Absolute Maximum Ratings
Item
(Ta = 25°C, VSS = 0V)
Symbol
Rating
Unit
–0.5 to +4.6
V
Remarks
Supply voltage
VDD
Input pin voltage
VI
–0.5 to VDD + 0.5
V
∗1
Input pin voltage
VI
–0.5 to +5.5
V
∗2
Output pin voltage
VO
–0.5 to VDD + 0.5
V
∗3
Output pin voltage
VO
–0.5 to +5.5
V
∗4
I/O pin voltage
VI/O
–0.5 to +5.5
V
1.0
W
Allowable power dissipation PD
Operating temperature
Topr
–20 to +75
°C
Storage temperature
Tstg
–55 to +150
°C
∗1 XTL0I and XTL2I pins
∗2 Input pins other than those in ∗1 above.
∗3 XTL0O and XTL2O pins
∗4 Output pins other than those in ∗3 above.
3-2. Recommended Operating Conditions
(Ta = –20 to +75°C, VSS = 0V)
Symbol
Min.
Typ.
Max.
Unit
Supply voltage
VDD
3.0
3.3
3.6
V
High level input voltage
VIH
2.2
—
VDD
V
∗1
High level input voltage
VIH
2.2
—
5.0
V
∗2
Low level input voltage
VIL
0
—
0.8
V
Input rise time
Tr
0
—
50
ns
Input fall time
Tf
0
—
50
ns
Operating temperature
Topr
–20
—
75
°C
Item
∗1 XTL0I and XTL2I pins
∗2 I/O pins and input pins other than those in ∗1 above.
–6–
Remarks
CXD1852Q
3-3. DC Characteristics
Item
(Ta = –20 to +75°C, VSS = 0V, VDD = 3.3 ± 0.3V)
Symbol Measurement conditions
Min.
Typ.
Max.
Unit Remarks
—
—
100
mA
–40
—
40
µA
∗1
VDD – 0.8
—
—
V
∗2
Average operating
supply current
IDD
Input leak current
II
VI = 0 to 5.0V
High level output voltage
VOH
IOH = –2mA
High level output voltage
VOH
IOH = –100µA
—
VDD – 0.4
—
V
∗2
Low level output voltage
VOL
IOL = 4mA
—
—
0.4
V
∗2
Low level output voltage
VOL
IOL = 100µA
—
0.04
—
V
∗2
Output leak current
IOZ
VO = 0 to 5.0V,
output disabled status
–40
—
40
µA
∗2
Feedback resistance
RFB
VI = 0V or VI = VDD
250k
1M
2.5M
Ω
∗3
Logic threshold value
LVth
—
VDD/2
—
V
∗4
High level output voltage
VOH
IOH = –12mA
VDD/2
—
—
V
∗5
Low level output voltage
VOL
IOL = 12mA
—
—
VDD/2
V
∗5
Min.
Typ.
Max.
—
—
60
MHz
∗1
∗1
∗1 Input pins other than XTL0I and XTL2I
∗2 I/O pins and output pins other than XTL0O and XTL2O
∗3 Oscillators (between XTL0I and XTL0O, and between XTL2I and XTL2O)
∗4 XTL0I and XTL2I pins
∗5 XTL0O and XTL2O pins
3-4. Clock Signal AC Characteristics
tCX0
tWLX0
XTL0I
tWHX0
tCX2
tWLX2
XTL2I
tWHX2
Item
Symbol
Unit Remarks
XTL0I frequency
fX0
XTL0I cycle
33.3
—
—
ns
10
—
—
ns
XTL0I low level interval
tCX0
tWHX0
tWLX0
10
—
—
ns
XTL2I frequency
fX2
44.7
45.1584
45.4
MHz
∗2
XTL2I cycle
tCX2
tWHX2
tWLX2
—
22.2
—
ns
∗2
8
—
—
ns
8
—
—
ns
XTL0I high level interval
XTL2I high level interval
XTL2I low level interval
∗1 When using in combination with the XTL0O pin as an oscillator, the maximum oscillation frequency is 50MHz.
∗2 When using in combination with the XTL2O pin as an oscillator, the maximum oscillation frequency is 50MHz.
–7–
CXD1852Q
3-5. Host Interface AC Characteristics
3-5-1. Serial Mode (write, read)
XHCS
tSCS
tWLSK
HRW
(SCK)
tCSK
tHCS
tWHSK
tSSI
tHSI
HA0
(SI)
tLZSQ
tOHSQ
tDSQ
tHZSQ
HD0
(SQ)
Item
Symbol
Serial clock frequency
fSK
Serial clock cycle
tCSK
tWHSK
tWLSK
tSCS
tHCS
tSSI
tHSI
tLZSQ
tDSQ
tOHSQ
tHZSQ
Serial clock high level interval
Serial clock low level interval
Chip select setup time
Chip select hold time
Serial input setup time
Serial input hold time
Serial output enable time
Serial output determination time
Serial output hold time
Serial output disable time
–8–
Min.
Max.
Unit
—
2
MHz
500
—
ns
100
—
ns
100
—
ns
0
—
ns
500
—
ns
30
—
ns
30
—
ns
0
15
ns
—
40
ns
5
—
ns
0
15
ns
Remarks
CXD1852Q
3-5-2. Parallel Mode, Register Write
HA0 to 3
tSA
tHA
tWCSH
XHCS
tWWL1
XHRW
tDWA1
tHW1
XHDT
tHZQ2
HD0 to 7
output
Item
Address setup time
Address hold time
Chip disable time
Write pulse width
Write pulse hold time
Wait signal delay time
HD output disable time (for WR)
HD input setup time
HD input hold time
∗1
∗2
∗3
∗4
∗5
tSD1
tHD1
input
Symbol
tSA
tHA
tWCSH
tWWL1
tHW1
tDWA1
tHZQ2
tSD1
tHD1
Specified for the edge of XHCS or HRW, whichever is later.
Specified for the edge of XHCS or HRW, whichever is earlier.
Interval during which both XHCS and HRW are low.
Applies only to access resulting in wait status.
Do not apply data while output is enabled.
–9–
Min.
Max.
Unit
Remarks
20
—
ns
∗1
20
—
ns
∗2
20
—
ns
60
—
ns
∗3
10
—
ns
∗2, ∗4
—
15
ns
∗1, ∗4
—
15
ns
∗5
25
—
ns
∗2
25
—
ns
∗2
CXD1852Q
3-5-3. Parallel Mode, Register Read
HA0 to 8
tWCSH
XHCS
(CS)
tSR
tHR
XHRW
(WR)
tDWA2
tDWA3
XHDT
(WAIT)
tDQ2
tDQ1
tHZQ1
tLZQ1
tDQ4
valid output
HD0 to 7
Item
Chip disable time
Read setup time
Read hold time
Wait signal delay time (for CE)
Wait signal delay time (for HA)
HD output enable time (for CE)
HD output determination time (for CE)
HD output determination time (for HA)
HD output determination time (for WAIT)
HD output disable time (for CE)
∗1
∗2
∗3
∗4
Symbol
tWCSH
tSR
tHR
tDWA2
tDWA3
tLZQ1
tDQ1
tDQ2
tDQ4
tHZQ1
Min.
Max.
Unit
Remarks
20
—
ns
10
—
ns
10
—
ns
—
15
ns
∗1
—
15
ns
∗1
0
—
ns
∗2
—
60
ns
∗3
0
60
ns
∗3
—
30
ns
∗3, ∗4
—
15
ns
Applies only to access resulting in wait status. XHDT goes low at the later timing of CE or HA.
HD output is enabled when both conditions are met.
HD output is determined when all conditions are met.
Applies only to access resulting in wait status.
– 10 –
CXD1852Q
3-6. Interface for CD Signal Processing LSI
BCKFEDG = 0
tBCKI
tBCKI
BCKI
DATI
tSBC1
tHBC1
LRCI, C2PO
tHBC2
tSBC2
BCKFEDG = 1
tBCKI
tBCKI
BCKI
DATI
tSBC1
tHBC1
LRCI, C2PO
tHBC2
Item
Symbol
BCKI frequency
fBCKI
BCKI pulse width
tBCKI
tSBC1
tHBC1
tSBC2
tHBC2
DATI setting time (for BCKI)
DATI hold time (for BCKI)
LRCI, C2PO setting time (for BCKI)
LRCI, C2PO hold time (for BCKI)
– 11 –
tSBC2
Max.
Unit
5.7
MHz
87
—
ns
20
—
ns
20
—
ns
20
—
ns
20
—
ns
Min.
Remarks
CXD1852Q
3-7. Image Data Output, Video Sync Signal Output AC Characteristics
tCDCK
tWLDCK
DCLK
tWHDCK
tHPD
R/Cr0 to 7
G/Y0 to 7
B/Cb0 to 7
tDPD
tDHSY
tDHSY
tDVSY
tDVSY
tDCSY
tDCSY
tDCBL
tDCBL
tDFID
tDFID
HSYNC
VSYNC
CSYNC
CBLNK
FID
Item
Symbol
Min.
Typ.
Max.
Unit Remarks
DCLK frequency
fDCK
—
13.5
—
MHz
∗1
DCLK cycle
tCDCK
tWHDCK
tWLDCK
tDPD
tHPD
tDHSY
tDVSY
tDCSY
tDCBL
tDFID
—
74.1
—
ns
∗1
—
37
—
ns
∗1
—
37
—
ns
∗1
—
—
15
ns
∗1, ∗2
0
—
—
ns
∗1, ∗2
—
—
30
ns
∗1
—
—
30
ns
∗1
—
—
30
ns
∗1
—
—
30
ns
∗1
—
—
30
ns
∗1
DCLK high level interval
DCLK low level interval
Image data output determination time
Image data output hold time
HSYNC output delay time
VSYNC output delay time
CSYNC output delay time
CBLNK output delay time
FID output delay time
∗1 When both inputting and outputting DCLK. For output, a load of 75pF is connected to DCLK.
∗2 The chart shows the case where the pixel data output is synchronized to the fall of DCLK, but is also the
same when synchronized to the rise of DCLK.
– 12 –
CXD1852Q
3-8. Video Sync Signal Input AC Characteristics
DCLK
tHHSY
tSHSY
tHHSY
tSHSY
tHVSY
tSVSY
tHVSY
tSVSY
tHCBL
tSCBL
tHCBL
tSCBL
tHFID
tSFID
tHFID
tSFID
HSYNC
VSYNC
CBLNK
FID
Item
HSYNC hold time
HSYNC setup time
VSYNC hold time
VSYNC setup time
CBLNK hold time
CBLNK setup time
FID hold time
FID setup time
Symbol
tHHSY
tSHSY
tHVSY
tSVSY
tHCBL
tSCBL
tHFID
tSFID
Min.
Max.
Unit
Remarks
5
—
ns
∗1
5
—
ns
∗1
5
—
ns
∗1
5
—
ns
∗1
5
—
ns
∗1
5
—
ns
∗1
5
—
ns
∗1
5
—
ns
∗1
∗1 When both inputting and outputting DCLK. For output, a load of 75pF is connected to DCLK.
– 13 –
CXD1852Q
3-9. fsc System Signal Output, DCLK Output AC Characteristics
tCX0
XTL0O
tCFSC
tDFSC
tWHFSC
FSC
tWLFSC
tDFHR
FHREF
tCDCK
tWHDCK
tDDCK
DCLK
tWLDCK
Item
Symbol
Min.
Typ.
Max.
Unit Remarks
FSC frequency
fFSC
—
1/(i × tCX0)
—
∗1
FSC cycle
—
i × tCX0
—
∗1
—
i × tCX0/2
—
∗1
—
i × tCX0/2
—
∗1
—
—
15
ns
FHREF output delay time
tCFSC
tWHFSC
tWLFSC
tDFSC
tDFHR
—
—
15
ns
DCLK frequency
fDCK
—
1/(j × tCX0)
—
∗2
DCLK cycle
tCDCK
tWHDCK
tWLDCK
tDDCK
—
j × tCX0
—
∗2
—
j × tCX0/2
—
∗2
—
j × tCX0/2
—
∗2
—
—
15
FSC high level interval
FSC low level interval
FSC output delay time
DCLK high level interval
DCLK low level interval
DCLK output delay time
∗1 The frequency division ratio i can be selected from 8 or 16.
∗2 The frequency division ratio j can be selected from 2 or 4.
– 14 –
ns
CXD1852Q
3-10. Audio Interface
tBCKO
tBCKO
BCKO
DATO
tDDAT
LRCO
tDLRC
Item
Symbol
BCKO frequency
fBCKO
BCKO pulse width
tBCKO
tDDAT
tDLRC
DATO delay time (for BCKO)
LRCO delay time (for BCKO)
– 15 –
Max.
Unit
3.1
MHz
160
—
ns
—
40
ns
—
40
ns
Min.
Remarks
CXD1852Q
3-11. DRAM Interface AC Characteristics
3-11-1. Write Cycle
tRP
XRAS
tPC
tRCD
tCAS
tCP
tRSH
XCAS0 to 3
tWCS
tWCH
XMWE
tASR
tRAH
tASC
tCAH
tDS
tDH
MA0 to 9
MD0 to 15
Item
RAS precharge time
RAS to CAS delay time
RAS hold time
Fast page mode cycle time
CAS pulse width
CAS precharge time
Write command setup time
Write command hold time
Row address setup time
Row address hold time
Column address setup time
Column address hold time
Write data setup time
Write data hold time
Symbol
tRP
tRCD
tRSH
tPC
tCAS
tCP
tWCS
tWCH
tASR
tRAH
tASC
tCAH
tDS
tDH
∗1 tv is the basic clock cycle for the DRAM interface circuit.
∗2 Same as the DRAM interface read cycle.
– 16 –
Min.
Unit Remarks
Typ.
Max.
2 × tv
—
ns
∗2
2 × tv
—
ns
∗2
tv
2 × tv
tv
tv
tv
2 × tv
tv
tv
tv
tv
tv
tv
—
ns
∗2
—
ns
∗2
—
ns
∗2
—
ns
∗2
—
ns
—
ns
—
ns
∗2
—
ns
∗2
—
ns
∗2
—
ns
∗2
—
ns
—
ns
CXD1852Q
3-11-2. Read Cycle
tRP
XRAS
tPC
tRCD
tCAS
tCP
tRSH
XCAS0 to 3
tRCS
tRCH
XMWE
tASR
tRAH
tASC
tCAH
MA0 to 9
tMDS
tMDH
MD0 to 15
Item
Read command setup time
Read command hold time
Read data setup time
Read data hold time
Symbol
tRCS
tRCH
tMDS
tMDH
Min.
Unit Remarks
Typ.
Max.
4 × tv
—
ns
tv
—
ns
2
—
ns
8
—
ns
∗1 tv is the basic clock cycle for the DRAM interface circuit.
∗2 See the DRAM interface write cycle for items which appear in the timing chart but not in the table.
– 17 –
CXD1852Q
4. Description of Functions
4-1. Host Interface Function
• The CXD1852Q operation is controlled by writing and reading registers. Write and read can also be
performed to an external DRAM via the registers. See the separately issued Register Manual for the
relationship between the registers and operation.
• The host interface operates while XHCS is low and does not operate while XHCS is high.
• The host interface operating mode can be set to 4-line serial or 8-bit parallel. The operating mode is selected
automatically at the end of the initial access after the hardware has been reset. (See the figure below.)
Registers are not accessed correctly until this selection has been determined, or in other words until the end
of the initial access after the hardware has been reset. Also, the HA3 to HA0 inputs should all be fixed low
during the operating mode selection access.
XHCS
XHCS
HRW
HRW
Access judged as parallel mode
XHCS
HRW
8 rises
Access judged as serial mode
• The serial mode signal format is as follows.
XHCS
HRW
(SCK)
HA0
(SI)
bit0
bit1
bit2
bit3
bit4
bit5
bit6
bit7
bit8
byte0
HD0
(SO)
bit0
bit1
bit2
bit3
bit4
bit9
byte1
bit5
bit6
bit7
bit8
bit9
1) In serial mode, input data is fetched in sync with the rise of HRW (SCK). Output data is synchronized with
the fall of HRW.
2) The initial byte (byte0) of the input after XHCS changes to low is a command. This command determines
the subsequent byte processing. See the following page for a description of commands and processing.
3) Input data is processed in one byte units. Therefore, when the final data consists of a number of bits which
is less than one byte, this deficient data is not processed. Be sure to input data with a number of bits which
is an integer multiple of 8. Also, the 0x20, 0x60, 0xA0 and 0xE0 commands process data in two byte units,
so data which is an even multiple of 8 should be input when using these commands.
– 18 –
CXD1852Q
Command write
2nd input byte 3rd input byte
bit7 ··· bit0 read
Successive
Successive
first Auto
4th input byte odd-numbered even-numbered
bit inc.
input bytes
input bytes
00000000 write
Register No. LSB
Register No.
Register No.
Register data
Register data
No
+U/L byte select first
+U/L byte select
+U/L byte select
00010000 read
Register No.
+U/L byte select
don’t care
Register No.
+U/L byte select
don’t care
00100000 write
Register No.
Register data
(Lower byte)
Register data
(Upper byte)
Register data
(Lower byte)
Register data
(Upper byte)
LSB
No
first
00110000 read
Register No.
don’t care
don’t care
don’t care
don’t care
LSB
No
first
01100000 write
Register No.
Register data
(Lower byte)
Register data
(Upper byte)
Register data
(Lower byte)
Register data
(Upper byte)
LSB
Yes
first
01110000 read
Register No.
don’t care
don’t care
don’t care
don’t care
LSB
Yes
first
Register No. LSB
No
+U/L byte select first
10000000 write
Register No.
Register No. MSB
Register No.
Register data
Register data
No
+U/L byte select first
+U/L byte select
+U/L byte select
10010000 read
Register No.
+U/L byte select
don’t care
Register No.
+U/L byte select
don’t care
10100000 write
Register No.
Register data
(Upper byte)
Register data
(Lower byte)
Register data
(Upper byte)
Register data
(Lower byte)
MSB
No
first
10110000 read
Register No.
don’t care
don’t care
don’t care
don’t care
MSB
No
first
11100000 write
Register No.
Register data
(Upper byte)
Register data
(Lower byte)
Register data
(Upper byte)
Register data
(Lower byte)
MSB
Yes
first
11110000 read
Register No.
don’t care
don’t care
don’t care
don’t care
MSB
Yes
first
Register No. MSB
No
+U/L byte select first
Description of Commands
1) The "write read" column indicates whether that command writes data to or reads data from the registers.
2) Bytes marked with "Register No. + U/L byte select" specify the register to be accessed as well as whether
to access the upper or lower bytes of the register. The upper 7 bits specify the register No., and the
lowermost bit specifies the upper or lower bytes. When the lowermost bit is "0", the lower bytes are
selected, when "1", the upper bytes are selected.
3) Bytes marked with "Register No." specify the register to be accessed. The upper 7 bits specify the register
No., and the lowermost bit can be either "0" or "1".
4) The "Auto inc." column indicates the presence of the register No. auto increment function. For commands
without this function, the most recently input register No. is valid. For example, in case of the command
0x00, the register data input by the odd bytes is written to the register specified by the previous byte's input.
For the command 0x20, all subsequent data is written sequentially to the register specified by the 2nd input
byte.
5) For commands with the register No. auto increment function, the register specified by the 2nd input byte is
accessed first, and then access shifts to the register No. incremented by one each time the data for one
register (2 bytes) is read or written. For example, when using the command 0x60, if 0x08 is specified by the
2nd input byte, the 3rd and 4th input bytes are written to register 0x08, and the 5th and 6th input bytes are
written to register 0x09.
6) Bytes marked with "register data" are the data to be written to the registers during write commands.
– 19 –
CXD1852Q
7) When executing read commands, register data output starts from the 3rd output byte (bit 16). All earlier
output data is invalid data. Access shifts to a new register each time the output for one register (2 bytes) is
finished. For example, in case of the command 0x10, the byte data specified by the 2nd input byte is output
to the 3rd output byte, the other byte data in the same register is output to the 4th byte, and the byte data
specified by the 4th input byte is output to the 5th output byte.
8) The "first bit" column indicates whether LSB first or MSB first processing is performed for input or output of
the 2nd and subsequent bytes. This specification does not apply to the 1st byte (command). Commands
are normally LSB first. If LSB first is specified, processing is performed in the order where the initial bit in
each byte is LSB and the final bit is MSB. This order is reversed for MSB first. Note that for registers, bit 15
noted in the Register Manual is MSB and bit 0 is LSB.
4-2. DRAM Interface Function
• The applicable DRAMs are speed version 70 devices (RAS access time (Trac) of 70ns or less) with the fast
page mode function.
• When the total capacity of the external DRAM is 4 Mbits, use a 2CAS type DRAM with a configuration of 256
Kwords × 16 bits. When the total capacity is 8 Mbits, use two 2CAS type DRAMs with a configuration of 256
Kwords × 16 bits or 512 Kwords × 8 bits.
• Refresh is performed automatically using RAS-only-refresh. External control is not necessary.
• The DRAM is divided into the image frame memory, audio bit stream buffer, video bit stream buffer, user
data and on-memory register areas.
• The user data area can be used freely by the user, and CD-ROM decoded output can also be transferred to
this area. This area can be used to store video CD PSD, etc.
• The desired DRAM areas can be accessed from the control microcomputer via the registers.
4-3. CD-ROM Decoder Function
• CD signal processor LSI interface
The CD-ROM decoder has a CD signal processor LSI (CD-DSP) interface which directly interfaces the serial
data output from the CD-DSP. This interface supports a wide variety of input formats to enable connection
with general CD-DSP.
• CD-ROM data decoding (supports CD-ROM XA format mode2, form1 and form2)
CD-ROM data input from the CD-DSP supports CD-ROM XA format (mode2, form1 and form2).
• Input CD-ROM data is decoded by the CD-ROM decoder block. Also, the CD-DA signal input from the CDDSP can be output directly from the audio interface.
• The CD-ROM decoder has the following decoding and data transfer operating modes. The real-time
correction and write-only modes facilitate the loading of video CD PSD to the external DRAM, etc.
1) Auto transfer mode
The MPEG pack data within one sector of the video CD is automatically transferred to the system
decoder, where the audio stream sector or video stream sector can be decoded. This mode transfers
2324 bytes counted from the initial byte of user data within one sector to the system decoder.
2) Real-time correction mode
This mode executes error detection and correction processing for mode2, form1 sectors. The 2048 bytes
of user data within the error processed sector are transferred to the user area of the external DRAM. The
4 bytes of header information within the sector can also be loaded in the on-memory register within the
DRAM.
3) Write-only mode
This mode transfers the 2340 bytes of header, subheader and user data within one sector to the user area
of the external DRAM. When a form1 sector is input, error detection and correction processing is
performed and then the data is transferred to the buffer memory. When a form2 sector is input, the data is
transferred as is.
– 20 –
CXD1852Q
CD-DSP Input Signal Formats
1) 32-bit slot, MSB first, BCKMOD1, 0 = 00, LSBFST = 0
LRCI
Lch
Rch
0
15 16
31
BCKI
MSB
DATI
LSB MSB
D15 D14 D13 D12 D11 D10 D9
C2PO
D8
D7
Upper
D6
D5 D4
D3
D2
D1
LSB
D0 D15 D14 D13 D12 D11 D10
Lower
D9 D8
D7
Upper
D6
D5
D4
D3 D2
D1
D0
Lower
2) 32-bit slot, LSB first, BCKMOD1, 0 = 00, LSBFST = 1
LRCI
Lch
Rch
0
15 16
31
BCKI
LSB
DATI
D0
C2PO
MSB LSB
D1
D2
D3
D4
D5 D6
D7
D8
Upper
D9 D10 D11 D12 D13 D14 D15
D0 D1
Lower
MSB
D2
D3
D4
D5
D6 D7
D8
Upper
D9 D10 D11 D12 D13 D14 D15
Lower
3) 48-bit slot, MSB first, BCKMOD1, 0 = 01, LSBFST = 0
Lch
LRCI
Rch
0
23 24
47
BCKI
MSB
LSB
MSB
LSB
DATI
D15 D14D13D12 D11D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
C2PO
Upper
Lower
D15 D14D13 D12D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Upper
– 21 –
Lower
CXD1852Q
4) 48-bit slot, LSB first, BCKMOD1, 0 = 01, LSBFST = 1
Lch
LRCI
Rch
0
23 24
47
BCKI
LSB
MSB
LSB
MSB
DATI
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10D11D12 D13D14 D15
C2PO
Upper
Lower
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10D11 D12D13 D14D15
Upper
Lower
5) 64-bit slot, MSB first, BCKMOD1, 0 = 10, LSBFST = 0
LRCI
Lch
Rch
0
31 32
63
BCKI
MSB
LSB
don't care
DATI
MSB
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
C2PO
LSB
don't care
Upper
Lower
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Upper
Lower
6) 64-bit slot, LSB first, BCKMOD1, 0 = 10, LSBFST = 1
Lch
LRCI
Rch
0
31 32
63
BCKI
LSB
DATI
MSB
don't care
LSB
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
C2PO
Upper
MSB
don't care
Lower
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Upper
– 22 –
Lower
CXD1852Q
4-4. System Decoder Function
• The MPEG1 system layer (ISO/IEC 11172-1) is decoded, the audio and video bit streams are separated, and
each bit stream is transferred to the respective bit stream buffer.
• The MPEG1 bit stream input can be selected from either the built-in CD-ROM decoder or the host interface.
• The system decoder has a 128-word (256-byte) FIFO for the bit stream input.
• Audio and video sync playback are controlled according to the time stamp within the bit stream.
4-5. Video Decoder Function
• The MPEG1 video layer (ISO/IEC 11172-2) is decoded. This function supports the range where
constrained_parameter_flag = "1" and video CD high resolution still picture.
• Video CD high resolution still picture (NTSC, PAL) can be decoded with a single external 4-Mbit DRAM.
• Special decoding functions are as follows. Slow playback, fast forward and other modes can be realized by
combining these functions.
I-Play: Only I-Pictures are decoded.
Still (Pause): Decoding is paused.
1 Frame Play: Only one frame (picture) is decoded.
IP-Play: Only I and P-Pictures are decoded.
IPB-Play: Alternate frames of continuous B-Pictures and all I and P-Pictures are decoded.
• This function supports digest play.
• The various information in the bit stream is loaded to the on-memory register area within the external DRAM.
4-6. Video Post Processor and Sync Generator Functions
• The image data output format can be selected from 24-bit RGB, 24-bit YCbCr and 16-bit YCbCr. See the
following page.
• Fade in and fade out are allowed.
• Image enlargement and reduction are allowed.
• The CXD1852Q contains an OSD color table and selector, and OSD display is achieved by inputting the
OSD character signal.
• The video sync signal can be generated using the built-in sync generator. Image data can also be output in
sync with an externally input video sync signal.
– 23 –
CXD1852Q
DCLK
HSYNC
R0 to 7
R (n)
R (n + 1)
R (0)
R (1)
R (2)
R (3)
G0 to 7
G (n)
G (n + 1)
G (0)
G (1)
G (2)
G (3)
B0 to 7
B (n)
B (n + 1)
B (0)
B (1)
B (2)
B (3)
24-bit RGB output format
DCLK
HSYNC
Y0 to 7
Y (n)
Y (n + 1)
Y (0)
Y (1)
Y (2)
Y (3)
Cb0 to 7
Cb (n)
Cb (n + 1)
Cb (0)
Cb (1)
Cb (2)
Cb (3)
Cr0 to 7
Cr (n)
Cr (n + 1)
Cr (0)
Cr (1)
Cr (2)
Cr (3)
24-bit YCbCr output format
DCLK
HSYNC
Y0 to 7
Y (n)
Y (n + 1)
Y (0)
Y (1)
Y (2)
Y (3)
C0 to 7
Cb (n)
Cr (n)
Cb (0)
Cr (0)
Cb (2)
Cr (2)
16-bit YCbCr output format
Note)
• The subscript (i) indicates the data for pixel i.
• The above timing charts show the timing when the pixel data output is synchronized with the fall of DCLK.
The pixel data output can also be synchronized with the rise of DCLK.
– 24 –
CXD1852Q
4-7. Audio Decoder Function
•
•
•
•
MPEG audio stream decoding is performed for MPEG1 standard (ISO/IEC 11172-3) layer 1 and layer 2.
Monaural, dual, stereo and joint stereo decoding modes are supported.
All MPEG1 standard sampling frequencies (32kHz, 44.1kHz, 48kHz) are supported.
All MPEG1 standard bit rates are supported.
Layer 1: 32Kbps (monaural/stereo) to 448Kbps (monaural/stereo)
Layer 2: 32Kbps (monaural) to 384Kbps (stereo)
• The audio decoder's audio interface output port is equipped with a PCM audio output which outputs decoded
audio data in bit serial format and a digital audio interface output (digital out). The audio interface is set by
setting the internal registers.
1) LRCK and BCK generation
The LR clock and bit clock can be generated by frequency dividing the clock input from external pins XTLI
or FSXI. The generated clocks are output from the BCKO and LRCO pins, respectively. LRCO and BCKO
can be output in the desired polarity. Also, the number of slots per sample supports the three types of 32,
48 and 64 bit clocks/LRCK.
2) PCM audio output format
The PCM audio output format can be set to any of the following combinations to allow connection with a
wide range of 1-bit D/A converters.
16-bit word length, MSB first or LSB first, frontward truncation or rearward truncation
18-bit word length, MSB first or LSB first, frontward truncation or rearward truncation
20-bit word length, MSB first or LSB first, frontward truncation or rearward truncation
24-bit word length, MSB first or LSB first, frontward truncation or rearward truncation
3) Digital out format
The digital out output format supports the type2, form1 format for consumer use. The output word length
can be selected from 16, 18, 20 or 24 bits.
4) Decoded channel assignment
Channels 1 and 0 of the audio sample obtained by decoding the MPEG audio stream can be assigned to
the L and R channel outputs in any combination.
5) Audio mute
The audio output contains a zero-cross mute circuit. Zero-cross detection is performed for 44 sample
sections (approximately 0.1ms when fs = 44.1kHz), and if zero-cross is not detected, the output is forcibly
muted.
6) Attenuator
The audio output contains an attenuator circuit. Attenuation of –12dB can be obtained by setting the
internal register.
7) CD-DA output mode
When playing back a CD-DA disc, the data input from the CD-DSP can be output directly from the PCM
audio output (DATO) and the digital audio interface output port (DOUT). Output ports LRCO and BCKO can
also select and output the clock inputs LRCI and BCKI from the CD-DSP.
– 25 –
CXD1852Q
PCM Audio Output Formats
1) 64-bit slot, frontward truncation, LSB first, OSLT1, 0 = 10, OTRUNK = 1, OLSBFST = 1
LRCO
Lch
Rch
0
31 32
63
BCKO
LSB
LSB
MSB
MSB
DATO
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
DAL1, 0 = 11
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
DAL1, 0 = 10
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
DAL1, 0 = 01
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
DAL1, 0 = 00
2) 64-bit slot, rearward truncation, LSB first, OSLT1, 0 = 10, OTRUNK = 0, OLSBFST = 1
Lch
LRCO
0
Rch
31 32
63
BCKO
LSB
MSB
LSB
MSB
DATO
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
DAL1, 0 = 11
DAL1, 0 = 10
DAL1, 0 = 01
DAL1, 0 = 00
LSB/MSB first setting
OLSBF = 1: set to LSB first
OLSBF = 0: set to MSB first
Data word length setting
DAL1, 0 = 11: 24 bits
DAL1, 0 = 10: 20 bits
DAL1, 0 = 01: 18 bits
DAL1, 0 = 00: 16 bits
– 26 –
CXD1852Q
3) 48-bit slot, frontward truncation, LSB first, OSLT1, 0 = 01, OTRUNK = 1, OLSBFST = 1
Lch
LRCO
Rch
0
23 24
LSB
MSB LSB
47
BCKO
MSB
DATO
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12D13 D14D15 D16D17 D18D19 D20D21 D22D23 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10D11 D12D13 D14D15 D16D17 D18 D19D20 D21D22 D23
DAL1, 0 = 11
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12D13 D14D15 D16D17 D18D19
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10D11 D12D13 D14D15 D16D17 D18 D19
DAL1, 0 = 10
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12D13 D14D15 D16D17
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10D11 D12D13 D14D15 D16D17
DAL1, 0 = 01
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12D13 D14D15
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10D11 D12D13 D14D15
DAL1, 0 = 00
4) 48-bit slot, rearward truncation, LSB first, OSLT1, 0 = 01, OTRUNK = 0, OLSBFST = 1
LRCO
Lch
Rch
0
23 24
LSB
MSB LSB
47
BCKO
MSB
DATO
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12D13 D14D15 D16D17 D18D19 D20D21 D22D23 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10D11 D12D13 D14D15 D16D17 D18 D19D20 D21D22 D23
DAL1, 0 = 11
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10D11 D12D13 D14D15 D16D17 D18 D19
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10D11 D12 D13D14 D15D16 D17D18 D19
DAL1, 0 = 10
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10D11 D12D13 D14 D15D16 D17
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11D12 D13D14 D15D16 D17
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10D11 D12D13 D14 D15
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11D12 D13D14 D15
DAL1, 0 = 01
DAL1, 0 = 00
LSB/MSB first setting
OLSBF = 1: set to LSB first
OLSBF = 0: set to MSB first
Data word length setting
DAL1, 0 = 11: 24 bits
DAL1, 0 = 10: 20 bits
DAL1, 0 = 01: 18 bits
DAL1, 0 = 00: 16 bits
– 27 –
CXD1852Q
5) 32-bit slot, LSB first, OSLT1, 0 = 00, OLSBFST = 1
LRCO
Lch
Rch
0
15 16
31
BCKO
LSB
DATO
D0
MSB LSB
D1
D2
D3
D4
D5 D6
D7
D8
D9 D10 D11 D12 D13 D14 D15 D0 D1
MSB
D2
D3
D4
D5
D6 D7
D8
D9 D10 D11 D12 D13 D14 D15
6) 32-bit slot, MSB first, OSLT1, 0 = 00, OLSBFST = 0
LRCO
Lch
Rch
0
15 16
31
BCKO
MSB
DATO
D15 D14 D13 D12 D11 D10 D9
LSB/MSB first setting
OLSBF = 1: set to LSB first
OLSBF = 0: set to MSB first
LSB MSB
D8
D7
D6
D5 D4
D3
D2
D1
D0 D15 D14 D13 D12 D11 D10 D9 D8
Data word length: 16 bits
– 28 –
LSB
D7
D6
D5
D4
D3 D2
D1
D0
CXD1852Q
Digital Audio Interface Output Formats
1) 24 bits/word
Parity
Channel status
User data
Validity flag
0
3
Sync
preamble
4
27 28 29 30 31
LSB
MSB
V
U
C P
2) 20 bits/word
0
3
7
4
Sync
preamble
(0) data
8
27 28 29 30 31
LSB
MSB
V
U
C P
3) 18 bits/word
0
3
9
4
Sync
preamble
(0) data
10
27 28 29 30 31
LSB
MSB
V
U
C P
4) 16 bits/word
0
3
Sync
preamble
11
4
(0) data
12
27 28 29 30 31
LSB
MSB
Data word length setting
DOL1, 0 = 11: 24 bits
DOL1, 0 = 10: 20 bits
DOL1, 0 = 01: 18 bits
DOL1, 0 = 00: 16 bits
– 29 –
V
U
C P
CXD1852Q
Package Outline
Unit: mm
120PIN QFP (PLASTIC)
31.2 ± 0.2
+ 0.1
0.15 – 0.05
28.0 ± 0.2
90
0.1
61
91
60
A
120
31
1
0.15 ± 0.1
30
0.35 ± 0.1
0.15 ± 0.1
(29.6)
0° to 10°
0.8 ± 0.2
0.8
DETAIL A
0.16 M
3.45 ± 0.25
PACKAGE STRUCTURE
PACKAGE MATERIAL
EPOXY RESIN
SONY CODE
QFP-120P-L01
LEAD TREATMENT
SOLDER PLATING
EIAJ CODE
∗QFP120-P-2828-A
LEAD MATERIAL
COPPER / 42 ALLOY
PACKAGE WEIGHT
4.9g
JEDEC CODE
– 30 –