CXD1807Q CD-G Decoder For the availability of this product, please contact the sales office. Description The CXD1807Q has functions to decode CD-G commands written in the CD subcode and write them into the DRAM to display them. It also has a built-in RGB 4-bit D/A converter. By adding 256K bits of DRAM and a video encoder, a CD graphics system can be configured. 80 pin QFP (Plastic) Functions • Real-time correction of subcode errors • Powerful protection circuit for subcode synchronization • RAM for color look-up table • Compatible with both NTSC and PAL • 4-bit DAC for RGB • 80-pin QFP Applications CD-G decoder Structure Silicon gate CMOS IC Absolute Maximum Ratings (Ta = 25°C) • Supply voltage VDD VSS–0.5 to +7.0 • Input voltage VI VSS–0.5 to VDD +0.5 • Output voltage VO VSS–0.5 to VDD +0.5 • Operating temperature Topr –20 to +75 • Storage temperature Tstg –55 to +150 V V V °C °C Recommended Operating Conditions • Supply voltage DVDD 5±0.5 AVDD 5±0.5 • Ambient temperature Ta –20 to +75 V V °C Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E94643-ST CXD1807Q Block Diagram 68, 72, 76 70, 74, 78 AVDD AVSS Buffer RAM SCOR 35 WFCK 36 SUB CODE Interface EXCK 37 Buffer RAM Manager SBSO 38 CD-G Instruction Decode 39 CDG MUTE 34 Error Correction CLK 26 DIN 27 CPU Interface VRAM Graphics Control XLT 28 46 OE1 47 WE1 48 RAS1 XRST 24 DRAM R/W Control Display Address Generation XIN 18 XOUT 17 49 CAS1 55 to A10 to A17 62 CK Gen. XTL1 20 50 XTL2 19 51 D10 to D13 53 54 INTR 15 CLUT RAM Control CLUT RAM NTSC 16 21 CBAR 22 APCJ 25 VOFF RGB Output Control SYNC Gen. FSC1 80 CBLK 75 VB 66 IRF 1 67 VRF VSYC 3 71 VG HSYC 4 D/A CSYC 5 R0 to R3 G0 to G3 B0 to B3 8, 33 2, 7, 12, 23, 32, 42, 52, 63 6, 9 to 11, 13, 14, 29 to 31, 40, 41, 43 to 45 DVDD DVSS TST0 to TSTD –2– 69 ROUT 73 GOUT 77 BOUT CXD1807Q Pin Description Pin No. Symbol I/O Description 1 CBLK O Composite blanking signal; negative logic 2 DVSS — Digital ground 3 VSYC O Vertical sync signal; negative logic 4 HSYC O Horizontal sync signal; negative logic 5 CSYC O Composite sync signal; negative logic 6 TST8 O Test pin 7 DVSS — Digital ground 8 DVDD — Digital power supply 9 TST9 O Test pin 10 TST4 I Test pin 11 TST5 I Test pin 12 DVSS — 13 TST6 I Test pin 14 TST7 I Test pin 15 INTR I Interlace/non-interlace (High/Low) switching signal 16 NTSC I NTSC/PAL (High/Low) select signal 17 XOUT O 14.31818MHz (NTSC 4fsc) crystal oscillator circuit output 18 XIN I 14.31818MHz (NTSC 4fsc) crystal oscillator circuit input 19 XTL2 O 17.734475MHz (PAL 4fsc) crystal oscillator circuit output 20 XTL1 I 17.734475MHz (PAL 4fsc) crystal oscillator circuit input 21 CBAR I Color bar output select signal; positive logic 22 APCJ I APC-adjusting input signal; positive logic 23 DVSS — 24 XRST I Reset input signal; negative logic 25 VOFF I R, G, B output mute select signal; positive logic 26 CLK I Data write clock signal from CPU 27 DIN I Serial data input signal from CPU 28 XLT I Data latch signal from CPU 29 TSTA O Test pin 30 TSTB O Test pin 31 TSTC O Test pin 32 DVSS — Digital ground 33 DVDD — Digital power supply 34 MUTE I Digital ground Digital ground Subcode data mute signal; positive logic –3– CXD1807Q Pin No. Symbol I/O Description 35 SCOR I Subcode sync signal from CD DSP; positive logic 36 WFCK I Write frame clock signal from CD DSP 37 EXCK O Subcode data readout clock signal to CD DSP 38 SBSO I Subcode data P to W serial input signal from CD DSP 39 CDG O Disc identification signal 40 TSTD O Test pin 41 TST3 I Test pin 42 DVSS — 43 TST2 I Test pin 44 TST1 I Test pin 45 TST0 I Test pin 46 OE1 O DRAM output enable signal; negative logic 47 WE1 O DRAM write enable signal; negative logic 48 RAS1 O DRAM row address strobe signal; negative logic 49 CAS1 O DRAM column address strobe signal; negative logic 50 D10 I/O DRAM data bus (LSB) 51 D11 I/O DRAM data bus 52 DVSS — Digital ground 53 D12 I/O DRAM data bus 54 D13 I/O DRAM data bus (MSB) 55 A10 O DRAM address (LSB) 56 A11 O DRAM address 57 A12 O DRAM address 58 A13 O DRAM address 59 A14 O DRAM address 60 A15 O DRAM address 61 A16 O DRAM address 62 A17 O DRAM address (MSB) 63 DVSS — Digital ground 64 N.C. — 65 N.C. — 66 IRF O Connect a resistance 15 times the output resistance. 67 VRF I Sets the full-scale value of RGB output signal. 68 AVDD1 — Analog power supply for R channel/DA converter 69 ROUT O Analog red signal output 70 AVSS1 — Analog ground for R channel/DA converter 71 VG I Digital ground Connect a power supply through an approximately 0.1µF capacitor. –4– CXD1807Q Pin No. Sumbol I/O 72 AVDD2 — Analog power supply for G channel/DA converter 73 GOUT O Analog green signal output 74 AVSS2 — Analog ground for G channel/DA converter 75 VB O Connect GND through an approximately 0.1µF capacitor. 76 AVDD3 — Analog power supply for B channel/DA converter 77 BOUT O Analog blue signal output 78 AVSS3 — Analog ground for B channel/DA converter 79 N.C. — 80 FSC1 O Description 3.58MHz (NTSC), 4.43MHz (PAL) clock output (sub carrier clock signal) –5– CXD1807Q Electrical Characteristics 1. DC Characteristics Item (VDD = 5V±10%, VSS = 0V, Topr = –20 to +75°C) Symbol Conditions Min. Typ. Operating state Supply current IDD High level input voltage (1) VIH1 Low level input voltage (1) VIL1 High level input voltage (2) VIH2 Low level input voltage (2) VIL2 High level input voltage (3) Vt1 + Low level input voltage (3) Vt1 – TTL Schmitt hysteresis Vt1 + – Vt1 – High level input voltage (4) Vt2 + Low level input voltage (4) Vt2 – CMOS Schmitt hysteresis Vt2 + – Vt2 – Input current of pull-up input (5) IIN VIN = 0V High level output voltage (6) VOH1 IOH1 = –2mA Low level output voltage (6) VOL1 IOL1 = 4mA High level output voltage (7) VOH2 IOH1 = –4mA Low level output voltage (7) VOL2 IOL1 = 8mA High level output voltage (8) VOH3 IOH1 = –6mA Low level output voltage (8) VOL3 IOL1 = 4mA Input leak current IIL1 Oscillation cell logic threshold LVth Oscillation cell high level input voltage VIH Oscillation cell low level input voltage VIL Oscillation cell feedback resistance RFB VIN = VSS or VDD Oscillation cell high level output voltage VOH IOH = –3mA Oscillation cell low level output voltage VOL IOL = 3mA Max. Unit 100 mA V 2.2 0.8 V 0.7VDD 0.3VDD 0.8 0.4 V 0.2VDD 0.6 –100 V V –240 µA V VDD–0.8 0.4 V V VDD–0.8 0.4 V V VDD–0.8 –10 0.4 V 10 µA 0.5VDD V V 0.7VDD 1M 0.3VDD V 2.5M Ω V 0.5VDD 1-1. Classification of input pins (1) TTL level input: DIN, XLT, D10 to D13 (2) CMOS level input: INTR, NTSC, SCOR, SBSO, MUTE, APCJ, VOFF, CBAR, TST0 to TST7 (3) TTL Schmitt input: CLK (4) CMOS Schmitt input: XRST, WFCK (5) Pull-up input: D10 to D13 –6– V V 0.8VDD 250k V V 2.2 –40 V 0.5VDD V CXD1807Q 1-2. Classification of output pins (6) Normal output: FSC1, CBLK, VSYC, HSYC, CSYC, A10 to A17, D10 to D13, OE1, WE1, EXCK, TST8 to TSTD (7) Powered output: CDG (8) Proportional output: RAS1, CAS1 1-3. Oscillation cell Input : XIN, XTL1 Output : XOUT, XTL2 1-4. I/O pin capacitances Item Symbol (VDD = VI = 0V, f = 1MHz) Min. Typ. Max. Unit Input pin CIN 9 pF Output pin COUT 11 pF Input/output pin CI/O 11 pF 2. AC Characteristics (VDD = 5V±10%, VSS = 0V, Topr = –20 to +75°C, Output Load = 75pF) 2-1. CPU interface (1) Write 1/Fck Twck Twck CLK DIN Tsu Th XLT Tcld Item Symbol Min. Typ. Twl Max. Unit 0.65 MHz Clock frequency Fck Clock pulse width Twck 750 ns Setup time (for CLK ↑) Tsu 300 ns Hold time (for CLK ↑) Th 300 ns CLK – XLT delay time Tcld 300 ns Latch pulse width Twl 750 ns –7– CXD1807Q 2-2. DRAM interface (1) Read (page mode) Tras Trp RAS1 Trcd Tcas Tpc CAS1 AAAAAAAAAAAAAAAAA Tasr A10 to A17 Tasc row col col Trah col row Tcah D10 to D13 Tddc Tdhc WE1 high OE1 low (2) Write (page mode) Tras Trp RAS1 Trcd CAS1 Tcas AAAAAAA AAAA AAAA AA AA AAA AA AA AAAAA Tasr A10 to A17 Tasc row Trah D10 to D13 Tpc col col col Tcah Tds Tdh WE1 OE1 Todd –8– row CXD1807Q (Tw = 1/f, f: master clock frequency) Item Min. Symbol Typ. Max. Unit ns RAS pulse width Tras 3Tw –10 RAS precharge width Trp 2Tw ns RAS – CAS delay time Trcd 2Tw ns CAS pulse width Tcas Tw ns Page mode cycle time Tpc 2Tw ns Row address setup time (for RAS, ↓) Tasr 2Tw –45 ns Row address hold time (for RAS, ↓) Trah Tw –15 ns Column address setup time (for CAS, ↓) Tasc Tw –35 ns Column address hold time (for CAS, ↓) Tcah Tw ns Data input delay time (for CAS, ↓) Tddc Data float time (relative to CAS, ↑) Tdhc 10 ns Data output setup time (for CAS, ↓) Tds Tw –50 ns Data output hold time (for CAS, ↓) Tdh Tw –15 ns Data output delay time (for OE, ↑) Todd Tw ns Tw –10 ns (3) Read modify write Trwc Tras RAS1 Trcd CAS1 AAA AA AAA AA Tcas Trah A10 to A17 row Tasr Tcah column row Tdhi Tasc in D10 to D13 Tdsi AAAA AAA AAAA AAA Tdh out Tds Twp WE1 Tcwd OE1 Tcod –9– Toeh CXD1807Q (Tw = 1/f, f: master clock frequency) Item Symbol Min. Typ. Max. Unit RAS pulse width Tras 7Tw ns Read/write cycle Trwc 9Tw ns RAS-CAS delay time Trcd 2Tw ns CAS pulse width Tcas 5Tw ns CAS-WE delay time Tcwd 4Tw ns WE pulse width Twp Tw ns OE hold time (for WE ↓) Toeh Tw ns CAS-OE delay time Tcod 2Tw ns Row address setup time (for RAS ↓) Tasr 2Tw – 45 ns Row address hold time (for RAS ↓) Trah Tw – 15 ns Column address setup time (for CAS ↓) Tasc Tw – 35 ns Column address hold time (for CAS ↓) Tcah 5Tw ns Data input setup time (for OE ↑) Tdsi 35 ns Data input hold time (for OE ↑) Tdhi 0 ns Data output setup time (for WE ↓) Tds Tw – 50 ns Data output hold time (for WE ↓) Tdh Tw – 15 ns 3. Built-in DAC Characteristics Recommended operating conditions Symbol Item AVDD1, AVDD2, AVDD3 Supply voltage Reference input voltage VRF Electrical characteristics Item Ratings Unit 4.5 to 5.5 V 0.5 to 2.0 V (VDD = 5V, VRF = 2V, R = 200Ω, Ta = 25°C) Symbol Conditions Min. Typ. Max. Unit Resolution n Differential linearity error ED –0.5 +0.5 LSB Integral linearity error EL –1.0 +1.0 LSB Full-scale output voltage VFS 1.9 2.0 2.1 V Full-scale output current IFS 10 15 mA Assured precision output voltage range VOC 2.0 2.1 V 4 0.5 – 10 – bit CXD1807Q Description of Functions 1. Pin Description 1-1. Subcode data interface Inputs subcode data and subcode sync detection signals using the following pins. These pins can be directly connected to Sony signal processing LSI for CD. 1) SCOR Inputs the signal that indicates detection of either subcode sync S0 or S1. Connect this pin to the SCOR pin of CD DSP. 2) WFCK Inputs WFCK (Write Frame Clock). Connect this pin to the WFCK pin of CD DSP. 3) EXCK Outputs the clock to read data from the SBSO pin. Connect this pin to the EXCK pin of CD DSP. 4) SBSO Serially inputs the subcode data P to W. Connect this pin to the SBSO pin of CD DSP. 5) MUTE Inputs the signal to mute subcode data inputs. This pin is in the mute state when High signal is input. 1-2. CPU interface Inputs data and sends commands to the CXD1807Q using the following pins. 1) CLK Inputs the clock to input serial data from the external CPU. 2) DIN Inputs serial data from the external CPU. 3) XLT Inputs the signal to latch serial data from the external CPU. The pin latches serial data at the falling edge of this signal. 1-3. DRAM interface The screen data are stored in the external DRAM. The DRAM read/write function is controlled using the following pins. Use a 64K × 4-bit DRAM with an access time of 100ns or less. 1) RAS1 Indicates the row address is effective. Connect this pin to the RAS pin of the external DRAM. 2) CAS1 Indicates the column address is effective. Connect this pin to the CAS pin of the external DRAM. 3) A10 to A17 (8 pins) Outputs DRAM addresses. Connect these pins to the A0 to A7 pins of the external DRAM, respectively. 4) D10 to D13 (4 pins) Inputs and outputs DRAM data. Connect these pins to the D0 to D3 pins of the external DRAM, respectively. 5) WE1 Outputs the write enable signal of DRAM. Connect this pin to the WE pin of the external DRAM. 6) OE1 Outputs the output enable signal of DRAM. Connect this pin to the OE pin of the external DRAM. – 11 – CXD1807Q 1-4. Sync signal generation Various sync signals are output from the following pins by dividing the clock frequency. 1) INTR Switches either interlace or non-interlace to display the image. The interlace display selected for High. 2) NTSC Inputs the signal for selecting either NTSC or PAL mode to output the sync signal. The NTSC mode selected for High. 3) FSC1 Outputs the signal with a quarter frequency of clock input to the XIN pin (NTSC) or to the XTL1 pin (PAL). This signal has the same frequency as the color signal subcarrier. 4) CBLK Outputs the composite blanking signal. Switched to Low during the blanking period. 5) VSYC Outputs the vertical sync signal. Negative logic. 6) HSYC Outputs the horizontal sync signal. Negative logic. 7) CSYC Outputs the composite sync signal. Negative logic. 1-5. RGB data output 1) VOFF Mute input for R, G, and B outputs. When this pin is set to High, all the screens for the RGB output show the color set by the external CPU; the initial color setting is blue. 2) CBAR When this pin is set to High, a color bar pattern is output from the RGB pin; the bar width varies with the color. 3) APCJ When this pin is set to High, a black-and-white cross-hatch screen is output from the RGB pin. 4) ROUT The red data analog output. It can be extracted by connecting a resistor; an output resistance of 200Ω should be connected. 5) GOUT The green data analog output. It can be extracted by connecting a resistor; an output resistance of 200Ω should be connected. 6) BOUT The blue data analog output. It can be extracted by connecting a resistor; an output resistance of 200Ω should be connected. 7) VB Connect this pin to ground through a capacitor of approximately 0.1µF. 8) IRF Connect a resistor equal to 15 times the RGB signal output resistance (3kΩ resistance). 9) VRF Sets the full-scale output value through external resistance dividing. 10) VG Connect this pin to a power supply through a capacitor of approximately 0.1µF. – 12 – CXD1807Q 1-6. Clock 1) XIN, XOUT In the NTSC mode, input the master clock (14.31818MHz) of this LSI. An oscillation circuit can be made by connecting X'TAL to the XIN and XOUT pins. (The capacitor values depend on the crystal oscillator.) When not used, XIN should be connected to GND. 2) XTL1, XTL2 In the PAL mode, input the master clock (17.734475MHz) of this LSI. An oscillation circuit can be made by connecting the X'TAL to the XTL1 and XTL2 pins. (The capacitor values depend on the crystal oscillator.) When not used, XTL1 should be connected to GND. 1-7. Others 1) XRST Reset input. When this pin is set to Low, this LSI is reset. 2) CDG The output goes to High after detection of a subcode input CD-G command. This signal is cleared by a reset input from the XRST pin. 3) TST0 to TSTD Test pins. (These pins used for the shipping test of the LSI.) Fix the TST0 to TST7 pins to Low. 2. CPU Interface Each command can be input to this LSI by inputting address or data to the three pins; DIN, XLT and CLK, with the timing shown in Fig. 1. Description of Each Command The following explains the various functions of each command. The relations between the address and data of each command are summarized in Table 1. 2-1. Color setting commands for VOFF (address = CH) The VOFF pin can make the screen monochromatic; the color then used is set using this command. D7 D6 D5 D4 RGB select (MSB) D3 D2 colour data D1 D0 — — The color is set using 4 bits for each of R, G and B. RGB select is used to select which of the colors R, G or B is to be set. D7 D6 Color selected 0 0 Red 0 1 Green 1 0 Blue 1 1 Don't care On reset, the values Red=[0000], Green=[0000], Blue=[1111] are set. – 13 – CXD1807Q 2-2. Graphic channel setting command (address = DH) This command sets and releases each of the 16 graphic channels. D7 D6 D5 D3 D2 D1 D0 Channel ON — — — D4 (MSB) Channel No. (1) Channel ON High ... The channel selected by the channel No. is set to High. Low ... The channel selected by the channel No. is reset to Low. Of the CD-G commands, the Write FONT and EOR FONT commands are executed only when the channel No. for those commands is set. On reset, only CH0 and CH1 can be set and the others are released. Fig. 1. CPU interface data format CLK DIN D0 D1 D2 D3 D4 D5 D6 D7 A0 A1 MSB LSB A2 A3 XLT LSB Address Data Table 1. List of CPU commands Register name Command Address Data 1 A3 A2 A1 A0 6 Reserved 0 1 1 0 7 Reserved 0 1 1 1 8 Reserved 1 0 0 0 9 Reserved 1 0 0 1 A Reserved 1 0 1 0 B Reserved 1 0 1 1 C Color setting for VOFF 1 1 0 0 D Graphic channel setting 1 1 0 1 E Reserved 1 1 1 0 F Reserved 1 1 1 1 – 14 – D7 D6 RGB Select D5 Data 2 D4 D3 D2 Color Data Color Data (MSB 2bit) (LSB 2bit) Channel No. ch-ON — D1 D0 — — — — RESET CXD2500BQ Microcomputer 38 SBSO 64 RAS1 15 21 VRF 67 CSYC 5 FSC1 80 IRF 66 VG 71 BOUT 77 GOUT 73 ROUT 69 75 DVSS D10 to 13 50, 51, 53, 54 16 DVDD X' tal 14.31818MHz 17 18 CXD1807Q A10 to 17 46 55 to 62 OE1 AVSS AVDD AVSS 3kW 200W B G R 17 CXA1645P/M 10 6 4 3 2 Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. 24 XRST 34 MUTE 28 XLT 27 DIN 26 CLK 37 EXCK 36 WFCK 62 65 35 SCOR CAS1 XIN WE1 XOUT 63 49 47 NTSC – 15 – INTR 48 CBAR 64k × 4bit DRAM VB Application Circuit (NTSC mode) CXD1807Q 262H (262.5H) – 16 – 25H (25.5) H 3H 25H (25.5) H 17H 192H BLANK BORDER 288dot × 192H DISPLAY AREA ) Interlace display inside parentheses. ( AAAAAAAAAAAAAA AAAAAAAAAAAAAA AAAAAAAAAAAAAA AAAAAAAAAAAAAA AAAAAAAAAAAAAA AAAAAAAAAAAAAA AAAAAAAAAAAAAA AAAAAAAAAAAAAA AAAAAAAAAAAAAA AAAAAAAAAAAAAA AAAAAAAAAAAAAA AAAAAAAAAAAAAA AAAAAAAAAAAAAA AAAAAAAAAAAAAA AAAAAAAAAAAAAA AAAAAAAAAAAAAA AAAAAAAAAAAAAA AAAAAAAAAAAAAA AAAAAAAAAAAAAA AAAAAAAAAAAAAA AAAAAAAAAAAAAA 68d VSYNC HSYNC Fig.2. NTSC Screen Composition 44d 455dot 288d 45d 10d CXD1807Q 312H (312.5H) 22.5H – 17 – 2.5H 47H (47.5) H 192H 48H (48.5) H VSYNC HSYNC BLANK 94d Fig. 3. PAL Screen Composition BORDER 84d 288d 288dot × 192H DISPLAY AREA 567dot ( ) Interlace display inside parentheses. 88d 13d CXD1807Q CXD1807Q Package Outline Unit: mm 80PIN QFP (PLASTIC) 23.9 ± 0.4 + 0.1 0.15 – 0.05 + 0.4 20.0 – 0.1 64 0.15 41 65 16.3 17.9 ± 0.4 + 0.4 14.0 – 0.1 40 A + 0.2 0.1 – 0.05 25 1 24 0.8 0.12 M + 0.15 0.35 – 0.1 + 0.35 2.75 – 0.15 0° to 10° DETAIL A PACKAGE STRUCTURE SONY CODE QFP-80P-L01 EIAJ CODE ∗QFP080-P-1420-A JEDEC CODE PACKAGE MATERIAL EPOXY RESIN LEAD TREATMENT SOLDER PLATING LEAD MATERIAL COPPER / 42 ALLOY PACKAGE WEIGHT 1.6g – 18 – 0.8 ± 0.2 80