CXD1196AR
CD-ROM DECODER
For the availability of this product, please contact the sales office.
Description
The CXD1196AR is a CD-ROM decoder LSI with a
built-in ADPCM decoder.
Features
• CD-ROM, CD-I and CD-ROM XA format
compatible
• Real time error correction
• Double speed playback compatible
(when VDD=5.0±10 %)
• Can be connected to a standard SRAM up to 32
Kbytes (256 Kbits).
• All audio output sampling frequency : 132.3 kHz
(Built-in oversampling filter)
• Built-in de-emphasis digital filter
• Capable of VDD 3.5 V operation
Applications
CD-ROM drive
Structure
Silicon gate CMOS IC
80 pin LQFP (Plastic)
Absolute Maximum Ratings (Ta=25 °C)
• Supply voltage
VDD
VSS –0.5 to +7.0
V
• Input voltage
VI
VSS –0.5 to VDD +0.5 V
• Output voltage
VO
VSS –0.5 to VDD +0.5 V
• Operating temperature
Topr
–20 to +75
°C
• Storage temperature
Tstg
–55 to +150
°C
Recommended Operating Conditions
• Supply voltage
VDD +3.5 to +5.5 (+5.0 Typ.) V
• Operating temperature
Topr
–20 to +75
°C
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
—1—
E92128B78-TE
CXD1196AR
Block Diagram
MAO-MA14
XMOE XMWR MDBO-MDB7
3
5-11.13-20
4
24-31
69
DO-D7
DMA FIFO
ADDRESS GEN
78
DMA
SEQUENCER
64 XRD
CPU I/F
65 XWR
66 XCS
PRIORITY
RESOLVER
68 AO
67 INT
44 INTP
C2PO 34
BCLK
36
DATA
37
LRCK
38
SYNDROME GEN
59
CPU DMA
53 XDAC
SYNC CONTROL
GALOIS FIELD
XRST
51 DRO
DESCRAMBLER
COP I/F
ADPCM
DECODER
ECC
CORRECTOR
45 WCKO
DAC
I/F
CLOCK GEN
DIGITAL
FILTER
55
54
57
XTL1 XTL2 CLK
2.12.23.32.42.52.63.72
33.73
35
GND
VDD
EMP
—2—
46 LRCO
47 DATO
48 BCKO
50 MUTE
CXD1196AR
Pin Description
No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
Symbol
TD7
GND
XMOE
XMWR
MA0
MA1
MA2
MA3
MA4
MA5
MA6
GND
MA7
MA8
MA9
MA10
MA11
MA12
MA13
MA14
TD6
TD5
GND
MDB0
MDB1
MDB2
MDB3
MDB4
MDB5
MDB6
MDB7
GND
VDD
C2PO
EMP
BCLK
DATA
LRCK
TD4
TD3
I/O
I/O
—
O
O
O
O
O
O
O
O
O
—
O
O
O
O
O
O
O
O
I/O
I/O
—
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
—
—
I
I
I
I
I
I/O
I/O
Description
Test pin
Ground pin
Buffer memory output enable negative logic signal
Buffer memory write enable negative logic signal
Buffer memory address (LSB)
Buffer memory address
Buffer memory address
Buffer memory address
Buffer memory address
Buffer memory address
Buffer memory address
Ground pin
Buffer memory address
Buffer memory address
Buffer memory address
Buffer memory address
Buffer memory address
Buffer memory address
Buffer memory address
Buffer memory address (MSB)
Test pin
Test pin
Ground pin
Buffer memory data bus (LSB)
Buffer memory data bus
Buffer memory data bus
Buffer memory data bus
Buffer memory data bus
Buffer memory data bus
Buffer memory data bus
Buffer memory data bus (MSB)
Ground pin
Power supply pin
C2 pointer positive logic signal from CD player
Emphasis positive logic signal from CD player
Bit clock signal from CD player
Data signal from CD player
LR clock signal from CD player
Test pin
Test pin
—3—
CXD1196AR
No.
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
Symbol
TD2
GND
TD1
INTP
WCKO
LRCO
DATO
BCKO
N. C
MUTE
DRQ
GND
XDAC
XTL2
XTL1
TD0
CLK
TDIO
XRST
TA3
TA2
TA1
GND
XRD
XWR
XCS
INT
A0
D7
D6
D5
GND
VDD
D4
D3
D2
D1
D0
TA0
N. C
I/O
I/O
—
I/O
I
O
O
O
O
—
O
O
—
I
O
I
I/O
O
I
I
I
I
I
—
I
I
I
O
I
I
I
I
—
—
I
I
I
I
I
I
—
Description
Test pin
Ground pin
Test pin
INT pin polarity control signal
Word clock signal to DA converter
LR clock signal to DA converter
Data signal to DA converter
Bit clock signal to DA converter
Mute positive logic signal
DMA request positive logic signal
Ground pin
Acknowledge negative logic signal for DRQ
Crystal oscillator circuit output pin
Crystal oscillator circuit input pin
Test pin
Clock with 1/2 frequency of XTL1
Test pin
Chip reset negative logic signal
Test pin
Test pin
Test pin
Ground pin
CPU register read strobe negative logic signal
CPU register write strobe negative logic signal
Chip select negative logic signal from CPU
Interrupt request signal to CPU
CPU address signal
CPU data bus (MSB)
CPU data bus
CPU data bus
Ground pin
Power supply pin
CPU data bus
CPU data bus
CPU data bus
CPU data bus
CPU data bus (LSB)
Test pin
—4—
CXD1196AR
Electrical Characteristics
DC characteristics
Item
TTL input level pin (∗1)
input voltage H level
TTL input level pin (∗1)
input voltage L level
CMOS input level pin (∗2)
input voltage H level
CMOS input level pin (∗2)
input voltage L level
TTL schmitt input level pin (∗3)
input voltage H level
TTL schmitt input level pin (∗3)
input voltage L level
TTL schmitt input level pin (∗3)
input voltage hysteresis
CMOS schmitt input level pin (∗4)
input voltage H level
CMOS schmitt input level pin (∗4)
input voltage L level
CMOS schmitt input level pin (∗4)
input voltage hysteresis
Pull-up resistor provided input pin
(∗5) input current
Pull-down resistor provided input pin
(∗6) input current
Pull-up resistor provided bidirectional
pin (∗7) input current
Output voltage H level (∗8)
Output voltage L level (∗8)
Input leak current (∗9)
Oscillation cell (∗10) input voltage
H level
Oscillation cell input voltage L level
Oscillation cell logic threshold value
Oscillation cell feedback
resistance value
Oscillation cell output voltage H level
Oscillation cell output voltage L level
(VDD=5 V±10 %, VSS=0 V, Topr=–20 to 75 °C)
Symbol
Conditions
Min.
Typ.
Max.
2.2
VIH1
V
0.8
VIL1
0.7 VDD
VIH2
0.3 VDD
2.2
0.8
0.4
VIH4
V
V
V
0.8 VDD
VIL4
0.2 VDD
VIH4
–VIL4
V
V
VIL3
VIH3
–VIL3
V
V
VIL2
VIH3
Unit
0.6
V
V
IIL1
VIN=0 V
–40
–100
–240
µA
IIL2
VIN=0 V
40
100
240
µA
IIL3
VIN=0 V
–90
–200
–440
µA
0.4
40
V
V
µA
VOH1
VOL1
IIL2
VOH=–2 mA
IOL=4 mA
VDD–0.8
–40
VIH4
0.7 VDD
VIL4
LVTH
V
0.3 VDD
V
V
2M
Ω
0.5 VDD
V
V
0.5 VDD
RFB
VIN=VSS or VDD
VOH2
VOL2
IOH=–3 mA
IOL=3 mA
—5—
500 K
1M
0.5 VDD
CXD1196AR
DC characteristics
Item
TTL input level pin (∗1)
input voltage H level
TTL input level pin (∗1)
input voltage L level
CMOS input level pin (∗2)
input voltage H level
CMOS input level pin (∗2)
input voltage L level
TTL schmitt input level pin (∗3)
input voltage H level
TTL schmitt input level pin (∗3)
input voltage L level
TTL schmitt input level pin (∗3)
input voltage hysteresis
CMOS schmitt input level pin (∗4)
input voltage H level
CMOS schmitt input level pin (∗4)
input voltage L level
CMOS schmitt input level pin (∗4)
input voltage hysteresis
Pull-up resistor provided input pin
(∗5) input current
Pull-down resistor provided input pin
(∗6) input current
Pull-up resistor provided bidirectional
pin (∗7) input current
Output voltage H level (∗8)
Output voltage L level (∗8)
Input leak current (∗9)
Oscillation cell (∗10) input voltage
H level
Oscillation cell input voltage L level
Oscillation cell threshold value
Oscillation cell feedback
resistance value
Oscillation cell output voltage H level
Oscillation cell output voltage L level
(VDD=3.5 V, VSS=0 V, Topr=–20 to 75 °C)
Symbol
Conditions
Min.
Typ.
Max.
2.2
VIH1
V
0.6
VIL1
0.7 VDD
VIH2
0.3 VDD
2.2
0.6
0.3
VIH4
V
V
V
0.8 VDD
VIL4
0.2 VDD
VIH4
–VIL4
V
V
VIL3
VIH3
–VIL3
V
V
VIL2
VIH3
Unit
0.5
V
V
IIL1
VIN=0 V
–10
–25
–60
µA
IIL2
VIN=0 V
10
25
60
µA
IIL3
VIN=0 V
–20
–50
–110
µA
0.4
40
V
V
µA
VOH1
VOL1
IIL2
VOH=–1.6 mA
IOL=3.2 mA
VDD–0.8
–40
VIH4
0.7 VDD
VIL4
LVTH
V
0.3 VDD
V
V
5M
Ω
0.5 VDD
V
V
0.5 VDD
RFB
VIN=VSS or VDD
VOH2
VOL2
IOH=–1.3 mA
IOL=1.3 mA
—6—
1.2 K
2.5 M
0.5 VDD
CXD1196AR
∗1.
∗2.
∗3.
∗4.
∗5.
∗6.
∗7.
∗8.
∗9.
∗10.
D7 to 0, MDB7 to 0, TD7 to 0
DATA, LRCK, C2PO, EMP, INTP, TDIO, TA3 to 0
XWR, XRD, XCS, A0, XDAC
BCLK, XRST
XDAC, TA3 to 0
C2PO, INTP
D7 to 0, MDB7 to 0, TD7 to 0
All output pins except XTL2
All input pins except ∗7
input : XTL1, output : XTL2
Input/Output Capacitance
Item
Input pin
Output pin
Input/Output pin
(VDD=VI=0 V, f=1 MHz)
Symbol
CIN
COUT
COUT
Min.
—7—
Typ.
Max.
9
11
11
Unit
pF
pF
pF
CXD1196AR
AC Characteristics
(VDD=5 V±10 %, VSS=0 V, Topr=–20 to 75 °C, Output load=50 pF)
The values in parentheses in the table are those obtained when VDD=3.5 V, VSS=0 V, Topr=–20 to 75 °C, and
output load=50 pF.
Values without parentheses are common to VDD=5 V±10 % and 3.5 V.
1. CPU interface
(1) Read
AO
Thar
XCS
Trrl
XRD
D7-D0
Tsar
Tdrd
Tfrd
Item
Address setting time (with respect to XCS & XRD ↓)
Address holding time (with respect to XCS & XRD ↑)
Data delay time (with respect to XCS & XRD ↓)
Data float time (with respect to XCS & XRD ↑)
L level XRD pulse width
Symbol
Tsar
Thar
Tdrd
Tfrd
Trr1
Min.
30 (70)
20 (50)
Typ.
Max.
120 (200)
20 (40)
0
150 (250)
Unit
ns
ns
ns
ns
ns
(2) Write
AO
XCS
Twwl
Thaw
XWR
D7-D0
Tsdw
Thdw
Tsaw
Item
Address setting time (with respect to XCS & XWR ↓)
Address holding time (with respect to XCS & XWR ↑)
Data setting time (with respect to XCS & XWR ↓)
Data holding time (with respect to XCS & XWR ↑)
L level XWR pulse width
Symbol
Tsaw
Thaw
Tsdw
Thwd
Twwl
—8—
Min.
30 (70)
20 (50)
50 (70)
20 (30)
70 (100)
Typ.
Max.
Unit
ns
ns
ns
ns
ns
CXD1196AR
(3) DMA
DRQ
Tdar2
Tdar1
XDAC
Trrl
XRD
Thac
Tsac
D7-D0
Tdrd
Tfrd
Item
DRQ fall time (with respect to XDAC ↓)
DRQ rise time (with respect to XDAC ↑)
XDAC setting time (with respect to XRD ↓)
XDAC holding time (with respect to XRD ↑)
Data delay time (with respect to XRD ↓)
Data float time (with respect to XRD ↑)
L level XRD pulse width
Symbol
Tdar1
Tdar2
Tsac
Thac
Tdrd
Tfrd
Trrl
—9—
Min.
Typ.
Max.
50 (120)
50 (120)
10 (30)
10 (30)
0
150 (250)
120 (200)
20 (40)
Unit
ns
ns
ns
ns
ns
ns
ns
CXD1196AR
2. SRAM interface
(1) Read
MA14-MA0
Tsao
Toel
Thao
XMOE
MDB7-MDB0
Tsdo
Item
Address setting time (with respect to XMOE ↓)
Address holding time (with respect to XMOE ↑)
Data setting time (with respect to XMOE ↑)
Data holding time (with respect to XMOE ↑)
L level XMOE pulse width
Symbol
Tsao
Thao
Tsdo
Thdo
Toel
Thdo
Min.
T1–30
T1–10
50 (100)
10 (20)
Typ.
Max.
Unit
ns
ns
ns
ns
ns
Max.
Unit
ns
ns
ns
ns
ns
2 • T1
(2) Write
MA14-MA0
Tsamw
Tmwl
Thamw
XMWR
MDB7-MDB0
Tdmw
Tfmw
Item
Address setting time (with respect to XMWR ↓)
Address holding time (with respect to XMWR ↑)
Data delay time (with respect to XMWR ↓)
Data float time (with respect to XMWR ↑)
L level XMWR pulse width
Symbol
Tsamw
Thamw
Tdmw
Tfmw
Tmwl
{
Min.
T1–30
T1–10
Typ.
0
10
2 • T1
59 ns : XSLOW = ‘H’
238 ns : XSLOW = ‘L’
Note that XSLOW is bit 7 of DRVIF register.
When XSLOW = ‘H’ , make sure that the CXD1196AR is connected to an SRAM with an access time of
less than 120 ns.
When XSLOW = ‘L’ , make sure that the CXD1196AR is connected to an SRAM with an access time of less
than 320 ns.
T1=
—10—
CXD1196AR
3. DSP Interface for CD
BCKRED= “H”
Tbck
Tbck
BCLK
DATA
Tsb1
Thb1
LRCK
C2PO
Thb2
Tsb2
BCKRED= “L”
Tbck
Tbck
BCLK
DATA
Tsb1
Thb1
LRCK
C2PO
Thb2
Item
BCLK frequency
BCLK pulse width
Data setting time (with respect to BCLK)
Data holding time (with respect to BCLK)
LRCK, C2PO setting time (with respect to BCLK)
LRCK, C2PO holding time (with respect to BCLK)
Symbol
Fbck
Tbck
Tsb1
Thb1
Tsb2
Thb2
—11—
Thb2
Min.
85
50
50
50
50
Typ.
Max.
5.7
Unit
MHz
ns
ns
ns
ns
ns
CXD1196AR
4. DAC interface
Tbco
Tbco
BCKO
DATO
Tsbo
Thbo
WCKO
LRCO
Thbc
Item
BCKO frequency
BCKO pulse width
DATO, WCKO, LRCO setting time
(with respect to BCKO ↑)
DATO, WCKO, LRCO holding time
(with respect to BCKO ↑)
Tsbo
Symbol
Fbco
Tbco
Min.
50
Unit
MHz
ns
Tsbo
30
ns
Thbo
30
ns
—12—
Typ.
8.4672
Max.
CXD1196AR
5. XTL1 pin, XTL2 pins
(1) Self-excited oscillation
Item
Symbol
Fmax
Oscillation frequency
Min.
Typ.
16.9344
Max.
Unit
MHz
(2) When pulses are to be input to XTL1 pin
Tw
Twhx
Twlx
Vihx
Vihx∗0.9
VDD/2
Vihx∗0.1
Vilx
Tr
Item
H level pulse width
L level pulse width
Pulse interval
Input H level
Input L level
Rise time
Fall time
Tf
Symbol
Twhx
Twlx
Tw
Vihx
Vilx
Tr
Tf
Note) Synchronize XTL1 clock with DSP clock for CD.
(Use the clock generated from the same oscillator unit.)
—13—
Min.
20
20
Typ.
Max.
59
VDD–1.0
0.8
15
15
Unit
ns
ns
ns
V
V
ns
ns
CXD1196AR
Description of Functions
1. Description of Pins
1.1 CD player interface
The CXD1196AR can be directly connected to digital signal processing LSIs for CD of Sony and other
company. The digital signal processing LSI for CD is referred to as a DSP for CD.
(1) DATA (DATA : Input)
Serial data stream from a CIRC LSI
(2) BCLK (Bit Clock : Input)
Bit clock signal for strobing DATA signal
(3) LRCK (LR Clock : Input)
LR clock signal indicating Lch and Rch of DATA signal
(4) C2PO (C2 Pointer : Input)
C2 pointer signal indicating that DATA input contains an error
(5) EMP (Emphasis : Input)
Emphasis indicating that the data from the DSP is emphasized. (positive logic signal)
1.2 Buffer memory interface
The CXD1196AR can be connected to a standard SRAM up to 32 Kbytes (256 Kbits).
(1) XMWR (BUFFER MEMORY WRITE : OUT)
Data write signal to buffer memory (strobe negative logic output)
(2) XMOE (BUFFER MEMORY OUTPUT ENABLE : OUT)
Data read signal to buffer memory (strobe negative logic output)
(3) MA0-14 (BUFFER MEMORY ADDRESS : OUT)
Address signals to buffer memory
(4) MDB0-7 (BUFFER MEMORY DATA BUS : BUS)
Buffer memory data bus signal pulled up by a typical 25 kΩ resistor
In an ADPCM decode playback drive, make sure that the CXD1196AR is connected to a 256 Kbit (8b ×
32 Kw, 32 Kbyte) SRAM
1.3 CPU interface
(1) XWR (CPU WRITE : Input)
Strobe signal for writing to register in chip (negative logic input)
(2) XRD (CPU READ : Input)
Strobe for reading out status of register chip (negative logic input signal)
(3) D0-7 (CPU DATA BUS : Input and output)
8-bit data bus
(4) A0 (CPU ADDRESS : Input)
CPU address signal for selecting internal register of the CXD1196AR
(5) INT (CPU INTERRUPT : Output)
Interrupt request output signal for CPU. The polarity of this signal can be controlled by the INTP pin.
(6) INTP (INTERRUPT POLARITY : Input)
This pin controls the polarity of the INT pin. In the IC, it is pulled up by a typical 50 kΩ register.
When INTP= ‘H’ or open, the INT pin goes low active.
When INTP= ‘L’ , the INT pin goes high active.
(7) XCS (CHIP SELECT : Input)
Chip select signal for CPU to select the CXD1196AR (negative logic input)
—14—
CXD1196AR
(8) DRQ (DATA REQUEST : Output)
DMA data request signal (positive logic output)
(9) XDAC (DATA ACKNOWLEDGE : Input)
The acknowledge signal for DRQ (negative logic input). In the IC, it is pulled up by a typical 50 kΩ
resistor.
1.4 DAC interface
(1) BCKO (BIT CLOCK OUTPUT : Output)
Bit clock output signal to DA converter
(2) WCKO (WORD CLOCK OUTPUT : Output)
Word clock output signal to DA converter
(3) LRCO (LR CLOCK OUTPUT : Output)
LR clock output signal to DA converter
(4) DATO (DATA OUTPUT : Output)
Data output signal to DA converter
Fig. 1.1 shows a timing chart for interface with the DA converter.
1.5 Miscellaneous
(1) MUTE (MUTE : Output)
Output H when DA data is muted
(2) XRST (RESET : Input)
Chip reset signal (negative logic input)
(3) XTL1 (X’TAI1 : Input)
(4) XTL2 (X’TAI2 : Output)
Connect a 16.9344 MHz crystal oscillator unit between XTL1 and XTL2. (The value of the capacitor
depends on the crystal oscillator unit.) Or input 16.9344 MHz clock to the XTL1 pin. For ADPCM or
CD-DA playback, the clocks of the DSP for CD and this IC must be synchronized.
(5) CLK (CLOCK : Output)
Output 8.4672 clock.
When this clock is not be used, the output of the CLK pin may be fixed at ‘L’.
1.6 Test pins
These pins are normally kept in the opened state.
(1) TD0-7 (Input/Output) : Data bus for IC test. Pulled up by a typical 25 kΩ resistor.
(2) TDIO (Input) : Input pin for IC test. Pulled up by a typical 50 kΩ resistor.
(3) TA0-3 (Input) : Input pins for IC test. Pulled up by a typical 50 kΩ resistor.
—15—
LCKO
WCKO
DATO
BCKO
16
1 2 3 4
L CH
L SB
32
Fig. 1.1 Output Format to DA Converter
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
MSB
17
R CH
64
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
MSB
49
CXD1196AR
—16—
CXD1196AR
2. Register Functions
2.1 Write register
2.1.1 Register address (REGADR) register
This register is used for selection of the internal registers.
(1) When A0 = XCS = ‘L’, the REGADR register is selected. When A0 = ‘H’ and XCS = ‘L’, the register
specified by the REGADR is selected.
(2) When the low order 4 bits of REGADR are not 0 (hex), and a register write or read is made by setting
A0 = ‘H’ and XCS = ‘L’, the low order 4 bits of REGADR are incremented.
(3) REGADR is cleared by rising edge of DMAEN bit (bit3) of the DMACTL register. (Cleared to 00 (hex).)
2.1.2 DRIVE Interface (DRVIF) register
Bit7 XSLOW (/SLOW SPEED)
‘H’ : A DMA cycle is performed in 4 clocks.
In this case, a standard SRAM with an access time of less than 120 nsec can be connected
to the CXD1196AR.
‘L’
: A DMA cycle is performed in 12 clocks. When the CXD1196R is connected to an SRAM
with a slower access time, set this bit at ‘L’. In this case, a standard SRAM with an access
time of less than 320 ns can be connected to the CXD1196AR. For operation at VDD = 3.5
V, set this bit to L.
Bit6 C2PL1ST (C2PO Ler-byte 1st)
‘H’ : To input two bytes of DATA input, each with a C2PO identifying the lower or upper byte, in
the order of the lower and upper bytes
‘L’
: To input two bytes of DATA input, each with a C2PO identifying the upper or lower byte, in
the order of the upper and lower bytes.
Here, the upper byte means the 8 (eight) upper bits including the MSB from the DSP for CD. And the lower
byte means the 8 (eight) lower bits including the LSB from the DSP for CD. For example, the minute byte
of the Header is a lower byte and the sec byte is a upper byte.
Bit5
LCHLOW (LCH LOW)
‘H’ : To determine that the data is Lch data when LRCK = ‘L’
‘L’
: To determine that the data is Lch data when LRCK = ‘H’
Bit4
BCKRED (BCLK Rising Edge)
‘H’ : To strobe DATA by the rising edge of BCLK
‘L’
: To strobe DATA by the falling edge of BCLK
Bit3, 2 BCKMD1, 0 (BCLK Mode 1, 0)
Set these bits, depending on the number of BCLK clocks output by the DSP for CD during a cycle of
WCLK.
BCKMD1
‘L’
‘L’
‘H’
Bit1
BCKMD0
‘L’
‘H’
‘X’
16BCLKs/WCLK
24BCLKs/WCLK
32BCLKs/WCLK
LSB 1ST (LSB First)
‘H’ : To connect to a DSP for CD which outputs DATA on an LSB first basis
‘L’
: To connect to a DSP for CD which outputs DATA on an MSB first basis
Bit0
CLKLOW (CLK LOW)
‘H’ : To fix CLK pin output at ‘L’
‘L’
: To output 8.4672 MHz clock from CLK pin output
The values of the individual bits of this register must be changed with the decoder in the disabled state.
Table 2.1.1 shows the values of bits of bit 6 through 1 to be set when the CXD1196AR is connected to
Sony DSPs for CD. Fig. 2.2.1 (1) through (3) show input timing charts.
—17—
CXD1196AR
Sony DSP for CD
bit6
CDL30 series
CDL35 series
CDL40 series
(48-bit slot mode)
CDL40 series
(64-bit slot mode)
DRVIF register
bit5 bit4 bit3 bit2
bit1
Timing chart
L
L
L
L
H
L
Fig. 2.1.1 (1)
L
L
H
L
H
L
Fig. 2.1.1 (2)
L
H
L
H
X
H
Fig. 2.1.1 (3)
Table 2.1.1 DRVIF Register Settings
(Note 1)
CDL30 series
CDL35 series
CDL40 series
CXD1125Q/QZ, CXD1130Q/QZ, CXD1135Q/QZ,
CXD1241Q/QZ, CXD1245Q, CXD1246Q/QZ,
CXD1247Q/QZ/R, etc.
CXD1165Q, CXD1167Q/QZ/R, etc.
CXD2500Q/QZ, etc.
2.1.3 Chip Control (CHPCTL) register
Bit7-5 RESERVED
Bit4 CHPRST (Chip Reset)
When this bit is set at ‘H’, the CXD1196AR is internally initialized. The bit setting will automatically
change to ‘L’ when the internal initialization of the CXD1196AR is completed. Therefore, there is no
need for the CPU to change the setting at ‘L’. Initialization of the CXD1196AR will be completed in
500ns after the bit has been set at ‘H’ by the CPU.
Bit3 CD-DA (CD-Digital Audio)
‘H’ : When a CD-DA disc is to be played back, this bit is set at ‘H’.
The decoder must be placed in the disabled state (DECCTL register) when this bit is set at
‘H’.
‘L’
: When a CD-ROM disc is to be played back, this bit is set at ‘L’.
Bit2 SWOPN (Sync Window Open)
‘H’ : When this bit is set at ‘H’, the window for detection of SYNC mark will open. In this case,
the SYNC protection circuit in the CXD1196AR will be disabled.
‘L’
: When this bit is set at ‘L’, the window for detection of SYNC mark will be controlled by the
SYNC protection circuit in the CXD1196AR.
Bit1 RPSTART (Repeat Correction Start)
When the DECODER is placed in the repeat correction mode, and this bit set at ‘H’, the error
correction of the current sector will begin. The bit setting will automatically change to ‘L’ when
correction begins. Therefore, there is no need for the CPU to change the setting at ‘L’.
Bit0 ADPEN (ADPCM Enable)
When the current sector is an ADPCM sector, the CPU sets this bit at ‘H’ in less than 11.5 ms after a
decoder interrupt (DECINT). When the current sector is not an ADPCM sector, the CPU changes the
bit setting at ‘L’ in less than 11.5 ms after a decoder interrupt (DECINT).
—18—
CXD1196AR
2.1.4 DECODER CONTROL (DECCTL) Register
Bit7 AUTOCI (Auto Coding Information)
‘H’ : To perform ADPCM playback according to the coding information from the drive. In this
case, the CI register need not be set.
‘L’
: To perform ADPCM playback according to the value of the CI register.
Bit6 RESERVED
Should be kept at ‘L’ at all times.
Bit5 MODESEL (Mode Select)
Bit4 FORMSEL (Form Select)
When AUTODIST = ‘L’, the sector is corrected as the following MODE and FORM.
MODESEL
‘L’
‘H’
‘H’
Bit3
Bit2-0
FORMSEL
‘L’
‘L’
‘L’
MODE1
MODE2, FORM1
MODE2, FORM2
AUTODIST (Auto Distinction)
‘H’ : Errors are corrected according to the MODE byte and FORM bit read from the drive.
‘L’
: Errors are corrected according to bit 5 MODESEL and bit4 FORMSEL.
:
DECMD 2-0 (Decoder Mode 2-0)
DECMD2
‘L’
‘L’
‘H’
‘H’
‘H’
‘H’
DECMD1
‘L’
‘H’
‘L’
‘L’
‘H’
‘H’
DECMD0
‘X’
‘X’
‘L’
‘H’
‘L’
‘H’
Decoder disable
Monitor only mode
Write only mode
Real time correction mode
Repeat correction mode
Inhibit
These bits are set at ‘L’ when the CDDA bit (bit3) of the CHPCTL register is ‘H’.
2.1.5 Interrupt Mask (INTMSK) Register
When the individual bits of this register are set at ‘H’, an interrupt request from the CXD1196AR to the CPU
is enabled in response to the corresponding interrupt status. (That is, when the interrupt status is created,
the INT pin is made active.) The value of the individual bits of the register does not affect the
corresponding interrupt status.
Bit7
Bit6
Bit5
ADPEND (ADPCM End)
When this chip has completed the ADPCM decode for a sector, if the ADPCM decode for the next
sector is not enabled, the ADPEND status is created.
DECTOUT (Decoder Time Out)
If no SYNC mark is detected during a period of 3 sectors (40.6 ms in normal speed playback mode)
after the DECODER has been set in the monitor only, and real time correction modes, the DECTOUT
status is created.
DMACMP (DMA Complete)
When DMA is ended by DMAXFRC, the DMACMP status is created.
—19—
CXD1196AR
Bit4
DECINT (Decoder Interrupt)
If a SYNC mark is detected or internally inserted during execution of the write only, monitor only and
real time correction modes by the DECODER, the DECINT status is created. When the SYNC mark
detected window is open, however, if the SYNC mark spacing is less than 2352 bytes, the DECINT
status is not created. During execution of the repeat correction mode by the DECODER, the
DECINT status is created each time a correction ends.
Bit3 CIERR (Coding Information Error)
When AUTOCI bit of DECCTL register is set at “H” and ADPCM decode playback is done, if there is
an error in a CI byte of an ADPCM sector, the CIERR status is created. ADPCM decode playback of
this sector will not be done.
Bit2-0 RESERVED
2.1.6 Clear Interrupt Status (INCTCLR) Register
When the individual bit of this register is set at ‘H’, the corresponding interrupt status is cleared. The
individual bit is automatically set at ‘L’ after the interrupt status has been cleared. Therefore, there is no
need for the CPU to change the setting at ‘L’.
Bit7 ADPEND (ADPCM End)
Bit6 DECTOUT (DECODER Time Out)
Bit5 DMACMP (DMA Complete)
Bit4 DECINT (DECODER Interrupt)
Bit3 CIERR (Coding Information Error)
Bit2-0 RESERVED
2.1.7 Coding Information (CI) Register
When ADPCM decoding is to be done by setting AUTOCI = ‘L’, the coding information is written to this
register. The bit configuration is the same as that of the coding information byte of the sub header.
2.1.8
DMA Address Counter-L (DMAADRC-L)
2.1.9 DMA Address Counter-H (DMAADRC-H)
This counter retains the address to be used by the CPU when reading data from the buffer. When the data
to be sent to the CPU is read from the buffer, the contents of the DMAADRC are output from MA0-14.
Each time data to be sent to the CPU is read from the buffer, the DMAADRC is incremented.
The CPU sets the head address of DMA in the DMAADRC before starting DMA. The CPU can read and
set the contents of the DMAADRC at any time. Do not change the contents of the DMAADRC during
execution of DMA.
—20—
CXD1196AR
2.1.10 DMAXFRC-L
2.1.11 DMA Control (DMACTL) register
Bit7 DMAXFRC11
Bit11 (MSB) of DMAXFRC (Transfer Counter)
Bit6 DMAXFRC10
bit10 of DMAXFRC
Bit5 DMAXFRC9
bit9 of DMAXFRC
Bit4 DMAXFRC8
bit8 of DMAXFRC
Bit3 DMAEN (CPU DMA Enable)
‘H’ : To enable DMA
‘L’
: To inhibit DMA
Bit2-0 RESERVED
The DMAXFRC (DMA Transfer Counter) is a counter which indicates the number of DMA transfers. Each
time the data to be transferred to the CPU is read from the buffer, the counter is decremented. When the
value of the DMAXFRC reaches 0, DMA ends. At this point, interrupt request may be output to the CPU.
When data transfer is not to be ended by DMAXFRC as in the case of data transfer in the I/O mode,
DMAXFRC should be set at 0 when data transfer is started (when DMAEN bit is set at ‘H’). The CPU can
read and set the contents of DMAXFRC at any time. During execution of DMA, do not change the contents
of DMAXFRC.
2.1.12 DRVADRC-L (Drive Address Counter-L)
2.1.13 DRVADRC-H
The DRVADRC is a counter which retains the address for writing the data from the drive to the buffer.
When the drive data is written to the buffer, the value of DRVADRC is output from MA01-14 pins. Each
time a byte of data from the drive is written to the buffer, the DRVADRC is incremented.
Before execution of the write only mode and real time correction mode of the DECODER, the CPU sets the
buffer write head address in the DRVADRC.
The CPU can read and set the contents of DRVADRC at any time. During execution of DMA, do not
change the contents of DRVADRC.
—21—
—22—
C2PO
DATA
BCLK
LRCK
C2PO
DATA
BCLK
LRCK
C2PO
DATA
BCLK
LRCK
1
1
1
2
Lch MSB
L14 L15
31 32
Rch LSB
Ro
24
Rch LSB
Ro
24
2
2
3
3
3
4
5
6
5
6
6
7
11
12
13
14
15
L15 L14 L13 L12 L11 L10
10
Lch MSB
9
L9
16
L8
17
7
8
10
11
12
13
14
15
Lch MSB
L15 L14 L13 L12 L11 L10 L9
9
L8
16
L6
19
L5
L6
18
L5
for Lower Byte
L7
17
19
for Lower Byte
L7
18
8
9
L4
20
L4
20
L3
21
L3
21
L2
22
L2
22
L1
23
L1
23
R1
Rch LSB
R0
R2
R3
R4
R6
R7
R8
for Lower Byte
R5
R9
1
LSB
1
Rch MSB
R10 R11 R12 R13 R14 R15
1
2
2
2
Lch LSB
L0
24
Lch
L0
24
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
Fig. 2.1.1 (3) CDL40 Series 64-Bit Slot Mode Timing Chart
for Upper Byte
5
8
Fig. 2.1.1 (1) CDL30 and 35 Series Timing Chart
7
Fig. 2.1.1 (2) CDL40 Series 48-Bit Slot Mode Timing Chart
for Upper Byte
4
for Upper Byte
4
3
3
3
CXD1196AR
CXD1196AR
2.2 Read register
In the descriptions of the registers STS, HDRFLG, HDR, SHDR and CMADR, what is referred to as the
current sector refers to the sector where registers are valid for a decoder interrupt (DECINT). In the monitor
only and write only modes, the sector from the DSP for CD just before a decoder interrupt is called the
current sector. In the real time correction mode and repeat correction mode, the sector that has gone
through error detection and correction is referred to as the current sector.
2.2.1
Register Address (REGADR) Register
2.2.2 DMADATA Register
When data transfer (buffer read) is to be made in the I/O mode, the CPU reads data from this register.
2.2.3 Interrupt Status (INTSTS) Register
The values of the individual bits of this register indicate the respective associated values of interrupt status.
These bits are not affected by the values of the individual bits of the INTMSK register.
Bit7 ADPEND (ADPCM End)
Bit6 DECTOUT (DECODER Time Out)
Bit5 DMACMP (DMA Complete)
Bit4 DECINT (DECODER Interrupt)
Bit3 CIERR (Coding Information Error)
2.2.4 Status (STS) Register
Bit7 DRQ (Data Request)
This bit indicates the value of the DRQ pin.
Bit6 ADPBSY (ADPCM BUSY)
This bit goes ‘H’ during ADPCM playback.
Bit5 ERINBLK (Erasure in Block)
On all the bytes of the current sector except the SYNC byte, this bit goes ‘H’ if there is one or more
bytes from the DSP for CD whose C2 pointer is ON.
Bit4 CORINH (Correction Inhibit)
When the DECCTL register is set AUTODIST bit = ‘H’, this bit goes ‘H’ if the error flag is ON in the
MODE (and FORM) byte.
Bit3 EDCOK
Indicates EDC check showed there were no errors in the current sector.
Bit2 ECCOK
Indicates there are no more errors from the Header to P parity bytes in the current sector. (In the
MODE2, FORM2 sector, this bit is treated as a DON’T CARE bit.)
Bit1 SHRTSCT (Short Sector)
Indicates the Sync Mark interval was less than 2351 bytes. On this sector, neither ECC nor EDC is
executed.
Bit0 NOSYNC
Indicates that the SYNC Mark, not detected in the predetermined position, is one internally inserted.
2.2.5 Header Flag (HDRFLG) Register
Indicates the value of the error pointer of the Header and Sub Header registers.
—23—
CXD1196AR
2.2.6 Header (HDR) Register
It is a 4-byte register indicating the Header byte of the current sector. The CPU can find the value of the
Header byte of the current sector from the Minute byte as it sets the REGADR register at X4 hex and
successively reads data.
2.2.7 Sub Header (SHDR) Register
It is a 4-byte register indicating the Sub Header byte of the current sector. The CPU can find the value of
the Sub Header byte of the current sector from the File byte as it sets the REGADR register at 08 hex and
successively reads data.
2.2.8
Current Minute Address L (CMADR-L) Register
2.2.9 Current Minute Address H (CMADR-H) Register
Indicates the buffer memory address where the Minute bytes of the current sector (after correction) is in
store.
2.2.10 MODE/FORM (MDFM) Register
Bit4-2 RMODE2-0
RMODE2 : Indicates the logic sum of the value of the high-order 6 bits of the raw MODE byte and the
pointer.
RMODE1, 0 : Respectively indicate the values of the low-order 2 bits of the raw MODE byte.
Bit1 CMODE (Correction Mode)
Bit0 CFORM (Correction Form)
These bits indicate which of the MODEs and FORMs this IC determined that the current sector was
associated with when it corrected errors.
CFORM
‘X’
‘L’
‘H’
CMODE
‘L’
‘H’
‘H’
MODE1
MODE2, FORM1
MODE2, FORM2
2.2.11 ADPCI (ADPCM Coding Information) Register
Bit7 MUTE
This bit goes ‘H’ when the DA data is muted on.
Bit6 EMPHASIS
This bit goes ‘H’ when the ADPCM data is emphasized.
Bit5 EOR (End of Record)
This bit goes ‘H’ when the Sub Mode byte bit0 = ‘H’ and there is no error in the Sub Mode byte.
Bit4 BITLNGTH (Bit Length)
This bit indicates the bit length of ADPCM playback coding information.
‘H’ : 8 bits
‘L’
: 4 bits
Bit2 FS (Sampling Frequency)
This bit indicates the ADPCM playback sampling frequency.
‘H’ : 18.9 kHz
‘L’
: 37.8 kHz
Bit0 M/S (MONO/STEREO)
This bit indicates “monaural” or “stereo” of ADPCM playback coding information.
‘H’ : Stereo
‘L’
: Monaural
—24—
CXD1196AR
2.2.12 DMAXFRC-L
2.2.13 DMAXFRC-H
2.2.14 DMAADRC-H
2.2.15 DMAADRC-H
2.2.16 DRVADRC-L
2.2.17 DRVADRC-H
REG
REGADR
A0
L
RA
X
L
L
L
bit4
RA4
bit3
RA3
bit2
RA2
bit1
RA1
bit0
RA0
RESERVED
H
X0
L
L
L
L
L
L
L
L
DRVIF
H
X1
XSLOW
C2PO
L1st
CHPCTL
H
X2
L
L
DECCTL
H
X3
X4
L
L
L
INTCLR
H
X5
BCK
MD1
CDDA
AUTO
DIST
CI
ERR
CI
ERR
LSB
1st
RPS
TART
DEC
MD1
H
L
L
L
CI
H
X6
L
BCK
RED
CHP
RST
FORM
SEL
DEC
INT
DEC
INT
BIT
L4H8
BCK
MD0
SW
OPEN
DEC
MD2
INTMSK
LCH
LOW
CLR
ADP
MODE
SEL
DMA
CMP
DMA
CMP
L
FS
L3H1
L
MONO
STE
H
X7
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
H
X8
L
bit14
bit13
bit12
bit11
bit10
bit9
bit8
H
X9
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
H
XA
xfrc11
xfrc10
xfrc9
xfrc8
DMA
EN
L
L
L
H
XB
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
H
XC
L
bit14
bit13
bit12
bit11
bit10
bit9
bit8
H
H
H
1D
1E
1F
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
DMA
ADRC-L
DMA
ADRC-H
DMA
XFRC-L
DMACTL
DRV
ADRC-L
DRV
ADRC-H
TEST2
TEST1
TEST0
AUTO
CI
ADP
END
ADP
END
bit5
bit6
bit7
L
DEC
TOUT
DEC
TOUT
EMPH
ASIS
L
Write Registers
—25—
CLKL
ADP
EN
DEC
MD0
CXD1196AR
REG
REGADR
DMA
DATA
A0
L
RA
X
X
X
X
bit4
RA4
bit3
RA3
bit2
RA2
bit1
RA1
bit0
RA0
H
00
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
INTSTS
H
01
ADP
END
DRQ
CI
ERR
EDC
OK
X
02
DEC
INT
COR
INH
X
H
H
03
MIN
SEC
MODE
FILE
ECC
OK
CHAN
NEL
SHRT
SCT
SUB
MODE
NO
SYNC
HDRFLG
DMA
CMP
ERIN
BLK
BLO
CK
X
STS
DEC
TOUT
ADP
BSY
H
X4
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
H
X5
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
H
X6
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
H
X7
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
H
08
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
H
09
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
H
0A
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
H
0B
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
H
0C
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
H
0D
X
bit14
bit13
bit12
bit11
bit10
bit9
bit8
MDFM
H
XE
X
X
X
RAW
MD1
H
XF
MUTE
EMPH
ASIS
EOR
RAW
MD0
FS
L3H1
C
MODE
ADPCI
RAW
MD2
BIT
L4H8
C
FORM
MONO
STE
H
18
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
H
19
X
bit14
bit13
bit12
bit11
bit10
bit9
bit8
H
1A
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
H
1B
X
bit14
bit13
bit12
bit11
bit10
bit9
bit8
H
1C
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
H
1D
X
bit14
bit13
bit12
bit11
bit10
bit9
bit8
H
10
to 2
X
X
X
X
X
X
X
X
HDR
MIN
HDR
SEC
HDR
BLOCK
HDR
MODE
SHDR
FILE
SHDR
CH
SHDR
S-MODE
SHDR
CI
CMADR
L
CMADR
H
DMA
XFRC-L
DMA
XFRC-H
DMA
ADRC-L
DMA
ADRC-H
DRV
ADRC-L
DRV
ADRC-H
TEST
0 to 2
bit7
bit6
bit5
Read Registers
—26—
X
X
CI
CXD1196AR
32K Byte SRAM
PSSL
DA15 35
36 BCLK
C2PO 44
34 C2PO
EMPH 61
35 EMP
24-31
MDBO-MDB7
37 DATA
13-20
MA7-MA14
DA16 34
5-11
MAO-MA6
38 LRCK
4
XMWR
LRCK 32
3
XMOE
CXD2500
D/A CONVERTER
WCKO 45
LRCO 46
DATO 47
CXD1196AR
BCKO 48
MUTE 50
44 INTP
30
DA12 38
DA14 36
DA13 37
38 LRCK
37 DATA
36 BCLK
XCS
INT
AO
D7-D5
D4-D0
Note)
CXD2500 is in 64-bit slot mode;
CXD2500
CXD1196A
XWR
CXD2500 : 48-bit slot mode
DRVIF register : ∗ LLHLHL ∗
XRD
XRST 59
64
65
66
67
68
69-71
74-78
CPU
DRVIF register : ∗ LHLHXH ∗
VDD, GND pins excluded.
CXD1196AR Connection Diagram
—27—
CXD1196AR
Unit : mm
80PIN LQFP (PLASTIC)
14.0 ± 0.2
∗
12.0 ± 0.1
60
41
40
(13.0)
61
21
(0.22)
80
0.5
0.5 ± 0.2
A
1
+ 0.08
0.18 – 0.03
20
0.13 M
+ 0.2
1.5 – 0.1
+ 0.05
0.127 – 0.02
0.1
0.1 ± 0.1
0° to 10°
0.5 ± 0.2
Package Outline
NOTE: Dimension “∗” does not include mold protrusion.
DETAIL A
PACKAGE STRUCTURE
PACKAGE MATERIAL
EPOXY RESIN
SONY CODE
LQFP-80P-L01
LEAD TREATMENT
SOLDER PLATING
EIAJ CODE
LQFP080-P-1212
LEAD MATERIAL
42 ALLOY
PACKAGE MASS
0.5g
JEDEC CODE
—28—