AD ADV7178KS

a
Integrated Digital CCIR-601
to PAL/NTSC Video Encoder
ADV7177/ADV7178
FEATURES
ITU-R BT601/656 YCrCb to PAL/NTSC Video Encoder
High Quality 9-Bit Video DACs
Integral Nonlinearity <1 LSB at 9 Bits
NTSC-M, PAL-M/N, PAL-B/D/G/H/I
Single 27 MHz Crystal/Clock Required (ⴛ2 Oversampling)
75 dB Video SNR
32-Bit Direct Digital Synthesizer for Color Subcarrier
Multistandard Video Output Support:
Composite (CVBS)
Component S-Video (Y/C)
Component YUV and RGB
Video Input Data Port Supports:
CCIR-656 4:2:2 8-Bit Parallel Input Format
4:2:2 16-Bit Parallel Input Format
SMPTE 170M NTSC-Compatible Composite Video
ITU-R BT.470 PAL-Compatible Composite Video
Full Video Output Drive or Low Signal Drive Capability
34.7 mA max into 37.5 ⍀ (Doubly-Terminated 75R)
5 mA min with External Buffers
Programmable Simultaneous Composite and S-VHS
(VHS) Y/C or RGB (SCART)/YUV Video Outputs
Programmable Luma Filters (Low-Pass/Notch/Extended)
Programmable VBI (Vertical Blanking Interval)
Programmable Subcarrier Frequency and Phase
Programmable LUMA Delay
Individual ON/OFF Control of Each DAC
CCIR and Square Pixel Operation
Color Signal Control/Burst Signal Control
Interlaced/Noninterlaced Operation
Complete On-Chip Video Timing Generator
OSD Support (AD7177 Only)
Programmable Multimode Master/Slave Operation
Macrovision Antitaping Rev 7.01 (ADV7178 Only)**
Closed Captioning Support
Onboard Voltage Reference
2-Wire Serial MPU Interface (I2C ® Compatible)
Single Supply +5 V or +3 V Operation
Small 44-Lead PQFP Package
Synchronous 27 MHz/13.5 MHz Clock O/P
APPLICATIONS
MPEG-1 and MPEG-2 Video, DVD, Digital Satellite/
Cable Systems (Set Top Boxes/IRDs), Digital TVs,
CD Video/Karaoke, Video Games, PC Video/Multimedia
GENERAL DESCRIPTION
The ADV7177/ADV7178 is an integrated digital video encoder
that converts Digital CCIR-601 4:2:2 8- or 16-bit component
video data into a standard analog baseband television signal
(Continued on page 11)
FUNCTIONAL BLOCK DIAGRAM
VAA
M
U 9
L
T
I 9
P
L
E 9
X
E
R
ADV7177/ADV7178
ADV7177
ONLY
YUV TO
RBG
MATRIX
OSD_EN
OSD_0
OSD_1
OSD_2
COLOR
DATA
P7–P0
P15–P8
8
4:2:2 TO
4:4:4
INTERPOLATOR
8
YCrCb
TO
YUV
MATRIX
8
8
ADD
SYNC
8
INTERPOLATOR
8
Y
LOW-PASS
FILTER
8
ADD 8
BURST
INTERPOLATOR
8
U
9
LOW-PASS
FILTER
8
ADD 8
BURST
INTERPOLATOR
8
V
9
LOW-PASS
FILTER
9
HSYNC
FIELD/VSYNC
9
VIDEO TIMING
GENERATOR
I 2 C MPU PORT
BLANK
CLOCK CLOCK CLOCK/2
RESET
SCLOCK SDATA ALSB
9
9-BIT
DAC
DAC A (PIN 31)
9-BIT
DAC
DAC B (PIN 27)
9-BIT
DAC
DAC C (PIN 26)
VOLTAGE
REFERENCE
CIRCUIT
SIN/COS
DDS BLOCK
VREF
RSET
COMP
GND
*Protected by U.S. Patent Numbers 5,343,196 and 5,442,355 and other intellectual property rights.
**This device is protected by U.S. Patent Numbers 4,631,603, 4,577,216, 4,819,098 and other intellectual property rights. The Macrovision anticopy process is
licensed for noncommercial home use only, which is its sole intended use in the device. Please contact sales office for latest Macrovision version available.
NOTE: ITU-R and CCIR are used interchangeably in this document (ITU-R has replaced CCIR recommendations).
I2C is a registered trademark of Philips Corporation.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 1998
ADV7177/ADV7178–SPECIFICATIONS
5 V SPECIFICATIONS (V
AA
= +5 V ⴞ 5%1, VREF = 1.235 V, RSET = 300 ⍀. All specifications TMIN to TMAX2 unless otherwise noted.)
Conditions1
Parameter
Min
Typ
Max
Units
9
Bits
± 1.0
± 1.0
LSB
LSB
0.8
±1
± 50
V
V
µA
µA
pF
0.4
10
V
V
µA
pF
3
STATIC PERFORMANCE
Resolution (Each DAC)
Accuracy (Each DAC)
Integral Nonlinearity
Differential Nonlinearity
Guaranteed Monotonic
DIGITAL INPUTS3
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IIN4
Input Current, IIN5
Input Capacitance, CIN
2
VIN = 0.4 V or 2.4 V
VIN = 0.4 V or 2.4 V
10
3
DIGITAL OUTPUTS
Output High Voltage, VOH
Output Low Voltage, VOL
Three-State Leakage Current
Three-State Output Capacitance
ISOURCE = 400 µA
ISINK = 3.2 mA
2.4
10
3
ANALOG OUTPUTS
Output Current6
Output Current7
DAC-to-DAC Matching
Output Compliance, VOC
Output Impedance, ROUT
Output Capacitance, COUT
VOLTAGE REFERENCE3
Reference Range, VREF
RSET = 300 Ω, RL = 75 Ω
16.5
17.35
5
0.6
0
18.5
30
mA
mA
%
V
kΩ
pF
5
+1.4
15
IOUT = 0 mA
IVREFOUT = 20 µA
1.112
1.235
1.359
V
4.75
5.0
5.25
V
150
0.5
mA
mA
mA
%/%
3, 8
POWER REQUIREMENTS
VAA
Low Power Mode
IDAC (max)9
IDAC (min)9
ICCT10
Power Supply Rejection Ratio
62
25
100
0.01
COMP = 0.1 µF
NOTES
11
The max/min specifications are guaranteed over this range. The max/min values are typical over 4.75 V to 5.25 V.
12
Temperature range T MIN to TMAX: 0°C to +70°C.
13
Guaranteed by characterization.
14
All digital input pins except pins RESET, OSD0 and CLOCK.
15
Excluding all digital input pins except pins RESET, OSD0 and CLOCK.
16
Full drive into 75␣ Ω load.
17
Minimum drive current (used with buffered/scaled output load).
18
Power measurements are taken with Clock Frequency = 27 MHz. Max T J = 110°C.
19
IDAC is the total current (min corresponds to 5 mA output per DAC, max corresponds to 18.5 mA output per DAC) to drive all three DACs. Turning off individual
DACs reduces I DAC correspondingly.
10
ICCT (Circuit Current) is the continuous current required to drive the device.
Specifications subject to change without notice.
–2–
REV. 0
ADV7177/ADV7178
3.3 V SPECIFICATIONS (V
AA
= +3.0 V–3.6 V1, VREF = 1.235 V, RSET = 300 ⍀. All specifications TMIN to TMAX2 unless otherwise noted.)
Conditions1
Parameter
Min
Typ
Max
Units
9
Bits
± 0.5
± 0.5
LSB
LSB
±1
± 50
V
V
µA
µA
pF
3
STATIC PERFORMANCE
Resolution (Each DAC)
Accuracy (Each DAC)
Integral Nonlinearity
Differential Nonlinearity
Guaranteed Monotonic
DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IIN3, 4
Input Current, IIN3, 5
Input Capacitance, CIN
2
0.8
VIN = 0.4 V or 2.4 V
VIN = 0.4 V or 2.4 V
10
DIGITAL OUTPUTS
Output High Voltage, VOH
Output Low Voltage, VOL
Three-State Leakage Current3
Three-State Output Capacitance3
ANALOG OUTPUTS3
Output Current6, 7
Output Current8
DAC-to-DAC Matching
Output Compliance, VOC
Output Impedance, ROUT
Output Capacitance, COUT
ISOURCE = 400 µA
ISINK = 3.2 mA
2.4
0.4
10
10
RSET = 300 Ω, RL = 75 Ω
16.5
17.35
5
2.0
30
mA
mA
%
V
kΩ
pF
3.3
3.6
V
113
15
45
116
mA
mA
mA
0
18.5
V
V
µA
pF
+1.4
15
IOUT = 0 mA
3, 9
POWER REQUIREMENTS
VAA
Normal Power Mode
IDAC (max)10
IDAC (min)10
ICCT9
Low Power Mode
IDAC (max)10
IDAC (min)10
ICCT11
Power Supply Rejection Ratio
3.0
RSET = 300 Ω, RL = 150 Ω
60
25
45
0.01
COMP = 0.1 µF
0.5
mA
mA
mA
%/%
NOTES
11
The max/min specifications are guaranteed over this range. The max/min values are typical over 3.0 V to 3.6 V.
12
Temperature range T MIN to TMAX: 0°C to +70°C.
13
Guaranteed by characterization.
14
All digital input pins except pins RESET, OSD0 and CLOCK.
15
Excluding all digital input pins except pins RESET, OSD0 and CLOCK.
16
Full drive into 75␣ Ω load.
17
DACs can output 35 mA typically at 3.3 V (R SET = 150 Ω and RL = 75 Ω), optimum performance obtained at 18 mA DAC current (R SET = 300 Ω and RL = 150 Ω).
18
Minimum drive current (used with buffered/scaled output load).
19
Power measurements are taken with Clock Frequency = 27 MHz. Max T J = 110°C.
10
IDAC is the total current (min corresponds to 5 mA output per DAC, max corresponds to 38 mA output per DAC) to drive all three DACs. Turning off individual
DACs reduces IDAC correspondingly.
11
ICCT (Circuit Current) is the continuous current required to drive the device.
Specifications subject to change without notice.
REV. 0
–3–
ADV7177/ADV7178–SPECIFICATIONS
(VAA = +4.75 V – 5.25 V1, VREF = 1.235 V, RSET = 300 ⍀. All specifications TMIN to TMAX2
5 V DYNAMIC SPECIFICATIONS1 unless otherwise noted.)
Parameter
Filter Characteristics
Luma Bandwidth3 (Low-Pass Filter)
Stopband Cutoff
Passband Cutoff F3 dB
Chroma Bandwidth
Stopband Cutoff
Passband Cutoff F3 dB
Luma Bandwidth3 (Low-Pass Filter)
Stopband Cutoff
Passband Cutoff F3 dB
Chroma Bandwidth
Stopband Cutoff
Passband Cutoff F3 dB
Differential Gain4
Differential Phase4
SNR4 (Pedestal)
SNR4 (Ramp)
Hue Accuracy4
Color Saturation Accuracy4
Chroma Nonlinear Gain4
Chroma Nonlinear Phase4
Chroma/Luma Intermod4
Conditions1
Min
NTSC Mode
>54 dB Attenuation
>3 dB Attenuation
NTSC Mode
>40 dB Attenuation
>3 dB Attenuation
PAL MODE
>50 dB Attenuation
>3 dB Attenuation
PAL MODE
>40 dB Attenuation
>3 dB Attenuation
Lower Power Mode
Lower Power Mode
RMS
Peak Periodic
RMS
Peak Periodic
Typ
Max
Units
7.0
4.2
MHz
MHz
3.2
2.0
MHz
MHz
7.4
5.0
MHz
MHz
4.0
2.4
MHz
MHz
%
Degrees
dB rms
dB p-p
dB rms
dB p-p
Degrees
%
±%
± Degrees
± Degrees
±%
±%
±%
ns
±%
dB
dB
Referenced to 40 IRE
NTSC
PAL
Referenced to 714 mV (NTSC)
Referenced to 700 mV (PAL)
Chroma/Luma Gain Ineq4
Chroma/Luma Delay Ineq4
Luminance Nonlinearity4
Chroma AM Noise4
Chroma PM Noise4
2.0
1.5
75
70
57
56
1.2
1.4
1.0
0.4
0.6
0.2
0.2
0.6
2.0
1.2
64
62
NOTES
1
The max/min specifications are guaranteed over this range. The max/min values are typical over 4.75 V to 5.25 V.
2
Temperature range T MIN to TMAX: 0°C to +70°C.
3
These specifications are for the low-pass filter only and guaranteed by design. For other internal filters, see Figure 5.
4
Guaranteed by characterization.
Specifications subject to change without notice.
–4–
REV. 0
ADV7177/ADV7178
1 (VAA = +3.0 V – 3.6 V , VREF = 1.235 V, RSET = 300 ⍀. All specifications TMIN to TMAX
2
1
3.3 V DYNAMIC SPECIFICATIONS
Parameter
Filter Characteristics
Luma Bandwidth3 (Low-Pass Filter)
Stopband Cutoff
Passband Cutoff F3 dB
Chroma Bandwidth
Stopband Cutoff
Passband Cutoff F3 dB
Luma Bandwidth3 (Low-Pass Filter)
Stopband Cutoff
Passband Cutoff F3 dB
Chroma Bandwidth
Stopband Cutoff
Passband Cutoff F3 dB
Differential Gain4
Differential Phase4
SNR4 (Pedestal)
SNR4 (Ramp)
Hue Accuracy4
Color Saturation Accuracy4
Luminance Nonlinearity4
Chroma AM Noise4
Chroma PM Noise4
Chroma AM Noise4
Chroma PM Noise4
unless otherwise noted.)
Conditions1
Min
NTSC Mode
>54 dB Attenuation
>3 dB Attenuation
NTSC Mode
>40 dB Attenuation
>3 dB Attenuation
PAL MODE
>50 dB Attenuation
>3 dB Attenuation
PAL MODE
>40 dB Attenuation
>3 dB Attenuation
Normal Power Mode
Normal Power Mode
RMS
Peak Periodic
RMS
Peak Periodic
–5–
Units
MHz
MHz
3.2
2.0
MHz
MHz
7.4
5.0
MHz
MHz
4.0
2.4
MHz
MHz
%
Degrees
dB rms
dB p-p
dB rms
dB p-p
Degrees
%
±%
dB
dB
dB
dB
NOTES
1
The max/min specifications are guaranteed over this range. The max/min values are typical over 3.0 V to 3.6 V.
2
Temperature range T MIN to TMAX: 0°C to +70°C.
3
These specifications are for the low-pass filter only and guaranteed by design. For other internal filters, see Figure 5.
4
Guaranteed by characterization.
REV. 0
Max
7.0
4.2
NTSC
NTSC
PAL
PAL
Specifications subject to change without notice.
Typ
1.0
1.0
70
64
56
54
1.2
1.4
1.4
64
62
64
62
ADV7177/ADV7178
(V = 4.75 V – 5.25 V , V
5 V TIMING SPECIFICATIONS otherwise noted.)
AA
Parameter
1
REF
= 1.235 V, RSET = 300 ⍀. All specifications TMIN to TMAX2 unless
Conditions
Min
Typ
Max
Units
100
kHz
µs
µs
µs
µs
ns
µs
ns
µs
3, 4
MPU PORT
SCLOCK Frequency
SCLOCK High Pulsewidth, t1
SCLOCK Low Pulsewidth, t2
Hold Time (Start Condition), t3
Setup Time (Start Condition), t4
Data Setup Time, t5
SDATA, SCLOCK Rise Time, t6
SDATA, SCLOCK Fall Time, t7
Setup Time (Stop Condition), t8
After This Period the First Clock Is Generated
Relevant for Repeated Start Condition
0
4.0
4.7
4.0
4.7
250
1
300
4.7
3, 5
ANALOG OUTPUTS
Analog Output Delay
DAC Analog Output Skew
CLOCK CONTROL
AND PIXEL PORT3, 6
fCLOCK
Clock High Time, t9
Clock Low Time, t10
Data Setup Time, t11
Data Hold Time, t12
Control Setup Time, t11
Control Hold Time, t12
Digital Output Access Time, t13
Digital Output Hold Time, t14
Pipeline Delay, t15
5
0
ns
ns
27
MHz
ns
ns
ns
ns
ns
ns
ns
ns
Clock Cycles
8
8
3.5
4
4
3
24
4
37
RESET CONTROL3, 4
RESET Low Time
6
ns
INTERNAL CLOCK CONTROL
Clock/2 Rise Time, t16
Clock/2 Fall Time, t17
7
7
ns
ns
OSD TIMING4
OSD Setup Time, t18
OSD Hold Time, t19
6
2
ns
ns
NOTES
1
The max/min specifications are guaranteed over this range.
2
Temperature range T MIN to TMAX: 0°C to +70°C.
3
TTL input values are 0 to 3 volts, with input rise/fall times ≤ 3 ns, measured between the 10% and 90% points. Timing reference points at 50% for inputs and
outputs. Analog output load ≤ 10 pF.
4
Guaranteed by characterization.
5
Output delay measured from the 50% point of the rising edge of CLOCK to the 50% point of full-scale transition.
6
Pixel Port consists of the following:
Pixel Inputs:
P15–P0
Pixel Controls:
HSYNC, FIELD/VSYNC, BLANK
Clock Input:
CLOCK
Specifications subject to change without notice.
–6–
REV. 0
ADV7177/ADV7178
(VAA = +3.0 V–3.6 V , VREF = 1.235 V, RSET = 300 ⍀. All specifications TMIN to TMAX2 unless
otherwise noted.)
1
3.3 V TIMING SPECIFICATIONS
Parameter
Conditions
Min
Typ
Max
Units
100
kHz
µs
µs
µs
µs
ns
µs
ns
µs
3, 4
MPU PORT
SCLOCK Frequency
SCLOCK High Pulsewidth, t1
SCLOCK Low Pulsewidth, t2
Hold Time (Start Condition), t3
Setup Time (Start Condition), t4
Data Setup Time, t5
SDATA, SCLOCK Rise Time, t6
SDATA, SCLOCK Fall Time, t7
Setup Time (Stop Condition), t8
After This Period the First Clock Is Generated
Repeated for Start Condition
0
4.0
4.7
4.0
4.7
250
1
300
4.7
3, 5
ANALOG OUTPUTS
Analog Output Delay
DAC Analog Output Skew
CLOCK CONTROL
AND PIXEL PORT3, 4, 6
fCLOCK
Clock High Time, t9
Clock Low Time, t10
Data Setup Time, t11
Data Hold Time, t12
Control Setup Time, t11
Control Hold Time, t12
Digital Output Access Time, t13
Digital Output Hold Time, t14
Pipeline Delay, t15
7
0
ns
ns
27
MHz
ns
ns
ns
ns
ns
ns
ns
ns
Clock Cycles
8
8
3.5
4
4
3
24
4
37
RESET CONTROL3, 4
RESET Low Time
6
ns
INTERNAL CLOCK CONTROL
Clock/2 Rise Time, t16
Clock/2 Fall Time, t17
10
10
ns
ns
OSD TIMING4
OSD Setup Time, t18
OSD Hold Time, t19
10
2
ns
ns
NOTES
1
The max/min specifications are guaranteed over this range.
2
Temperature range T MIN to TMAX: 0°C to +70°C.
3
TTL input values are 0 to 3 volts, with input rise/fall times ≤ 3 ns, measured between the 10% and 90% points. Timing reference points at 50% for inputs and
outputs. Analog output load ≤ 10 pF.
4
Guaranteed by characterization.
5
Output delay measured from the 50% point of the rising edge of CLOCK to the 50% point of full-scale transition.
6
Pixel Port consists of the following:
Pixel Inputs:
P15–P0
Pixel Controls:
HSYNC, FIELD/VSYNC, BLANK
Clock Input:
CLOCK
Specifications subject to change without notice.
REV. 0
–7–
ADV7177/ADV7178
t5
t3
t3
SDATA
t6
t1
SCLOCK
t2
t7
t4
t8
Figure 1. MPU Port Timing Diagram
CLOCK
t9
CONTROL
I/PS
t12
t10
HSYNC,
FIELD/VSYNC,
BLANK
PIXEL INPUT
DATA
Cb
Y
Cr
Y
Cb
t11
CONTROL
O/PS
Y
t13
HSYNC,
FIELD/VSYNC,
BLANK
t14
Figure 2. Pixel and Control Data Timing Diagram
t16
t17
CLOCK
CLOCK/2
t16
t17
CLOCK
CLOCK/2
Figure 3. Internal Timing Diagram
t18
t19
CLOCK
OSD EN
OSD0–2
Figure 4. OSD Timing Diagram
–8–
REV. 0
ADV7177/ADV7178
ABSOLUTE MAXIMUM RATINGS 1
PACKAGE THERMAL PERFORMANCE
VAA to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Voltage on Any Digital Input Pin . . GND – 0.5 V to VAA + 0.5 V
Storage Temperature (TS) . . . . . . . . . . . . . . –65°C to +150°C
Junction Temperature (TJ) . . . . . . . . . . . . . . . . . . . . . . +150°C
Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . . +260°C
Analog Outputs to GND2␣ . . . . . . . . . . . . . . GND – 0.5 to VAA
The 44-lead PQFP package used for this device has a junctionto-ambient thermal resistance (θJA) in still air on a four-layer
PCB of 53.2°C/W. The junction-to-case thermal resistance (θJC)
is 18.8°C/W.
Care must be taken when operating the part in certain conditions to prevent overheating. Table I illustrates what conditions
are to be used when using the part.
NOTES
1
Stresses above those listed under Absolute Maximum Ratings may cause permanent
damage to the device. This is a stress rating only; functional operation of the device
at these or any other conditions above those listed in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
2
Analog output short circuit to any power supply or common can be of an indefinite
duration.
Table I. Allowable Operating Conditions for ADV7177/
ADV7178 in 44-Lead PQFP Package
Condition
1
3 DACs ON, Double 75R
3 DACs ON, Low Power2
3 DACs ON, Buffered3
2 DACs ON, Double 75R
2 DACs ON, Low Power
2 DACs ON, Buffered
ORDERING GUIDE
Model
Temperature Package
Range
Description
ADV7178KS
ADV7177KS
0°C to +70°C
0°C to +70°C
Package
Option
Plastic Quad Flatpack S-44
Plastic Quad Flatpack S-44
5V
3V
No
Yes
Yes
No
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
NOTES
1
DAC ON, Double 75R refers to a condition where the DACs are terminated
into a double 75R load and low power mode is disabled.
2
DAC ON, Low Power refers to a condition where the DACs are terminated in a
double 75R load and low power mode is enabled.
3
DAC ON, Buffered refers to a condition where the DAC current is reduced to
5 mA and external buffers are used to drive the video loads.
OSD_0
OSD_2
OSD_1
P0
P2
P1
P4
P3
CLOCK
GND
CLOCK
PIN CONFIGURATION
44 43 42 41 40 39 38 37 36 35 34
VAA 1
CLOCK/2 2
33 RSET
PIN 1
IDENTIFIER
32 VREF
P5 3
31 DAC A
P6 4
30 VAA
P7 5
29 GND
ADV7177/ADV7178
PQFP
P8 6
28 VAA
TOP VIEW
(Not to Scale)
P9 7
P10 8
27 DAC B
26 DAC C
P11 9
25 COMP
P12 10
24 SDATA
OSD_EN 11
23 SCLOCK
RESET
GND
VAA
GND
ALSB
BLANK
HSYNC
FIELD/VSYNC
P15
P13
P14
12 13 14 15 16 17 18 19 20 21 22
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the ADV7177/ADV7178 feature proprietary ESD protection circuitry, permanent
damage may occur on devices subjected to high energy electrostatic discharges. Therefore, pr oper
ESD precautions are recommended to avoid performance degradation or loss of functionality.
REV. 0
–9–
WARNING!
ESD SENSITIVE DEVICE
ADV7177/ADV7178
PIN FUNCTION DESCRIPTIONS
Pin
No.
Mnemonic
Input/
Output
1, 20, 28, 30
2
VAA
CLOCK/2
P
O
3–10, 12–14,
37–41
11
15
P15–P0
I
OSD_EN
HSYNC
I
I/O
16
FIELD/VSYNC
I/O
17
BLANK
I/O
18
19, 21, 29, 42
22
ALSB
GND
RESET
I
G
I
23
24
25
26
27
31
32
33
SCLOCK
SDATA
COMP
DAC C
DAC B
DAC A
VREF
RSET
I
I/O
O
O
O
O
I/O
I
34–36
43
44
OSD_0–2
CLOCK
CLOCK
I
O
I
Function
+5 V Supply.
Synchronous Clock output signal. Can be either 27 MHz or 13.5 MHz; this
can be controlled by MR32 and MR33 in Mode Register 3.
8-Bit 4:2:2 Multiplexed YCrCb Pixel Port (P7–P0) or 16-Bit YCrCb
Pixel Port (P15–P0). P0 represents the LSB.
Enables OSD input data on the video outputs.
HSYNC (Modes 1 and 2) Control Signal. This pin may be configured to
output (Master Mode) or accept (Slave Mode) Sync signals.
Dual Function FIELD (Mode 1) and VSYNC (Mode 2) Control Signal. This
pin may be configured to output (Master Mode) or accept (Slave Mode)
these control signals.
Video Blanking Control Signal. The pixel inputs are ignored when this is
Logic Level “0.” This signal is optional.
TTL Address Input. This signal sets up the LSB of the MPU address.
Ground Pin.
The input resets the on-chip timing generator and sets the ADV7177/ADV7178
into default mode. This is NTSC operation, Timing Slave Mode 0, 8-Bit
Operation, 2 × Composite and S VHS out.
MPU Port Serial Interface Clock Input.
MPU Port Serial Data Input/Output.
Compensation Pin. Connect a 0.1 µF Capacitor from COMP to VAA.
DAC C Analog Output.
DAC B Analog Output.
DAC A Analog Output.
Voltage Reference Input for DACs or Voltage Reference Output (1.2 V).
A 300 Ω resistor connected from this pin to GND is used to control full-scale
amplitudes of the Video Signals.
On Screen Display Inputs.
Crystal Oscillator output (to crystal). Leave unconnected if no crystal is used.
Crystal Oscillator input. If no crystal is used this pin can be driven by an
external TTL Clock source; it requires a stable 27 MHz reference Clock for
standard operation. Alternatively, a 24.52 MHz (NTSC) or 29.5 MHz (PAL)
can be used for square pixel operation.
–10–
REV. 0
ADV7177/ADV7178
three data paths. Y typically has a range of 16 to 235, Cr and
Cb typically have a range of 128 ± 112; however, it is possible
to input data from 1 to 254 on both Y, Cb and Cr. The
ADV7177/ADV7178 supports PAL (B, D, G, H, I, N, M) and
NTSC (with and without Pedestal) standards. The appropriate SYNC, BLANK and Burst levels are added to the YCrCb
data. Macrovision antitaping (ADV7178 only), closed captioning,
OSD (ADV7177 only), and teletext levels are also added to Y,
and the resultant data is interpolated to a rate of 27 MHz. The
interpolated data is filtered and scaled by three digital FIR
filters.
(Continued from page 1)
compatible with worldwide standards. The 4:2:2 YUV video
data is interpolated to two times the pixel rate. The colordifference components (UV) are quadrature modulated using
a subcarrier frequency generated by an on-chip 32-bit digital
synthesizer (also running at two times the pixel rate). The two
times pixel rate sampling allows for better signal-to-noise ratio.
A 32-bit DDS with a 9-bit look-up table produces a superior
subcarrier in terms of both frequency and phase. In addition
to the composite output signal, there is the facility to output
S-Video (Y/C) video, YUV or RGB video.
The U and V signals are modulated by the appropriate subcarrier
sine/cosine phases and added together to make up the chrominance signal. The luma (Y) signal can be delayed 1–3 luma
cycles (each cycle is 74 ns) with respect to the chroma signal.
The luma and chroma signals are then added together to make
up the composite video signal. All edges are slew rate limited.
Each analog output is capable of driving the full video-level
(34.7 mA) signal into an unbuffered, doubly terminated 75 Ω
load. With external buffering, the user has the additional option
to scale back the DAC output current to 5 mA min, thereby significantly reducing the power dissipation of the device.
The ADV7177/ADV7178 also supports both PAL and NTSC
square pixel operation.
The YCrCb data is also used to generate RGB data with
appropriate SYNC and BLANK levels. The RGB data is in
synchronization with the composite video output. Alternatively
analog YUV data can be generated instead of RGB.
The output video frames are synchronized with the incoming
data timing reference codes. Optionally, the encoder accepts
(and can generate) HSYNC, VSYNC and FIELD timing signals.
These timing signals can be adjusted to change pulsewidth and
position while the part is in the master mode. The encoder
requires a single two times pixel rate (27 MHz) clock for standard
operation. Alternatively, the encoder requires a 24.54 MHz clock
for NTSC or 29.5 MHz clock for PAL square pixel mode
operation. All internal timing is generated on-chip.
The three 9-bit DACs can be used to output:
1.
2.
3.
3.
Alternatively, each DAC can be individually powered off if not
required.
The ADV7177/ADV7178 modes are set up over a two-wire
serial bidirectional port (I2C-Compatible) with two slave addresses.
Video output levels are illustrated in Appendix 3, Appendix 4 and
Appendix 5.
Functionally the ADV7178 and ADV7177 are the same with
the exception that the ADV7178 can output the Macrovision
anticopy algorithm, and OSD is only supported on the ADV7177.
INTERNAL FILTER RESPONSE
The Y filter supports several different frequency responses,
including two 4.5 MHz/5.0 MHz low-pass responses, PAL/
NTSC subcarrier notch responses and a PAL/NTSC extended
response. The U and V filters have a 2/2.4 MHz low-pass
response for NTSC/PAL. These filter characteristics are illustrated in Figures 7 to 13.
The ADV7177/ADV7178 is packaged in a 44-lead thermally
enhanced PQFP package.
DATA PATH DESCRIPTION
For PAL B, D, G, H, I, M, N and NTSC M, N modes, YCrCb
4:2:2 data is input via the CCIR-656 compatible pixel port at a
27 MHz data rate. The pixel data is demultiplexed to from
FILTER SELECTION
PASSBAND
CUTOFF (MHz)
PASSBAND
RIPPLE (dB)
MR04
0
0
0
0
1
1
1
2.3
3.4
1.0
1.4
4.0
2.3
3.4
0.026
0.098
0.085
0.107
0.150
0.054
0.106
NTSC
PAL
NTSC
PAL
NTSC/PAL
NTSC
PAL
MR03
0
0
1
1
0
1
1
RGB Video.
YUV Video
One Composite Video Signal + LUMA and CHROMA
(S-Video).
STOPBAND
CUTOFF (MHz)
STOPBAND
ATTENUATION (dB)
F3 dB
>54
>50
>27.6
>29.3
>40
>54
>50.3
7.0
7.3
3.57
4.43
7.5
7.0
7.3
4.2
5.0
2.1
2.7
5.35
4.2
5.0
Figure 5. Luminance Internal Filter Specifications
FILTER SELECTION
NTSC
PAL
PASSBAND
CUTOFF (MHz)
PASSBAND
RIPPLE (dB)
STOPBAND
CUTOFF (MHz)
STOPBAND
ATTENUATION (dB)
ATTENUATION @
1.3MHz (dB)
F3 dB
1.0
1.3
0.085
0.04
3.2
4.0
>40
>40
0.3
0.02
2.05
2.45
Figure 6. Chrominance Internal Filter Specifications
REV. 0
–11–
ADV7177/ADV7178
0
0
–10
–10
–20
AMPLITUDE – dB
AMPLITUDE – dB
TYPE A
–30
–40
–20
–30
–40
–50
–50
TYPE B
–60
0
2
4
6
8
FREQUENCY – MHz
10
–60
0
12
0
0
–10
–10
–20
–20
–30
–40
6
8
FREQUENCY – MHz
10
12
–30
–40
–50
–50
–60
0
4
Figure 10. PAL Notch Filter
AMPLITUDE – dB
AMPLITUDE – dB
Figure 7. NTSC Low-Pass Filter
2
2
4
6
8
FREQUENCY – MHz
10
–60
0
12
Figure 8. NTSC Notch Filter
2
4
6
8
FREQUENCY – MHz
10
12
Figure 11. NTSC/PAL Extended Mode Filter
0
0
–10
–10
–20
AMPLITUDE – dB
AMPLITUDE – dB
TYPE A
–30
–40
–20
–30
–40
TYPE B
–50
–60
0
–50
2
4
6
8
FREQUENCY – MHz
10
–60
0
12
Figure 9. PAL Low-Pass Filter
2
4
6
8
FREQUENCY – MHz
10
12
Figure 12. NTSC UV Filter
–12–
REV. 0
ADV7177/ADV7178
16-Bit YCrCb Mode
0
This mode accepts Y inputs through the P7–P0 pixel inputs and
multiplexed CrCb inputs through the P15–P8 pixel inputs. The
data is loaded on every second rising edge of CLOCK. The inputs
follow the sequence Cb0, Y0 Cr0, Y1 Cb1, Y2, etc.
AMPLITUDE – dB
–10
–20
OSD
The ADV7177 supports OSD. There are twelve 8-bit OSD
registers, loaded with data from the four most significant bits of
Y, Cb, Cr input pixel data bytes. A choice of eight colors can,
therefore, be selected via the OSD_0, OSD_1, OSD_2 pins,
each color being a combination of 12 bits of Y, Cb, Cr pixel
data. The display is under control of the OSD_EN pin. The
OSD window can be an entire screen or just one pixel, its size
may change by using the OSD_EN signal to control the width on a
line-by-line basis. Figure 4 illustrates OSD timing on the ADV7177.
–30
–40
–50
–60
0
2
4
6
8
FREQUENCY – MHz
10
12
Figure 13. PAL UV Filter
SUBCARRIER RESET
The ADV7177/ADV7178 can be used in subcarrier reset
mode. The subcarrier will reset to Field 0 at the start of the
following field when a low to high transition occurs on this
input pin.
COLOR BAR GENERATION
The ADV7177/ADV7178 can be configured to generate 75%
amplitude, 75% saturation (75/7.5/75/7.5) for NTSC or 75%
amplitude, 100% saturation (100/0/75/0) for PAL color bars.
These are enabled by setting MR17 of Mode Register 1 to
Logic “1.”
VIDEO TIMING DESCRIPTION
The ADV7177/ADV7178 is intended to interface to offthe-shelf MPEG1 and MPEG2 decoders. Consequently, the
ADV7177/ADV7178 accepts 4:2:2 YCrCb pixel data via a
CCIR-656 pixel port, and has several video timing modes of
operation that allow it to be configured as either system master
video timing generator or a slave to the system video timing
generator. The ADV7177/ADV7178 generates all of the required horizontal and vertical timing periods and levels for the
analog video outputs.
SQUARE PIXEL MODE
The ADV7177/ADV7178 can be used to operate in square pixel
mode. For NTSC operation an input clock of 24.5454 MHz is
required. Alternatively an input clock of 29.5 MHz is required
for PAL operation. The internal timing logic adjusts accordingly
for square pixel mode operation.
COLOR SIGNAL CONTROL
The color information can be switched on and off the video
output using Bit MR24 of Mode Register 2.
The ADV7177/ADV7178 calculates the width and placement of
analog sync pulses, blanking levels and color burst envelopes.
Color bursts are disabled on appropriate lines, and serration and
equalization pulses are inserted where required.
BURST SIGNAL CONTROL
The burst information can be switched on and off the video
output using Bit MR25 of Mode Register 2.
In addition, the ADV7177/ADV7178 supports a PAL or NTSC
square pixel operation in slave mode. The part requires an input
pixel clock of 24.5454 MHz for NTSC and an input pixel clock
of 29.5 MHz for PAL. The internal horizontal line counters
place the various video waveform sections in the correct location
for the new clock frequencies.
NTSC PEDESTAL CONTROL
The pedestal on both odd and even fields can be controlled on a
line-by-line basis using the NTSC Pedestal Control Registers.
This allows the pedestals to be controlled during the vertical
blanking interval (Lines 10 to 25 and Lines 273 to 288).
PIXEL TIMING DESCRIPTION
The ADV7177/ADV7178 can operate in either 8-bit or
16-bit YCrCb Mode.
8-Bit YCrCb Mode
This default mode accepts multiplexed YCrCb inputs through
the P7–P0 pixel inputs. The inputs follow the sequence Cb0, Y0
Cr0, Y1 Cb1, Y2, etc. The Y, Cb and Cr data are input on a
rising clock edge.
REV. 0
The ADV7177/ADV7178 has four distinct master and four
distinct slave timing configurations. Timing Control is established with the bidirectional SYNC, BLANK and FIELD/
VSYNC pins. Timing Mode Register 1 can also be used to vary
the timing pulsewidths and where they occur in relation to each
other.
–13–
ADV7177/ADV7178
Vertical Blanking Data Insertion
It is possible to allow encoding of incoming YCbCr data on those lines of VBI that do not bear line sync or pre-/post-equalization
pulses (see Figures 14 to 25). This mode of operation is called “Partial Blanking” and is selected by setting MR31 to 1. It allows the
insertion of any VBI data (Opened VBI) into the encoded output waveform. This data is present in digitized incoming YCbCr data
stream (e.g., WSS data, CGMS, VPS, etc.). Alternatively, the entire VBI may be blanked (no VBI data inserted) on these lines by
setting MR31 to 0.
The complete VBI comprises of the following lines:
525/60 Systems, Lines 525 to 21 for Field 1 and Lines 262 to Line 284 for Field 2.
625/50 Systems, Lines 624 to Line 22 and Lines 311 to 335.
The “Opened VBI” consists of:
525/60 Systems, Lines 10 to 21 for Field 1 and second half of Line 273 to Line 284 for Field 2.
625/50 Systems, Line 7 to Line 22 and Lines 319 to 335.
Mode 0 (CCIR-656): Slave Option
(Timing Register 0 TR0 = X X X X X 0 0 0)
The ADV7177/ADV7178 is controlled by the SAV (Start Active Video) and EAV (End Active Video) time codes in the pixel data.
All timing information is transmitted using a 4-byte synchronization pattern. A synchronization pattern is sent immediately before
and after each line during active picture and retrace. Mode 0 is illustrated in Figure 14. The HSYNC, FIELD/VSYNC and BLANK
(if not used) pins should be tied high during this mode.
ANALOG
VIDEO
EAV CODE
INPUT PIXELS
C
F 0 0 X 8 1 8 1
Y
Y
r
F 0 0 Y 0 0 0 0
4 CLOCK
NTSC/PAL M SYSTEM
(525 LlNES/60Hz)
SAV CODE
0 F F A A A
0 F F B B B
C
C
8 1 8 1 F 0 0 X C Y C Y C
Y r Y b
b
0 0 0 0 F 0 0 Y b
r
ANCILLARY DATA
(HANC)
4 CLOCK
268 CLOCK
4 CLOCK
PAL SYSTEM
(625 LINES/50Hz)
1440 CLOCK
4 CLOCK
280 CLOCK
END OF ACTIVE
VIDEO LINE
1440 CLOCK
START OF ACTIVE
VIDEO LINE
Figure 14. Timing Mode 0 (Slave Mode)
Mode 0 (CCIR-656): Master Option
(Timing Register 0 TR0 = X X X X X 0 0 1)
The ADV7177/ADV7178 generates H, V and F signals required for the SAV (Start Active Video) and EAV (End Active Video) time
codes in the CCIR-656 standard. The H bit is output on the HSYNC pin, the V bit is output on the BLANK pin, and the F bit is
output on the FIELD/VSYNC pin. Mode 0 is illustrated in Figure 15 (NTSC) and Figure 16 (PAL). The H, V and F transitions
relative to the video waveform are illustrated in Figure 17.
–14–
REV. 0
ADV7177/ADV7178
DISPLAY
DISPLAY
VERTICAL BLANK
522
523
524
525
1
2
3
4
6
5
7
8
9
10
11
20
21
22
H
V
EVEN FIELD
F
ODD FIELD
DISPLAY
DISPLAY
VERTICAL BLANK
260
261
262
263
264
265
266
267
268
269
270
271
272
273
283
274
284
285
H
V
F
ODD FIELD
EVEN FIELD
Figure 15. Timing Mode 0 (NTSC Master Mode)
DISPLAY
DISPLAY
VERTICAL BLANK
622
623
624
625
1
2
3
4
5
6
7
21
22
23
H
V
EVEN FIELD
F
ODD FIELD
DISPLAY
DISPLAY
VERTICAL BLANK
309
310
311
312
313
314
315
316
317
318
319
320
H
V
F
ODD FIELD
EVEN FIELD
Figure 16. Timing Mode 0 (PAL Master Mode)
REV. 0
–15–
334
335
336
ADV7177/ADV7178
ANALOG
VIDEO
H
F
V
Figure 17. Timing Mode 0 Data Transitions (Master Mode)
Mode 1: Slave Option HSYNC, BLANK, FIELD
(Timing Register 0 TR0 = X X X X X 0 1 0)
In this mode the ADV7177/ADV7178 accepts horizontal SYNC and Odd/Even FIELD signals. A transition of the FIELD input
when HSYNC is low indicates a new frame, i.e., vertical retrace. The BLANK signal is optional. When the BLANK input is disabled, the ADV7177/ADV7178 automatically blanks all normally blank lines. Mode 1 is illustrated in Figure 18 (NTSC) and
Figure 19 (PAL).
DISPLAY
522
523
DISPLAY
VERTICAL BLANK
524
525
1
2
3
4
6
5
7
8
9
10
11
20
21
22
HSYNC
BLANK
FIELD
EVEN FIELD
ODD FIELD
DISPLAY
DISPLAY
VERTICAL BLANK
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
283
284
285
HSYNC
BLANK
FIELD
ODD FIELD
EVEN FIELD
Figure 18. Timing Mode 1 (NTSC)
–16–
REV. 0
ADV7177/ADV7178
DISPLAY
622
623
DISPLAY
VERTICAL BLANK
624
625
1
2
3
4
5
6
7
21
22
23
HSYNC
BLANK
FIELD
EVEN FIELD
ODD FIELD
DISPLAY
DISPLAY
309
310
VERTICAL BLANK
311
312
313
314
315
316
317
318
319
320
334
335
336
HSYNC
BLANK
FIELD
ODD FIELD
EVEN FIELD
Figure 19. Timing Mode 1 (PAL)
Mode 1: Master Option HSYNC, BLANK, FIELD
(Timing Register 0 TR0 = X X X X X 0 1 1)
In this mode the ADV7177/ADV7178 can generate horizontal SYNC and Odd/Even FIELD signals. A transition of the FIELD
input when HSYNC is low indicates a new frame, i.e., vertical retrace. The BLANK signal is optional. When the BLANK input is
disabled, the ADV7177/ADV7178 automatically blanks all normally blank lines. Pixel data is latched on the rising clock edge following the timing signal transitions. Mode 1 is illustrated in Figure 18 (NTSC) and Figure 19 (PAL). Figure 20 illustrates the HSYNC,
BLANK and FIELD for an odd or even field transition relative to the pixel data.
HSYNC
FIELD
PAL = 12 * CLOCK/2
NTSC = 16 * CLOCK/2
BLANK
PIXEL
DATA
Cb
Y
PAL = 132 * CLOCK/2
NTSC = 122 * CLOCK/2
Figure 20. Timing Mode 1 Odd/Even Field Transitions Master/Slave
REV. 0
–17–
Cr
Y
ADV7177/ADV7178
Mode 2: Slave Option HSYNC, VSYNC, BLANK
(Timing Register 0 TR0 = X X X X X 1 0 0)
In this mode the ADV7177/ADV7178 accepts horizontal and vertical SYNC signals. A coincident low transition of both HSYNC and
VSYNC inputs indicates the start of an odd field. A VSYNC low transition when HSYNC is high indicates the start of an even field.
The BLANK signal is optional. When the BLANK input is disabled, the ADV7177/ADV7178 automatically blanks all normally
blank lines as per CCIR-624. Mode 2 is illustrated in Figure 21 (NTSC) and Figure 22 (PAL).
DISPLAY
522
DISPLAY
VERTICAL BLANK
523
524
525
1
2
3
4
6
5
7
8
10
9
20
11
21
22
HSYNC
BLANK
VSYNC
EVEN FIELD
ODD FIELD
DISPLAY
260
261
DISPLAY
VERTICAL BLANK
262
263
264
265
266
267
268
269
270
271
272
273
283
274
284
285
HSYNC
BLANK
VSYNC
ODD FIELD
EVEN FIELD
Figure 21. Timing Mode 2 (NTSC)
DISPLAY
622
623
DISPLAY
VERTICAL BLANK
624
625
1
2
3
4
5
6
7
21
22
23
HSYNC
BLANK
VSYNC
EVEN FIELD
ODD FIELD
DISPLAY
DISPLAY
309
310
VERTICAL BLANK
311
312
313
314
315
316
317
318
319
320
334
335
336
HSYNC
BLANK
VSYNC
ODD FIELD
EVEN FIELD
Figure 22. Timing Mode 2 (PAL)
–18–
REV. 0
ADV7177/ADV7178
Mode 2: Master Option HSYNC, VSYNC, BLANK
(Timing Register 0 TR0 = X X X X X 1 0 1)
In this mode, the ADV7177/ADV7178 can generate horizontal and vertical SYNC signals. A coincident low transition of both
HSYNC and VSYNC inputs indicates the start of an Odd Field. A VSYNC low transition when HSYNC is high indicates the start
of an even field. The BLANK signal is optional. When the BLANK input is disabled, the ADV7177/ADV7178 automatically blanks
all normally blank lines as per CCIR-624. Mode 2 is illustrated in Figure 21 (NTSC) and Figure 22 (PAL). Figure 23 illustrates the HSYNC, BLANK and VSYNC for an even-to-odd field transition relative to the pixel data. Figure 24 illustrates the
HSYNC, BLANK and VSYNC for an odd-to-even field transition relative to the pixel data.
HSYNC
VSYNC
PAL = 12 * CLOCK/2
BLANK
NTSC = 16 * CLOCK/2
PIXEL
DATA
Cb
Y
PAL = 132 * CLOCK/2
NTSC = 122 * CLOCK/2
Figure 23. Timing Mode 2 Even-to-Odd Field Transition Master/Slave
HSYNC
VSYNC
PAL = 12 * CLOCK/2
NTSC = 16 * CLOCK/2
PAL = 864 * CLOCK/2
NTSC = 858 * CLOCK/2
BLANK
PIXEL
DATA
Cb
Y
Cr
Y
Cb
PAL = 132 * CLOCK/2
NTSC = 122 * CLOCK/2
Figure 24. Timing Mode 2 Odd-to-Even Field Transition Master/Slave
REV. 0
–19–
Cr
ADV7177/ADV7178
Mode 3: Master/Slave Option HSYNC, BLANK, FIELD
(Timing Register 0 TR0 = X X X X X 1 1 0 or X X X X X 1 1 1)
In this mode, the ADV7177/ADV7178 accepts or generates Horizontal SYNC and Odd/Even FIELD signals. A transition of the
FIELD input when HSYNC is high indicates a new frame, i.e., vertical retrace. The BLANK signal is optional. When the BLANK
input is disabled, the ADV7177/ADV7178 automatically blanks all normally blank lines as per CCIR-624. Mode 3 is illustrated in
Figure 25 (NTSC) and Figure 26 (PAL).
DISPLAY
522
523
DISPLAY
VERTICAL BLANK
524
525
1
2
3
4
6
5
7
8
9
10
20
11
21
22
HSYNC
BLANK
FIELD
EVEN FIELD
ODD FIELD
DISPLAY
DISPLAY
VERTICAL BLANK
260
261
262
263
264
265
266
267
268
269
270
271
272
273
283
274
284
285
HSYNC
BLANK
FIELD
ODD FIELD
EVEN FIELD
Figure 25. Timing Mode 3 (NTSC)
DISPLAY
622
623
DISPLAY
VERTICAL BLANK
624
625
1
2
3
4
5
6
7
21
22
23
HSYNC
BLANK
FIELD
EVEN FIELD
ODD FIELD
DISPLAY
DISPLAY
309
310
VERTICAL BLANK
311
312
313
314
315
316
317
318
319
320
334
335
336
HSYNC
BLANK
FIELD
EVEN FIELD
ODD FIELD
Figure 26. Timing Mode 3 (PAL)
–20–
REV. 0
ADV7177/ADV7178
this configuration the SCH phase will never be reset, which
means that the output video will now track the unstable input
video. The subcarrier phase reset, when applied, will reset the
SCH phase to Field 0 at the start of the next field (e.g., subcarrier
phase reset applied in Field 5 [PAL] on the start of the next
field SCH phase will be reset to Field 0).
OUTPUT VIDEO TIMING
The video timing generator generates the appropriate SYNC,
BLANK and BURST sequence that controls the output analog
waveforms. These sequences are summarized below. In slave
modes, the following sequences are synchronized with the input
timing control signals. In master modes, the timing generator
free runs and generates the following sequences in addition to
the output timing control signals.
MPU PORT DESCRIPTION
NTSC–Interlaced: Scan Lines 1–9 and 264–272 are always
blanked and vertical sync pulses are included. Scan Lines 525,
10–21 and 262, 263, 273–284 are also blanked and can be used
for closed captioning data. Burst is disabled on lines 1–6, 261–
269 and 523–525.
NTSC–Noninterlaced: Scan Lines 1–9 are always blanked,
and vertical sync pulses are included. Scan Lines 10–21 are also
blanked and can be used for closed captioning data. Burst is
disabled on Lines 1–6, 261–262.
PAL–Interlaced: Scan Lines 1–6, 311–318 and 624–625 are
always blanked, and vertical sync pulses are included in Fields
1, 2, 5 and 6. Scan Lines 1–5, 311–319 and 624–625 are always blanked, and vertical sync pulses are included in Fields 3,
4, 7 and 8. The remaining scan lines in the vertical blanking
interval are also blanked and can be used for teletext data.
Burst is disabled on Lines 1–6, 311–318 and 623–625 in Fields
1, 2, 5 and 6. Burst is disabled on Lines 1–5, 311–319 and
623–625 in Fields 3, 4, 7 and 8.
The ADV7178 and ADV7177 support a two-wire serial (I2CCompatible) microprocessor bus driving multiple peripherals.
Two inputs, serial data (SDATA) and serial clock (SCLOCK),
carry information between any device connected to the bus.
Each slave device is recognized by a unique address. The
ADV7178 and ADV7177 each have four possible slave addresses for both read and write operations. These are unique
addresses for each device and are illustrated in Figure 27 and
Figure 28. The LSB sets either a read or write operation. Logic
Level “1” corresponds to a read operation, while Logic Level
“0” corresponds to a write operation. A1 is set by setting the
ALSB pin of the ADV7177/ADV7178 to Logic Level “0” or
Logic Level “1.”
0
0
1
0
1
A1
X
ADDRESS
CONTROL
SET UP BY
ALSB
READ/WRITE
CONTROL
PAL–Noninterlaced: Scan Lines 1–6 and 311–312 are always
blanked, and vertical sync pulses are included. The remaining
scan lines in the vertical blanking interval are also blanked and
can be used for teletext data. Burst is disabled on Lines 1–5,
310–312.
0
1
WRITE
READ
Figure 27. ADV7178 Slave Address
1
POWER-ON RESET
After power-up, it is necessary to execute a reset operation. A
reset occurs on the falling edge of a high-to-low transition on
the RESET pin. This initializes the pixel port so that the
pixel inputs, P7–P0 are selected. After reset, the ADV7177/
ADV7178 is automatically set up to operate in NTSC mode.
Subcarrier frequency code 21F07C16HEX is loaded into the
subcarrier frequency registers. All other registers, with the
exception of Mode Register 0, are set to 00H. All bits in Mode
Register 0 are set to Logic Level “0” except Bit MR02. Bit
MR02 of Mode Register 0 is set to Logic Level “1.” This enables the 7.5 IRE pedestal.
1
1
1
0
1
A1
X
ADDRESS
CONTROL
SET UP BY
ALSB
READ/WRITE
CONTROL
0
1
WRITE
READ
Figure 28. ADV7177 Slave Address
SCH Phase Mode
The SCH phase is configured in default mode to reset every
four (NTSC) or eight (PAL) fields to avoid an accumulation of
SCH phase error over time. In an ideal system, zero SCH phase
error would be maintained forever, but in reality, this is impossible to achieve due to clock frequency variations. This effect is
reduced by the use of a 32-bit DDS, which generates this SCH.
Resetting the SCH phase every four or eight fields avoids the
accumulation of SCH phase error, and results in very minor
SCH phase jumps at the start of the four or eight field sequence.
Resetting the SCH phase should not be done if the video source
does not have stable timing or the ADV7177/ADV7178 is configured in RTC mode (MR21 = 1 and MR22 = 1). Under these
conditions (unstable video) the subcarrier phase reset should be
enabled MR22 = 0 and MR21 = 1) but no reset applied. In
REV. 0
0
To control the various devices on the bus, the following protocol must be followed: First, the master initiates a data transfer by
establishing a start condition, defined by a high-to-low transition
on SDATA while SCLOCK remains high. This indicates that
an address/data stream will follow. All peripherals respond to
the start condition and shift the next eight bits (7-bit address
+ R/W bit). The bits transfer from MSB down to LSB. The
peripheral that recognizes the transmitted address responds by
pulling the data line low during the ninth clock pulse. This is
known as an acknowledge bit. All other devices withdraw from
the bus at this point and maintain an idle condition. The idle
condition is where the device monitors the SDATA and SCLOCK
lines waiting for the start condition and the correct transmitted
address. The R/W bit determines the direction of the data. A
Logic “0” on the LSB of the first byte means that the master
will write information to the peripheral. A Logic “1” on the
LSB of the first byte means that the master will read information from the peripheral.
–21–
ADV7177/ADV7178
The ADV7177/ADV7178 acts as a standard slave device on the
bus. The data on the SDATA pin is 8 bits long, supporting
the 7-bit addresses, plus the R/W bit. The ADV7178 has 36
subaddresses and the ADV7177 has 31 subaddresses to enable
access to the internal registers. It therefore interprets the first
byte as the device address and the second byte as the starting
subaddress. The subaddresses auto increment allows data to
be written to or read from the starting subaddress. A data
transfer is always terminated by a stop condition. The user can
also access any unique subaddress register on a one-by-one basis
without having to update all the registers. There is one exception. The subcarrier frequency registers should be updated in
sequence, starting with Subcarrier Frequency Register 0. The
auto increment function should then be used to increment and
access Subcarrier Frequency Registers 1, 2 and 3. The subcarrier
frequency registers should not be accessed independently.
2. In Write Mode, the data for the invalid byte will not be
loaded into any subaddress register, a no-acknowledge will
be issued by the ADV7177/ADV7178 and the part will return to the idle condition.
Stop and start conditions can be detected at any stage during
the data transfer. If these conditions are asserted out of sequence
with normal read and write operations, they cause an immediate
jump to the idle condition. During a given SCLOCK high period, the user should issue only one start condition, one stop
condition or a single stop condition followed by a single start
condition. If an invalid subaddress is issued by the user, the
ADV7177/ADV7178 will not issue an acknowledge and will
return to the idle condition. If, in auto-increment mode, the
user exceeds the highest subaddress, the following action will be
taken:
REGISTER ACCESSES
Figure 29 illustrates an example of data transfer for a read sequence and the start and stop conditions.
SDATA
SCLOCK
S
SLAVE ADDR A(S)
SUB ADDR
S
SLAVE ADDR A(S)
S = START BIT
P = STOP BIT
8
9
1-7
8
9
1-7
DATA
8
9
P
ACK
STOP
Figure 29. Bus Data Transfer
The MPU can write to or read from all of the ADV7177/
ADV7178 registers except the subaddress register, which is a
write-only register. The subaddress register determines which
register the next read or write operation accesses. All communications with the part through the bus start with an access to the
subaddress register. A read/write operation is performed from/to
the target address, which then increments to the next address
until a stop command on the bus is performed.
REGISTER PROGRAMMING
The following section describes each register, including subaddress
register, mode registers, subcarrier frequency registers, subcarrier
phase register, timing registers, closed captioning extended data
registers, closed captioning data registers and NTSC pedestal
control registers in terms of its configuration.
DATA
A(S)
DATA
A(S) P
LSB = 1
LSB = 0
READ
SEQUENCE
A(S)
1-7
Figure 30 shows bus write and read sequences.
1. In Read Mode, the highest subaddress register contents will
continue to be output until the master device issues a noacknowledge. This indicates the end of a read. A noacknowledge condition is where the SDATA line is not
pulled low on the ninth pulse.
WRITE
SEQUENCE
S
START ADDR R/W ACK SUBADDRESS ACK
SUB ADDR
A(S) S SLAVE ADDR
A(S) = ACKNOWLEDGE BY SLAVE
A(M) = ACKNOWLEDGE BY MASTER
A(S)
DATA
A(M)
DATA
A(M) P
A(S) = NO-ACKNOWLEDGE BY SLAVE
A(M) = NO-ACKNOWLEDGE BY MASTER
Figure 30. Write and Read Sequences
–22–
REV. 0
ADV7177/ADV7178
Subaddress Register (SR7–SR0)
MR0 BIT DESCRIPTION
Encode Mode Control (MR01–MR00)
The communications register is an 8-bit write-only register.
After the part has been accessed over the bus, and a read/write
operation is selected, the subaddress is set up. The subaddress
register determines to/from which register the operation takes
place.
These bits are used to set up the encode mode. The ADV7177/
ADV7178 can be set up to output NTSC, PAL (B, D, G, H, I)
and PAL (M) standard video.
Pedestal Control (MR02)
Figure 31 shows the various operations under the control of
the subaddress register. Zero should always be written to
SR7–SR6.
This bit specifies whether a pedestal is to be generated on
the NTSC composite video signal. This bit is invalid if the
ADV7177/ADV7178 is configured in PAL mode.
Register Select (SR5–SR0)
Luminance Filter Control (MR04–MR03)
These bits are set up to point to the required starting address.
The luminance filters are divided into two sets (NTSC/PAL) of
four filters, low-pass A, low-pass B, notch and extended. When
PAL is selected, bits MR03 and MR04 select one of four PAL
luminance filters; likewise, when NTSC is selected, bits MR03
and MR04 select one of four NTSC luminance filters. The
filters are illustrated in Figures 7 to 13.
MODE REGISTER 0 MR0 (MR07–MR00)
(Address [SR4–SR0] = 00H)
Figure 32 shows the various operations under the control of Mode
Register 0. This register can be read from as well as written to.
SR7
SR6
SR5
SR4
SR3
SR1
SR2
SR0
SR7–SR6 (00)
ZERO SHOULD BE WRITTEN
TO THESE BITS
ADV7178 SUBADDRESS REGISTER
ADV7177 SUBADDRESS REGISTER
SR5 SR4 SR3 SR2 SR1 SR0
SR5 SR4 SR3 SR2 SR1 SR0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
•
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
•
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
•
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
•
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
•
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
•
MODE REGISTER 0
MODE REGISTER 1
SUBCARRIER FREQ REGISTER 0
SUBCARRIER FREQ REGISTER 1
SUBCARRIER FREQ REGISTER 2
SUBCARRIER FREQ REGISTER 3
SUBCARRIER PHASE REGISTER
TIMING REGISTER 0
CLOSED CAPTIONING EXTENDED DATA – BYTE 0
CLOSED CAPTIONING EXTENDED DATA – BYTE 1
CLOSED CAPTIONING DATA – BYTE 0
CLOSED CAPTIONING DATA – BYTE 1
TIMING REGISTER 1
MODE REGISTER 2
NTSC PEDESTAL CONTROL REG 0 (FIELD 1/3)
NTSC PEDESTAL CONTROL REG 1 (FIELD 1/3)
NTSC PEDESTAL CONTROL REG 2 (FIELD 2/4)
NTSC PEDESTAL CONTROL REG 3 (FIELD 2/4)
MODE REGISTER 3
MACROVISION REGISTER
"
"
•
1
•
0
•
0
•
0
•
1
•
1
"
"
MACROVISION REGISTER
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
•
•
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
•
•
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
•
•
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
•
•
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
•
•
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
•
•
0
MODE REGISTER 0
MODE REGISTER 1
SUBCARRIER FREQ REGISTER 0
SUBCARRIER FREQ REGISTER 1
SUBCARRIER FREQ REGISTER 2
SUBCARRIER FREQ REGISTER 3
SUBCARRIER PHASE REGISTER
TIMING REGISTER 0
CLOSED CAPTIONING EXTENDED DATA – BYTE 0
CLOSED CAPTIONING EXTENDED DATA – BYTE 1
CLOSED CAPTIONING DATA – BYTE 0
CLOSED CAPTIONING DATA – BYTE 1
TIMING REGISTER 1
MODE REGISTER 2
NTSC PEDESTAL CONTROL REG 0 (FIELD 1/3)
NTSC PEDESTAL CONTROL REG 1 (FIELD 1/3)
NTSC PEDESTAL CONTROL REG 2 (FIELD 2/4)
NTSC PEDESTAL CONTROL REG 3 (FIELD 2/4)
MODE REGISTER 3
OSD REGISTER
"
"
"
"
OSD REGISTER
Figure 31. Subaddress Register
MR07
MR06
MR05
MR04
OUTPUT SELECT
MR07
(0)
ZERO SHOULD
BE WRITTEN TO
THIS BIT
MR02
YC OUTPUT
RGB/YUV OUTPUT
0
0
1
1
0
1
0
1
RGB SYNC
0
1
MR01 MR00
LOW-PASS FILTER (A)
NOTCH FILTER
EXTENDED MODE
LOW-PASS FILTER (B)
0
0
1
1
0
1
0
1
PEDESTAL CONTROL
MR02
MR05
0
1
DISABLE
ENABLE
–23–
MR00
OUTPUT VIDEO
STANDARD SELECTION
MR04 MR03
PEDESTAL OFF
PEDESTAL ON
Figure 32. Mode Register 0 (MR0)
REV. 0
MR01
FILTER SELECT
MR06
0
1
MR03
NTSC
PAL (B, D, G, H, I)
PAL (M)
RESERVED
ADV7177/ADV7178
MR17
MR16
MR14
MR13
MR16
(1)
LUMA
DAC CONTROL
ONE SHOULD
BE WRITTEN TO
THIS BIT
MR14
0
NORMAL
1
POWER-DOWN
COLOR BAR
CONTROL
MR17
0
1
MR15
DISABLE
ENABLE
MR11
MR12
MR10
CLOSED CAPTIONING
FIELD SELECTION
MR12 MR11
0
0
1
1
0
1
0
1
COMPOSITE
DAC CONTROL
CHROMA
DAC CONTROL
MR15
0
NORMAL
1
POWER-DOWN
MR13
0
NORMAL
1
POWER-DOWN
NO DATA OUT
ODD FIELD ONLY
EVEN FIELD ONLY
DATA OUT
(BOTH FIELDS)
INTERLACE
CONTROL
MR10
0
INTERLACED
1
NONINTERLACED
Figure 33. Mode Register 1 (MR1)
RGB Sync (MR05)
This bit is used to set up the RGB outputs with the sync information encoded on all RGB outputs.
i.e.: NTSC Mode,
FCLK = 27 MHz,
FSCF = 3.5795454 MHz
232 – 1
Output Control (MR06)
This bit specifies if the part is in composite video or RGB/YUV
mode. Please note that the main composite signal is still available in RGB/YUV mode.
MODE REGISTER 1 MR1 (MR17–MR10)
(Address (SR4–SR0) = 01H)
Subcarrier Frequency Value =
= 21F07C16 HEX
MR1 BIT DESCRIPTION
Interlaced Mode Control (MR10)
This bit is used to set up the output to interlaced or noninterlaced mode. This mode is only relevant when the part is in
composite video mode.
These bits can be used to power down the DACs. This can
be used to reduce the power consumption of the ADV7177/
ADV7178 if any of the DACs are not required in the application.
Color Bar Control (MR17)
This bit can be used to generate and output an internal color
bar test pattern. The color bar configuration is 75/7.5/75/7.5
for NTSC and 100/0/75/0 for PAL. It is important to note that
when color bars are enabled the ADV7177/ADV7178 is configured in a master timing mode as per the one selected by bits
TR01 and TR02.
SUBCARRIER
FREQUENCY
REG 3
FSC31
SUBCARRIER
FREQUENCY
REG 2
FSC23 FSC22 FSC21 FSC20 FSC19 FSC18 FSC17
FSC16
SUBCARRIER
FREQUENCY
REG 1
FSC15 FSC14 FSC13 FSC12
SUBCARRIER
FREQUENCY
REG 0
FSC7
FSC30 FSC29 FSC28 FSC27 FSC26 FSC25 FSC24
FSC6
FSC5
FSC4
FSC11 FSC10
FSC9
FSC8
FSC3
FSC1
FSC0
FSC2
Figure 34. Subcarrier Frequency Register
Closed Captioning Field Control (MR12–MR11)
DAC Control (MR15–MR13)
× 3.5795454 × 106
Figure 34 shows how the frequency is set up by the four registers.
Figure 33 shows the various operations under the control of Mode
Register 1. This register can be read from as well as written to.
These bits control the fields on which closed captioning data is
displayed; closed captioning information can be displayed on an
odd field, even field or both fields.
27 × 106
SUBCARRIER PHASE REGISTER (FP7–FP0)
(Address [SR4–SR0] = 06H)
This 8-bit-wide register is used to set up the subcarrier phase.
Each bit represents 1.41 degrees.
TIMING REGISTER 0 (TR07–TR00)
(Address [SR4–SR0] = 07H)
Figure 35 shows the various operations under the control of
Timing Register 0. This register can be read from as well as
written to. This register can be used to adjust the width and
position of the master mode timing signals.
TR0 BIT DESCRIPTION
Master/Slave Control (TR00)
SUBCARRIER FREQUENCY REGISTER 3-0
(FSC3–FSC0)
(Address [SR4–SR0] = 05H–02H)
This bit controls whether the ADV7177/ADV7178 is in master
or slave mode. This register can be used to adjust the width and
position of the master timing signals.
These 8-bit-wide registers are used to set up the subcarrier
frequency. The value of these registers are calculated by using
the following equation:
Timing Mode Control (TR02–TR01)
Subcarrier Frequency Register =
232 –1
× FSCF
FCLK
These bits control the timing mode of the ADV7177/ADV7178.
These modes are described in the Timing and Control section
of the data sheet.
BLANK Control (TR03)
This bit controls whether the BLANK input is used when the
part is in slave mode
–24–
REV. 0
ADV7177/ADV7178
TR06
TR07
TR05
TR04
TR03
TR00
BLACK INPUT
CONTROL
TIMING
REGISTER RESET
TR03
0
1
TR07
PIXEL PORT
CONTROL
0
0
1
1
0
1
0
1
TR00
0
1
SLAVE TIMING
MASTER TIMING
TIMING MODE
SELECTION
LUMA DELAY
8-BIT
16-BIT
MASTER/SLAVE
CONTROL
ENABLE
DISABLE
TR05 TR04
TR06
0
1
TR01
TR02
TR02 TR01
0ns DELAY
74ns DELAY
148ns DELAY
222ns DELAY
0
0
1
1
0
1
0
1
MODE 0
MODE 1
MODE 2
MODE 3
Figure 35. Timing Register 0
Luma Delay Control (TR05–TR04)
Toggling TR07 from low to high and low again resets the internal timing counters. This bit should be toggled after power-up,
reset or changing to a new timing mode.
BYTE 1
These 8-bit-wide registers are used to set up the closed captioning
extended data bytes on even fields. Figure 36 shows how the
high and low bytes are set up in the registers.
HSYNC TO PIXEL
DATA ADJUSTMENT
0
1
0
1
BYTE 0
TR14
TR13
TR15 TR14
x
x
0
1
CCD15
CCD7
CCD14
CCD6
TR12
CCD13
CCD5
TC
TB
TB + 32ms
0
0
1
1
0
1
0
1
TB
0 x TPCLK
4 x TPCLK
8 x TPCLK
16 x TPCLK
0
0
1
1
0
1
0
1
TA
1 x TPCLK
4 x TPCLK
16 x TPCLK
128 x TPCLK
1 x TPCLK
4 x TPCLK
16 x TPCLK
128 x TPCLK
TIMING MODE 1 (MASTER/PAL)
LINE 1
HSYNC
LINE 313
TA
TC
TB
FIELD/VSYNC
Figure 38. Timing Register 1
REV. 0
CCD3
HSYNC WIDTH
TR11 TR10
TR15 TR14
0
1
0
1
CED10
CED2
CCD11
TR10
VSYNC WIDTH
(MODE 2 ONLY)
0
0
1
1
CED3
CCD12
CCD4
TR11
HSYNC TO
FIELD/VSYNC DELAY
TR13 TR12
0 x TPCLK
1 x TPCLK
2 x TPCLK
3 x TPCLK
CED4
CED11
CED9
CED1
CED8
CED0
CCD10
CCD2
CCD9
CCD1
–25–
LINE 314
CCD8
CCD0
Figure 37. Closed Captioning Data Register
HSYNC TO FIELD
RISING EDGE DELAY
(MODE 1 ONLY)
TR17 TR16
CED5
CED12
These 8-bit-wide registers are used to set up the closed captioning
data bytes on odd fields. Figure 37 shows how the high and low
bytes are set up in the registers.
CLOSED CAPTIONING EVEN FIELD
DATA REGISTER 1–0 (CED15–CED00)
(Address [SR4–SR0] = 09–08H)
TR15
CED6
CED13
CLOSED CAPTIONING ODD FIELD
DATA REGISTER 1–0 (CCD15–CCD00)
(Subaddress [SR4–SR0] = 0B–0AH)
Timing Register Reset (TR07)
TR16
CED14
Figure 36. Closed Captioning Extended Data Register
This bit is used to set the pixel port to accept 8-bit or 16-bit data.
If an 8-bit input is selected the data will be set up on Pins P7–P0.
0
0
1
1
CED7
BYTE 0
Pixel Port Select (TR06)
TR17
CED15
BYTE 1
These bits control the addition of a luminance delay. Each bit
represents a delay of 74 ns.
ADV7177/ADV7178
TIMING REGISTER 1 (TR17–TR10)
(Address [SR4–SR0] = 0CH)
MR2 BIT DESCRIPTION
Square Pixel Mode Control (MR20)
Timing Register 1 is an 8-bit-wide register.
This bit is used to set up square pixel mode. This is available in
slave mode only. For NTSC, a 24.54 MHz clock must be supplied. For PAL, a 29.5 MHz clock must be supplied.
Figure 38 shows the various operations under the control of
Timing Register 1. This register can be read from as well as
written to. This register can be used to adjust the width and
position of the master mode timing signals.
Active Video Line Control (MR23)
TR1 BIT DESCRIPTION
HSYNC Width (TR11–TR10)
This bit switches between two active video line durations. A
zero selects ITU-R BT.470 (720 pixels PAL/NTSC) and a one
selects ITU-R/SMPTE “analog” standard for active video duration (710 pixels NTSC 702 pixels PAL).
These bits adjust the HSYNC pulsewidth.
Chrominance Control (MR24)
HSYNC to VSYNC/FIELD Delay Control (TR13–TR12)
This bit enables the color information to be switched on and off
the video output.
These bits adjust the position of the HSYNC output relative to
the FIELD/VSYNC output.
Burst Control (MR25)
HSYNC to FIELD Delay Control (TR15–TR14)
This bit enables the burst information to be switched on and off
the video output.
When the ADV7177/ADV7178 is in Timing Mode 1, these bits
adjust the position of the HSYNC output relative to the FIELD
output rising edge.
RGB/YUV Control (MR26)
This bit enables the output from the RGB DACs to be set to
YUV output video standard. Bit MR06 of Mode Register 0
must be set to Logic Level “1” before MR26 is set.
VSYNC Width (TR15–TR14)
When the ADV7177/ADV7178 is in Timing Mode 2, these bits
adjust the VSYNC pulsewidth.
Table II. DAC Output Configuration Matrix
HSYNC to Pixel Data Adjust (TR17–TR16)
This enables the HSYNC to be adjusted with respect to the
pixel data. This allows the Cr and Cb components to be
swapped. This adjustment is available in both master and slave
timing modes.
MODE REGISTER 2 MR2 (MR27–MR20)
(Address [SR4-SR0] = 0DH)
MR06
MR26
DAC A
DAC B
DAC C
0
0
1
1
0
1
0
1
CVBS
CVBS
B
U
Y
Y
S
Y
C
C
R
V
CVBS:
Y:
C:
U:
V:
R:
G:
B:
Mode Register 2 is an 8-bit-wide register.
Figure 39 shows the various operations under the control of Mode
Register 2. This register can be read from as well as written to.
Composite Video Baseband Signal
Luminance Component Signal (For YUV or Y/C Mode)
Chrominance Signal (For Y/C Mode)
Chrominance Component Signal (For YUV Mode)
Chrominance Component Signal (For YUV Mode)
RED Component Video (For RGB Mode)
GREEN Component Video (For RGB Mode)
BLUE Component Video (For RGB Mode)
Low Power Control (MR27)
This bit enables the lower power mode of the ADV7177/
ADV7178. This will reduce DAC current by 50%.
MR27
MR26
MR25
RGB OUTPUT
YUV OUTPUT
LOW POWER
MODE
0
1
0
1
ENABLE COLOR
DISABLE COLOR
BURST
CONTROL
MR25
DISABLE
ENABLE
0
1
MR22
CCIR624/CCIR601
CONTROL
0
1
MR20
ZERO SHOULD
BE WRITTEN TO
THESE BITS
MR23
ENABLE BURST
DISABLE BURST
MR21
MR22–MR21
(00)
MR24
MR26
MR27
MR23
CHROMINANCE
CONTROL
RGB/YUV
CONTROL
0
1
MR24
SQUARE PIXEL
CONTROL
MR20
CCIR624 OUTPUT
CCIR601 OUTPUT
0
1
DISABLE
ENABLE
Figure 39. Mode Register 2
–26–
REV. 0
ADV7177/ADV7178
NTSC PEDESTAL REGISTERS 3–0 (PCE15–0, PCO15–0)
(Subaddress [SR4–SR0] = 11–0EH)
MR3 BIT DESCRIPTION
Revision Code (MR30)
These 8-bit-wide registers are used to set up the NTSC pedestal
on a line-by-line basis in the vertical blanking interval for both
odd and even fields. Figure 40 show the four control registers.
A Logic “1” in any of the bits of these registers has the effect of
turning the pedestal OFF on the equivalent line when used in
NTSC.
This bit is read only and indicates the revision of the device.
VBI Pass-Through Control (MR31)
This bit determines whether or not data in the vertical blanking
interval (VBI) is output to the analog outputs or blanked.
Clock Output Select (MR33–MR32)
These bits control the synchronous clock output signal. The
clock can be 27 MHz, 13.5 MHz or disabled, depending on the
values of these bits.
LINE 17 LINE 16 LINE 15 LINE 14 LINE 13 LINE 12 LINE 11 LINE 10
FIELD 1/3
PCO7
PCO6
PCO5
PCO4
PCO3
PCO2
PCO1
PCO0
OSD Enable (MR35)
LINE 25 LINE 24 LINE 23 LINE 22 LINE 21 LINE 20 LINE 19 LINE 18
FIELD 1/3
PCO15
PCO14
PCO13
PCO12
PCO11
PCO10
PCO9
A logic one in MR35 will enable the OSD function on the
ADV7177.
PCO8
Reserved (MR36)
LINE 17 LINE 16 LINE 15 LINE 14 LINE 13 LINE 12 LINE 11 LINE 10
FIELD 2/4
PCE7
PCE6
PCE5
PCE4
PCE3
PCE2
PCE1
These bits are reserved.
PCE0
Input Default Color (MR36)
LINE 25 LINE 24 LINE 23 LINE 22 LINE 21 LINE 20 LINE 19 LINE 18
FIELD 2/4
PCE15
PCE14
PCE13
PCE12
PCE11
PCE10
PCE9
This bit determines the default output color from the DACs for
zero input data (or disconnected). A Logical “0” means that the
color corresponding to 00000000 will be displayed. A Logical
“1” forces the output color to black for 00000000 input video
data.
PCE8
Figure 40. Pedestal Control Registers
MODE REGISTER 3 MR3 (MR37–MR30)
(Address [SR4–SR0] = 12H)
OSD REGISTER 0–11
(Address [SR4–SR0] = 12H–1DH)
Mode Register 3 is an 8-bit-wide register.
Figure 41 shows the various operations under the control of
Mode Register 3.
There are 12 OSD registers as shown in Figure 42. There are
four bits for each Y, Cb and Cr value, there are four zero added
to give the complete byte for each value loaded internally.
(Y0 = [Y03, Y02, Y01, Y00, 0, 0, 0, 0], Cb = [Cb3, Cb2, Cb1,
Cb0, 0, 0, 0, 0,], Cr = [Cr3, Cr2, Cr1, Cr0, 0, 0, 0, 0].)
MR36
MR37
MR35
MR34
MR33
MR32
MR31
MR30
CLOCK CONTROL
MR37
ZERO SHOULD
BE WRITTEN TO
THIS BIT
DISABLE
ENABLE
INPUT DEFAULT COLOR
MR36
0
1
0
0
1
1
MR35
0
1
MR30
MR33-32
OSD ENABLE
0
1
0
1
CLOCK OUTPUT OFF
13.5MHz OUTPUT
27MHz OUTPUT
CLOCK OUTPUT OFF
MR34
ZERO SHOULD
BE WRITTEN TO
THIS BIT
INPUT COLOR
BLACK
REV CODE
(READ ONLY)
VBI PASSTHROUGH
MR31
0
1
DISABLE
ENABLE
Figure 41. Mode Register 3
OSD
REG 0
Y0
OSD
REG 1
Cb0
OSD
REG 2
OSD
REG 11
Cr0
Y1
Cr1
Cb1
Cr7
Cb7
Figure 42. OSD Registers
REV. 0
–27–
ADV7177/ADV7178
APPENDIX 1
BOARD DESIGN AND LAYOUT CONSIDERATIONS
Supply Decoupling
The ADV7177/ADV7178 is a highly integrated circuit containing
both precision analog and high speed digital circuitry. It has
been designed to minimize interference effects on the integrity
of the analog circuitry by the high speed digital circuitry. It is
imperative that these same design and layout techniques be
applied to the system level design so that high speed, accurate
performance is achieved. The “Recommended Analog Circuit
Layout” shows the analog interface between the device and
monitor.
For optimum performance, bypass capacitors should be installed using the shortest leads possible, consistent with reliable
operation, to reduce the lead inductance. Best performance is
obtained with 0.1 µF ceramic capacitor decoupling. Each
group of VAA pins on the ADV7177/ADV7178 must have at
least one 0.1 µF decoupling capacitor to GND. These capacitors
should be placed as close to the device as possible.
The layout should be optimized for lowest noise on the ADV7177/
ADV7178 power and ground lines by shielding the digital inputs
and providing good decoupling. The lead length between groups
of VAA and GND pins should by minimized to minimize inductive ringing.
It is important to note that while the ADV7177/ADV7178 contains circuitry to reject power supply noise, this rejection decreases with frequency. If a high frequency switching power
supply is used, the designer should pay close attention to reducing power supply noise and consider using a three terminal voltage
regulator for supplying power to the analog power plane.
Ground Planes
Digital Signal Interconnect
The ground plane should encompass all ADV7177/ADV7178
ground pins, voltage reference circuitry, power supply bypass
circuitry for the ADV7177/ADV7178, the analog output traces,
and all the digital signal traces leading up to the ADV7177/
ADV7178. The ground plane is the board’s common ground
plane.
The digital inputs to the ADV7177/ADV7178 should be isolated as much as possible from the analog outputs and other
analog circuitry. Also, these input signals should not overlay the
analog power plane.
This should be as substantial as possible to maximize heat
spreading and power dissipation on the board.
Any active termination resistors for the digital inputs should be
connected to the regular PCB power plane (VCC) and not the
analog power plane.
Due to the high clock rates involved, long clock lines to the
ADV7177/ADV7178 should be avoided to reduce noise pickup.
Power Planes
The ADV7177/ADV7178 and any associated analog circuitry
should have its own power plane, referred to as the analog
power plane (VAA). This power plane should be connected to
the regular PCB power plane (VCC) at a single point through a
ferrite bead. This bead should be located within three inches of
the ADV7177/ADV7178.
The metallization gap separating device power plane and board
power plane should be as narrow as possible to minimize the
obstruction to the flow of heat from the device into the general
board.
The PCB power plane should provide power to all digital logic
on the PC board, and the analog power plane should provide
power to all ADV7177/ADV7178 power pins and voltage reference circuitry.
Plane-to-plane noise coupling can be reduced by ensuring that
portions of the regular PCB power and ground planes do not
overlay portions of the analog power plane unless they can be
arranged so that the plane-to-plane noise is common-mode.
Analog Signal Interconnect
The ADV7177/ADV7178 should be located as close to the
output connectors as possible to minimize noise pickup and
reflections due to impedance mismatch.
The video output signals should overlay the ground plane, not
the analog power plane, to maximize the high frequency power
supply rejection.
Digital inputs, especially pixel data inputs and clocking signals,
should never overlay any of the analog signal circuitry and
should be kept as far away as possible.
For best performance, the outputs should each have a 75 Ω load
resistor connected to GND. These resistors should be placed as
close as possible to the ADV7177/ADV7178 as to minimize
reflections.
The ADV7177/ADV7178 should have no inputs left floating.
Any inputs that are not required should be tied to ground.
–28–
REV. 0
ADV7177/ADV7178
POWER SUPPLY DECOUPLING
FOR EACH POWER SUPPLY GROUP
+5V (VAA)
0.1mF
+5V (VAA)
0.01mF
+5V (VAA)
0.1mF
L1
(FERRITE BEAD)
0.1mF
1, 20, 28, 30
VREF
33mF
10mF
31
32
GND
VAA
COMP
11 OSD_EN
34 OSD_0
OSD
INPUTS
35 OSD_1
36 OSD_2
LUMA 27
37–41,
3–10, 12–14
+5V (VAA)
CHROMA 26
75V
PIXEL
DATA
4kV
75V
ADV7177/
ADV7178
P15–P0
CVBS 25
RESET
100nF
75V
15 HSYNC
“UNUSED
INPUTS
SHOULD BE
GROUNDED”
16 FIELD/VSYNC
17 BLANK
+5V (VCC)
+5V (VCC)
5kV
5kV
22 RESET
44 CLOCK
33pF
27MHz
XTAL
33pF
100V
SCLOCK 23
100V
43 CLOCK
2
SDATA 24
CLOCK/2
27MHz OR 13.5MHz
CLOCK OUTPUT
ALSB
18
+5V (VAA)
RSET 33
GND
150V
19, 21
29, 42
10kV
Figure 43. Recommended Analog Circuit Layout
REV. 0
–29–
+5V
(VCC)
MPU BUS
ADV7177/ADV7178
APPENDIX 2
CLOSED CAPTIONING
The ADV7177/ADV7178 supports closed captioning, conforming to the standard television synchronizing waveform for color
transmission. Closed captioning is transmitted during the
blanked active line time of Line 21 of the odd fields and Line
284 of even fields.
FCC Code of Federal Regulations (CFR) 47 Section 15.119
and EIA608 describe the closed captioning information for
Lines 21 and 284.
Closed captioning consists of a 7-cycle sinusoidal burst that is
frequency and phase locked to the caption data. After the clock
run-in signal, the blanking level is held for two data bits and is
followed by a Logic Level “1” start bit. 16 bits of data follow
the start bit. These consist of two 8-bit bytes, seven data bits
and one odd parity bit. The data for these bytes is stored in
closed captioning Data Registers 0 and 1.
The ADV7177/ADV7178 also supports the extended closed
captioning operation, which is active during even fields, and is
encoded on scan Line 284. The data for this operation is stored
in closed captioning extended Data Registers 0 and 1.
All clock run-in signals and timing to support closed captioning
on Lines 21 and 284 are generated automatically by the ADV7177/
ADV7178. All pixels inputs are ignored during Lines 21 and
284.
10.5 6 0.25ms
The ADV7177/ADV7178 uses a single buffering method. This
means that the closed captioning buffer is only one byte deep,
therefore there will be no frame delay in outputting the closed
captioning data unlike other 2-byte deep buffering systems. The
data must be loaded at least one line before (Line 20 or Line
283) it is outputted on Line 21 and Line 284. A typical implementation of this method is to use VSYNC to interrupt a microprocessor, which will in turn load the new data (two bytes) every
field. If no new data is required for transmission you must
insert zeros in both the data registers; this is called NULLING.
It is also important to load “control codes,” all of which are
double bytes on Line 21, or a TV will not recognize them. If
you have a message like “Hello World,” which has an odd number of characters, it is important to pad it out to an even number
to get “end of caption” 2-byte control code to land in the same
field.
12.91ms
7 CYCLES
OF 0.5035 MHz
(CLOCK RUN-IN)
TWO 7-BIT + PARITY
ASCII CHARACTERS
(DATA)
S
T
A
R
T
50 IRE
D0–D6
P
A
R
I
T
Y
D0–D6
P
A
R
I
T
Y
BYTE 1
BYTE 0
40 IRE
REFERENCE COLOR BURST
(9 CYCLES)
FREQUENCY = FSC = 3.579545MHz
AMPLITUDE = 40 IRE
10.003ms
33.764ms
27.382ms
Figure 44. Closed Captioning Waveform (NTSC)
–30–
REV. 0
ADV7177/ADV7178
APPENDIX 3
NTSC WAVEFORMS (WITH PEDESTAL)
130.8 IRE
PEAK COMPOSITE
1268.1mV
100 IRE
REF WHITE
1048.4mV
714.2mV
7.5 IRE
0 IRE
BLACK LEVEL
BLANK LEVEL
387.6mV
334.2mV
–40 IRE
SYNC LEVEL
48.3mV
REF WHITE
1048.4mV
Figure 45. NTSC Composite Video Levels
100 IRE
714.2mV
7.5 IRE
0 IRE
BLACK LEVEL
BLANK LEVEL
–40 IRE
SYNC LEVEL
387.6mV
334.2mV
48.3mV
Figure 46. NTSC Luma Video Levels
PEAK CHROMA
1067.7mV
835mV (pk-pk)
286mV (pk-pk)
BLANK/BLACK LEVEL
650mV
PEAK CHROMA
232.2mV
0mV
Figure 47. NTSC Chroma Video Levels
100 IRE
REF WHITE
1052.2mV
720.8mV
7.5 IRE
0 IRE
BLACK LEVEL
BLANK LEVEL
–40 IRE
SYNC LEVEL
Figure 48. NTSC RGB Video Levels
REV. 0
–31–
387.5mV
331.4mV
45.9mV
ADV7177/ADV7178
NTSC WAVEFORMS (WITHOUT PEDESTAL)
130.8 IRE
PEAK COMPOSITE
1289.8mV
100 IRE
REF WHITE
1052.2mV
714.2mV
0 IRE
BLANK/BLACK LEVEL
338mV
–40 IRE
SYNC LEVEL
52.1mV
Figure 49. NTSC Composite Video Levels
100 IRE
REF WHITE
1052.2mV
714.2mV
0 IRE
BLANK/BLACK LEVEL
SYNC LEVEL
–40 IRE
338mV
52.1mV
Figure 50. NTSC Luma Video Levels
PEAK CHROMA
1101.6mV
903.2mV (pk-pk)
307mV (pk-pk)
BLANK/BLACK LEVEL
650mV
PEAK CHROMA
198.4mV
0mV
Figure 51. NTSC Chroma Video Levels
100 IRE
REF WHITE
1052.2mV
715.7mV
BLANK/BLACK LEVEL
0 IRE
SYNC LEVEL
–40 IRE
336.5mV
51mV
Figure 52. NTSC RGB Video Levels
–32–
REV. 0
ADV7177/ADV7178
PAL WAVEFORMS
PEAK COMPOSITE
1284.2mV
1047.1mV
REF WHITE
696.4mV
350.7mV
BLANK/BLACK LEVEL
50.8mV
SYNC LEVEL
Figure 53. PAL Composite Video Levels
REF WHITE
1047mV
696.4mV
BLANK/BLACK LEVEL
350.7mV
SYNC LEVEL
50.8mV
Figure 54. PAL Luma Video Levels
PEAK CHROMA
1092.5mV
885mV (pk-pk)
300mV (pk-pk)
BLANK/BLACK LEVEL
650mV
PEAK CHROMA
207.5mV
0mV
Figure 55. PAL Chroma Video Levels
REF WHITE
1050.2mV
698.4mV
BLANK/BLACK LEVEL
351.8mV
SYNC LEVEL
51mV
Figure 56. PAL RGB Video Levels
REV. 0
–33–
334mV
BLACK
BLUE
RED
MAGENTA
GREEN
CYAN
505mV
YELLOW
WHITE
BLACK
RED
BLUE
UV WAVEFORMS
MAGENTA
GREEN
CYAN
WHITE
YELLOW
ADV7177/ADV7178
505mV
423mV
171mV
BETACAM LEVEL
BETACAM LEVEL
82mV
0mV
0mV
0mV
0mV
–82mV
2171mV
2334mV
–423mV
–505mV
2505mV
309mV
BLACK
BLUE
RED
MAGENTA
GREEN
CYAN
WHITE
467mV
YELLOW
Figure 60. NTSC 100% Color Bars No Pedestal V Levels
BLACK
BLUE
RED
MAGENTA
GREEN
CYAN
WHITE
YELLOW
Figure 57. NTSC 100% Color Bars No Pedestal U Levels
467mV
391mV
158mV
BETACAM LEVEL
BETACAM LEVEL
76mV
0mV
0mV
0mV
0mV
–76mV
–158mV
–309mV
–391mV
–467mV
–467mV
BLACK
BLUE
RED
MAGENTA
GREEN
CYAN
WHITE
350mV
YELLOW
Figure 61. NTSC 100% Color Bars with Pedestal V Levels
BLACK
BLUE
RED
MAGENTA
GREEN
CYAN
YELLOW
WHITE
Figure 58. NTSC 100% Color Bars with Pedestal U Levels
350mV
232mV
293mV
118mV
SMPTE LEVEL
SMPTE LEVEL
57mV
0mV
0mV
0mV
0mV
–57mV
–118mV
–232mV
–293mV
–350mV
–350mV
Figure 59. PAL 1005 Color Bars U Levels
Figure 62. PAL 100% Color Bars V Levels
–34–
REV. 0
ADV7177/ADV7178
APPENDIX 4
REGISTER VALUES
Address
The ADV7177/ADV7178 registers can be set depending on the
user standard required.
The following examples give the various register formats for
several video standards.
In each case the output is set to composite o/p with all DACs
powered up and with the BLANK input control disabled. Additionally, the burst and color information are enabled on the
output and the internal color bar generator is switched off. In
the examples shown, the timing mode is set to Mode 0 in slave
format. TR02–TR00 of the Timing Register 0 control the timing modes. For a detailed explanation of each bit in the command registers, please turn to the Register Programming section
of the data sheet. TR07 should be toggled after setting up a new
timing mode. Timing Register 1 provides additional control over
the position and duration of the timing signals. In the examples,
this register is programmed in default mode.
NTSC (FSC = 3.5795454 MHz)
Address
Data
00Hex
01Hex
02Hex
03Hex
04Hex
05Hex
06Hex
07Hex
08Hex
09Hex
0AHex
0BHex
0CHex
0DHex
0EHex
0FHex
10Hex
11Hex
12Hex
04Hex
00Hex
16Hex
7CHex
F0Hex
21Hex
00Hex
08Hex
00Hex
00Hex
00Hex
00Hex
00Hex
80Hex
00Hex
00Hex
00Hex
00Hex
00Hex
Mode Register 0
Mode Register 1
Subcarrier Frequency Register 0
Subcarrier Frequency Register 1
Subcarrier Frequency Register 2
Subcarrier Frequency Register 3
Subcarrier Phase Register
Timing Register 0
Closed Captioning Ext Register 0
Closed Captioning Ext Register 1
Closed Captioning Register 0
Closed Captioning Register 1
Timing Register 1
Mode Register 2
Pedestal Control Register 0
Pedestal Control Register 1
Pedestal Control Register 2
Pedestal Control Register 3
Mode Register 3
PAL B, D, G, H, I (FSC = 4.43361875 MHz)
Address
Data
00Hex
01Hex
02Hex
03Hex
04Hex
05Hex
06Hex
07Hex
08Hex
09Hex
0AHex
0BHex
0CHex
0DHex
01Hex
00Hex
CBHex
8AHex
09Hex
2AHex
00Hex
08Hex
00Hex
00Hex
00Hex
00Hex
00Hex
80Hex
REV. 0
Mode Register 0
Mode Register 1
Subcarrier Frequency Register 0
Subcarrier Frequency Register 1
Subcarrier Frequency Register 2
Subcarrier Frequency Register 3
Subcarrier Phase Register
Timing Register 0
Closed Captioning Ext Register 0
Closed Captioning Ext Register 1
Closed Captioning Register 0
Closed Captioning Register 1
Timing Register 1
Mode Register 2
0EHex
0FHex
10Hex
11Hex
12Hex
Data
Pedestal Control Register 0
Pedestal Control Register 1
Pedestal Control Register 2
Pedestal Control Register 3
Mode Register 3
00Hex
00Hex
00Hex
00Hex
00Hex
PAL M (FSC = 3.57561149 MHz)
Address
Data
00Hex
01Hex
02Hex
03Hex
04Hex
05Hex
06Hex
07Hex
08Hex
09Hex
0AHex
0BHex
0CHex
0DHex
0EHex
0FHex
10Hex
11Hex
12Hex
06Hex
00Hex
A3Hex
EFHex
E6Hex
21Hex
00Hex
08Hex
00Hex
00Hex
00Hex
00Hex
00Hex
80Hex
00Hex
00Hex
00Hex
00Hex
00Hex
–35–
Mode Register 0
Mode Register 1
Subcarrier Frequency Register 0
Subcarrier Frequency Register 1
Subcarrier Frequency Register 2
Subcarrier Frequency Register 3
Subcarrier Phase Register
Timing Register 0
Closed Captioning Ext Register 0
Closed Captioning Ext Register 1
Closed Captioning Register 0
Closed Captioning Register 1
Timing Register 1
Mode Register 2
Pedestal Control Register 0
Pedestal Control Register 1
Pedestal Control Register 2
Pedestal Control Register 3
Mode Register 3
ADV7177/ADV7178
APPENDIX 5
OPTIONAL OUTPUT FILTER
0
VdB – OP
–5
–10
DECIBELS
If an output filter is required for the CVBS, Y, UV, Chroma and
RGB outputs of the ADV7177/ADV7178, the following filter in
Figure 63 can be used. Plots of the filter characteristics are
shown in Figures 64, 65 and 66. An output filter is not required
if the outputs of the ADV7177/ADV7178 are connected to an
analog monitor or an analog TV; however, if the output signals
are applied to a system where sampling is used (e.g., digital
TV), a filter is required to prevent aliasing.
–15
–20
–25
L
1mH
L
2.7mH
L
0.68mH
IN
–30
OUT
R
75V
C
470pF
C
330pF
C
56pF
R
75V
–35
10
FREQUENCY – MHz
1
Figure 63. Output Filter
Figure 65. Output Filter Close Up
0
0.0
–5
–10
100
–0.5
VdB – OP
VdB – OP
–15
–1.0
–1.5
–25
DECIBELS
DECIBELS
–20
–30
–35
–40
–45
–2.0
–2.5
–3.0
–50
–3.5
–55
–60
–4.0
–65
–70
10k
100k
1M
FREQUENCY – Hz
10M
–4.5
100M
Figure 64. Output Filter Plot
1
2
4
FREQUENCY – MHz
6
8
10
Figure 66. Output Filter Plot Close Up
–36–
REV. 0
ADV7177/ADV7178
APPENDIX 6
OPTIONAL DAC BUFFERING
For external buffering of the ADV7177/ADV7178 DAC outputs, the configuration in Figure 67 is recommended. This
configuration shows the DAC outputs running at half (18 mA)
their full current (34.7 mA) capability. This will allow the
ADV7177/ADV7178 to dissipate less power, the analog current is
reduced by 50% with a RSET of 300 Ω and a RLOAD of 75 Ω. This
mode is recommended for 3.3 volt operation as optimum performance is obtained from the DAC outputs at 18 mA with a VAA of
3.3 volts. This buffer also adds extra isolation on the video out-
puts, see buffer circuit in Figure 68. When calculating absolute
output full current and voltage, use the following equation:
V OUT = IOUT × RLOAD
IOUT =
(V
REF
×K
)
RSET
K = 4.2146 constant , VREF = 1.235 V
VAA
VCC
ADV7177/ADV7178
VREF
DAC A
36V
OUTPUT
BUFFER
OUTPUT TO
TV/MONITOR
75V
DAC B
PIXEL
PORT
DIGITAL
CORE
2N2907
75V
75V
DAC C
RSET
INPUT
OUTPUT
BUFFER
75V
OUTPUT
BUFFER
75V
300V
Figure 67. Output DAC Buffering Configuration
REV. 0
Figure 68. Recommended Output DAC Buffer
–37–
ADV7177/ADV7178
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
Plastic Quad Flatpack
(S-44)
0.096 (2.44)
MAX
0.037 (0.94)
0.025 (0.64)
C3314–2.5–8/98
0.548 (13.925)
0.546 (13.875)
0.398 (10.11)
0.390 (9.91)
88
0.88
33
23
34
22
SEATING
PLANE
TOP VIEW
(PINS DOWN)
44
0.040 (1.02)
0.032 (0.81)
0.040 (1.02)
0.032 (0.81)
12
1
11
0.033 (0.84)
0.029 (0.74)
0.016 (0.41)
0.012 (0.30)
PRINTED IN U.S.A.
0.083 (2.11)
0.077 (1.96)
–38–
REV. 0