CXD2053AM/AS Auto Wide, EDTV-II ID Detection, ID-1 Detection For the availability of this product, please contact the sales office. Description The CXD2053AM/AS is an IC which has the three functions of identifying the wide video (auto wide), detecting the EDTV-II ID, and detecting ID-1 (EIAJ, CPX1024) from the video signal. CXD2053AM 28 pin SOP (Plastic) Features • Video aspect ratio identification used with wide TVs is realized with a single chip. • I2C bus interface. This IC can also be used without the bus. • For auto wide function, 525/60 (NTSC) and 625/50 (PAL, SECAM) can be Supported. CXD2053AS 28 pin SDIP (Plastic) Absolute Maximum Ratings VSS – 0.5 to +7.0 • Supply voltage VDD • Input voltage VI VSS – 0.5 to VDD + 0.5 • Output voltage VO VSS – 0.5 to VDD + 0.5 • Storage temperature Tstg –55 to +150 Applications Wide TV V V V °C Recommended Operating Conditions • Supply voltage VDD 4.5 to 5.5 Structure Silicon gate CMOS IC • Operating temperature Topr –20 to +70 V °C Block Diagram Auto wide Identification ADIN 2 AD Converter EDTV-II ID Decoder 26 OAW1 27 OAW2 28 OED 25 O164 ID-1 Decoder 24 OLBX VSIN 10 I2C Bus Interface Data Slice Sync Separator Timing Signal Generator XI 22 15 SCL 16 SDA 19 MCON 21 XO VDIN 11 Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E96531-ST CXD2053AM/AS Pin Description Pin No. Symbol 1 AVDD 2 ADIN 3 AVSS 4 CPV 5 I/O I/O level Description ANALOG Analog power supply. ANALOG AD converter input. ANALOG Analog ground. I ANALOG Clamp voltage. VRB I ANALOG AD converter bottom voltage. 6 VRT I ANALOG AD converter top voltage. 7 CCP I ANALOG AD converter clamp integrating capacitor connection. 8 ISET I ANALOG Bias current setting. 9 AVDD 10 VSIN I ANALOG Sync separation input. 11 VDIN I ANALOG Data slicer input. 12 AVSS Test input; connect to VSS. Test input; connect to VSS. I Analog power supply Analog ground. 13 TST1 I TTL∗2 14 TST2 I TTL∗2 15 SCL [EDDEC2] I CMOS∗1 16 SDA [ED2FSC] I/O CMOS∗1, 3 17 VSS 18 XRST I TTL∗1 19 MCON I TTL 20 VDD 21 XO O CMOS Oscillator connection (14.318MHz). 22 XI I CMOS Oscillator connection or clock input. 23 VSS 24 OLBX O CMOS VB-ID detection output; 1 = letter-box, 0 = normal. 25 O164 O CMOS VB-ID detection output; 1 = full mode. 26 OAW1 O CMOS Auto wide identification output; 1 = wide video subtitles not present. 27 OAW2 O CMOS Auto wide identification output; 1 = wide video subtitles present. 28 OED O CMOS EDTV-II ID bit 3 detection output. I2C bus clock [EDTV-II decoding identification switching] I2C bus data [EDTV-II 3.58 M check existence] Digital ground. Reset at 0. I2C bus-free mode switching; 0 = I2C-free. Digital system power supply. Digital ground. ∗1 Schmitt input ∗2 With pull-down resistor ∗3 Open drain Note) In I2C-free mode when Pin 19 (MCON) = 0, Pins 15 and 16 switch to the functions in parentheses [ –2– ]. CXD2053AM/AS Electrical Characteristics DC Characteristics (Logic Section) Item Output voltage Output voltage Output voltage Input voltage Input voltage Input voltage Symbol (VDD = 5.0V, VSS = 0V, Ta = 25°C) Condition Min. Typ. VDD – 0.8 Remarks V Pins 24, 25, 26, 27 and 28 IOH = –2mA VOL IOL = 4mA VOH IOH = –3mA VOL IOL = 3mA VDD/2 V VOL IOL = 3mA 0.4 V Pin 16 only V Pins 13, 14, 18 and 19 0.4 VDD/2 VIH VIL 0.8 0.7 × VDD VIH 0.3 × VDD 0.8 × VDD 0.2 × VDD 0.05 × VDD Ii VIN = either VSS or VDD –10 Output leak current IOZ VIN = eother VSS or VDD –40 Input current Ii VIN = VDD 40 Feedback resistor Rfbk XI (Pin 22) = either VDD or VSS 250k Current consumption IDD V Pin 21 only Pin 22 only Pins 15 and 16 V Pins 15 and 16 V Pin 18 +10 µA Except for Pins 13, 14 and 22 +40 µA Pin 16 only 100 240 µA Pins 13 and 14 1M 2.5M Ω Between Pins 21 and 22 mA Sum of Pins 1, 9 and 20 0.4 Clock 14.318MHz V V VIL Input leak current V V VIL VIH V V 2.2 Vhys 29 AC Characteristics Clock frequency Unit VOH Input hysteresis width Item Max. (VDD = 5.0V, VSS = 0V, Ta = 25°C) Symbol Condition Min. fxi Typ. Max. Unit Remarks MHz Pin 22 input, or oscillator between Pins 21 and 22 Max. Unit Remarks 14.318 I/O Pin Capacitance Item Symbol Condition Min. Typ. Input pin capacitance CIN VDD = VI = 0V, f = 1MHz 9 pF Output pin capacitance COUT VDD = VI = 0V, f = 1MHz 11 pF Input/output pin capacitance CI/O VDD = VI = 0V, f = 1MHz 11 pF –3– CXD2053AM/AS Pins and Electrical Characteristics Analog Section Pin No. Symbol (VDD = 5.0V, VSS = 0V, Ta = 25°C) Equivalent circuit Description 1 AVDD Not connected to VDD (Pin 20) or AVDD (Pin 9) inside the IC. AD converter analog power supply. Connect a low-noise power supply from the digital system. 3 AVSS Not connected to VSS (Pins 17 and 23) or AVSS (Pin 12) inside the IC. AD converter analog ground. Connect to the same potential as other VSS and AVSS. AVDD 2 AD converter input. This pin is pedestal clamped to the potential of CPV (Pin 4), so input the video signal with capacitor coupled. 2 ADIN AVSS AVDD 4 ADIN (Pin 2) pedestal clamp voltage setting. 4 CPV AVSS AVDD 5 VRB 6 AD converter input range setting. The resistor between Pins 5 and 6 is 310Ω (Typ.). AVSS AVDD 5 6 VRT AVSS AVDD 7 CCP Clamp circuit integrating capacitor connection. Connect 0.022µF between this pin and AVSS (Pin 3). 7 AVSS –4– CXD2053AM/AS Pin No. 9 12 Symbol Equivalent circuit Description AVDD Not connected to VDD (Pin 20) or AVDD (Pin 1) inside the IC. Sync separation system analog power supply. Connect a low-noise power supply from the digital system. AVSS Not connected to AVSS (Pin 3) or VSS (Pins 17 and 23) inside the IC. Sync separation system analog ground. Connect to the same potential as other VSS and AVSS. AVDD 8 Bias setting. Connect to AVDD (Pin 9) with 33kΩ. 8 ISET AVSS Chip clamp, sync separation input. Input with capacitor coupled. AVDD 10 VSIN 10 Clamp voltage 1.5V AVSS Pedestal clamp, ID-1 data slicer input. Input with capacitor coupled. AVDD 11 VDIN 11 Clamp voltage 1.5V AVSS –5– CXD2053AM/AS 1. Description of auto wide function The auto wide function performs wide screen identification from the black bands at the top and bottom of the screen. As shown below, the CXD2053AM/AS identifies the three types of 4:3 normal video, 16:9 wide video, and wide video with subtitles. 4:3 normal video 16:9 wide video Wide video with subtitles Fig. 1. Wide identification types The results of this auto wide identification are expressed by 2 bits, and are output through the I2C bus during bus mode. Also, these results are output directly to the OAW1 (Pin 26) and OAW2 (Pin 27) pins regardless of bus or bus-free mode. Auto wide identification is provided with a transition time of about 1 to 15 seconds to prevent misoperation. During I2C bus mode, wide identification can be changed quickly without this transition time by manipulating the INST bit. 2. Description of ID-1 (transmitter method of additional video information, aspect ratio identification) As shown in the table below, the additional video information consists of 14-bit data, to which a 6-bit CRCC is appended for a total of 20 bits. On an NTSC video signal, this information is carried on lines 20 and 283 of the vertical blanking interval. bit-No Description A 1 2 3 Transmitter aspect ratio Pictorial representation format Undefined B 4 5 6 Discrimination information about the video signal and any other signal (audio signal, etc.) incident to the video and transmitted simultaneously. WORD0 WORD1 WORD2 "1" "0" Full mode (16:9) Letter-box 4:3 Normal 4-bit width Word 0 dependent discrimination signal 4-bit width Word 0 dependent discrimination signal, information, etc. (From the Provisional Standard of EIAJ, CPX-1204) Table 1. Description of ID-1 signal Of the 14-bit data noted above, only the first 2 bits are handled by the CXD2053AM/AS. These 2 bits are obtained by the I2C bus during bus mode. Also, these bits are output directly to the OLBX (Pin 24) and O164 (Pin 25) regardless of bus or bus-free mode. –6– CXD2053AM/AS 3. Description of EDTV-II ID As shown in the table below, EDTV-II ID consists of 27-bit data. On an NTSC video signal, this information is carried on lines 22 and 285 of the vertical blanking interval. Bit No. Description 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Reference signal Reference signal Letter-box Parity of bits 3 and 5 Undefined Field No. Multiphase VT VH HH HH precombing Broadcasting station operation bit Broadcasting station operation bit Broadcasting station operation bit 0 1 — 0 Full line 0 0 1 A No No No No 1 — Letter-box 1 — 2 B Yes Yes Yes Yes Bit No. 15 16 17 18 19 20 21 22 23 24 25 26 27 Description 0 1 — Undefined — Undefined — Undefined Error correction signal Error correction signal Error correction signal Error correction signal Error correction signal Error correction signal 0 0 Confirmation sine wave Confirmation sine wave Confirmation sine wave — — — — Table 2. Description of EDTV-II ID (discrimination control signal) signal Of the 27 bits noted above, the CXD2053AM/AS outputs only bits 3 and 5. These 2 bits are obtained by the I2C bus during bus mode. Also, bit 3 only is output directly to the OED (Pin 28) regardless of bus or bus-free mode. Since the CXD2053AM/AS does not perform decode processing for bits 6 to 23, this results in simple identification which does not use the error correction signals. 4. Clock The CXD2053AM/AS requires a 4fsc clock (14.318MHz). Connect XI (Pin 22) and XO (Pin 21) when using a crystal oscillator. When inputting the clock from an external source, input to XI (Pin 22). Clock is 14.318MHz regardless of switching auto wide 525/60 (NTSC) or 625/50 (PAL, SECAM). 5. Settings and data input/output The CXD2053AM/AS settings and data input/output can be performed by direct setting by pins or with the I2C bus interface. –7– CXD2053AM/AS 5-1. I2C bus Settings and data can be taken out via the I2C bus when MCON (Pin 19) is set to "1". This LSI supports the I2C bus slave RECEIVER and slave TRANSMITTER modes. The slave address is 1C (H). Also, in addition to standard mode (Max. 100K bit/s), this LSI also supports high-speed mode (Max. 400K bit/s). Even when the IC power supply falls to 0V, it does not occupy the bus. However, the Absolute Maximum Ratings should be strictly observed. The I2C bus transfer sequence is shown in the figure below. The amount of data transferred by this IC is 2 bytes for the write (RECEIVER) side and 1 byte for the readout (TRANSMITTER) side. Data write (RECEIVER mode) Sm 7654321 0 1 76543210 1 76543210 1 SLAm Wm As DATAm As DATAm As Data readout (TRANSMITTER mode) Sm 7654321 0 1 76543210 1 SLAm Rm As DATAs XAm Symbol ∗m from master to slave ∗s from slave to master S Start Condition P Stop Condition SLA Slave Address DATA Description Data W 0: Write Master→ Slave R 1: Read Slave → Master A Clock pulse for Acknowledgement (SDA: L) XA Acknowledgement none (SDA: H) –8– P P CXD2053AM/AS R/W Bit Name 1st byte bit 7 MSB ED2FSC WR ED2RES EDTV-II ID decoding function reset. 1 = reset. bit 5 bit 4 EDDEC1 EDTV-II ID decoding function detection switching. Standard values: bit 5 = 0, bit 4 = 1. bit 3 bit 2 EDDEC2 EDTV-II ID decoding function detection switching. Standard values: bit 3 = 0, bit 2 = 1. bit 1 VBLNJ1 Decoding not only of line 20 but also of the 1 line before and after line 20 by the ID-1 decoding function. 0 = yes, 1 = line 20 only. bit 0 LSB VBRES 2nd byte bit 7 MSB AWRES ID-1 decoding function reset. 1 = reset. Auto wide function reset. 1 = reset to 4:3. bit 6 INST Auto wide switching is performed without the wait time by changing INST from 0 to 1. bit 5 bit 4 bit 3 bit 2 No Use and TEST Not used and LSI test bits. Be sure to set all bits to 0. bit 1 UPAREA Normally. Set the same value as that of PAL bit below. When PAL = 0, UPAREA = 0, etc. LSB PAL bit 7 MSB bit 6 bit 5 1st byte 0 when checking the 3.58MHz amplitude during EDTV-II ID decoding; 1 when not checking the amplitude. bit 6 bit 0 RD Description ED2ID EDVLD bit 4 VBID bit 3 bit 2 LSB EDTV-II ID decoding results. 3rd bit of the EDTV-II ID. EDTV-II ID decoding results. 5th bit of the EDTV-II ID. EDTV-II ID decoding results judgment. Becomes 1 when a valid EDTV-II ID exists. The above noted ED2ID is output and held regardless of this judgment. ID-1 decoding results. 1st bit: full mode bit. ID-1 decoding results. 2nd bit: letter-box bit. VBVLD VB-ID decoding results judgment. Becomes 1 when a valid VB-ID exists. The above noted VB-ID is output and held regardless of this judgment. AWS Auto wide identification results. For 4:3 video, bit 1 = 0 and bit 0 = 0. For 16:9 wide video, bit 1 = 0 and bit 0 = 1. For subtitle video, bit 1 = 1 and bit 0 = 0. bit 1 bit 0 Auto wide function switching. 525/60 when PAL = 0 and 625/50 when PAL = 1. Table 3. List of I2C bus controls –9– CXD2053AM/AS 5-2. Bus-free mode The CXD2053AM/AS can be operated without using the I2C bus when Pin 19 (MCON) is set to 0 and the IC is switched to bus-free mode. In this case, the contents normally set by the I2C are fixed to the values below. Also, only the two functions listed in the table below can be switched by Pins 15 (SCL) and 16 (SDA). 1st byte 2nd byte I2C setting information Bit Name Description bit 7 MSB ED2FSC Directly controlled by Pin 16 (SDA). The unmodified SDA pin level becomes ED2FSC. bit 6 ED2RES ED2RES = 0 bit 5 bit 4 EDDEC1 bit5 = 0, bit4 = 1. bit 3 bit 2 EDDEC2 Directly controlled by Pin 15 (SCL). When SCL = 0, bit 3 = 0 and bit 2 = 1. When SCL = 1, bit 3 = 1 and bit 2 = 0. bit 1 VBLNJ1 VBLNJ1 = 0 bit 0 LSB VBRES VBRES = 0 bit 7 MSB AWRES AWRES = 0 bit 6 INST INST = 0 bit 5 bit 4 bit 3 bit 2 No Use and TEST All 0 bit 1 UPAREA UPAREA = 0 bit 0 LSB PAL PAL = 0 Fixed to 525/60 mode. Table 4. Setting values during bus-free mode (Pin 19 (MCON) = 0) – 10 – CXD2053AM/AS 6. Processing of EDTV-II ID and ID-1 data from the bus EDTV-II ID or ID-1 Pin direct output Decoder I2C to microcomputer Data validity judgment EDVLD or VBVLD CXD2053AM/AS As shown in the figure above, the data validity judgment and decoding results are obtained independently during EDTV-II ID or ID-1 decoding. When outputting these results directly to pins, the results are output after first taking their logical product (AND). These results are output independently to the I2C bus. Therefore, processing inside the microcomputer which has acquired the information from the I2C is performed either by simply outputting this data directly to the pins or by taking the logical product (AND) as above. In addition, performing the processing when the data validity judgment result (EDVLD or VBVLD) is 1 and the decoding result is 0 allows video to be judged as 4:3 video. Even video which has had the top and bottom of the screen blacked out due to picture composition intentions can be viewed as the original 4:3 video by giving this judgment priority over the auto wide function. 7. Setting EDTV-II ID decoding function The performance of the EDTV-II ID decoding function can be switched directly by pin settings during either I2C bus or bus-free mode. I2C exists ED2FSC = 0 ED2FSC = 0 ED2FSC = 1 EDDEC2 bit3 = 0, bit2 = 1 EDDEC2 bit3 = 1, bit2 = 0 EDDEC2 bit3 = 1, bit2 = 0 I2C -free SCL (15pin) = Low SDA (16pin) = Low Setting SCL (15pin) = High SDA (16pin) = Low SCL (15pin) = High SDA (15pin) = High Resistance to ghosting Medium Strong Strong Resistance to weak electric fields Medium Medium Strong Table 5. EDTV-II ID decoding function switching ED2FSC is originally a function which stops the 3.58MHz amplitude check for the Y signal input from the S terminal, etc. However, it can also be used in combination with the EDDEC2 setting to increase the resistance to ghosting and weak electric fields as shown in the table above. EDDEC2 is the luminance check level switching during the 3.58MHz or 2.04MHz confirmation signal interval. Similarly, although EDDEC1 is the 2.04MHz amplitude check level switching, it should be set to bit 5 = 0 and bit 4 = 1. Since EDTV-II ID identification for this IC is simple identification, increasing the resistance to weak electric fields, etc. results in a tradeoff which increases the possibility of misoperation. Accordingly, the leftmost settings in the table above should be used as the standard settings, and other settings used only when necessary. – 11 – CXD2053AM/AS 8. Judgment time during auto wide and shortening this time An appropriate judgment transition wait time is provided during auto wide in order to prevent misjudgments. During I2C bus mode, this transition time can be shortened as necessary using the INST bit. At the rising edge of INST, the screen changes without waiting to the screen being judged at that time. The INST pulse width should be set to 3 fields or more as shown below. 3 fields (50ms) or more INST The wait time-free status ends with the auto wide judgment transition or when INST becomes 0. This situation is illustrated in the figure below. INST Wait time-free status (inside the IC) Auto wide identification After transition Transition time wait INST Wait time-free status (inside the IC) Auto wide identification No screen change Transition time wait The screen change here. – 12 – INST does not function. –40 IRE 0 IRE 100 IRE 2.0Vp-p Vin 10k 3.3k 10µ 2.2k – 13 – 100 100 0.1µ 1µ 10µ 15 33 100 100 1000p 100 100 10 470p 0.022µ VSIN ADIN CCP VRB CPV VRT ISET AVSS AVSS 11 VDIN 10 2 7 5 4 6 8 12 3 CXD2053AM/AS XI 22 XO 21 VSS 23 VSS 17 TST2 14 TST1 13 SCL 15 SDA 16 OAW2 27 OAW1 26 O164 25 OLBX 24 OED 28 XRST 18 MCON 19 20 9 1 22p 14.3MHZ 22p I2C Direct output (open when not used) Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. 0.01µ 0.01µ 100 33k AVDD 60 to 80mA AVDD VDD = 5.0V ± 5% VDD Application Circuit CXD2053AM/AS CXD2053AM/AS Package Outline Unit: mm CXD2053AM 28PIN SOP (PLASTIC) 375mil + 0.4 18.8 – 0.1 + 0.4 2.3 – 0.15 28 15 + 0.2 0.1 – 0.05 14 1 0.45 ± 0.1 1.27 0.5 ± 0.2 9.3 10.3 ± 0.4 + 0.3 7.6 – 0.1 0.15 + 0.1 0.2 – 0.05 ± 0.12 M PACKAGE STRUCTURE PACKAGE MATERIAL EPOXY / PHENOL RESIN SONY CODE SOP-28P-L04 LEAD TREATMENT SOLDER PLATING EIAJ CODE ∗SOP028-P-0375-D LEAD MATERIAL 42 ALLOY PACKAGE WEIGHT 0.7g JEDEC CODE CXD2053AS + 0.1 05 0.25 – 0. 28PIN SDIP (PLASTIC) 400mil + 0.4 26.9 – 0.1 10.16 15 1 + 0.3 8.5 – 0.1 28 0° to 15° 14 0.5 ± 0.1 + 0.4 3.7 – 0.1 3.0 MIN 0.5 MIN 1.778 0.9 ± 0.15 PACKAGE STRUCTURE PACKAGE MATERIAL EPOXY RESIN SONY CODE SDIP-28P-01 LEAD TREATMENT SOLDER PLATING EIAJ CODE SDIP028-P-0400-A LEAD MATERIAL COPPER / 42 ALLOY PACKAGE WEIGHT 1.7g JEDEC CODE – 14 –