CXD2131Q Video Aspect Ratio Identification Signal Encoder/Decoder For the availability of this product, please contact the sales office. Description The CXD2131Q is an IC that encodes and decodes video aspect ratio identification signal (conforming to EIAJ Standard CPX-1204) in the vertical blanking interval of an NTSC video signal. 32 pin QFP (Plastic) Features • The processing formerly carried out by the two chips CXA1727Q and CXD2122AQ has been consolidated into this one chip. • Both microcomputer serial interface and I2C interface functions are built in. Applications Wide-screen converters televisions, VCRs, MUSE-NTSC Structure Silicon gate CMOS IC Absolute Maximum Ratings • Supply voltage VDD VSS – 0.5 to +7.0 • Input voltage VI VSS – 0.5 to VDD + 0.5 • Output voltage VO VSS – 0.5 to VDD + 0.5 • Storage temperature Tstg –55 to +150 Recommended Operating Conditions • Supply voltage VDD 4.5 to 5.5 • Operating temperature Topr –20 to +70 V V V °C V °C Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E94Z26-ST CXD2131Q CSYC Block Diagram 16 VIN11 27 Sync Separator Chip Clamp VIN12 28 Pedestal Clamp Data Slicer Timing Signal Generator 21 O164 20 OLBX 2 14 Decoder 15 CRCO 14 VIN21 29 Sync Separator Chip Clamp CRCC-OK CRCC Check VIN22 30 Pedestal Clamp Data Slicer 10 SROT VALID Data Validity Criterion 11 XCS VCR 4-line Serial Interface VIN3 31 14 12 2 SCLK 13 SRIN 17 SCL 18 SDA 9 MCON I2C Bus Interface 14 Encoder 2 1/4 Frequency Divider –2– 2 3 4 XO XI 7 SELXT 6 PRTC/ILBX Internal clock I164 VOUT 32 12 CXD2131Q Pin Description Pin No. Symbol I/O I/O level Description ANALOG Analog ground. I TTL Clock fsc/4 fsc switching; 4 fsc at 1. XO O CMOS Oscillator connection (fsc or 4 fsc). 4 XI I CMOS Oscillator connection or clock input. 5 VSS — — Digital ground. 6 I164 I TTL Encoder input; 16:9 at 1, 4:3 at 0. Fixed to 0 when not used. 7 PRTC [ILBX] I TTL Microcomputer interface switching; 0 = I2C, 1 = serial. [Encoder input; 1 = letter-box, 0 = normal]. 8 VDD — Digital system power supply. 9 MCON I TTL Microcomputer interface exists; 1 = yes, 0 = no. 10 SROT I/O TTL∗1 Serial interface output to microcomputer [fixed to 0]. 11 XCS [OE] I TTL Select from microcomputer [encoding exists; 1 = yes]. 12 SCLK [ISEL] I TTL Clock from microcomputer [decoder input channel switching]. 13 SRIN [LNJ1] I Data from microcomputer [decoder line ±1 existence]. 14 XRST I TTL TTL∗2 15 CRCO O CMOS CRCC check monitor output. 16 CSYC O Composite Sync monitor output. 17 SCL I CMOS CMOS∗2 18 SDA I/O CMOS∗2, 4 I2C bus data. 19 VSS — — Digital ground. 20 OLBX O CMOS Decoder output; 1 = letter-box, 0 = normal. 21 O164 (DTHI) O CMOS Decoder output; 16:9 at 1, 4:3 at 0 (decode slicer output). 22 TST1 I TTL∗3 Test input; normally connected to Vss; when 1, Pin 21 switches to the function in parentheses ( ). 23 TST2 I TTL∗3 Test input; connect to Vss. 24 ISET1 I ANALOG Analog bias current setting. 25 ISET2 I ANALOG Analog bias current setting. 26 AVDD — ANALOG Analog system power supply. 27 VIN11 I ANALOG Sync separation input. 28 VIN12 I ANALOG Decoder data slicer input. 29 VIN21 I ANALOG Sync separation input. 30 VIN22 I ANALOG Decoder data slicer input. 31 VIN3 I ANALOG Encoder input. 32 VOUT O ANALOG Encoder output. 1 AVSS 2 SELXT 3 — — Standby and reset at 0. I2C bus clock. ∗2 Schmitt input ∗3 With pull-down resistor ∗4 Open drain ∗1 Three-state Note 1) In microcomputer-free mode when MCON = 0, Pin 7 and Pins 10 to 13 switch to the functions in parentheses [ ]. At this time connect SROT (Pin 10) to Vss. Note 2) When TST1 = 1, Pin 21 switches to the function in parentheses ( ). –3– CXD2131Q Electrical Characteristics DC Characteristics (Logic Section) Item Output voltage Output voltage Output voltage Input voltage Input voltage Input voltage Symbol Condition (VDD = 5.0V, VSS = 0V, Ta = 25°C) Min. Typ. Max. Unit Remarks VOH IOH = –2mA VOL IOL = 4mA VOH IOH = –3mA VOL IOL = 3mA VDD/2 V VOL IOL = 4mA 0.4 V Pin 18 only V Except for Pins 4, 17 and 18 VIH VDD – 0.8 V 0.4 VDD/2 V 2.2 VIL 0.8 0.7 × VDD VIH V V 0.3 × VDD VIL 0.8 × VDD VIH V Pin 3 only Pin 4 only V V VIL Except for Pins 3 and 18 0.2 × VDD V Pins 17 and 18 only Input leak current II VIN = either VSS or VDD –10 +10 µA Except for Pins 4, 10, 22 and 23 Output leak current IOZ VIN = either VSS or VDD –40 +40 µA Pin 10 only Current consumption IDD mA Sum of Pins 8 and 26 15 AC Characteristics Item Symbol Clock frequency fxi Serial transmission clock frequency fsclk (VDD = 5.0V, VSS = 0V, Ta = 25°C) Condition Min. Typ. Max. Unit Remarks SELXT (Pin 2) = VSS 3.58 5.0 MHz SELXT (Pin 2) = VDD 14.3 20.0 MHz Pin 4 input, or oscillator between Pins 3 and 4 10 MHz Pin 12 Duty ratio = 50% Max. Unit MCON (Pin 9) = VDD PRTC (Pin 7) = VDD I/O Pin Capacitance Item Symbol Condition Min. Typ. Input pin CIN VDD = VI = 0V, f = 1MHz 9 pF Output pin COUT VDD = VI = 0V, f = 1MHz 11 pF Input/output pins CI/O VDD = VI = 0V, f = 1MHz 11 pF –4– Remarks CXD2131Q Description of Pins and Electrical Characteristics Analog Section Pin No. (VDD = 5.0V, VSS = 0V, Ta = 25°C) Symbol Equivalent circuit Description AVDD 24 ISET1 Bias setting pins. Connect to AVDD with 33kΩ. 24 25 25 ISET2 AVSS AVDD 27 AVDD Chip clamp, sync separation input. VIN11 27 29 29 clamp voltage 1.5V VIN21 AVSS AVSS AVDD 28 Pedestal clamp, data slicer input. VIN12 28 30 30 clamp voltage 1.5V VIN22 AVSS AVDD 31 31 VIN3 AVSS Input/output pins for encoder. ON resistance value between Pins 31 and 32: max. 350Ω. AVDD 32 32 VOUT AVSS 26 AVDD Not connected to digital power supply (Pin 8) inside the IC. 1 AVSS Not connected to digital ground (Pins 5 and 19) inside the IC. –5– Analog power supply. Connect power supply low in noise from the digital system. Analog ground. Connect to same potential as digital ground (Pins 5 and 19). CXD2131Q 1. Description of video aspect ratio identification signal transfer method (aspect ratio identification) As shown in the table below, video aspect ratio identification signal consists of 14-bit data, to which a 6-bit CRCC is appended for a total of 20 bits. On an NTSC video signal, this information is carried on lines 20 and 283 of the vertical blanking interval. bit-No. Description “1” “0” Full mode (16 : 9) Letter-box 4:3 Normal A 1 2 3 Transfer aspect ratio Pictorial representation format Undefined B 4 5 6 Discrimination information about the video signal and any other signal (audio signal, etc.) incident to the video and transferred simultaneously. WORD0 WORD1 WORD2 4-bit width 4-bit width Word 0 dependent discrimination signal Word 0 dependent discrimination signal, information, etc. (From Provisional Standard of EIAJ, CPX-1204) 2. Decoding The CXD2131Q has a decoding function which extracts video aspect ratio identification signals from the video signal. A 1Vp-p video signal is input. There are two video signal input systems, CH1 (Pins 27 and 28) and CH2 (Pins 29 and 30). These are switched and decoded one at a time. As shown below, the decoding circuit and CRCC check circuit are in one system, but there are two systems for the data validity criterion circuit and decoding result, for each channel. This means that even when one channel is being decoded, the decoding result for the other channel is held. ISEL performs channel switching. ISEL is set by microcomputer transmission or by pins. For CH1, ISEL = “0”, and for CH2, ISEL = “1”. CH1/CH2 switching CH1 input Sync Separator Timing Signal Generator Data Slicer CH2 input Sync Separator Data Slicer 14 Latch Latch Decode Circuit 14 Decoding Result Output Data Validity Criterion CRCC Check Data Validity Criterion Data validity Criterion Output CRCC Check Output Further, the composite sync signal of the channel being decoded can be monitored at CSYC (Pin 16) and the CRCC check result can be monitored at CRCO (Pin 15), even during decoding. Also, when TST1 (Pin 22) is held at high level, the data slice result for decoding can be monitored at O164 (Pin 21). For the decoding operation, the range of the scanning lines to be decoded on the video signal can be switched by LNJ1. LNJ1 can be set by microcomputer control or by pins. When LNJ1 is “1”, only lines 20 and 283 are decoded, and when LNJ1 is “0”, one line on each side of lines 20 and 283 are decoded in addition. –6– CXD2131Q 3. Encoding The CXD2131Q has an encoding function which adds video aspect ratio identification signals to the video signal. A 1Vp-p video signal is encoded. An encoded video signal is output on VOUT (Pin 32) by inputting the video signal input to the decoding function CH2 side to VIN3 (Pin 31) as well. When this encoding function is used, decoding input must be switched to CH2. Encoding is controlled by OE, which is set by microcomputer control or by pins. Encoding is off when OE is “0”, and the input video signal is output as it is from VOUT (Pin 32). For example, even when CH1 is decoding, the video signal input to CH2 can be obtained as it is at VOUT if OE is set to “0”. 4. Clock The CXD2131Q requires an fsc (= 3.579545MHz) or 4 fsc clock. When SELXT (Pin 2) is “0” the clock is fsc; when it is “1”, the clock is 4 fsc. Connect XI (Pin 4) and XO (Pin 3) when using a crystal oscillator. Input to XI for external input. 5. Settings and data input/output There are three methods of performing the CXD2131Q settings and data input/output: direct setting by pins without using a microcomputer, the 4-line microcomputer serial interfaces, and I2C bus interface. 5-1. Microcomputer-free mode Direct input/output by pins, without using a microcomputer, can be carried out by setting MCON (Pin 9) to“0”. In this case, only the first 2 bits of the total 14 bits of video aspect ratio identification signals are input or output. The decoding result is obtained at O164 (Pin 21) and OLBX (Pin 20). The data for encoding is input to I164 (Pin 6) and PRTC/ILBX (Pin 7). For the various settings, decode channel switching ISEL is input to SCLK (Pin 12), decode scanning line range switching LNJ1 to SRIN (Pin 13) and encode operation existence OE to XCS (Pin 11). Connect SROT (Pin 10), SCL (Pin 17) and SDA (Pin 18), which are unused, to Vss. 5-2. 4-line serial interface Setting and data input/output can be carried out by microcomputer serial interface when MCON (Pin 9) is set at “1” and PRTC (Pin 7) is set at “1”. In this case, all 14 bits of video aspect ratio identification signals are input or output. Serial data from the microcomputer of serial transmission connects to SRIN (Pin 13), the serial clock to SCLK (Pin 12), and select to XCS (Pin 11). Serial data to the microcomputer is output at SROT (Pin 10). Connect SCL (Pin 17) and SDA (Pin 18), which are unused, to Vss. Serial interface bit configuration is shown in the following figures. –7– CXD2131Q µCOM → CXD2131 2bit 2bit 4bit 4bit 4bit 1bit 1bit 1bit 1bit WORD0 bit1, bit2 don’t care WORD0 bit3 to bit6 WORD1 WORD2 ISEL IRES OE TEST Video aspect ratio identification signals carried on video signal (encoded) Decode input switching 1bit Encode ON/OFF Decode/encode; "1" = circuit reset, not standby 2bit 1bit LNJ1 don’t care Total 24 bits SIEN Existence of 1 line before and after decode range Normally "0" Validity/invalidity of all setting data; "1" = valid CXD2131 → µCOM 2bit 1bit 1bit 4bit 4bit 4bit WORD0 bit1, bit2 CRCC VALID WORD0 bit3 to bit6 WORD1 WORD2 Total 16 bits Video aspect ratio identification signals extracted from video signal (decoded) "1" when CRCC result is correct "1" when data validity criterion result is correct Video aspect ratio identification signals extracted from video signal (decoded) Fig. 1 (a). Bit configuration of 4-line serial interface tzsro tzsro XCS SCLK don’t care tsusc thdsc SRIN SROT HI-Z HI-Z tdsot Item Symbol Set-up to SRIN SCLK rising edge Hold to SRIN SCLK rising edge Delay from SROT SCLK falling edge Three-state control delay by SROT XCS tsusc thdsc tdsot tzsro Condition Min. Typ. Max. Unit 10 ns 10 ns Cload = 20pF 40 ns Rload = 2kΩ 40 ns Fig. 1 (b). 4-line serial interface timing –8– CXD2131Q 5-3. I2C bus interface Setting and data input/output can be carried out by microcomputer I2C bus interface when MCON (Pin 9) is set at “1” and PRTC (Pin 7) is set at “0”. In this case, all 14 bits of video aspect ratio identification signals are input or output. This I2C bus corresponds to standard mode. I2C address is 40H. I2C bus data connects to SDA (Pin 18) and I2C bus clock to SCL (Pin 17). Connect SRIN (Pin 13), SCLK (Pin 12) and XCS (Pin 11), which are unused, to Vss. And leave SROT (Pin 10) open. I2C bus interface bit configuration is shown in Fig. 2. µCOM → CXD2131 2bit 2bit 4bit 4bit 4bit 1bit 1bit 1bit 1bit WORD0 bit1, bit2 don’t care WORD0 bit2 to bit6 WORD1 WORD2 ISEL IRES OE TEST Video aspect ratio identification signals carried on video signal (encoded) Decode input switching 1bit 3bit Total 24 bits LNJ1 don’t care Existence of 1 line before and after decode range Encode ON/OFF Normally "0" Decode/encode; "1" = circuit reset, not standby CXD2131 → µCOM 2bit 1bit 1bit 4bit 4bit 4bit WORD0 bit1, bit2 CRCC VALID WORD0 bit3 to bit6 WORD1 WORD2 Total 16 bits Video aspect ratio identification signals extracted from video signal (decoded) "1" when CRCC result is correct Video aspect ratio identification signals extracted from video signal (decoded) "1" when data validity criterion result is correct Fig. 2. Bit configuration of I2C bus interface –9– CXD2131Q The CXD2131Q I2C bus interface has a subaddress function. With the subaddress function, only the bytes after setting has started are set. There is no subaddress function at the read side. When subaddress = 0 during setting I2C address Subaddress WORD0 byte 0 When subaddress = 2 during setting I 2C address WORD1, 2 SEL to LNJ1 byte 1 Subaddress SEL to LNJ1 byte 2 No subaddress during read I 2C address WORD0 crcc, valid WORD1, 2 Fig. 3. Description of I2C bus and subaddress – 10 – byte 2 – 11 – 1.1k 33/16 82 10/16 82 10/16 110 15k 10k 15k 10k 510 510 5.1k 1µ 1µ 1µ 1µ 0.1µ 1500p 1500p 220 510k 100 100 47/16 32 31 30 29 28 27 25 24 1 2 Pedestal Clamp Data Slicer 3 Sync Separator Chip Clamp Pedestal Clamp Data Slicer Sync Separator Chip Clamp 26 33k 22p 3.58M 33k 4 22p Encoder 5 23 6 22 0.1µ 9 SROT 10 47/16 XCS SCLK 12 11 SRIN To microcomputer 13 14 15 16 17 18 19 20 21 JP1 Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. 8 VCR 4-line Interface I2C Bus Interface 10k 7 Timing Signal Generator Decoder CXD2131Q 39µH Note) JP1 in the figure above normally is not connected. It is only connected when monitoring slicer output from Pin 21, when checking the circuit or the like. Vout Vin2 Vin1 VDD = 5.0V Application Circuit (4-line microcomputer I/F for VCR, with encoder) CXD2131Q – 12 – 82 10/16 82 10/16 33k 22k 33k 22k 1k 1k 1µ 1µ 1µ 1µ 0.1µ 100 100 1500p 1500p 47/16 32 31 30 29 28 27 25 24 1 2 Pedestal Clamp Data Slicer 3 Sync Separator Chip Clamp Pedestal Clamp Data Slicer Sync Separator Chip Clamp 26 33k 22p 3.58M 33k 4 22p Encoder 5 23 6 22 0.1µ 9 10 11 12 13 14 15 16 17 18 19 20 21 JP1 47/16 clock I2C-bus data Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. 8 VCR 4-line Interface I2C Bus Interface 10k 7 Timing Signal Generator Decoder CXD2131Q 39µH Note) JP1 in the figure above normally is not connected. It is only connected when monitoring slicer output from Pin 21, when checking the circuit or the like. Vin2 Vin1 VDD = 5.0V Application Circuit (With I2C bus, no encoder) CXD2131Q CXD2131Q Package Outline Unit: mm 32PIN QFP (PLASTIC) 9.0 ± 0.2 24 0.1 + 0.35 1.5 – 0.15 + 0.3 7.0 – 0.1 17 16 32 9 (8.0) 25 1 + 0.2 0.1 – 0.1 0.8 + 0.15 0.3 – 0.1 0.24 M + 0.1 0.127 – 0.05 0° to 10° PACKAGE MATERIAL EPOXY RESIN SOLDER PLATING SONY CODE QFP-32P-L01 LEAD TREATMENT EIAJ CODE QFP032-P-0707 LEAD MATERIAL 42 ALLOY PACKAGE MASS 0.2g JEDEC CODE – 13 – 0.50 8