SONY CXD2586R-1

CXD2586R/-1
CD Digital Signal Processor with Built-in Digital Servo and DAC
For the availability of this product, please contact the sales office.
Description
The CXD2586R/-1 is a digital signal processor LSI
for CD players. This LSI incorporates the digital
servo, digital filter and 1-bit DAC.
144 pin LQFP (Plastic)
Features
• All digital signal processing during playback is
performed with a single chip
• Highly integrated mounting possible due to a builtin RAM
Digital Signal Processor Block
• Playback mode which supports CAV (Constant
Angular Velocity)
• Frame jitter free
• Half-speed to octuple-speed continuous playback
possible with a low external clock (only CXD2586R-1
supports up to octuple speed)
• Allows relative rotational velocity readout
• Wide capture range playback mode
• Spindle rotational velocity following method
• Supports normal-speed, double-speed, quadruplespeed, sextuple-speed and octuple-speed playback
(only CXD2586R-1)
• Wide frame jitter margin (±28 frames) due to a
built-in 32K RAM
• The bit clock, which strobes the EFM signal, is
generated by the digital PLL
• EFM data demodulation
• Enhanced EFM frame sync signal protection
• Refined super strategy-based powerful error correction
C1: double correction, C2: quadruple correction
• Octuple-speed (only CXD2586R-1), sextuple-speed,
quadruple-speed and double-speed playback (digital
signal processor and digital servo blocks)
• Noise reduction during track jumps
• Auto zero-cross mute
• Subcode demodulation and Sub Q data error detection
• Digital spindle servo (with oversampling filter)
• 16-bit traverse counter
• Asymmetry compensation circuit
• CPU interface on serial bus
• Error correction monitor signal, etc. output from a
new CPU interface
• Servo auto sequencer
• Fine search performs track jumps with high accuracy
• Digital audio interface outputs
• Digital level meter, peak meter
• Bilingual compatible
Digital Servo Block
• Microcomputer software-based flexible servo control
• Servo error signal, offset cancel function
• Servo loop, auto gain control function
• E:F balance, focus bias adjustment function
Digital Filters (DAC and LPF blocks)
• Low-pass filter for DAC
• Digital de-emphasis
• Digital attenuation
• 4fs oversampling filter
• Adopts secondary ∆∑ noise shaper
• LPF for DAC analog output
Structure
Silicon gate CMOS IC
Absolute Maximum Ratings
• Supply voltage
VDD
–0.3 to +7.0 V
• Input voltage
VI
–0.3 to +7.0 V
(VSS – 0.3V to VDD +0.3V)
• Output voltage
VO
–0.3 to +7.0 V
• Storage temperature Tstg
–40 to +125 °C
• Supply voltage difference VSS – AVSS –0.3 to +0.3 V
VDD – AVDD –0.3 to +0.3 V
Recommended Operating Conditions
• Supply voltage
• Operating temperature
∗ The VDD (min.) for the CXD2586R/-1 varies according
to the playback speed and built-in VCO selection. The
VDD (min.) is 4.5V when high-speed VCO and
quadruple-speed playback are selected (variable pitch
off). The VDD (min.) for the CXD2586R/-1 under
various conditions are as shown in the following table.
Playback
speed
VDD (min.) [V]
VCO1 high VCO1 normal
speed
speed
DAC
block
×8
(only CXD2586R-1)
4.75
—
—
×6
4.50
—
—
×4
4.50
—
—
× 2∗1
4.00
—
—
×2
3.40
4.00
—
× 1∗2
3.40
3.40
—
×1
3.40
3.40
4.50
—: Dashes indicate that there is no assurance of the
processor operating. All values are for variable pitch off.
∗1 When the internal operation of the LSI is set to normalspeed playback and the operating clock of the signal
processor is doubled, double-speed playback results.
∗2 When the internal operation of the LSI is set to doublespeed mode and the crystal oscillating frequency is
halved in low power consumption mode, normal-speed
playback results.
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E95Y01A65-ST
CXD2586R/-1
62 63 64 65 66 67 68
LRCKI
BCKI
PCMDI
DTS7
DTS6
DTS5
XTSL
DTS3
5 105 72
DTS4
4
DTS2
VPCO1
VPCO2
53
DTS1
XTLI
52
ACDT
XTLO
Block Diagram
25 27 23
DAC block
58 AOUT1
MCKO 73
LPF
57 AIN1
4fs Digital Filter
+
1 bit DAC
MCLK 74
VPCO1, 2 4, 5
56 LOUT1
47 AOUT2
VCKI 135
LPF
FSTO 76
48 AIN2
49 LOUT2
Clock
Generator
C4M 77
C16M 78
32K RAM
PDO 134
VCOI 128
VCOO 127
FILI 8
EFM
Demodulator
Priority
encoder
Address
generator
Register
Digital PLL
Vari-Pitch
double speed
PCO 9
Serial/parallel
processor
8
FILO 7
CLTV 10
RFAC 12
ASYI 14
∗
D/A
data
processor
Sync
protector
MUX
20 PSSL
42 to 31,
29, 28, DA01 to DA16
26, 24
ASYO 15
82 MUTE
ASYE 19
WFCK 83
Timing
Generator1
SCOR 84
Peak
detector
Subcode
P to W
processor
EXCK 86
SBSO 85
80 DOUT
Digital out
SQCK 88
79 MD2
Subcode Q
processor
SQSO 87
MON 108
Error
corrector
FSW 107
96 DATA
MDP 110
CLV
processor
MDS 111
98 CLOK
CPU interface
97 XLAT
Timing
Generator2
18-times
oversampling
filter
Noise
Shaper
PWMI 106
Servo
auto
sequencer
89 SENS
Servo
Interface
VCTL 6
OSC
99 COUT
102 MIRR
MIRR
V16M 136
DFCT
Signal processor block
103 DFCT
FOK
104 FOK
Servo block
2
RFDC 142
PWM GENERATOR
SERVO DSP
CE 143
A/D
CONVERTER
FE 2
TRACKING SERVO
SLED SERVO
SLED PWM
GENERATOR
–2–
120, 119 TRDR, TRON
2
122, 125 FFDR, FFON
2
124, 123 FRDR, FRON
XRST
AVSS5
AVSS42
AVSS32
AVSS41
AVSS1
DVSS3
DVSS2
DVSS1
AVDD5
AVDD3
AVDD4
AVDD2
AVDD1
DVDD3
DVDD2
DVDD0
TES3
ADIO
118, 121 TFDR, TFON
2
129 131 132 18 101 126 16 137 59 46 51 43 81 130 11 139 55 60 45 50 54 91
TES2
140
TEST
141
RFC
VC 3
116, 115 SRDR, SRON
2
TRACKING PWM
GENERATOR
AVSS31
SE 1
OpAmp
AnaSw
FOCUS PWM
GENERATOR
FOCUS SERVO
AVSS2
TE 144
114, 117 SFDR, SFON
2
CXD2586R/-1
MCKO
MCLK
FSTI
FSTO
C16M
C4M
MD2
DOUT
DVSS2
WFCK
MUTE
SBSO
SCOR
SQSO
EXCK
SQCK
SENS
XRST
NC.
DIRC
SCLK
ATSK
DFSW
XLAT
DATA
CLOK
COUT
NC.
MIRR
DVDD2
FOK
DFCT
PWMI
TESTA
MON
FSW
Pin Configuration
108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73
NC. 109
72 XTSL
MDP 110
71 DAS1
MDS 111
70 DAS0
LOCK 112
69 XWO
SSTP 113
68 DTS7
SFDR 114
67 DTS6
SRON 115
66 DTS5
SRDR 116
65 DTS4
SFON 117
64 DTS3
TFDR 118
63 DTS2
TRON 119
62 DTS1
TRDR 120
61 NC.
TFON 121
60 AVSS32
FFDR 122
59 AVDD3
FRON 123
58 AOUT1
FRDR 124
57 AIN1
FFON 125
56 LOUT1
DVDD3 126
55 AVSS31
VCOO 127
54 AVSS5
VCOI 128
53 XTLI
TEST 129
52 XTLO
DVSS3 130
51 AVDD5
TES2 131
50 AVSS42
49 LOUT2
TES3 132
48 AIN2
NC. 133
47 AOUT2
PDO 134
VCKI 135
46 AVDD4
V16M 136
45 AVSS41
44 NC.
AVDD2 137
IGEN 138
43 DVSS1
AVSS2 139
42 DA01
ADIO 140
41 DA02
RFC 141
40 DA03
RFDC 142
39 DA04
DA07
DA08
DA10
DA09
DA11
DA12
NC.
DA14
DA13
BCKI
DA15
DA16
PCMDI
PCO
LRCKI
FILI
LRCK
FILO
PSSL
VCTL
–3–
WDCK
VPCO2
ASYE
VC
DVDD1
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
NC.
8
AVDD1
7
ASYI
6
ASYO
5
BIAS
4
RFAC
3
AVSS1
2
CLTV
1
VPCO1
37 DA06
FE
38 DA05
TE 144
SE
CE 143
CXD2586R/-1
Pin Description
Pin
No.
Symbol
I/O
Description
1
SE
I
Sled error signal input.
2
FE
I
Focus error signal input.
3
VC
I
Center voltage input.
4
VPCO1
O
1, Z, 0
Wide-band EFM PLL VCO2 charge pump output.
5
VPCO2
O
1, Z, 0
Wide-band EFM PLL VCO2 charge pump output.
6
VCTL
I
7
FILO
O
8
FILI
I
9
PCO
O
10
CLTV
I
11
AVSS1
12
RFAC
I
EFM signal input.
13
BIAS
I
Asymmetry circuit constant current input.
14
ASYI
I
Asymmetry comparator voltage input.
15
ASYO
O
16
AVDD1
Analog power supply.
18
DVDD1
Digital power supply.
19
ASYE
I
Asymmetry circuit on/off (low = off, high = on).
20
PSSL
I
Audio data output mode switching input (low = serial, high = parallel).
21
WDCK
O
1, 0
D/A interface for 48-bit slot. Word clock f = 2Fs.
22
LRCK
O
1, 0
D/A interface for 48-bit slot. LR clock f = Fs.
23
LRCKI
I
24
DA16
O
25
PCMDI
I
26
DA15
O
27
BCKI
I
28
DA14
O
1, 0
DA14 output when PSSL = 1, 64-bit slot serial data output (two's
complement, LSB first) when PSSL = 0.
29
DA13
O
1, 0
DA13 output when PSSL = 1, 64-bit slot bit clock output when PSSL = 0.
31
DA12
O
1, 0
DA12 output when PSSL = 1, 64-bit slot LR clock output when PSSL = 0.
32
DA11
O
1, 0
DA11 output when PSSL = 1, GTOP output when PSSL = 0.
33
DA10
O
1, 0
DA10 output when PSSL = 1, XUGF output when PSSL = 0.
34
DA09
O
1, 0
DA09 output when PSSL = 1, XPLCK output when PSSL = 0.
35
DA08
O
1, 0
DA08 output when PSSL = 1, GFS output when PSSL = 0.
36
DA07
O
1, 0
DA07 output when PSSL = 1, RFCK output when PSSL = 0.
Wide-band EFM PLL VCO2 control voltage input.
Analog
Master PLL filter output (slave = digital PLL).
Master PLL filter input.
1, Z, 0
Master PLL charge pump output.
Master VCO control voltage input.
Analog GND.
1, 0
EFM full-swing output (low = VSS, high = VDD).
LR clock input to DAC (48-bit slot).
1, 0
DA16 (MSB) output when PSSL = 1, 48-bit slot serial data output (two's
complement, MSB first) when PSSL = 0.
Audio data input to DAC (48-bit slot).
1, 0
DA15 output when PSSL = 1, 48-bit slot bit clock output when PSSL = 0.
Bit clock input to DAC (48-bit slot).
–4–
CXD2586R/-1
Pin
No.
Symbol
I/O
Description
37
DA06
O
1, 0
DA06 output when PSSL = 1, C2PO output when PSSL = 0.
38
DA05
O
1, 0
DA05 output when PSSL = 1, XRAOF output when PSSL = 0.
39
DA04
O
1, 0
DA04 output when PSSL = 1, MNT3 output when PSSL = 0.
40
DA03
O
1, 0
DA03 output when PSSL = 1, MNT2 output when PSSL = 0.
41
DA02
O
1, 0
DA02 output when PSSL = 1, MNT1 output when PSSL = 0.
42
DA01
O
1, 0
DA01 output when PSSL = 1, MNT0 output when PSSL = 0.
43
DVSS1
Digital GND.
45
AVSS41
Analog GND.
46
AVDD4
Analog power supply.
47
AOUT2
O
48
AIN2
I
49
LOUT2
O
50
AVSS42
Analog GND.
51
AVDD5
Master clock power supply.
52
XTLO
O
53
XTLI
I
54
AVSS5
Master clock GND.
55
AVSS31
Analog GND.
56
LOUT1
O
57
AIN1
I
58
AOUT1
O
59
AVDD3
Analog power supply.
60
AVSS32
Analog GND.
62
DTS1
I
DAC test pin. Normally fixed to high.
63
DTS2
I
DAC test pin. Normally fixed to high.
64
DTS3
DAC test pin. Leave this open.
65
DTS4
DAC test pin. Leave this open
66
DTS5
DAC test pin. Leave this open.
67
DTS6
DAC test pin. Leave this open.
68
DTS7
I
DAC test pin. Normally fixed to low.
69
XWO
I
DAC sync window open input. Normally high, window open when low.
70
DAS0
I
DAC test pin. Normally fixed to low.
71
DAS1
I
DAC test pin. Normally fixed to low.
72
XTSL
I
Crystal selection input.
73
MCKO
O
74
MCLK
I
DSP clock input.
75
FSTI
I
2/3 frequency division input for MCLK pin.
Analog
Channel 2 analog output.
Channel 2 analog input.
Analog
1, 0
Channel 2 LINE output.
Master clock 33.8688MHz crystal oscillation circuit output.
Master clock 33.8688MHz crystal oscillation circuit output.
Analog
Channel 1 LINE output pin.
Channel 1 analog input pin.
Analog
1, 0
Channel 1 analog output pin.
DSP clock output.
–5–
CXD2586R/-1
Pin
No.
Symbol
I/O
Description
76
FSTO
O
1, 0
2/3 frequency division output for MCLK pin. Does not change with variable pitch.
77
C4M
O
1, 0
1/4 frequency division output for MCLK pin. Changes with variable pitch.
78
C16M
O
1, 0
16.9344MHz output. Changes simultaneously with variable pitch.
79
MD2
I
80
DOUT
O
81
DVSS2
82
MUTE
I
83
WFCK
O
1, 0
WFCK (Write Flame Clock) output.
84
SCOR
O
1, 0
Outputs a high signal when either subcode sync S0 or S1 is detected.
85
SBSO
O
1, 0
Sub P to W serial output.
86
EXCK
I
87
SQSO
O
88
SQCK
I
89
SENS
O
91
XRST
I
System reset. Reset when low.
92
DIRC
I
Used during 1-track jumps.
93
SCLK
I
SENS serial data readout clock input.
94
DFSW
I
DFCT switching pin. High: DFCT countermeasure circuit off.
95
ATSK
I
Anti-shock pin.
96
DATA
I
Serial data input from CPU.
97
XLAT
I
Latch input from CPU. Serial data is latched at the falling edge.
98
CLOK
I
Serial data transfer clock input from CPU.
99
COUT
O
101
DVDD2
102
MIRR
O
1, 0
Mirror signal output.
103
DFCT
O
1, 0
Defect signal output.
104
FOK
O
1, 0
Focus OK signal output.
105
TESTA
106
PWMI
I
107
FSW
O
Z, 0
Spindle motor output filter switching output.
108
MON
O
1, 0
Spindle motor on/off control output.
110
MDP
O
1, 0
Spindle motor servo control output.
111
MDS
O
1, 0
Spindle motor servo control output.
112
LOCK
O
1, 0
GFS is sampled at 460Hz; when GFS is high, this pin outputs a high signal.
If GFS is low eight consecutive samples, this pin outputs low.
113
SSTP
I
114
SFDR
O
1, 0
Sled drive output.
115
SRON
O
1, 0
Sled drive output.
Digital Out on/off control. (low: off, high: on)
1, 0
Digital Out output pin.
Digital GND.
Mute (low: off, high: on)
SBSO readout clock input.
1, 0
Sub Q 80-bit and PCM peak and level data 16-bit output.
SQSO readout clock input.
1, 0
1, 0
SENS output to CPU.
Track count signal output.
Digital power supply.
Test pin. Not connected.
Spindle motor external pin input.
Disc innermost track detection signal input.
–6–
CXD2586R/-1
Pin
No.
Symbol
I/O
Description
116
SRDR
O
1, 0
Sled drive output.
117
SFON
O
1, 0
Sled drive output.
118
TFDR
O
1, 0
Tracking drive output.
119
TRON
O
1, 0
Tracking drive output.
120
TRDR
O
1, 0
Tracking drive output.
121
TFON
O
1, 0
Tracking drive output.
122
FFDR
O
1, 0
Focus drive output.
123
FRON
O
1, 0
Focus drive output.
124
FRDR
O
1, 0
Focus drive output.
125
FFON
O
1, 0
Focus drive output.
126
DVDD3
127
VCOO
O
128
VCOI
I
Analog EFM PLL oscillation circuit input. flock = 8.6436MHz.
129
TEST
I
Test pin. Normally fixed to low.
130
DVSS3
131
TES2
I
Test pin. Normally fixed to low.
132
TES3
I
Test pin. Normally fixed to low.
134
PDO
O
135
VCKI
I
136
V16M
O
137
AVDD2
138
IGEN
139
AVSS2
140
ADIO
O
Operational amplifier output.
141
RFC
I
RF signal LPF time constant capacitor connection.
142
RFDC
I
RF signal input.
143
CE
I
Center servo analog input.
144
TE
I
Tracking error signal input.
Digital power supply.
1, 0
Analog EFM PLL oscillation circuit output.
Digital GND.
1, Z, 0
Analog EFM PLL charge pump output.
Variable pitch clock input from the external VCO. fcenter = 16.9344MHz.
1, 0
Wide-band EFM PLL VCO2 oscillation output.
Analog power supply.
I
Operational amplifier current source reference resistance connection.
Analog GND.
∗ In the 144-pin LQFP, the following pins are NC:
Pins 17, 30, 44, 61, 90, 100, 109, and 133
Notes) • The 64-bit slot is an LSB first, two's complement output. The 48-bit slot is an MSB first, two's
complement output.
• GTOP is used to monitor the frame sync protection status. (High: sync protection window released.)
• XUGF is the negative pulse for the frame sync obtained from the EFM signal. It is the signal before
sync protection.
• XPLCK is the inverse of the EFM PLL clock. The PLL is designed so that the falling edge and the
EFM signal transition point coincide.
• The GFS signal goes high when the frame sync and the insertion protection timing match.
• RFCK is derived from the crystal accuracy, and has a cycle of 136µs.
• C2PO represents the data error status.
• XRAOF is generated when the 32K RAM exceeds the ±28F jitter margin.
–7–
CXD2586R/-1
Electrical Characteristics
1. DC Characteristics
(VDD = AVDD = 5.0V ± 10%, Vss = AVss = 0V, Topr = –20 to +75°C)
Item
Input voltage (1)
Input voltage (2)
Conditions
High level input voltage
VIH (1)
Low level input voltage
VIL (1)
High level input voltage
VIH (2)
Low level input voltage
VIL (2)
Min.
Typ.
Max.
0.7VDD
V
0.3VDD
Schmitt input
Unit Applicable pins
0.8VDD
∗1
V
V
∗2
0.2VDD
V
Vss
VDD
V
∗3, 11, 12
VDD – 0.8
VDD
V
∗4
0
0.4
V
VDD – 0.8
VDD
V
Low level output voltage VOL (2) IOL = 4mA
0
0.4
V
Output voltage (1) Low level output voltage VOL (3) IOL = 4mA
0
0.4
V
High level output voltage VOH (4) IOH = –0.28mA VDD – 0.5
VDD
V
Low level output voltage VOL (4) IOL = 0.36mA
0
0.4
V
VDD – 0.5
VDD
V
0
0.4
V
Input voltage (3) Input voltage
Output voltage (1)
Output voltage (2)
Output voltage (4)
Output voltage (5)
VIN (3) Analog input
High level output voltage VOH (1) IOH = –4mA
Low level output voltage VOL (1) IOL = 4mA
High level output voltage VOH (2) IOH = –2mA
High level output voltage VOH (5) IOH = –2mA
Low level output voltage VOL (5) IOL = 8mA
∗5
∗6
∗7
∗13
Input leak current (1)
ILI (1)
VI = 0 to 5.5V
–10
10
µA
∗1, 2, 3, 12
Input leak current (2)
ILI (2)
VI = 1.5 to 3.5V
–20
20
µA
∗8
Input leak current (3)
ILI (3)
VI = 0 to 5.0V
–40
600
µA
∗9
Tri-state pin output leak current
ILO
VO = 0 to 5.5V
–5
5
µA
∗10
Applicable pins
∗1 XTSL, DATA, XLAT, MD2, PSSL, TEST, TES2, TES3, DFSW, DIRC, SSTP, ATSK, BCKI, LRCKI, PCMDI,
DTS1, DTS2, DTS7, DAS0, DAS1, XWO, PWMI
∗2 CLOK, XRST, EXCK, SQCK, MUTE, VCKI, ASYE, FSTI, SCLK, MCLK
∗3 CLTV, FILI, RFAC, ASYI, RFDC, TE, SE, FE, VC, VCTL
∗4 MDP, PDO, PCO, VPCO1, VPCO2
∗5 ASYO, DOUT, FSTO, C4M, C16M, SBSO, SQSO, SCOR, MON, LOCK, WDCK, SENS, MDS, DA01 to
DA16, LRCK, WFCK, FOK, COUT, MIRR, DFCT, FFON, FRDR, FRON, FFDR, TFON, TRDR, TRON,
TFDR, SFON, SRDR, SRON, SFDR, MCKO, V16M
∗6 FSW
∗7 FILO
∗8 TE, SE, FE, VC
∗9 RFDC
∗10 SENS, MDS, MDP, FSW, PDO, PCO, VPCO1, VPCO2
∗11 RFC
∗12 AIN1, AIN2
∗13 AOUT1, AOUT2, LOUT1, LOUT2
–8–
CXD2586R/-1
2. AC Characteristics
(1) XTLI pin, VCOI pin
(a) When using self-excited oscillation
(Topr = –20 to +75°C, VDD = AVDD = 5.0V ±10%)
Item
Symbol
Min.
Oscillation frequency fMAX
Typ.
7
Max.
Unit
34
MHz
(b) When inputting pulses to XTLI and VCOI pins
(Topr = –20 to +75°C, VDD = AVDD = 5.0V ±10%)
Item
Symbol
Min.
Typ.
Max.
Unit
High level pulse
width
tWHX
13
500
ns
Low level pulse
width
tWLX
13
500
ns
Pulse cycle
tCX
26
1000
ns
Input high level
VIHX
VDD – 1.0
Input low level
VILX
0.8
V
Rise time,
fall time
tR, tF
10
ns
V
tCX
tWLX
tWHX
VIHX
VIHX × 0.9
VDD/2
XTLI
VIHX × 0.1
VILX
tR
tF
(c) When inputting sine waves to XTLI and VCOI pins via a capacitor
(Topr = –20 to +75°C, VDD = AVDD = 5.0V ±10%)
Item
Input amplitude
Symbol
Min.
VI
2.0
Typ.
Max.
Unit
VDD + 0.3 Vp-p
–9–
CXD2586R/-1
(2) CLOK, DATA, XLAT, SQCK, and EXCK pins
(VDD = AVDD = 5.0V ±10%, VSS = AVSS = 0V, Topr = –20 to +75˚C)
Item
Symbol
Clock frequency
fCK
Clock pulse width
Latch pulse width
tWCK
tSU
tH
tD
tWL
EXCK SQCK frequency
fT
EXCK SQCK pulse width
tWT
Setup time
Hold time
Delay time
Min.
Typ.
MHz
300
ns
300
ns
300
ns
750
ns
0.65
750
tH
tD
tWL
EXCK
SQCK
tWT
MHz
ns
DATA
tWT
1/fT
SBSO
SQSO
tSU
0.65
ns
CLOK
tSU
Unit
750
1/fCK
tWCK
tWCK
XLAT
Max.
tH
– 10 –
CXD2586R/-1
(3) SCLK pin
XLAT
tDLS
tSPW
•••
SCLK
1/fSCLK
Serial Read Out Data
(SENS)
•••
MSB
Item
Symbol
SCLK frequency
fSCLK
SCLK pulse width
tSPW
tDLS
Delay time
Min.
Typ.
Max.
Unit
1
MHz
500
ns
15
µs
LSB
(4) COUT, MIRR and DFCT pins
Operating frequency
(VDD = AVDD = 5.0V ±10%, VSS = AVSS = 0V, Topr = –20 to +75°C)
Item
Symbol
Min.
Typ.
Max.
Unit
Conditions
COUT maximum operating frequency
fCOUT
40
kHz
∗1
MIRR maximum operating frequency
fMIRR
40
kHz
∗2
DFCT maximum operating frequency
fDFCTH
5
kHz
∗3
∗1 When using a high-speed traverse TZC.
∗2
B
A
When the RF signal continuously satisfies the following conditions during the above traverse.
• A = 0.6 to A1.3V
•
B
= less than 25%
A+B
∗3 During complete RF signal omission.
When settings related to DFCT signal generation are Typ.
– 11 –
CXD2586R/-1
(5) BCKI, LRCKI and PCMDI pins
Item
(VDD = 5.0V ±10%, Topr = –20 to +75°C)
Symbol
Min.
tBCK
tWIB
tIDS
tIDH
tILRH
tILRS
Input BCKI frequency
Input BCKI pulse width
Input data setup time
Input data hold time
Input LRCK setup time
Input LRCK hold time
Typ.
Max.
Unit
4.5
MHz
100
10
15
ns
10
15
tWIB
tWIB
BCKI
50%
tIDS
tIDH
PCMDI
tILRH
tILRS
LRCKI
(6) AOUT1, AOUT2, LOUT1 and LOUT2 pins
(VDD = AVDD =5.0V ±5%, VSS = AVSS = 0V, Topr = –20 to +75°C)
Item
Symbol
Min.
Output voltage (1)
VOUT (1) 0.1VDD∗
Output voltage (2)
VOUT (2)
VSS
Load resistance
RL
10
Typ.
Max.
Unit
Applicable pins
0.9VDD∗
V
∗1
VDD
V
∗2
kΩ
∗1, ∗2
∗ When a sine wave of 1kHz and 0dB is output.
Applicable pins
∗1 AOUT1, AOUT2
∗2 LOUT1, LOUT2
– 12 –
CXD2586R/-1
DAC Analog Characteristics
Measurement conditions
(Ta = 25°C, VDD = 5.0V, FS = 44.1kHz, signal frequency = 1kHz, measurement band = 4Hz to 20kHz, master clock = 768fs)
Typ.
Unit
S/N ratio
93
dB
Remarks
(EIAJ) ∗1
THD + N
0.01
%
(EIAJ)
Dynamic range
91
dB
(EIAJ) ∗1, ∗2
Channel separation
91
dB
(EIAJ)
Output level
1.31
V (rms)
Difference in gain between channels
0.1
dB
Item
∗1 Using "A" weighting filter
∗2 –60dB, 1kHz input
The analog characteristics measurement circuit is shown below.
12k
AOUT1 58
12k
680p
12k
SHIBASOKU (AM51A)
AIN1 57
150p
Audio Analyzer
LOUT1 56
47µ
100k
LPF external circuit diagram
768fs
SHIBASOKU (AM51A)
AOUT1
Analog
1ch
AIN1
TEST DISK
DATA
LOUT1
CXD2586
AOUT2
Audio Circuit
AIN2
LOUT2
Fs = 44.1kHz
Block diagram of analog characteristics measurement
– 13 –
Audio Analyzer
2ch
CXD2586R/-1
Contents
[1] CPU Interface
§1-1. CPU Interface Timing ...................................................................................................................... 15
§1-2. CPU Interface Command Table ...................................................................................................... 15
§1-3. CPU Command Presets .................................................................................................................. 25
§1-4. Description of SENS Signals ........................................................................................................... 30
[2] Subcode Interface
§2-1. P to W Subcode Readout ................................................................................................................ 57
§2-2. 80-bit Sub Q Readout ...................................................................................................................... 57
[3] Description of Modes
§3-1. CLV-N Mode .................................................................................................................................... 63
§3-2. CLV-W Mode ................................................................................................................................... 63
§3-3. CAV-W Mode ................................................................................................................................... 63
[4] Description of Other Functions
§4-1. Channel Clock Regeneration by the Digital PLL Circuit .................................................................. 65
§4-2. Frame Sync Protection .................................................................................................................... 67
§4-3. Error Correction ............................................................................................................................... 67
§4-4. DA Interface ..................................................................................................................................... 68
§4-5. Digital Out ........................................................................................................................................ 71
§4-6. Servo Auto Sequence ...................................................................................................................... 72
§4-7. Digital CLV ....................................................................................................................................... 80
§4-8. Playback Speed ............................................................................................................................... 81
§4-9. DAC Block Playback Speed ............................................................................................................ 82
§4-10. DAC Block Input Timing .................................................................................................................. 82
§4-11. CXD2586R/-1 Clock System ........................................................................................................... 84
[5] Description of Servo Signal Processing-System Functions and Commands
§5-1. General Description of the Servo Signal Processing System .......................................................... 85
§5-2. Digital Servo Block Master Clock (MCK) ......................................................................................... 86
§5-3. AVRG Measurement and Compensation ........................................................................................ 86
§5-4. E:F Balance Adjustment Function ................................................................................................... 88
§5-5. FCS Bias Adjustment Function ........................................................................................................ 88
§5-6. AGCNTL Function ........................................................................................................................... 90
§5-7. FCS Servo and FCS Search ........................................................................................................... 92
§5-8. TRK and SLD Servo Control ........................................................................................................... 93
§5-9. MIRR and DFCT Signal Generation ................................................................................................ 94
§5-10. DFCT Countermeasure Circuit ........................................................................................................ 95
§5-11. Anti-Shock Circuit ............................................................................................................................ 95
§5-12. Brake Circuit .................................................................................................................................... 96
§5-13. COUT Signal ................................................................................................................................... 97
§5-14. Serial Readout Circuit ...................................................................................................................... 97
§5-15. Writing the Coefficient RAM ............................................................................................................ 98
§5-16. PWM Output .................................................................................................................................... 98
§5-17. DIRC Input Pin ............................................................................................................................... 100
§5-18. Servo Status Changes Produced by the LOCK Signal .................................................................. 101
§5-19. Description of Commands and Data Sets ..................................................................................... 101
§5-20. List of Servo Filter Coefficients ...................................................................................................... 113
§5-21. FILTER Composition ..................................................................................................................... 115
§5-22. TRACKING and FOCUS Frequency Response ............................................................................ 122
[6] Application Circuit
§6-1. Application Circuit .......................................................................................................................... 123
Explanation of abbreviations
AVRG:
AGCNTL:
FCS:
TRK:
SLD:
DFCT:
– 14 –
Average
Automatic gain control
Focus
Tracking
Sled
Defect
CXD2586R/-1
[1] CPU Interface
§1-1. CPU Interface Timing
• CPU interface
This interface uses DATA, CLOK, and XLAT to set the modes.
The interface timing chart is shown below.
750ns or more
CLOK
DATA
D18
D19
D20
D21
D22
D23
750ns or more
XLAT
Valid
Registers
• The internal registers are initialized by a reset when XRST = 0.
§1-2. CPU Interface Command Table
Total bit length for each register
Register
0 to 2
3
Total bit length
8bit
8 to 24bit
4 to 6
16bit
7
20bit
8
24bit
9
20bit
A
28bit
B
20bit
C to D
16bit
E
20bit
– 15 –
1
FOCUS
CONTROL
0
TRACKING
CONTROL
Command
Register
0001
0000
– 16 –
—
—
—
—
—
—
—
0
—
—
1
—
—
—
—
—
—
—
—
0
—
—
0
1
1
1
0
D18
—
—
1
0
—
—
—
—
1
1
1
0
—
—
D17
Data 1
1
D23 to D20 D19
Address
Command Table ($0X to 1X)
0
1
—
—
—
—
—
—
1
0
—
—
—
—
D16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
D15
—
—
—
—
—
—
—
—
—
—
—
—
—
—
D14
—
—
—
—
—
—
—
—
—
—
—
—
—
—
D13
Data 2
—
—
—
—
—
—
—
—
—
—
—
—
—
—
D12
—
—
—
—
—
—
—
—
—
—
—
—
—
—
D11
—
—
—
—
—
—
—
—
—
—
—
—
—
—
D10
—
—
—
—
—
—
—
—
—
—
—
—
—
—
D9
Data 3
—
—
—
—
—
—
—
—
—
—
—
—
—
—
D8
—
—
—
—
—
—
—
—
—
—
—
—
—
—
D7
—
—
—
—
—
—
—
—
—
—
—
—
—
—
D6
—
—
—
—
—
—
—
—
—
—
—
—
—
—
D5
Data 4
—
—
—
—
—
—
—
—
—
—
—
—
—
—
D4
—
—
—
—
—
—
—
—
—
—
—
—
—
—
D3
—
—
—
—
—
—
—
—
—
—
—
—
—
—
D2
—
—
—
—
—
—
—
—
—
—
—
—
—
—
D1
Data 5
—
—
—
—
—
—
—
—
—
—
—
—
—
—
D0
—: Don’t care
TRACKING GAIN UP
FILTER SELECT 2
TRACKING GAIN UP
FILTER SELECT 1
TRACKING GAIN UP
TRACKING GAIN
NORMAL
BRAKE OFF
BRAKE ON
ANTI SHOCK OFF
ANTI SHOCK ON
FOCUS SEACH
VOLTAGE UP
FOCUS SEARCH
VOLTAGE DOWN
FOCUS SERVO OFF,
FOCUS SEARCH
VOLTAGE OUT
FOCUS SERVO OFF,
0V OUT
FOCUS SERVO ON
(FOCUS GAIN
DOWN)
FOCUS SERVO ON
(FOCUS GAIN
NORMAL)
CXD2586R/-1
2
– 17 –
3
SELECT
Command
TRACKING
MODE
Register
Command
Register
0011
0
0
0
0
0
0
0
D18
0
D23 to D20 D19
—
—
—
—
—
—
1
1
—
0
1
—
1
0
Address
0010
0
D18
1
0
1
0
—
—
—
—
D16
1
1
0
0
D17
1
0
1
0
D16
Data 1
1
1
0
0
—
—
—
—
D17
Data 1
0
D23 to D20 D19
Address
Command Table ($2X to 3X)
—
—
—
—
D15
—
—
—
—
—
—
—
—
D15
—
—
—
—
—
—
—
—
D13
—
—
—
—
D14
—
—
—
—
D13
Data 2
—
—
—
—
—
—
—
—
D14
Data 2
—
—
—
—
D12
—
—
—
—
—
—
—
—
D12
—
—
—
—
D11
—
—
—
—
—
—
—
—
D11
—
—
—
—
—
—
—
—
D9
—
—
—
—
D10
—
—
—
—
D9
Data 3
—
—
—
—
—
—
—
—
D10
Data 3
—
—
—
—
D8
—
—
—
—
—
—
—
—
D8
—
—
—
—
D7
—
—
—
—
—
—
—
—
D7
—
—
—
—
—
—
—
—
D5
—
—
—
—
D6
—
—
—
—
D5
Data 4
—
—
—
—
—
—
—
—
D6
Data 4
—
—
—
—
D4
—
—
—
—
—
—
—
—
D4
—
—
—
—
D3
—
—
—
—
—
—
—
—
D3
—
—
—
—
—
—
—
—
D1
—
—
—
—
D2
—
—
—
—
D1
Data 5
—
—
—
—
—
—
—
—
D2
Data 5
—
—
—
—
D0
—
—
—
—
—
—
—
—
D0
—: Don’t care
SLED KICK LEVEL
(±4 × basic value)
SLED KICK LEVEL
(±3 × basic value)
SLED KICK LEVEL
(±2 × basic value)
SLED KICK LEVEL
(±1 × basic value) (Default)
REVERSE SLED
MOVE
FORWARD SLED
MOVE
SLED SERVO ON
SLED SERVO OFF
REVERSE TRACK
JUMP
FORWARD TRACK
JUMP
TRACKING SERVO ON
TRACKING SERVO
OFF
CXD2586R/-1
3
Register
SELECT
Command
Address 2
Address 3
0011
0100
0000
0
0
1
1
1
0
0
0
0
0
– 18 –
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
D10
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
D9
Address 4
0
D23 to D20 D19 to D16 D15 to D12 D11
Address 1
Command Table ($340X)
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
D8
D6
D5
D4
D3
D2
D1
Data 2
D0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
D7
Data 1
KRAM DATA (K0F)
FOCUS DEFECT HOLD GAIN
KRAM DATA (K0E)
FOCUS PHASE COMPENSATE FILTER A
KRAM DATA (K0D)
FOCUS LOW BOOST FILTER B-L
KRAM DATA (K0C)
FOCUS LOW BOOST FILTER B-H
KRAM DATA (K0B)
FOCUS LOW BOOST FILTER A-L
KRAM DATA (K0A)
FOCUS LOW BOOST FILTER A-H
KRAM DATA (K09)
FOCUS HIGH CUT FILTER B
KRAM DATA (K08)
FOCUS HIGH CUT FILTER A
KRAM DATA (K07)
SLED AUTO GAIN
KRAM DATA (K06)
FOCUS INPUT GAIN
KRAM DATA (K05)
SLED OUTPUT GAIN
KRAM DATA (K04)
SLED LOW BOOST FILTER B-L
KRAM DATA (K03)
SLED LOW BOOST FILTER B-H
KRAM DATA (K02)
SLED LOW BOOST FILTER A-L
KRAM DATA (K01)
SLED LOW BOOST FILTER A-H
KRAM DATA (K00)
SLED INPUT GAIN
CXD2586R/-1
3
Register
SELECT
Command
Address 2
Address 3
0011
0100
0001
0
0
1
1
1
0
0
0
0
0
– 19 –
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
D10
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
D9
Address 4
0
D23 to D20 D19 to D16 D15 to D12 D11
Address 1
Command Table ($341X)
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
D8
D6
D5
D4
D3
D2
D1
Data 2
D0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
D7
Data 1
KRAM DATA (K1F)
TRACKING LOW BOOST FILTER B-L
KRAM DATA (K1E)
TRACKING LOW BOOST FILTER B-H
KRAM DATA (K1D)
TRACKING LOW BOOST FILTER A-L
KRAM DATA (K1C)
TRACKING LOW BOOST FILTER A-H
KRAM DATA (K1B)
TRACKING HIGH CUT FILTER B
KRAM DATA (K1A)
TRACKING HIGH CUT FILTER A
KRAM DATA (K19)
TRACKING INPUT GAIN
KRAM DATA (K18)
FIX
KRAM DATA (K17)
HPTZC / AUTO GAIN LOW PASS FILTER B
KRAM DATA (K16)
ANTI SHOCK HIGH PASS FILTER A
KRAM DATA (K15)
HPTZC / AUTO GAIN HIGH PASS FILTER B
KRAM DATA (K14)
HPTZC / AUTO GAIN HIGH PASS FILTER A
KRAM DATA (K13)
FOCUS AUTO GAIN
KRAM DATA (K12)
ANTI SHOCK INPUT GAIN
KRAM DATA (K11)
FOCUS OUTPUT GAIN
KRAM DATA (K10)
FOCUS PHASE COMPENSATE FILTER B
CXD2586R/-1
3
Register
SELECT
Command
Address 2
Address 3
0011
0100
0010
0
0
1
1
1
0
0
0
0
0
– 20 –
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
D10
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
D9
Address 4
0
D23 to D20 D19 to D16 D15 to D12 D11
Address 1
Command Table ($342X)
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
D8
D6
D5
D4
D3
D2
D1
Data 2
D0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
D7
Data 1
KRAM DATA (K2F)
NOT USED
KRAM DATA (K2E)
NOT USED
KRAM DATA (K2D)
FOCUS GAIN DOWN OUTPUT GAIN
KRAM DATA (K2C)
FOCUS GAIN DOWN PHASE COMPENSATE FILTER B
KRAM DATA (K2B)
FOCUS GAIN DOWN DEFECT HOLD GAIN
KRAM DATA (K2A)
FOCUS GAIN DOWN PHASE COMPENSATE FILTER A
KRAM DATA (K29)
FOCUS GAIN DOWN LOW BOOST FILTER B-L
KRAM DATA (K28)
FOCUS GAIN DOWN LOW BOOST FILTER B-H
KRAM DATA (K27)
FOCUS GAIN DOWN LOW BOOST FILTER A-L
KRAM DATA (K26)
FOCUS GAIN DOWN LOW BOOST FILTER A-H
KRAM DATA (K25)
FOCUS GAIN DOWN HIGH CUT FILTER B
KRAM DATA (K24)
FOCUS GAIN DOWN HIGH CUT FILTER A
KRAM DATA (K23)
TRACKING AUTO GAIN
KRAM DATA (K22)
TRACKING OUTPUT GAIN
KRAM DATA (K21)
TRACKING PHASE COMPENSATE FILTER B
KRAM DATA (K20)
TRACKING PHASE COMPENSATE FILTER A
CXD2586R/-1
3
Register
SELECT
Command
Address 2
Address 3
0011
0100
0011
0
0
1
1
1
0
0
0
0
0
– 21 –
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
D10
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
D9
Address 4
0
D23 to D20 D19 to D16 D15 to D12 D11
Address 1
Command Table ($343X)
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
D8
D6
D5
D4
D3
D2
D1
Data 2
D0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
D7
Data 1
KRAM DATA (K3F)
NOT USED
KRAM DATA (K3E)
TRACKING GAIN UP OUTPUT GAIN
KRAM DATA (K3D)
TRACKING GAIN UP PHASE COMPENSATE FILTER B
KRAM DATA (K3C)
TRACKING GAIN UP PHASE COMPENSATE FILTER A
KRAM DATA (K3B)
TRACKING GAIN UP2 LOW BOOST FILTER B-L
KRAM DATA (K3A)
TRACKING GAIN UP2 LOW BOOST FILTER B-H
KRAM DATA (K39)
TRACKING GAIN UP2 LOW BOOST FILTER A-L
KRAM DATA (K38)
TRACKING GAIN UP2 LOW BOOST FILTER A-H
KRAM DATA (K37)
TRACKING GAIN UP2 HIGH CUT FILTER B
KRAM DATA (K36)
TRACKING GAIN UP2 HIGH CUT FILTER A
KRAM DATA (K35)
ANTI SHOCK FILTER COMPARATE GAIN
KRAM DATA (K34)
ANTI SHOCK HIGH PASS FILTER B-L
KRAM DATA (K33)
ANTI SHOCK HIGH PASS FILTER B-H
KRAM DATA (K32)
NOT USED
KRAM DATA (K31)
ANTI SHOCK LOW PASS FILTER B
KRAM DATA (K30)
FIX
CXD2586R/-1
3
Register
SELECT
Command
Address 2
Address 3
0011
0100
0100
0
0
1
1
1
0
0
0
0
0
– 22 –
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
D10
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
D9
Address 4
0
D23 to D20 D19 to D16 D15 to D12 D11
Address 1
Command Table ($344X)
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
D8
D6
D5
D4
D3
D2
D1
Data 2
D0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
D7
Data 1
KRAM DATA (K4F)
NOT USED
KRAM DATA (K4E)
NOT USED
KRAM DATA (K4D)
FOCUS HOLD FILTER OUTPUT GAIN
KRAM DATA (K4C)
FOCUS HOLD FILTER B-L
KRAM DATA (K4B)
FOCUS HOLD FILTER B-H
KRAM DATA (K4A)
FOCUS HOLD FILTER A-L
KRAM DATA (K49)
FOCUS HOLD FILTER A-H
KRAM DATA (K48)
FOCUS HOLD FILTER INPUT GAIN
KRAM DATA (K47)
NOT USED
KRAM DATA (K46)
NOT USED
KRAM DATA (K45)
TRACKING HOLD FILTER OUTPUT GAIN
KRAM DATA (K44)
TRACKING HOLD FILTER B-L
KRAM DATA (K43)
TRACKING HOLD FILTER B-H
KRAM DATA (K42)
TRACKING HOLD FILTER A-L
KRAM DATA (K41)
TRACKING HOLD FILTER A-H
KRAM DATA (K40)
TRACKING HOLD FILTER INPUT GAIN
CXD2586R/-1
3
Register
SELECT
Command
0
1
0
Address
0
– 23 –
0011
1
1
1
1
1
D18
1
1
D17
0
0
1
Address
1
D23 to D20 D19
0011
1
D17
1
0
1
D18
1
0
1
Address
0
0
1
1
1
0
0
1
1
0
0
0
1
0
1
D17
D18
D23 to D20 D19
0011
0
1
1
D17
D18
0
D23 to D20 D19
0011
0
D23 to D20 D19
Address 1
Command Table ($34FX to 3FX)
1
0
D16
1
0
D16
1
0
1
0
1
0
1
D16
0
0
0
D16
1
1
1
D13
D12
1
1
1
D12
TJ4
FS5 FS4
D13
DTZC TJ5
FT0
D14
Data 1
1
1
1
D14
D8
TJ2
D6
D5
D4
D3
D2
D1
Data 3
TJ1
TV5
FB5
D4
D3
TV3
FB3
TV1
FB1
D2
D1
Data 4
TV2
FB2
D0
TV0
—
0
0
0
0
0
—
—
D13
D14
D13
Data 1
—
—
D14
D12
—
—
D12
D11
—
—
D11
—
—
D9
D10
D9
Data 2
—
—
D10
Data 2
D8
—
—
D8
D7
—
—
D7
—
—
D5
D6
D5
Data 3
—
—
D6
Data 3
0
AGG4 XT4D XT2D
0
DRR2 DRR1 DRR0
0
ASFG
0
F1NM F1DM F3NM F3DM T1NM T1UM T3NM T3UM DFIS TLCD RFLP
D15
—
—
D15
Data 1
0
0
0
SERIAL DATA READ
MODE/SELECT
LEVEL/AUTO GAIN/
DFSW/ (Initialize)
FZSL/SLED MOVE/
Voltage/AUTO GAIN
0
D3
—
—
D3
—
—
D1
0
D2
D0
—
—
D0
—: Don’t care
TZC for COUT SLCT
DTZC
TZC for COUT SLCT
HPTZC (Default)
Operation for MIRR/
DFCT/FOK
MIRI XT1D Filter
D1
Data 4
—
—
D2
0
LPAS SRO1 SRO0 AGHF COT2 Others
0
D4
—
—
D4
0
Data 4
0
TJD0 FPS1 FPS0 TPS1 TPS0 CEIT SJHD INBK MTI0 FOCUS BIAS
0
SFO2 SFO1 SDF2 SDF1 MAX2 MAX1 SFOX BTF D2V2 D2V1 D1V2 D1V1 RINT
FBON FBSS FBUP FBV1 FBV0
DAC SD6 SD5 SD4 SD3 SD2 SD1 SD0
VCLM VCLC FLM FLC0 RFLM RFLC AGF AGT DFSW LKSW TBLM TCLM FLC1 TLC2 TLC1 TLC0
0
TRVSC DATA
FOCUS BIAS DATA
DTZC/TRACK JUMP
VOLTAGE/AUTO GAIN
D5
TV4
FB4
TJ0 SFJP TG6 TG5 TG4 TG3 TG2 TG1 TG0
D6
Data 3
TV6
FB6
FOCUS BIAS LIMIT
FOCUS SEARCH SPEED/
VOLTAGE/AUTO GAIN
D7
TV7
FB7
—
D0
FTZ FG6 FG5 FG4 FG3 FG2 FG1 FG0
FS2 FS1 FS0
FS3
D9
D8
TV9 TV8
FB9 FB8
D10
TJ3
D7
Data 2
FBL9 FBL8 FBL7 FBL6 FBL5 FBL4 FBL3 FBL2 FBL1
D9
Data 2
0
1
0
D10
D11
0
0
1
D11
Data 1
FZSH FZSL SM5 SM4 SM3 SM2 SM1 SM0 AGS AGJ AGGF AGGT AGV1 AGV2 AGHS AGHT
0
FT1
D15
1
1
1
D15
Address 2
CXD2586R/-1
– 24 –
0
1
1
1
1
1
1
1
Auto sequence
(N) track jump
count setting
MODE setting
Function
specification
Audio CTRL
Traverse monitor
counter setting
Spindle servo
coefficient setting
CLV CTRL
SPD MODE
7
8
9
A
B
C
D
E
A
Audio CTRL
1
1
1
0
0
0
0
1
1
1
1
D2
1 0 1 0
0
1
0
1
0
1
0
1
0
1
0
D0
Data 1
1
0
0
1
1
0
0
1
1
0
0
D1
Address
Address
0
Sled KICK,
KICK (F),
BRAKE (D)
6
Command
0
Blind (A, E),
Overflow (C, G),
Brake (B)
5
Register
0
Auto sequence
4
D3
Command
Register
Command Table ($4X to EX)
SD2
TR2
AS2
D2
0
8192
Mute
4096
ATT
DCLV
CM2
TB
Data 2
CM3
PWM MD
2048
1024
VP7
VP6
VP5
0
512
Data 4
DAC
EMP
KSL3
128
0
0
LSSL
D3
DAC
ATT
KSL2
64
0
0
0
D2
0
KSL1
32
0
0
0
D1
0
KSL0
16
0
0
0
D0
0
4
—
—
—
D2
1
2
—
—
—
D1
0
1
—
—
—
D0
PLM3 PLM2 PLM1 PLM0
0
8
—
—
—
D3
Data 4
VP3
0
128
D2
D1
Data 5
SFSL VC2C
VP4
0
256
VP1
0
32
VP0
0
16
D0
D3
D2
8
—
—
4
—
—
2
D1
D0
0
—
—
1
—: Don’t care
Gain Gain
FCSW
CAV1 CAV0
—
—
Data 6
HIFC LPWR VPON
VP2
0
64
AT2D7 AT2D6 AT2D5 AT2D4 AT2D3 AT2D2 AT2D1 AT2D0
D3
CM0 EPWM SPDC ICAP
CLVS
Gain
Data 3
CM1
TP
0
VCO
SEL2
256
KF0
0
MT0
D0
Data 3
PCT1 PCT2 DADS SOC2 AT1D7 AT1D6 AT1D5 AT1D4 AT1D3 AT1D2 AT1D1 AT1D0
Gain Gain Gain Gain Gain Gain
MDP1 MDP0 MDS1 MDS0 DCLV1 DCLV0
32768 16384
0
DCLV DSPB ASEQ DPLL BiliGL BiliGL
FLFC
ON/OFF ON/OFF ON/OFF ON/OFF MAIN SUB
ASHS SOCT
512
KF1
0
MT1
D1
VCO
SEL
KF2
0
MT2
D2
CD- DOUT DOUT
WSEL
ROM Mute Mute-F
KF3
0
MT3
D3
1024
SD0
TR0
AS0
D0
2048
8192
SD1
TR1
AS1
D1
Data 2
4096
32768 16384
SD3
TR3
AS3
D3
Data 1
CXD2586R/-1
Command
Register
SELECT
0010
TRACKING
MODE
2
3
0001
TRACKING
CONTROL
1
0
0
0
– 25 –
0011
0
D18
0
0
0
D18
0
1
D18
0
1
0
D16
0
D17
0
D17
0
D16
0
D16
Data 1
0
0
0
D17
Data 1
Address 1
0
D23 to D20 D19
0011
D23 to D20 D19
Address
0000
FOCUS
CONTROL
0
D23 to D20 D19
Command
Register
Address
Command Preset Table ($0X to 34X)
§1-3. CPU Command Presets
0
D15
—
D15
—
—
—
D15
—
—
—
D13
—
D13
D14
D13
Address 2
—
D14
Data 2
—
—
—
D14
Data 2
D12
—
D12
—
—
—
D12
D11
—
D11
—
—
—
D11
—
—
—
D9
—
D9
D9
D8
—
D8
—
—
—
D8
D7
—
D7
—
—
—
D7
—
—
—
D5
—
D5
D6
D5
Data 1
—
D6
Data 4
—
—
—
D6
Data 4
D4
—
D4
—
—
—
D4
See the coefficient preset values table.
D10
Address 3
—
D10
Data 3
—
—
—
D10
Data 3
D3
—
D3
—
—
—
D3
—
—
—
D1
—
D0
D2
D0
Data 2
—
D2
Data 5
—
—
—
D2
Data 5
D0
—
D0
—
—
—
D0
—: Don’t care
KRAM DATA
($3400XX to $344fXX)
SLED KICK LEVEL
(±1 + basic value) (Default)
TRACKING SERVO OFF
SLED SERVO OFF
TRACKING GAIN UP
FILTER SELECT 1
FOCUS SERVO OFF,
0V OUT
CXD2586R/-1
3
Register
SELECT
Command
0
1
0
– 26 –
0011
1
1
1
1
D18
1
1
D17
0
1
Address
1
D23 to D20 D19
0011
D17
1
0
1
D18
1
0
1
Address
0
0
1
0
1
1
0
0
1
1
0
1
0
1
0
D23 to D20 D19
0011
D17
D18
Address
0
0
1
1
D17
D18
0
D23 to D20 D19
0011
0
D23 to D20 D19
Address 1
Command Preset Table ($34FX to 3FX)
1
0
D16
0
D16
1
0
1
0
1
0
1
D16
0
0
0
D16
1
1
1
D13
—
D13
1
0
0
0
0
0
0
D13
0
0
0
0
0
0
0
0
D12
D13
—
D12
0
0
0
0
1
0
1
D12
1
1
1
D12
D14
Data 1
—
D14
Data 1
1
0
0
0
1
0
1
D14
Data 1
1
1
1
D14
D15
—
D15
1
0
0
0
0
0
0
D15
1
1
1
D15
Address 2
0
0
D11
—
D11
0
0
0
0
0
1
1
D11
0
0
1
D11
0
0
0
D9
0
0
0
0
0
1
0
D9
—
D9
0
0
D10
0
0
D9
Data 2
—
D10
Data 2
0
0
0
0
0
1
0
D10
Data 2
0
1
0
D10
0
0
D8
—
D8
0
0
0
0
0
0
0
D8
0
0
0
D8
Data 1
0
0
D7
—
D7
0
0
0
0
1
0
0
D7
0
0
0
D7
0
0
0
D5
0
0
0
0
1
1
1
D5
—
D5
0
0
D6
0
0
D5
data 3
—
D6
data 3
1
0
0
0
0
0
0
D6
Data 3
0
0
0
D6
Data 2
0
0
D4
—
D4
1
0
0
0
1
0
0
D4
0
0
0
D4
0
0
D3
—
D3
0
0
0
0
1
1
1
D3
0
0
0
D3
0
0
0
D1
0
0
0
0
1
1
0
D1
—
D1
0
0
D2
0
0
D1
Data 4
—
D2
Data 4
0
0
0
0
0
1
1
D2
Data 4
0
0
0
D2
Data 3
0
0
D0
—
D0
0
0
0
0
0
0
1
D0
0
0
0
D0
Others
Filter
—: Don’t care
TZC for COUT SLCT
HPTZC (Default)
Operation for MIRR/
DFCT/FOK
FOCUS BIAS
SERIAL DATA READ
MODE/SELECT
LEVEL/AUTO GAIN/
DFSW/ (Initialize)
FZSL/SLED MOVE/
Voltage/AUTO GAIN
DTZC/TRACK JUMP
VOLTAGE AUTO GAIN
FOCUS SEARCH SPEED/
VOLTAGE AUTO GAIN
TRVSC DATA
FOCUS BIAS DATA
FOCUS BIAS LIMIT
CXD2586R/-1
– 27 –
0
1
1
1
1
1
1
1
Auto sequence
(N) track jump
count setting
MODE setting
Function
specification
Audio CTRL
Traverse monitor
counter setting
Spindle servo
coefficient setting
CLV CTRL
SPD MODE
7
8
9
A
B
C
D
E
A
Audio CTRL
1
1
1
0
0
0
0
1
1
1
1
D2
1 0 1 0
0
1
0
1
0
1
0
1
0
1
0
D0
Data 1
1
0
0
1
1
0
0
1
1
0
0
D1
Address
Address
0
Sled KICK,
BRAKE (D),
KICK (F)
6
Command
0
Blind (A, E),
Brake (B),
Overflow (C, G)
5
Register
0
Auto sequence
4
D3
Command
Register
Command Preset Table ($4X to EX)
0
0
0
0
0
0
0
0
1
1
0
D2
Data 2
0
0
0
0
0
1
0
0
0
0
0
D3
0
0
0
0
1
1
0
0
1
1
0
D0
Data 3
0
0
0
0
1
0
0
0
1
0
0
D1
Data 1
0
0
0
0
0
0
0
0
0
0
0
D2
Data 4
0
0
0
0
0
0
0
0
0
0
0
D3
1
D3
0
0
0
0
0
0
0
0
0
0
0
D1
Data 2
1
D2
1
D1
0
0
0
0
1
0
0
0
0
0
0
D3
Data 5
0
0
0
1
0
0
0
1
0
0
0
D0
1
D0
0
0
0
0
1
0
0
0
0
0
0
D2
1
D3
0
0
0
0
1
0
0
0
0
0
0
D1
Data 3
1
D2
1
D1
0
—
—
0
1
1
0
0
—
—
—
D3
Data 6
0
0
0
0
1
0
0
0
0
0
0
D0
1
D0
0
—
—
0
1
0
0
0
—
—
—
D2
0
—
—
0
1
1
0
0
—
—
—
D0
—: Don’t care
0
—
—
0
1
0
1
0
—
—
—
D1
Data 4
CXD2586R/-1
CXD2586R/-1
<Coefficient ROM Preset Values Table (1)>
ADDRESS
DATA
K00
K01
K02
K03
K04
K05
K06
K07
K08
K09
K0A
K0B
K0C
K0D
K0E
K0F
E0
81
23
7F
6A
10
14
30
7F
46
81
1C
7F
58
82
7F
SLED INPUT GAIN
SLED LOW BOOST FILTER A-H
SLED LOW BOOST FILTER A-L
SLED LOW BOOST FILTER B-H
SLED LOW BOOST FILTER B-L
SLED OUTPUT GAIN
FOCUS INPUT GAIN
SLED AUTO GAIN
FOCUS HIGH CUT FILTER A
FOCUS HIGH CUT FILTER B
FOCUS LOW BOOST FILTER A-H
FOCUS LOW BOOST FILTER A-L
FOCUS LOW BOOST FILTER B-H
FOCUS LOW BOOST FILTER B-L
FOCUS PHASE COMPENSATE FILTER A
FOCUS DEFECT HOLD GAIN
K10
K11
K12
K13
K14
K15
K16
K17
K18
K19
K1A
K1B
K1C
K1D
K1E
K1F
4E
32
20
30
80
77
80
77
00
F1
7F
3B
81
44
7F
5E
FOCUS PHASE COMPENSATE FILTER B
FOCUS OUTPUT GAIN
ANTI SHOCK INPUT GAIN
FOCUS AUTO GAIN
HPTZC / Auto Gain HIGH PASS FILTER A
HPTZC / Auto Gain HIGH PASS FILTER B
ANTI SHOCK HIGH PASS FILTER A
HPTZC / Auto Gain LOW PASS FILTER B
Fix∗
TRACKING INPUT GAIN
TRACKING HIGH CUT FILTER A
TRACKING HIGH CUT FILTER B
TRACKING LOW BOOST FILTER A-H
TRACKING LOW BOOST FILTER A-L
TRACKING LOW BOOST FILTER B-H
TRACKING LOW BOOST FILTER B-L
K20
K21
K22
K23
K24
K25
K26
K27
K28
K29
K2A
K2B
K2C
K2D
K2E
K2F
82
44
18
30
7F
46
81
3A
7F
66
82
44
4E
1B
00
00
TRACKING PHASE COMPENSATE FILTER A
TRACKING PHASE COMPENSATE FILTER B
TRACKING OUTPUT GAIN
TRACKING AUTO GAIN
FOCUS GAIN DOWN HIGH CUT FILTER A
FOCUS GAIN DOWN HIGH CUT FILTER B
FOCUS GAIN DOWN LOW BOOST FILTER A-H
FOCUS GAIN DOWN LOW BOOST FILTER A-L
FOCUS GAIN DOWN LOW BOOST FILTER B-H
FOCUS GAIN DOWN LOW BOOST FILTER B-L
FOCUS GAIN DOWN PHASE COMPENSATE FILTER A
FOCUS GAIN DOWN DEFECT HOLD GAIN
FOCUS GAIN DOWN PHASE COMPENSATE FILTER B
FOCUS GAIN DOWN OUTPUT GAIN
NOT USED
NOT USED
CONTENTS
– 28 –
CXD2586R/-1
<Coefficient ROM Preset Values Table (2)>
ADDRESS
DATA
K30
K31
K32
K33
K34
K35
K36
K37
K38
K39
K3A
K3B
K3C
K3D
K3E
K3F
80
66
00
7F
6E
20
7F
3B
80
44
7F
77
86
0D
57
00
Fix∗
ANTI SHOCK LOW PASS FILTER B
NOT USED
ANTI SHOCK HIGH PASS FILTER B-H
ANTI SHOCK HIGH PASS FILTER B-L
ANTI SHOCK FILTER COMPARATE GAIN
TRACKING GAIN UP2 HIGH CUT FILTER A
TRACKING GAIN UP2 HIGH CUT FILTER B
TRACKING GAIN UP2 LOW BOOST FILTER A-H
TRACKING GAIN UP2 LOW BOOST FILTER A-L
TRACKING GAIN UP2 LOW BOOST FILTER B-H
TRACKING GAIN UP2 LOW BOOST FILTER B-L
TRACKING GAIN UP PHASE COMPENSATE FILTER A
TRACKING GAIN UP PHASE COMPENSATE FILTER B
TRACKING GAIN UP OUTPUT GAIN
NOT USED
K40
K41
K42
K43
K44
K45
K46
K47
K48
K49
K4A
K4B
K4C
K4D
K4E
K4F
04
7F
7F
79
17
6D
00
00
02
7F
7F
79
17
54
00
00
TRACKING HOLD FILTER INPUT GAIN
TRACKING HOLD FILTER A-H
TRACKING HOLD FILTER A-L
TRACKING HOLD FILTER B-H
TRACKING HOLD FILTER B-L
TRACKING HOLD FILTER OUTPUT GAIN
NOT USED
NOT USED
FOCUS HOLD FILTER INPUT GAIN
FOCUS HOLD FILTER A-H
FOCUS HOLD FILTER A-L
FOCUS HOLD FILTER B-H
FOCUS HOLD FILTER B-L
FOCUS HOLD FILTER OUTPUT GAIN
NOT USED
NOT USED
CONTENTS
∗ Fix indicates that normal preset values should be used.
– 29 –
CXD2586R/-1
§1-4. Description of SENS Signals
SENS output
ASEQ = 0
ASEQ = 1
Output data
length
$0X
Z
FZC
—
$1X
Z
AS
—
$2X
Z
TZC
—
$38
Z
AGOK∗
—
$38
Z
XAVEBSY∗
—
$30 to 37
Z
SSTP
—
$3A
Z
FBIAS Count STOP
—
$3B to 3F
Z
SSTP
—
$3904
Z
TE Avrg Reg.
9 bit
$3908
Z
FE Avrg Reg.
9 bit
$390C
Z
VC Avrg Reg.
9 bit
$391C
Z
TRVSC Reg.
9 bit
$391D
Z
FB Reg.
9 bit
$391F
Z
RFDC Avrg Reg.
8 bit
$4X
Z
XBUSY
—
$5X
Z
FOK
—
$6X
Z
0
—
$AX
GFS
GFS
—
$BX
COMP
COMP
—
$CX
COUT
COUT
—
$EX
OV64
OV64
—
Z
0
—
Microcomputer serial register
(latching not required)
$7X, 8X, 9X,
DX, FX
∗ $38 outputs AGOK during AGT and AGF command settings, and XAVEBSY during AVRG measurement.
SSTP is output in all other cases.
– 30 –
CXD2586R/-1
Description of SENS Signals
SENS output
Z
The SENS pin is high impedance.
XBUSY
Low while the auto sequencer is in operation, high when operation terminates.
FOK
Outputs the same signal as the FOK pin.
High for "focus OK".
GFS
High when the regenerated frame sync is obtained with the correct timing.
COMP
Counts the number of tracks set with Reg B.
High when Reg B is latched, low when the initial Reg B number is input by CNIN.
COUT
Counts the number of tracks set with Reg B.
High when Reg B is latched, toggles each time the Reg B number is input by CNIN. While $44
and $45 are being executed, toggles with each CNIN 8-count instead of the Reg B number.
OV64
Low when the EFM signal is lengthened by 64 channel clock pulses or more after passing
through the sync detection filter.
– 31 –
CXD2586R/-1
The meaning of the data for each address is explained below.
$4X commands
Register name
4
AS3
Data 1
Data 2
Data 3
Command
MAX timer value
Timer range
AS2
Command
AS1
AS0
MT3
MT2
MT1
MT0
LSSL
0
0
AS3
AS2
AS1
AS0
Cancel
0
0
0
0
Fine Search
0
1
0
RXF
Focus-On
0
1
1
1
1 Track Jump
1
0
0
RXF
10 Track Jump
1
0
1
RXF
2N Track Jump
1
1
0
RXF
M Track Move
1
1
1
RXF
0
RXF = 0 Forward
RXF = 1 Reverse
• When the Focus-on command ($47) is canceled, $02 is sent and the auto sequence is interrupted.
• When the Track jump commands ($44 to $45, $48 to $4D) are canceled, $25 is sent and the auto sequence
is interrupted.
MAX timer value
Timer range
MT3
MT2
MT1
MT0
LSSL
0
0
0
23.2ms
11.6ms
5.8ms
2.9ms
0
0
0
0
1.49s
0.74s
0.37s
0.18s
1
0
0
0
• To disable the MAX timer, set the MAX timer value to 0.
$5X commands
Timer
TR3
TR2
TR1
TR0
Blind (A, E), Overflow (C, G)
0.18ms
0.09ms
0.045ms
0.022ms
Brake (B)
0.36ms
0.18ms
0.09ms
0.045ms
– 32 –
CXD2586R/-1
$6X commands
Register name
6
SD3
Data 1
Data 2
KICK (D)
KICK (F)
SD2
SD1
SD0
Timer
KF3
KF2
KF1
KF0
SD3
SD2
SD1
SD0
When executing KICK (D)
$44 or $45
23.2ms
11.6ms
5.8ms
2.9ms
When executing KICK (D)
$4C or $4D
11.6ms
5.8ms
2.9ms
1.45ms
KF3
KF2
KF1
KF0
0.72ms
0.36ms
0.18ms
0.09ms
Timer
KICK (F)
$7X commands
Auto sequence track jump count setting
Command
Auto sequence track
jump count setting
Data 1
Data 2
Data 3
Data 4
D3 D2 D1 D0 D3 D2 D1 D0 D3 D2 D1 D0 D3 D2 D1 D0
215 214 213 212 211 210
29
28
27
26
25
24
23
22
21
20
This command is to set N when a 2N track jump is executed, to set M when an M track move is executed and
to set the jump count when fine search is executed for auto sequence.
• The maximum track count is 65,535, but note that with a 2N-track jump the maximum track jump count
depends on the mechanical limitations of the optical system.
• When the track jump count is from 0 to 15, the COUT signal is used to count tracks for 2N-track jump/M track
move; when the count is 16 or over, the MIRR signal is used. For fine search, the COUT signal is used to
count tracks.
– 33 –
CXD2586R/-1
$8X commands
Data 1
Command
Mode
specification
D3
D2
Data 2
D1
D0
D3
D2
Data 3
D1
D0
CD- DOUT DOUT
VCO
VCO
WSEL
ASHS SOCT
ROM Mute Mute-F
SEL1
SEL2
D3
D2
D1
D0
KSL3
KSL2
KSL1
KSL0
Command bit
C2PO timing
Processing
CDROM = 1
See the Timing
Chart 1-3
CDROM mode; average value interpolation and pre-value hold
are not performed.
CDROM = 0
See the Timing
Chart 1-3
Audio mode; average value interpolation and pre-value hold
are performed.
Command bit
Processing
DOUT Mute = 1
When Digital Out is on (MD2 pin = 1), DOUT output is muted.
DOUT Mute = 0
When Digital Out is on, DOUT output is not muted.
Command bit
Processing
D. out Mute F = 1
When Digital Out is on (MD2 pin = 1), DA output is muted.
D. out Mute F = 0
DA output mute is not affected when Digital Out is either on or off.
MD2
Other mute conditions∗
0
0
0
0
0
0
0
1
0
0
1
0
0
0
1
1
0
1
0
0
0
1
0
1
0
1
1
0
0
1
1
1
1
0
0
0
1
0
0
1
1
0
1
0
1
0
1
1
1
1
0
0
1
1
0
1
1
1
1
0
1
1
1
1
DOUT Mute D.out Mute F DOUT output DA output
0dB
OFF
–∞dB
0dB
0dB
–∞dB
0dB
–∞dB
–∞dB
∗ See mute conditions (1), (2), and (4) to (6) under $AX commands for other mute conditions.
– 34 –
CXD2586R/-1
Command bit
Sync protection window width
Application
WSEL = 1
±26 channel clock∗
Anti-rolling is enhanced.
WSEL = 0
±6 channel clock
Sync window protection is enhanced.
∗ In normal-speed playback, channel clock = 4.3218MHz.
Command bit
Function
ASHS = 0
The command transfer rate to SSP is set to normal speed.
ASHS = 1
The command transfer rate to SSP is set to half speed.
∗ See "§4-8. Playback Speed" for settings.
Command bit
Function
SOCT = 0
Sub Q is output from the SQSO pin.
SOCT = 1
Each output signal is output from the SQSO pin. Input the readout clock to SQCK.
(See the Timing Chart 2-4.)
Command bit
Processing
VCOSEL1 KSL3 KSL2
0
0
0
Multiplier PLL VCO1 is set to normal speed, and the output is 1/1 frequency-divided.
0
0
1
Multiplier PLL VCO1 is set to normal speed, and the output is 1/2 frequency-divided.
0
1
0
Multiplier PLL VCO1 is set to normal speed, and the output is 1/4 frequency-divided.
0
1
1
1
0
0
Multiplier PLL VCO1 is set to normal speed, and the output is 1/8 frequency-divided.
Multiplier PLL VCO1 is set to high speed∗, and the output is 1/1 frequency-divided.
1
0
1
1
1
0
Multiplier PLL VCO1 is set to high speed∗, and the output is 1/2 frequency-divided.
Multiplier PLL VCO1 is set to high speed∗, and the output is 1/4 frequency-divided.
1
1
1
Multiplier PLL VCO1 is set to high speed∗, and the output is 1/8 frequency-divided.
∗ Approximately twice the normal speed
Command bit
Processing
VCOSEL2 KSL1 KSL0
0
0
0
Wide-band PLL VCO2 is set to normal speed, and the output is 1/1 frequency-divided.
0
0
1
Wide-band PLL VCO2 is set to normal speed, and the output is 1/2 frequency-divided.
0
1
0
Wide-band PLL VCO2 is set to normal speed, and the output is 1/4 frequency-divided.
0
1
1
1
0
0
Wide-band PLL VCO2 is set to normal speed, and the output is 1/8 frequency-divided.
Wide-band PLL VCO2 is set to high speed∗, and the output is 1/1 frequency-divided.
1
0
1
1
1
0
Wide-band PLL VCO2 is set to high speed∗, and the output is 1/2 frequency-divided.
Wide-band PLL VCO2 is set to high speed∗, and the output is 1/4 frequency-divided.
1
1
1
Wide-band PLL VCO2 is set to high speed∗, and the output is 1/8 frequency-divided.
∗ Approximately twice the normal speed
– 35 –
CXD2586R/-1
$9X commands
Command
Data 1
D3
D2
Data 2
D1
Function
DCLV
DSPB
A.SEQ
D.PLL
specifications ON-OFF ON-OFF ON-OFF ON-OFF
Command bit
D2
D1
D0
BiliGL
MAIN
BiliGL
SUB
FLFC
0
CLV mode
Contents
In CLVS mode
FSW = low, MON = high, MDS = Z; MDP = servo control signal,
carrier frequency of 230Hz at TB = 0, and 460Hz at TB = 1.
In CLVP mode
FSW = Z, MON = high; MDS = speed control signal, carrier frequency
of 7.35kHz; MDP = phase control signal, carrier frequency of 1.8kHz.
DCLV on/off = 0
DCLV on/off = 1
(FSW, MON not
required)
D3
D0
In CLVS and
CLVP modes
When DCLV PWM
and MD = 1
(Prohibited in CLVW and CAV-W
modes)
MDS = PWM polarity signal, carrier frequency
of 132kHz.
MDP = PWM absolute value output (binary),
carrier frequency of 132kHz.
When DCLV PWM
and MD = 0
MDS = Z
MDP = ternary PWM output, carrier frequency
of 132kHz.
When DCLV on/off = 1 for the Digital CLV servo, the sampling frequency of the internal digital filter switches
simultaneously with the CLVP/CLVS switching.
Therefore, the cut-off frequency for the CLVS is fc = 70Hz when TB = 0, and fc = 140Hz when TB = 1.
Command bit
Processing
DSPB = 0
Normal-speed playback, C2 error correction quadruple correction.
DSPB = 1
Double-speed playback, C2 error correction double correction.
FLFC is normally 0.
FLFC is 1 in CAV-W mode, for any playback speed.
– 36 –
CXD2586R/-1
Command bit
Meaning
DPLL = 0 ∗
RFPLL is analog. PDO, VCOI and VCOO are used.
DPLL = 1
RFPLL is digital. PDO is high impedance.
∗ External parts for the FILI, FILO, PCO pins are required even when analog PLL is selected.
Command bit
BiliGL MAIN = 0
BiliGL MAIN = 1
BiliGL SUB = 0
STEREO
MAIN
BiliGL SUB = 1
SUB
Mute
Definition of bilingual capable MAIN, SUB and STEREO:
The left channel input is output to the left and right channels for MAIN.
The right channel input is output to the left and right channels for SUB.
The left and right channel inputs are output to the left and right channels for STEREO.
Data 3
Command
Function
specifications
Data 4
D11
D10
D9
D8
D7
D6
D5
D4
DAC
EMPH
DAC
ATT
0
0
PLM3
PLM2
PLM1
PLM0
The command bits control the DAC.
Note) For normal stereo, channel 1 is the left channel and channel 2 is the right channel.
Command bit
Processing
DAC EMPH = 1
Applies digital de-emphasis. When Fs = 44.1kHz, the emphasis constants are
τ1 = 50µs and τ2 = 15µs.
DAC EMPH = 0
Turns digital de-emphasis off.
Command bit
Processing
DAC ATT = 1
Identical digital attenuation control is used for both channels 1 and 2.
When common attenuation data is specified, the attenuation values for channel 1 is used.
DAC ATT = 0
Independent digital attenuation control is used for both channels 1 and 2.
• DAC PLAY MODE
Command
DAC play mode
D7
D6
D5
D4
PLM3
PLM2
PLM1
PLM0
By controlling these command bits, the DAC outputs channel 1 and channel 2 can be output in 16 different
combinations of left channel, right channel, left + right channel, and mute.
The relationship between the commands and the outputs is shown on the table on the following page.
– 37 –
CXD2586R/-1
PLM3
PLM2
PLM1
PLM0
0
0
0
0
Mute
Mute
0
0
0
1
L
Mute
0
0
1
0
R
Mute
0
0
1
1
L+R
Mute
0
1
0
0
Mute
L
0
1
0
1
L
L
0
1
1
0
R
L
0
1
1
1
L+R
L
1
0
0
0
Mute
R
1
0
0
1
L
R
1
0
1
0
R
R
1
0
1
1
L+R
R
1
1
0
0
Mute
L+R
1
1
0
1
L
L+R
1
1
1
0
R
L+R
1
1
1
1
L+R
L+R
Channel 1 output Channel 2 output
Remarks
Mute
Reverse
Stereo
Mono
Note) For normal stereo, channel 1 is the left channel and channel 2 is the right channel.
The output data of L+R is (L+R)/2 to prevent overflow.
– 38 –
CXD2586R/-1
$AX commands
Data 1
Command
Audio CTRL
Data 2
D3
D2
D1
D0
D3
D2
D1
D0
0
0
Mute
ATT
PCT1
PCT2
DADS
SOC2
Command bit
Command bit
Meaning
Mute = 0
Mute off if other mute
conditions are not set.
Mute = 1
Mute on. Peak register
reset.
Meaning
ATT = 0
Attenuation off
ATT = 1
–12dB
Mute conditions
(1) When register A mute = 1.
(2) When Mute pin = 1.
(3) When register 8 D.out Mute F = 1 and the Digital Out is on (MD2 pin =1).
(4) When GFS stays low for over 35ms (during normal-speed).
(5) When register 9 BiliGL MAIN = Sub =1.
(6) When register A PCT1 = 1 and PCT2 = 0.
(1) to (4) perform zero-cross muting with a 1 ms time limit.
Command bit
Meaning
PCM Gain
ECC error
correction ability
PCT1
PCT2
0
0
Normal mode
× 0dB
C1: double; C2: quadruple
0
1
Level meter mode
× 0dB
C1: double; C2: quadruple
1
0
Peak meter mode
Mute
C1: double; C2: double
1
1
Normal mode
× 0dB
C1: double; C2: double
Description of level meter mode (See the Timing Chart 1-4.)
• When the LSI is set to this mode, it performs digital level meter functions.
• When the 96-bit clock is input to SQCK, 96 bits of data are output to SQSO.
The initial 80 bits are Sub Q data. (See §2. Subcode Interface.) The last 16 bits are LSB first, which are 15-bit
PCM data (absolute values) and L/R flag.
L/R flag is high when the 15-bit PCM data is from the left channel and low from the right channel.
• PCM data is reset zero and the L/R flag is reversed after one readout.
Then level measuring continues until the next readout.
– 39 –
CXD2586R/-1
Description of peak meter mode (See the Timing Chart 1-5.)
• When the LSI is set to this mode, the maximum PCM data value is detected regardless of if it comes from the
left or right channel.
The 96-bit clock must be input to SQCK to read out this data.
• When the 96-bit clock is input, 96 bits of data are output to SQSO and the LSI internal register is set the
value again.
In other words, the PCM maximum value detection register is not reset to zero by the readout.
• To reset the PCM maximum value register to zero, set PCT1 = PCT2 = 0 or set the $AX mute.
• The Sub Q absolute time is automatically controlled in this mode.
In other words, after the maximum value is generated, the absolute time for CRC to become OK is retained in
the memory. Normal operation is conducted for the relative time.
• The final bit (L/R flag) of the 96-bit data is normally 0.
• The pre-value hold and average value interpolation data are fixed to level (– ∞) in this mode.
Command bit
Processing
DADS = 0
Set to 0 when crystal = 33.8688MHz.
DADS = 1
Set to 1 when crystal = 16.9344MHz.
Command bit
Processing
SOC2 = 0
The SENS signal is output from the
SENS pin as usual.
SOC2 = 1
The SQSO pin signal is output from
the SENS pin.
SENS output switching
• This enables the SQSO pin signal to be output from the SENS pin.
When SOC2 = 0, SENS output is performed as usual.
When SOC2 = 1, the SQSO pin signal is output from the SENS pin.
At this time, the readout clock is input to the SCLK pin.
Note) SOC2 should be switched when SQCK = SCLK = high.
– 40 –
CXD2586R/-1
• DAC digital attenuator
Command
Data 3
D3
D2
D1
Data 4
D0
D3
D2
D1
Data 5
D0
D3
D2
D1
Data 6
D0
D3
D2
D1
D0
Audio
AT1D7 AT1D6 AT1D5 AT1D4 AT1D3 AT1D2 AT1D1 AT1D0 AT2D7 AT2D6 AT2D5 AT2D4 AT2D3 AT2D2 AT2D1 AT2D0
Ctrl
Note) AT1D7 to AT1D0 are the channel 1 ATT control bits.
AT2D7 to AT2D0 are the channel 2 ATT control bits.
Command bits
AT1D7 to AT1D0
(AT2D7 to AT2D0)
Audio output
FF (H)
0dB
FE (H)
↓
01 (H)
–0.034dB
↓
–48.131dB
00 (H)
–∞
The attenuation data consists of 8 bits each for channels 1
and 2; the DAC ATT bit can be used to control channels 1
and 2 with common attenuation data. (When common
attenuation data is specified, the attenuation values for
channel 1 is used.)
An attenuation value, from 00(H) to FF(H), is determined
according to the following expression:
ATT = 20 log [input data/255] dB
Example: When the attenuation data is FA(H):
ATT = 20 log [250/255] dB = –0.172dB
• Soft mute
With the soft mute function, when the attenuation data goes from FF(H) to 00(H) and vice versa, muting is
turned on and off over the muting time of 1024fs [s] = 23.2 [ms] (Fs = 44.1kHz).
• Attenuation
Assume the attenuation data ATT1, ATT2, and ATT3, where ATT1 > ATT3 > ATT2. First, assume ATT1 is
transferred and then ATT2 is transferred. If ATT2 is transferred before ATT1 is reached (state "A" in the
diagram), then the value continues approaching ATT2. Next, if ATT3 is transferred before ATT2 is reached
(state "B" or "C" in the diagram), the attenuation begins approaching ATT3 from the current point. Note that it
takes 1024/Fs [s] (Fs = 44.1kHz for CD players) to transit between attenuation data (from 0dB to – ∞).
0dB
A
ATT1
B
ATT3
C
ATT2
Handling of the Attenuation Value
– 41 –
CXD2586R/-1
• I/O sync circuit
Related pins: LRCK and XWO
During normal operation, the I/O sync circuit automatically synchronizes with the input LRCK, and its operation
proceeds in phase with the serial input data. However, there is a chance that synchronization will not be
performed if there is a great deal of jitter in LRCK, if the power has just been turned on, etc. In this case, forced
synchronization is possible by setting XWO low for 2/Fs or more. The forced synchronization operation is
performed at the second rising edge of LRCK after the XWO pin is set low.
$BX commands
This command sets the traverse monitor count.
Command
Traverse monitor count
setting
Data 1
Data 2
Data 3
Data 4
D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4
215 214 213 212 211 210
29
28
27
26
25
24
23
22
21
20
• When the set number of tracks are counted during fine search, the sled control for the traverse cycle control
goes off.
• The traverse monitor count is set to monitor the traverse status from the SENS output as COMP and COUT.
– 42 –
CXD2586R/-1
$CX commands
Data 1
Command
D3
Servo coefficient
setting
D1
D2
Data 2
D0
D3
D2
Gain Gain Gain Gain Gain Gain
MDP1 MDP0 MDS1 MDS0 DCLV1 DCLV0
D1
D0
0
0
Valid only when DCLV = 1.
Gain
CLVS
CLV CTRL ($DX)
Explanation
Valid when DCLV = 1 or 0.
The spindle servo gain is externally set when DCLV = 1.
• CLVS mode gain setting: GCLVS
Gain
MDS1
Gain
MDS0
Gain
CLVS
GCLVS
0
0
0
–12dB
0
0
1
–6dB
0
1
0
–6dB
0
1
1
0dB
1
0
0
0dB
1
0
1
+6dB
Note) When DCLV = 0, the CLVS gain is as follows.
When Gain CLVS = 0, GCLVS = –12dB.
When Gain CLVS = 1, GCLVS = 0dB.
• CLVP mode gain setting: GMDP, GMDS
Gain
MDP1
Gain
MDP0
GMDP
Gain
MDS1
Gain
MDS0
GMDS
0
0
–6dB
0
0
–6dB
0
1
0dB
0
1
0dB
1
0
+6dB
1
0
+6dB
• DCLV overall gain setting: GDCLV
Gain
DCLV1
Gain
DCLV0
GDCLV
0
0
0dB
0
1
+6dB
1
0
+12dB
– 43 –
CXD2586R/-1
$DX commands
Data 1
Command
CLV CTRL
Data 2
Data 3
D3
D2
D1
D0
D3
D2
D1
D0
D3
D2
D1
D0
DCLV
PWM MD
TB
TP
Gain
CLVS
VP7
VP6
VP5
VP4
VP3
VP2
VP1
VP0
See the $CX commands.
Command bit
Explanation
DCLV PWM MD = 1
Digital CLV PWM mode specified. Both MDS and MDP are used.
CLV-W and CAV-W modes can not be used.
DCLV PWM MD = 0
Digital CLV PWM mode specified. Ternary MDP values are output.
CLV-W and CAV-W modes can be used.
Command bit
Explanation
TB = 0
Bottom hold at a cycle of RFCK/32 in CLVS and CLVH modes.
TB = 1
Bottom hold at a cycle of RFCK/16 in CLVS and CLVH modes.
TP = 0
Peak hold at a cycle of RFCK/4 in CLVS mode.
TP = 1
Peak hold at a cycle of RFCK/2 in CLVS mode.
• For the CXD2586R
Command bit
Description
VP0 to 7 = F0 (H)
Playback at half (normal) speed
:
to
VP0 to 7 = E0 (H)
Playback at normal (double) speed
:
to
VP0 to 7 = C0 (H)
Playback at double (quadruple) speed
:
to
VP0 to 7 = A0 (H)
Playback at (sextuple) speed
The rotational velocity R of the spindle can
be expressed with the following equation.
R=
256 – n
32
R: Relative velocity at normal speed = 1
n: VP0 to 7 setting value
Note)
1. Values when MCLK is 16.9344MHz and XTSL is low or when MCLK is 33.8688MHz and XTSL is high.
2. Values in parentheses are for when DSPB is 1.
6
R — Relative velocity [times]
5
4
3
DSPB = 1
2
DSPB = 0
1
F0
E0
D0
VP0 to 7 setting value [HEX]
– 44 –
C0
B0
A0
CXD2586R/-1
• For the CXD2586R-1
Command bit
Description
VP0 to 7 = F0 (H)
Playback at half (normal) speed
:
to
VP0 to 7 = E0 (H)
Playback at normal (double) speed
:
to
VP0 to 7 = C0 (H)
Playback at double (quadruple) speed
:
to
VP0 to 7 = A0 (H)
Playback at triple (sextuple) speed
:
to
VP0 to 7 = 80 (H)
Playback at (octuple) speed
Note)
1. Values when MCLK is 16.9344MHz and XTSL is low or when MCLK is 33.8688MHz and XTSL is high.
2. Values in parentheses are for when DSPB is 1.
8
7
R — Relative velocity [times]
6
5
4
3
DSPB = 1
2
DSPB = 0
1
F0
E0
D0
C0
VP0 to 7 setting value [HEX]
– 45 –
B0
A0
90
80
CXD2586R/-1
$EX commands
Data 1
Command
SPD mode
Data 2
D3
D2
D1
D0
CM3
CM2
CM1
D3
D2
Data 3
D1
D0
CM0 EPWM SPDC ICAP
Command bit
Mode
D3
SFSL VC2C
D2
D1
D0
HIFC LPWR VPON
Explanation
CM3
CM2
CM1
CM0
0
0
0
0
STOP
Spindle stop mode.∗
1
0
0
0
KICK
Spindle forward rotation mode.∗
1
0
1
0
BRAKE
Spindle reverse rotation mode. Valid only when LPWR=0,
in any modes.∗
1
1
1
0
CLVS
Rough servo mode. When the RF-PLL circuit isn't locked,
this mode is used to pull the disc rotations within the RFPLL capture range.
1
1
1
1
CLVP
PLL servo mode.
0
1
1
0
CLVA
Automatic CLVS/CLVP switching mode.
Used for normal playback.
∗ See the Timing Charts 1-6 to 1-12.
Command bit
EPWM SPDC
Mode
ICAP
SFSL
VC2C
HIFC
LPWR VPON
Explanation
0
0
0
0
0
0
0
0
CLV-N
Crystal reference CLV servo.
0
0
0
0
1
1
0
0
CLV-W
Used for playback in CLV-W
mode.∗
0
1
1
0
0
1
0
1
CAV-W
Spindle control with VP0 to 7.
1
0
1
0
0
1
0
1
CAV-W
Spindle control with the external
PWM.
∗ Figs. 3-1 and 3-2 show the control flow with the microcomputer software in CLV-W mode.
– 46 –
CXD2586R/-1
Mode
DCLV
0
CLV-N
DCLV PWM MD
0
0
LPWR
0
0
1
1
0
0
CLV-W
1
0
1
0
CAV-W
1
0
1
Mode
DCLV
CLV-N
1
CLV-W
1
CAV-W
1
Command
Timing chart
KICK
1-6 (a)
BRAKE
1-6 (b)
STOP
1-6 (c)
KICK
1-7 (a)
BRAKE
1-7 (b)
STOP
1-7 (c)
KICK
1-8 (a)
BRAKE
1-8 (b)
STOP
1-8 (c)
KICK
1-9 (a)
BRAKE
1-9 (b)
STOP
1-9 (c)
KICK
1-10 (a)
BRAKE
1-10 (b)
STOP
1-10 (c)
KICK
1-11 (a)
BRAKE
1-11 (b)
STOP
1-11 (c)
KICK
1-12 (a)
BRAKE
1-12 (b)
STOP
1-12 (c)
DCLV PWM MD
LPWR
Timing chart
0
0
1-13
1
0
1-14
0
1-15
1
1-16
0
1-17 (CAV = 0)
1
1-18 (CAV = 0)
0
1-19 (CAV = 1)
1
1-20 (CAV = 1)
0
0
Note) The CLV-W and CAV-W modes support control only by the ternary output of the MDP pin.
Therefore, set DCLV to 1 and DCLV PWM MD to 0 in CLV-W and CAV-W modes.
– 47 –
CXD2586R/-1
Data 4
Command
SPD mode
D3
D2
D1
D0
Gain
CAV1
Gain
CAV0
FCSW
0
Gain
CAV1
Gain
CAV0
0
0
0dB
0
1
–6dB
1
0
–12dB
1
1
–18dB
Gain
• This sets the gain when controlling the spindle with the phase
comparator in CAV-W mode.
Command bit
Processing
FCSW = 0
The VPCO2 pin is not used and it is Hi-Z.
FCSW = 1
The VPCO2 pin is used and the pin signal is the same as VPCO1.
– 48 –
– 49 –
C2PO
CDROM=1
C2PO
CDROM = 0
WDCK
LRCK
Timing Chart 1-3
C2 Pointer for lower 8bits
Rch C2 Pointer
C2 Pointer for upper 8bits
Rch 16bit C2 Pointer
C2 Pointer for lower 8bits
Lch C2 Pointer
C2 Pointer for upper 8bits
Lch 16bit C2 Pointer
If C2 Pointer = 1,
data is NG
48 bit slot
CXD2586R/-1
– 50 –
SQSO
SQCK
WFCK
SQSO CRCF
SQCK
Timing Chart 1-4
2
L/R
2
3
Sub Q Data
See "Sub Code Interface"
3
96 bit data
Hold section
1
96 clock pulses
1
D0
CRCF
81
D1
D2
1
Level Meter Timing
16 bit
96 clock pulses
Peak data of this section
80
D4
D5
D6
R/L
2
3
CRCF
15-bit peak-data
Absolute value display, LSB first
D3
750ns to 120µs
D13
D14
L/R
Peak data
L/R flag
96
CXD2586R/-1
SQCK
WFCK
– 51 –
96 clock pulses
Measurement
CRCF
Timing Chart 1-5
1
2
3
Peak Meter Timing
Measurement
CRCF
96 clock pulses
1
2
3
Measurement
CRCF
CXD2586R/-1
CXD2586R/-1
Timing Chart 1-6
CLV-N mode DCLV = DCLV PWM MD = LPWR = 0
KICK
Z
MDS
H
MDP
FSW
L
H
MON
BRAKE
MDS
Z
MDP
L
FSW
L
H
MON
(a) KICK
STOP
MDS
MDP
FSW
MON
(b) BRAKE
Z
L
L
L
(c) STOP
Timing Chart 1-7
CLV-N mode DCLV = 1, DCLV PWM MD = LPWR = 0
KICK
Z
MDS
MDP
FSW
MON
BRAKE
Z
MDS
STOP
MDS
Z
MDP
Z
Z
H
MDP
Z
L
H
(a) KICK
L
FSW
L
H
MON
(b) BRAKE
– 52 –
FSW
MON
L
L
(c) STOP
CXD2586R/-1
Timing Chart 1-8
CLV-N mode DCLV = DCLV PWM MD = 1, LPWR = 0
KICK
H
MDS
MDP
H
BRAKE
MDS
MDP
L
H
L
FSW
MDS
MDP
L
L
L
H
MON
STOP
FSW
L
H
MON
(a) KICK
FSW
MON
L
L
(c) STOP
(b) BRAKE
Timing Chart 1-9
CLV-W mode (when following the spindle rotational velocity) DCLV = 1, DCLV PWM MD = LPWR = 0
KICK
Z
MDS
MDP
BRAKE
MON
MDS
Z
MDP
Z
Z
H
MDP
Z
FSW
Z
MDS
STOP
L
H
(a) KICK
Other than when following the velocity,
the timing is the same as Timing Chart 1-6 (a).
L
FSW
L
H
MON
(b) BRAKE
Other than when following the velocity,
the timing is the same as Timing Chart 1-6 (b).
– 53 –
FSW
MON
L
L
(c) STOP
CXD2586R/-1
Timing Chart 1-10
CLV-W mode (when following the spindle rotational velocity) DCLV = 1, DCLV PWM MD = 0, LPWR = 1
KICK
Z
MDS
MDP
FSW
MON
H
Z
L
H
BRAKE
STOP
MDS
Z
MDS
Z
MDP
Z
MDP
Z
FSW
L
L
H
MON
(a) KICK
FSW
MON
(b) BRAKE
L
(c) STOP
Other than when following the velocity,
the timing is the same as Timing Chart 1-6 (a).
Timing Chart 1-11
CAV-W mode DCLV = 1, DCLV PWM MD = LPWR = 0
KICK
MDS
MDP
FSW
MON
Z
H
L
H
(a) KICK
BRAKE
Z
MDS
MDP
L
FSW
L
H
MON
(b) BRAKE
– 54 –
STOP
MDS
Z
MDP
Z
FSW
MON
L
H
(c) STOP
CXD2586R/-1
Timing Chart 1-12
CAV-W mode DCLV = 1, DCLV PWM MD = 0, LPWR = 1
KICK
Z
MDS
H
MDP
FSW
L
H
MON
BRAKE
STOP
MDS
Z
MDS
Z
MDP
Z
MDP
Z
FSW
L
FSW
L
H
MON
H
MON
(a) KICK
(c) STOP
(b) BRAKE
Timing Chart 1-13
CLV-N mode DCLV PWM MD = LPWR = 0
MDS
Z
n • 236 (ns) n = 0 to 31
Acceleration
MDP
Z
132kHz
Deceleration
7.6µs
Timing Chart 1-14
CLV-N mode DCLV PWM MD = 1, LPWR = 0
MDS
Acceleration
Deceleration
MDP
132kHz
n • 236 (ns) n = 0 to 31
7.6µs
Output Waveforms with DCLV = 1
– 55 –
CXD2586R/-1
Timing Chart 1-15
CLV-W mode DCLV PWM MD = LPWR = 0
MDS
Z
Acceleration
MDP
Z
264kHz
3.8µs
Deceleration
Output Waveforms with DCLV = 1
Timing Chart 1-16
CLV-W mode DCLV PWM MD = 0, LPWR = 1
Z
MDS
Acceleration
MDP
Z
264kHz
3.8µs
Output Waveforms with DCLV = 1
The BRAKE pulse is masked when LPWR = 1.
Timing Chart 1-17
CAV-W mode EPWM = DCLV PWM MD = LPWR = 0
Acceleration
MDP
Z
264kHz
Deceleration
3.8µs
Timing Chart 1-18
CAV-W mode EPWM = 1, DCLV PWM MD = 0, LPWR = 1
Acceleration
MDP
Z
264kHz
3.8µs
The BRAKE pulse is masked when LPWR = 1.
– 56 –
CXD2586R/-1
Timing Chart 1-19
CAV-W mode EPWM = 1, DCLV PWM MD = LPWR = 0
H
PWMI
L
Acceleration
H
MDP
L
Deceleration
Timing Chart 1-20
CAV-W mode EPWM = 1, DCLV PWM MD = 0, LPWR = 1
H
PWMI
L
Acceleration
H
MDP
Z
The BRAKE pulse is masked when LPWR = 1.
Note) The CLV-W and CAV-W modes support control only by the ternary output of the MDP pin. Therefore,
set DCLV PWM MD to 0 in CLV-W and CAV-W modes.
– 57 –
CXD2586R/-1
§2. Subcode Interface
There are two methods for reading out a subcode externally. The 8-bit subcodes P to W can be read from
SBSO by inputting EXCK.
Sub Q can be read out after checking CRC of the 80 bits in the subcode frame.
Sub Q can be read out from the SQSO pin by inputting 80 clock pulses to SQCK pin when SCOR comes
correctly and CRCF is high.
§2-1. P to W Subcode Readout
Data can be read out by inputting EXCK immediately after WFCK falls. (See the Timing Chart 2-1.)
§2-2. 80-bit Sub Q Readout
Fig. 2-2 shows the peripheral block of the 80-bit Sub Q register.
• First, Sub Q, regenerated at one bit per frame, is input to the 80-bit serial/parallel register and the CRC check
circuit.
• 96-bit Sub Q has been inputted, and if the CRC is OK, it is output to SQSO with CRCF = 1. In addition, the
80 bits are loaded into the parallel/serial register.
When SQSO goes high after SCOR is output, the CPU determines that new data (which passed the CRC
check) has been loaded.
• In the CXD2586R/-1, when 80-bit data is loaded, the order of the MSB and LSB is inverted within each byte.
As a result, although the sequence of the bytes is the same, the bits within the bytes are now ordered LSB
first.
• Once the 80-bit data load is confirmed, SQCK is input so that the data can be read. The SQSO input is
detected, and the retriggerable monostable multivibrator for low is reset.
• The retriggerable monostable multivibrator has a time constant from 270 to 400µs. When the duration when
SQCK is high is less than this time constant, the monostable multivibrator is kept reset; during this interval,
the S/P register is not loaded into the P/S register.
• While the monostable multivibrator is being reset, data cannot be loaded in the peak detection parallel/serial
register or the 80-bit parallel/serial register.
In other words, while reading out with a clock cycle shorter than this time constant, the register will not be
rewritten by CRCOK and others.
• In this LSI, the previously mentioned peak detection register can be connected to the shift-in of the 80-bit P/S
register.
Input for ring control 1 is connected to the output of it in peak meter or level meter mode.
Same goes for ring 2 in peak meter mode.
This is because the register is reset with each readout in level meter mode, and to prevent readout
destruction in peak meter mode.
As a result , the 96-bit clock must be input in peak meter mode.
• The absolute time after peak is stored in the memory in peak meter mode. (See the Timing Chart 2-3.)
• The high and low intervals for SQCK should be between 750ns and 120µs.
– 58 –
CXD2586R/-1
Timing Chart 2-1
Internal
PLL clock
4.3218 ± ∆MHz
WFCK
SCOR
EXCK
750ns max
S0 • S1
SBSO
Q
R
WFCK
SCOR
EXCK
SBSO
S0•S1 Q R S T U V W S0•S1
Same
P1
Q R S T
U V W
P1
Same
Subcode P.Q.R.S.T.U.V.W Read Timing
– 59 –
P2
P3
SUBQ
Block Diagram 2-2
SI
8
(ASEC)
LD
Order
Inversion
8
(AMIN)
LD
SUBQ
LD
– 60 –
LD
LD
Peak detection
16
16 bit P/S register
Monostable
multivibrator
8
SI
8
8
Ring control 2
SHIFT
8
LD
SO
LOAD CONTROL
CRCC
80 bit P/S Register
8
80 bit S/P Register
SHIFT
8
CRCF
Mix
8
ADDRS CTRL
LD
Ring control 1
ABS time load control
for peak value
H G F E D C B A
A B C D E F G H
SIN
(AFRAM)
SQCK
SO
SQSO
CXD2586R/-1
LD
– 61 –
SQSO
SQCK
SQCK
SQSO
SCOR
WFCK
Timing Chart 2-3
CRCF
Monostable
Multivibrator
(Internal)
CRCF1
1
2
3
2
1
ADR1
ADR2
ADR3
CTL0
270 to 400µs when SQCK = high.
Register load forbidder
CRCF1
94
Determined by mode
93
92
91
80 or 96 Clock
750ns to 120µs
300ns max
ADR0
3
95
CTL1
96
CTL2
97
CTL3
CRCF2
98
CXD2586R/-1
SQSO
SQCK
XLAT
PER2
PER3
PER4
PER5
PER6
PER7
C1F0
C1F1
C1F2
C2F0
C2F1
FOK
GFS
Explanation
C2F2
LOCK
EMPH
ALOCK
VF0
– 62 –
C1F1
0
0
1
1
0
0
1
1
0
0
0
0
1
1
1
1
1
0
1
0
1
0
1
0
C1F0
; C1 pointer reset
; C1 pointer set
C1 correction impossible ; C1 pointer set
Two C1 errors corrected ; C1 pointer set
One C1 error corrected ; C1 pointer set
No C1 errors
—
—
One C1 error corrected ; C1 pointer reset
No C1 errors
Description
C2F1
0
0
1
1
0
0
1
1
C2F2
0
0
0
0
1
1
1
1
1
0
1
0
1
0
1
0
C2F0
; C2 pointer reset
; C2 pointer reset
C2 correction impossible ; C2 pointer set
C2 correction impossible ; C1 pointer copy
Four C2 errors corrected ; C2 pointer reset
—
Three C2 errors corrected; C2 pointer reset
Two C2 errors corrected ; C2 pointer reset
One C2 error corrected
No C2 errors
Description
Used in CAV-W mode. The result obtained by measuring the rotational velocity of the disc. (See the Timing Chart 2-5.)
VF0 = LSB, VF7 = MSB.
VF0 to 7
C1F2
High when sampled value of GFS at 460Hz is high by 8 times successively.
Low when sampled value of GFS at 460Hz is low by 8 times successively.
ALOCK
VF7
High when the playback disc has emphasis.
VF6
EMPH
VF5
High when sampled value of GFS at 460Hz is high. Low when sampled value of GFS at 460Hz is low by 8 times successively.
VF4
LOCK
VF3
High when the frame sync and the insertion protection timing match.
VF2
GFS
VF1
Focus OK
RF jitter amount (used to adjust the focus bias). 8-bit binary data in PER0 = LSB, PER7 = MSB.
PER1
750ns or more
FOK
PER0 to 7
Signal
PER0
Internal signal latch
Set SQCK high during this interval.
Example: $8020 latch
Timing Chart 2-4
CXD2586R/-1
CXD2586R/-1
Timing Chart 2-5
Measurement interval (approximately 3.8µs)
Reference window
(132.2kHz)
Measurement pulse
(V16M/2)
Measurement counter
Load
m
VF0 to 7
The relative velocity of the disc can be obtained with the following equation.
R=
m+1
(R: Relative velocity, m: Measurement results)
32
VF0 to 7 is the result obtained by counting VCKI/2 pulses while the reference signal (132.2kHz) generated
from MCLK (384Fs) is high. This count is 31 when the disc is rotating at normal speed and 63 when it is
rotating at double speed (when DSPB is low).
– 63 –
CXD2586R/-1
§3. Description of Modes
This LSI has three basic operating modes using a combination of spindle control and the PLL. The operations
for each mode are described below.
§3-1. CLV-N Mode
This mode is compatible with the CXD2500 series, and operation is the same (however, variable pitch cannot
be used). The PLL capture range is ±150kHz.
§3-2. CLV-W Mode
This is the wide capture range mode. This mode allows PLL to follow the rotational velocity of the disc. This
rotational following control has two types: using the built-in VCO2 or providing an external VCO. The spindle is
the same CLV servo as for the CXD2500 series. Operation using the built-in VCO2 is described below. (When
using an external VCO, input the signal from the VPCO pin to the low-pass filter, use the output from the lowpass filter as the control voltage for the external VCO, and input the oscillation from the VCO to the VCKI pin.)
While starting to rotate a disc and/or speeding up to the lock range from the condition that a disc stops, CAV-W
mode should be used. Concretely saying, firstly send $E665X to set CAV-W mode and kick a disc, secondly
send $E60CX to set CLV-W mode if ALOCK is high, which can be read serially from SQSO pin. CLV-W mode
can be used while ALOCK is high. The microcomputer monitors the serial data output, and must return to
adjust speed operation (CAV-W mode) when ALOCK becomes low. The control flow according to the
microcomputer software in CLV-W mode is shown in Fig. 3-2.
In CLV-W mode (normal), low power consumption is achieved by setting LPWR to high. Control was formerly
performed by applying acceleration and deceleration pulses to the spindle motor. However, when LPWR is set
to high, deceleration pulses are not output, thereby achieving low power consumption mode.
CLV-W mode supports control only by the ternary output of the MDP pin. Therefore, when using CLV-W mode,
set DCLV PWM MD to low.
Note) The capture range for this mode is theoretically up to the signal processing limit.
§3-3. CAV-W Mode
This is the CAV mode. In this mode, it is possible to control spindle to variable rotational velocity, the external
crystal is fixed though. The rotational velocity is determined by the VP0 to 7 setting values or the external
PWM. When controlling the spindle with VP0 to 7, setting the CAV-W mode with $E665X command and
controlling VP0 to 7 with the $DX commands allows the rotational velocity to be varied from low speed to
sextuple-speed. (See $DX Commands.) Also, when controlling the spindle with the external PWM, the PWMI
pin is binary input which becomes KICK during high intervals and BRAKE during low intervals.
The microcomputer can know the rotational velocity using V16M. And the reference for the velocity
measurement is a signal of 132.2kHz obtained by 1/128 of MCLK (384Fs). The velocity is obtained by counting
V16M/2 pulses while the reference is high, and the result is output from the new CPU interface as 8 bits (VP0
to 7). These measurement results are 31 when the disc is rotating at normal speed or 127 when it is rotating at
quadruple speed. These values match those of the 256-n for control with VP0 to 7. (See Table 2-5 and Fig. 26.)
In CAV-W mode, the spindle is set to the desired rotational velocity and the operation speed for the entire
system follows this rotational velocity. Therefore, the cycles for the Fs system clock, PCM data and all other
output signals from this LSI change according to the rotational velocity of the disc.
Note) The capture range for this mode is theoretically up to the signal processing limit.
Note) Set FLFC to 1 for this mode.
– 64 –
CXD2586R/-1
CAV-W
CLV-W
Operation mode
Rotational velocity
CLVS
CLVP
Spindle mode
Target velocity
KICK
Time
LOCK
ALOCK
Fig. 3-1. Disc Stop to regular playback in CLV-W Mode
CLV-W Mode
CLV-W MODE
START
KICK
$E8000
Mute OFF $A00XXXX
CAV-W $E665X
(CLVA)
NO
ALOCK = H ?
YES
CAV-W $E6C00
(CLVA)
(WFCK PLL)
YES
ALOCK = L ?
NO
Fig. 3-2. CLV-W Mode Flow Chart
– 65 –
CXD2586R/-1
§4. Description of Other Functions
§4-1. Channel Clock Regeneration by the Digital PLL Circuit
• The channel clock is needed to demodulate the EFM signal regenerated by the optical system.
Assuming T as the channel clock cycle, the EFM signal is modulated in an integer multiple of T from 3T to
11T. In order to read the information in the EFM signal, this integer value must be read correctly. As a result,
T, that is the channel clock, is necessary.
In an actual player, PLL is necessary to regenerate the channel clock because the fluctuation in the spindle
rotation alters the width of the EFM signal pulses.
Practically, PLL is necessary to regenerate the channel clock, because the EFM pulse width is altered by
spindle rotation fluctuation.
The block diagram of this PLL is shown in Fig. 4-1.
The CXD2586R/-1 has a built-in three-stage PLL.
• The first-stage PLL is for the wide-band PLL. When the built-in VCO2 is used, LPF is required externally.
When the built-in VCO2 is not used, LPF and VCO are required externally.
The output of this first-stage PLL is used as a reference for all clocks within the LSI.
• The second-stage PLL generates a high-frequency clock needed by the third-stage digital PLL.
• The third-stage PLL is a digital PLL that regenerates the actual channel clock.
• The digital PLL in CLV-N mode has a secondary loop, which is the primary loop (phases) and the secondary
loop (frequency). When FLFC = 1, the secondary loop can be turned off. High-frequency components such
as 3T and 4T may contain deviations. In such a case, turning the secondary loop off yields better playability.
However, in this case the capture range becomes ±50kHz.
• The new digital PLL in CLV-W mode follows the rotational velocity of the disc, in addition to the abovementioned secondary loop.
– 66 –
CXD2586R/-1
Block Diagram 4-1
CLV-W
CAV-W
Selector
Spindle rotation information
VPCO1 to 2
CLV-W
CAV-W /CLV-N
LPF
Clock input
1/32
MCLK
XTSL
1/2
1/n
Microcomputer
control
n = 1 to 256
(VP7 to 0)
1/K
(KSL1, 0)
Phase comparator
1/2
CLV-N
VCOSEL2
VCTL
VCO2
V16M
VCKI
VPON
1/M
1/N
Phase comparator
2/1 MUX
PCO
FILI
FILO
1/K
(KSL3, 2)
CLTV
VCO1
VCOSEL1
Digital PLL
RFPLL
CXD2586
– 67 –
CXD2586R/-1
§4-2. Frame Sync Protection
• In normal speed playback, a frame sync is recorded approximately every 136µs (7.35kHz). This signal is
used as a reference to recognize the data within a frame. Conversely, if the frame sync cannot be
recognized, the data is processed as error data because the data cannot be recognized. As a result,
recognizing the frame sync properly is extremely important for improving playability.
• In the CXD2586R/-1, window protection and forward protection/backward protection have been adopted for
frame sync protection. These functions achieve very powerful frame sync protection. There are two window
widths: one for cases where a rotational disturbance affects the player and the other for cases where there is
no rotational disturbance (WSEL = 0/1). In addition, the forward protection counter is fixed to 13, and the
backward protection counter to 3. Concretely, when the frame sync has been played back normally and then
cannot be detected due to scratches, a maximum of 13 frames are inserted. If frame sync cannot be detected
for 13 frames or more, the window is released and try to resyncronize the frame sync.
In addition, immediately after the window is released and the resynchronization is executed, if a proper frame
sync cannot be detected within 3 frames, the window is released immediately.
§4-3. Error Correction
• In the CD format, one 8-bit data contains two error correction codes, C1 and C2. For C1 correction, the code
is created with 28-byte information and 4-byte C1 parity.
For C2 correction, the code is created with 24-byte information and 4-byte parity.
Both C1 and C2 are Reed Solomon codes with a minimum distance of 5.
• The CXD2586R/-1 uses refined super strategy to achieve double correction for C1 and quadruple correction
for C2.
• In addition, to prevent C2 miscorrection, a C1 pointer is attached to data after C1 correction according to the
C1 error status, the playback status of the EFM signal, and the operating status of the player.
• The correction status can be monitored externally.
See the Table 4-2.
• When the C2 pointer is high, the data in question was uncorrectable. Either the pre-value was held or an
average value interpolation was made for the data.
MNT3
MNT2
MNT1
MNT0
0
0
0
0
No C1 errors
; C1 pointer reset
0
0
0
1
One C1 error corrected
; C1 pointer reset
0
0
1
0
—
0
0
1
1
—
0
1
0
0
No C1 errors
; C1 pointer set
0
1
0
1
One C1 error corrected
; C1 pointer set
0
1
1
0
Two C1 errors corrected
; C1 pointer set
0
1
1
1
C1 correction impossible
; C1 pointer set
1
0
0
0
No C2 errors
; C2 pointer reset
1
0
0
1
One C2 error corrected
; C2 pointer reset
1
0
1
0
Two C2 errors corrected
; C2 pointer reset
1
0
1
1
Three C2 errors corrected ; C2 pointer reset
1
1
0
0
Four C2 errors corrected
1
1
0
1
1
1
1
0
C2 correction impossible
; C1 pointer copy
1
1
1
1
C2 correction impossible
; C2 pointer set
Description
; C2 pointer reset
—
Table 4-2.
– 68 –
CXD2586R/-1
Timing Chart 4-3
Normal-speed PB
400 to 500ns
RFCK
t = Dependent on error
condition
MNT3
C1 correction
C2 correction
MNT2
MNT1
MNT0
Strobe
Strobe
§4-4. DA Interface
• The CXD2586R/-1 has two modes as DA interfaces.
a) 48-bit slot interface
This interface includes 48 cycles of the bit clock within one LRCK cycle, and is MSB first.
When LRCK is high, the data is for the left channel.
b) 64-bit slot interface
This interface includes 64 cycles of the bit clock within one LRCK cycle, and is LSB first.
When LRCK is low, the data is for the left channel.
– 69 –
R0
1
2
– 70 –
DA16
WDCK
DA15
(4.23M)
LRCK
(88.2K)
R0
1 2
3
4
5
Lch MSB (15)
Lch MSB (15)
48bit slot Double-Speed Playback
DA16
WDCK
DA15
(2.12M)
LRCK
(44.1K)
48bit slot Normal-Speed Playback PSSL = L
Timing Chart 4-4
6
7
8
9
L14
10
L13
11
L12
12
L0
24
L11
L9
Rch MSB
L10
L8
L7
L6
L5
L4
L3
L2
L1
L0
24
RMSB
CXD2586R/-1
– 71 –
DA14
1
2
3
4
5
L15
1
2
3
4
5
64 Bit slot Double- Speed PB
DA13
(5.64M)
DA12
(88.2K)
DA14
DA13
(2.82M)
DA12
(44.1K)
64 Bit slot Normal Speed PB PSSL = L
Timing Chart 4-5
6
9
10
10
R ch LSB (0)
8
R ch LSB (0)
7
11
12
15
13
14
15
1
2
3
20
4
1
5
2
6
3
20
7
8
25
4
9
5
7
9
10
30 31 32
8
10 11 12 13 14 15
6
11
13
L ch LSB
12
30
32
14 R15 L ch LSB (0)
31
CXD2586R/-1
CXD2586R/-1
§4-5. Digital Out
There are three digital output formats: the type 1 format for broadcasting stations, the type 2 form 1 format for
home use, and the type 2 form 2 format for the manufacture of software.
The CDX2586R/-1 supports type 2 form 1.
In addition, regarding the clock accuracy of the channel status, level II is set for crystal clock use and level III
for CAV-W mode. In addition, Sub Q data which are matched twice in succession after a CRC check are input
to the first four bits (bits 0 to 3).
DOUT is output when the crystal is 34MHz and DSPB is set to 1 with XTSL high in CLV-N or CLV-W mode.
Therefore, set MD2 to 0 and turn DOUT off.
Digital Out C bit
0
2
3
From sub Q
0
ID0
16
1
0
4
5
6
7
8
9
10
11
12
13
14
15
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0/1
0
0
ID1 COPY Emph
0
0
0
32
48
0
176
bit0 to 3
Sub Q control bits that matched twice with CRCOK
bit29
VPON: 1
Crystal: 0
Table 4-6.
– 72 –
CXD2586R/-1
§4-6. Servo Auto Sequence
This function performs a series of controls, including auto focus and track jumps. When the auto sequence
command is received from the CPU, auto focus, 1 track jump, 2N track jumps, fine search, and M track move
are executed automatically.
Servo is used in an exclusive manner during the auto sequence execution (when XBUSY = low), so that
commands from the CPU are not transferred to the servo, but can be sent to the CXD2586R/-1.
In addition, when using the auto sequence, turn the A.SEQ of register 9 on.
When CLOK goes from low to high while XBUSY is low, XBUSY does not become high for a maximum of
100µs after that point. This is to prevent the transfer of erroneous data to the servo when XBUSY changes
from low to high by the monostable multivibrator, which is reset by CLOK being low (when XBUSY is low).
In addition, a MAX timer is built in this LSI as a countermeasure against abnormal operation due to external
disturbances, etc. When the auto sequence command is sent from the CPU, this command assumes a $4XY
format, in which X specifies the command and Y sets the MAX timer value and timer range. If the executed
auto sequence command does not terminate within the set timer value, the auto sequence is interrupted (like
$40). See §1, $4X commands concerning the timer value and range. Also, the MAX timer is invalidated by
inputting $4X0.
Although this command is explained in the format of $4X in the following command descriptions, the timer
value and timer range are actually sent together from the CPU.
(a) Auto focus ($47)
Focus search-up is performed, FOK and FZC are checked, and the focus servo is turned on.
If $47 is received from the CPU, the focus servo is turned on according to Fig. 4-8. The auto focus starts with
focus search-up, and note that the pickup should be lowered beforehand (focus search down). In addition,
blind E of register 5 is used to eliminate FZC chattering. Concretely, the focus servo is turned on at the falling
edge of FZC after FZC has been continuously high for a longer time than E.
(b) Track jump
1, 10, and 2N-track jumps are performed respectively. Always use this when focus, tracking and sled servo
are on. Note that tracking gain-up and braking-on ($17) should be sent beforehand because they are not
involved in this sequence.
• 1-track jump
When $48 ($49 for REV) is received from the CPU, a FWD (REV) 1-track jump is performed in accordance
with Fig. 4-9. Set blind A and brake B with register 5.
• 10-track jump
When $4A ($4B for REV) is received from the CPU, a FWD (REV) 10-track jump is performed in
accordance with Fig. 4-10. The principal difference from the 1-track jump is to kick the sled. In addition,
after kicking the actuator, when 5 tracks have been counted through COUT, the brake is applied to the
actuator. Then, when the actuator speed is found to have slowed up enough (determined by the COUT
cycle becoming longer than the overflow C set in register 5), the tracking and sled servos are turned on.
– 73 –
CXD2586R/-1
• 2N-track jump
When $4C ($4D for REV) is received from the CPU, a FWD (REV) 2N-track jump is performed in
accordance with Fig. 4-11. The track jump count "N" is set in register 7. Although N can be set to 216 tracks,
note that the setting is actually limited by the actuator. COUT is used for counting the number of jumps
when N is less than 16, and MIRR is used when N is 16 or more.
Although the 2N-track jump basically follows the same sequence as the 10-track jump, the one difference is
that after the tracking servo is turned on, the sled continues to move only for "D", set in register 6.
• Fine search
When $44 ($45 for REV) is received from the CPU, a FWD (REV) fine search (N-track jump) is performed
in accordance with Fig. 4-12. The differences from a 2N-track jump are a higher precision jump achieved by
controlling the traverse speed and a longer distance jump achieved by controlling the sled. The track jump
count is set in register 7. N can be set to 216 tracks. After kicking the actuator and sled, the traverse speed
is controlled based on the overflow G. Set kick D and F in register 6 and overflow G in register 5. Also, sled
speed control during traverse can be turned off by causing COMP to fall. Set the number of tracks during
which COMP falls in register B. After N tracks have been counted through COUT, the brake is applied to
the actuator and sled. (This is performed by turning on the tracking servo for the actuator, and by kicking
the sled in the opposite direction during the time for kick D set in register 6.) Then, the tracking and sled
servos are turned on. Set overflow G to the speed required to slow up just before the track jump terminates.
(The speed should be such that it will come on-track when the tracking servo turns on at the termination of
the track jump.) For example, set the target track count N-α for the traverse monitor counter which is set in
register B, and COMP will be monitored. When the falling edge of this COMP is detected, overflow G can
be reset.
• M track move
When $4E ($4F for REV) is received from the CPU, a FWD (REV) M track move is performed in
accordance with Fig. 4-13. M can be set to 216 tracks. COUT is used for counting the number of moves
when M is less than 16, and MIRR is used when M is 16 or more. The M track move is executed only by
moving the sled, and is therefore suited for moving across several thousand to several ten-thousand tracks.
In addition, the track and sled servo are turned off after M tracks have been counted through COUT or
MIRR unlike for the other jumps. Transfer $25 after the actuator is stabled.
– 74 –
CXD2586R/-1
Auto focus
Focus search up
FOK = H
NO
YES
FZC = H
NO
YES
FZC = L
Check whether FZC is
continuously high for the
period of time E set with
register 5.
NO
YES
Focus servo ON
END
Fig. 4-8 (a). Auto Focus Flow Chart
$47 Latch
XLAT
FOK
SEIN (FZC)
BUSY
Command
for SSP
Blind E
$03
Fig. 4-8 (b). Auto Focus Timing Chart
– 75 –
$08
CXD2586R/-1
1 Track
REV kick for REV
jump
Track kick
sled servo
WAIT
(Blind A)
COUT =
NO
YES
Track REV
kick
FWD kick for REV
jump
WAIT
(Brake B)
Track sled
servo ON
END
Fig. 4-9 (a). 1-Track Jump Flow Chart
$48 (REV = $49) Latch
XLAT
COUT
BUSY
Brake B
Blind A
Command
for SSP
$28 ($2C)
$2C ($28)
Fig. 4-9 (b). 1-Track Jump Timing Chart
– 76 –
$25
CXD2586R/-1
10 Track
Track, sled
FWD kick
WAIT
(Blind A)
(Counts CNIN × 5)
COUT = 5 ?
NO
YES
Track, REV
kick
Check whether the CNIN
cycle is longer than overflow C.
C = Over-flow ?
NO
YES
Track, sled
servo ON
END
Fig. 4-10 (a). 10-Track Jump Flow Chart
$4A (REV = $4B) Latch
XLAT
COUT
BUSY
Blind A
COUT 5 count
Over-flow C
Command
for SSP
$2E ($2B)
$2A ($2F)
Fig. 4-10 (b). 10-Track Jump Timing Chart
– 77 –
$25
CXD2586R/-1
2N Track
Track, sled
FWD kick
WAIT
(Blind A)
Counts COUT for the first 16 times
and MIRR for more times
COUT (MIRR) = N
NO
YES
Track REV
kick
C = Over-flow
NO
YES
Track servo
ON
WAIT
(Kick D)
Sled servo
ON
END
Fig. 4-11 (a). 2N-Track Jump Flow Chart
$4C (REV = $4D) Latch
XLAT
COUT
(MIRR)
BUSY
Blind A
Command
for SSP
$2A ($2F)
COUT (MIRR)
N count
Over-flow C
$2E ($2B)
$26 ($27)
Fig. 4-11 (b). 2N Track Jump Timing Chart
– 78 –
Kick D
$25
CXD2586R/-1
Fine Search
Track Servo ON
Sled FWD Kick
WAIT
(Kick D)
Track Sled
FWD Kick
WAIT
(Kick F)
Traverse
Speed Ctrl
(Over-flow G)
COUT = N ?
NO
YES
Track Servo ON
Sled REV Kick
WAIT
(Kick D)
Track Sled
Servo ON
END
Fig. 4-12 (a). Fine Search Flow Chart
$44 (REV = $45) latch
XLAT
COUT
BUSY
Kick D
$26 ($27)
Kick F
Traverse Speed Control (Overflow G)
&
COUT N count
$2A ($2F)
Kick D
$27 ($26)
$25
Fig. 4-12 (b). Fine Search Timing Chart
– 79 –
CXD2586R/-1
M Track Move
Track Servo OFF
Sled FWD Kick
WAIT
(Blind A)
Counts CNIN till M < 16.
Counts MIRR till M ≥ 16.
COUT (MIRR) = M
NO
YES
Track, Sled
Servo ON
END
Fig. 4-13 (a). M-Track Move Flow Chart
$4E (REV = $4F) Latch
XLAT
COUT
(MIRR)
BUSY
Blind A
Command
for servo
COUT (MIRR)
M count
$20
$22 ($23)
Fig. 4-13 (b). M-Track Move Timing Chart
– 80 –
CXD2586R/-1
§4-7. Digital CLV
Fig. 4-14 shows the block diagram. Digital CLV outputs MDS error and MDP error with PWM, sampling
frequency is 130Hz at most during normal-speed playback in CLVS, CLVP and other modes.
In addition, the digital spindle servo gain is variable.
Digital CLV
CLVS U/D
MDS Error
MDP Error
Measure
Measure
Over Sampling
Filter-1
2/1 MUX
CLV P/S
Gain
MDS
Gain
MDP
1/2
Mux
+
Gain
DCLV
CLV P/S
Over Sampling
Filter-2
Noise Shape
Modulation
KICK, BRAKE, STOP
PWMI
DCLVMD, LPWR
Mode Select
MDS
CLVS U/D:
MDS error:
MDP error:
PWMI:
MDP
Up/down signal from CLVS servo
Frequency error for CLVP servo
Phase error for CLVP servo
Spindle drive signal from the microcomputer
Fig. 4-14. Block Diagram
– 81 –
CXD2586R/-1
§4-8. Playback Speed
In the CXD2586R/-1, the following playback modes can be selected through different combinations of MCLK,
XTSL pin, double-speed command (DSPB), VCO1 selection command (VCOSEL1), VCO1 frequency dividing
command (KSL3, KSL2) and command transfer rate selector (ASHS) in CLV-N or CLV-W mode.
• For the CXD2586R/-1
Mode
MCLK
XTSL
DSPB
VCOSEL1∗1
ASHS
Playback speed
Error correction
1
1152Fs
1
0
0/1
1
× 1.5
C1: double; C2: quadruple
2
1152Fs
1
1
1
×3
C1: double; C2: double
3
1152Fs
0
0
1
1
∗2
×3
C1: double; C2: quadruple
4
1152Fs
0
1
1
∗2
×6
C1: double; C2: double
5
768Fs
1
0
0/1
0
×1
C1: double; C2: quadruple
6
768Fs
1
1
0/1
0
×2
C1: double; C2: double
7
768Fs
0
0
1
1
×2
C1: double; C2: quadruple
8
768Fs
0
1
1
1
×4
C1: double; C2: double
9
384Fs
0
0
0/1
0
×1
C1: double; C2: quadruple
10
384Fs
0
1
0/1
0
×2
C1: double; C2: double
11
384Fs
1
1
0/1
0
×1
C1: double; C2: double
∗1 Actually, use the optimal value by combining KSL3 with KSL2.
∗2 The built-in auto sequencer can not be used.
The playback speed can be varied by setting VP0 to 7 in CAV-W mode. See "§3. Description of Modes" for
details.
– 82 –
CXD2586R/-1
§4-9. DAC Block Playback Conditions
• The DAC block playback speed is controlled by sending the DADS command to the DSP block.
Mode
X'tal
DADS
1
768fs
0
2
384fs
1
§4-10. DAC Block Input Timing
The timing charts for input to the DAC are shown below.
In the CXD2586R/-1, audio data is not sent from the CD signal processor block to the DAC block inside the
LSI. The reason why is to allow data to be passed through an audio DSP, etc., on its way to the DAC block. To
input data to the DAC block without passing it through an audio DSP, etc., the data connection must be made
externally.
In this case, LRCK, BCK, and PCMD can be connected directly to LRCKI, BCKI, and PCMDI.
(See the Application Circuit.)
Normal-speed Playback
LRCKI
(44.1k)
1
2
3
4
5
6
7
8
9
10
11
12 13
14
15 16
17
18 19
20
21 22
23 24
BCKI
(2.12M)
PCMDI
Invalid
L15 L14 L13 L12 L11 L10
– 83 –
L9
L8
L7
L6
L5
L4
L3
L2
L1
L0
CXD2586R/-1
LPF Block
The CXD2586R/-1 contains an initial-stage secondary active LPF with numerous resistors and capacitors and
an operational amplifier with reference voltage.
The resistors and capacitors are attached externally, allowing the cut-off frequency fc to be determined flexibly.
The reference voltage (VC) is (AVDD – AVSS)/2.
The LPF block application circuit is shown below.
In this circuit, the cut-off frequency is fc ≈ 40kHz.
The capacitance of the external capacitors when fc = 30kHz and 50kHz are noted below as a reference.
• When fc ≈ 30kHz:
C1 = 200pF, C2 = 910pF
• When fc ≈ 50kHz:
C1 = 120pF, C2 = 560pF
LPF Block Application Circuit
12k
AOUT1
58
C2
680p
VC
12k
AIN1
12k
57
C1
150p
LOUT1
56
Analog out
LPF external circuit
– 84 –
CXD2586R/-1
§4-11. CXD2586R/-1 Clock System
The DAC, digital signal processor and digital servo blocks can be switched to each playback mode according
to how the crystal and clock circuit are connected. Each circuit is as shown in the diagram below; during
normal use, MCKO and MCLK are directly connected to each other, and FSTO and FSTI are directly
connected to each other.
Clock supplied to DAC
384fs
XTLI
384fs or
768fs
XTLO
OSC
1/2
To DAC block
DADS
(command register)
MCKO
External connection
MCLK
1/2
XTSL
To digital signal processor block
FSTO
2/3
External connection
FSTI
1/2
128fs
To digital servo block
1/4
XT2D
XT4D
(command register)
– 85 –
CXD2586R/-1
[5] Description of Servo Signal Processing-System Functions and Commands
§5-1. General Description of the Servo Signal Processing System
(Voltages are the values for a 5V power supply.)
Focus servo
Sampling rate:
88.2kHz
Input range:
2.5V center ±1.0V
Output format:
7-bit PWM
Others:
Offset cancel
Focus bias adjustment
Focus search
Gain-down function
Defect countermeasure
Automatic gain control
Tracking servo
Sampling rate:
Input range:
Output format:
Others:
Sled servo
Sampling rate:
Input range:
Output format:
Others:
88.2kHz
2.5V center ±1.0V
7-bit PWM
Offset cancel
E:F balance adjustment
Track jump
Gain-up function
Defect countermeasure
Drive cancel
Automatic gain control
Vibration countermeasure
345Hz
2.5V center ±1.0V
7-bit PWM
Sled move
FOK, MIRR, DFCT signals generation
RF signal sampling rate: 1.4MHz
Input range:
2.15V to 5.0V
Others:
RF zero level automatic measurement
The signal input from the RFDC pin is multiplied by a factor of 0.7 and
loaded into the A/D converter.
– 86 –
CXD2586R/-1
§5-2. Digital Servo Block Master Clock (MCK)
The FSTI pin is the reference clock input pin. The internal master clock (MCK) is generated by dividing the
frequency of the signal input to FSTI. The frequency division ratio is 1/2 or 1/4.
Table 3-1 below shows the hypothetical case where the crystal clock generated from the digital signal
processor block is 2/3 frequency-divided and input to the FSTI pin by externally connecting the FSTI pin and
the FSTO pin.
The XT4D and XT2D command settings can be made with D13 and D12 of $3F. (Default = 0)
The digital servo block is designed with an MCK frequency of 5.6448MHz.
Mode MCLK FSTO
FSTI
XTSL
XT4D
XT2D
Frequency division ratio
MCK frequency
1
384Fs 256Fs
256Fs
∗
0
1
1/2
128Fs
2
384Fs 256Fs
256Fs
0
0
0
1/2
128Fs
3
768Fs 512Fs
512Fs
∗
1
0
1/4
128Fs
4
768Fs 512Fs
512Fs
1
0
0
1/4
128Fs
Fs = 44.1kHz, ∗: Don’t care
Table 5-1.
§5-3. AVRG (Average) Measurement and Compensation
The CXD2586R/-1 has a circuit that measures AVRG of RFDC, VC, FE, and TE and a circuit that
compensates them to control servo effectively.
AVRG measurement and compensation is necessary to initialize the CXD2586R/-1, and is able to cancel the
offset by performing each AVRG measurement before playback operation and using these results for
compensation. The level applied to the VC, FE RFDC and TE pins can be measured by setting D15 (VCLM),
D13 (FLM), D11 (RFLM) and D4 (TCLM) of $38 respectively to 1.
AVRG measurement consists of digitally measuring the level applied to each analog input pin by taking the
average of 256 samples, and then loading these values into the AVRG register.
AVRG measurement requires approximately 2.9ms to 5.8ms after the command is received.
During AVRG measurement, if the upper 8 bits of the serial command are 38 (Hex), the completion of AVRG
measurement operation can be confirmed through the SENS pin. (See the Timing Chart 5-2.)
XLAT
2.9 to 5.8ms
SENS
(= XAVEBSY)
Completion of AVRG measurement
Max. 1µs
Timing Chart 5-2.
– 87 –
CXD2586R/-1
<Measurement>
• VC AVRG
The offset can be canceled by measuring the VC level which is the center voltage for the system and using
that value to apply compensation to each input error signal.
• FE AVRG
CXD2586R/-1 measures the FE signal DC level, and can apply it to compensate the FZC comparator level
output from the SENS pin during FCS SEARCH (focus search) using these measurement results.
• TE AVRG
This measures the TE signal DC level.
• RE AVRG
The CXD2586R/-1 generates the MIRR, DFCT and FOK signals from the RF signal. However, the FOK
signal is generated by comparing the RF signal at a certain level, so that it is necessary to establish a zero
level which becomes the comparator level reference. Therefore, the RF signal is measured before playback
operation, and compensation is applied to bring this level to the zero level.
An example of sending AVRG measurement and compensation commands is shown below.
(Example) $380800 (RF Avrg. measurement on)
$382000 (FE Avrg. measurement on)
$380010 (TE Avrg. measurement on)
$388000 (VC Avrg. measurement on)
(Complete each AVRG measurement before starting the next.)
$38140A (RFLC, FLC0, FLC1 and TLC1 commands on)
(The required compensation should be turn on together; see Fig. 5-3.)
An interval of 5.8ms or more must be maintained between each command, or the SENS pin must be monitored
to confirm that the previous command has been completed before the next AVRG command is sent.
<Compensation>
See Fig. 5-3 for the contents of each compensation below.
• RFLC
The difference by which the RF signal exceeds the RF AVRG value is input to the RF In register.
(00 is input when the RF signal is lower than the RF AVRG value.)
• TCL0
The value obtained by subtracting the VC AVRG value from the TE signal is input to the TRK In register.
• TCL1
The value obtained by subtracting the TE AVRG value from the TE signal is input to the TRK In register.
• VCLC
The value obtained by subtracting the VC AVRG value from the FE signal is input to the FCS In register.
• FLC1
The value obtained by subtracting the FE AVRG value from the FE signal is input to the FCS In register.
• FLC0
The value obtained by subtracting the FE AVRG value from the FE signal is input to the FZC register.
– 88 –
CXD2586R/-1
§5-4. E:F Balance Adjustment Function
When the disc is rotated with the laser on, and with the FCS (focus) servo on via FCS Search (focus search),
the traverse waveform appears in the TE signal due to disc eccentricity.
In this condition, the low-frequency component can be extracted from the TE signal using the built-in TRK hold
filter by setting D5 (TBLM) of $38 to 1.
The extracted low-frequency component is loaded into the TRVSC register as a digital value, and the TRVSC
register value is established when TBLM returns to 0.
Next, setting D2 (TLC2) of $38 to 1 applies only the amount of compensation (subtraction) equal to the TRVSC
register value to the values obtained from the TE and SE input pins, enabling the E:F balance offset to be
adjusted. (See Fig. 5-3.)
§5-5. FCS Bias (Focus Bias) Adjustment Function
The FBIAS register value can be added to the FCS servo filter input by setting D14 (FBON) of $3A to 1. (See
Fig. 3-3.)
When the FBIAS register value is set to D11 = 0 and D10 = 1 by $34F, data can be written using the 9-bit
value of D9 to D1 (D9: MSB).
In addition, the RF jitter can be monitored by setting the SCOT command of $8 to 1. (See the DSP Block
Timing Chart.)
The FBIAS register can be used as a counter by setting D13 (FBSS) of $3A to 1. It works as an up/down
counter. The FBIAS register works as an up counter when D12 (FBUP) of $3A = 1, and as a down counter
when D12 (FBUP) of $3A = 0. The number of up and down steps can be changed by setting D11 and 10
(FBV1 and FBV0) of $3A.
When using the FBIAS register as a counter, the counter stops when the value set beforehand in FBL9 to 1 of
$34 matches the FCSBIAS value. Also, if the upper 8 bits of the serial command are $3A at this time, the
counter stop can be monitored through SENS.
A
B
Here, the FBIAS setting values FB9 to 1 and the
FBIAS LIMIT values FBL9 to 1 are assumed to
be set in status A. For example, if command
registers FBUP = 0, FBV1 = 0, FBV0 = 0 and
FBSS = 1 are set from this status, down count
starts from status A and approaches the set
LIMIT value. When the LIMIT value is reached
and the FBIAS value matches FBL9 to 1, the
counter stops and the SENS pin goes to high.
Note that the up/down counter changes with
each sampling cycle of the focus servo filter. The
number of steps by which the count value
changes can be selected from 1, 2, 4 or 8 steps
by FBV1 and FBV0. When converted to FE
input, 1 step corresponds to approximately 3.9
[mV].
C
FBIAS setting value (FB9 to 1)
LIMIT value (FBL9 to 1)
SENS pin
A: Register mode
B: Counter mode
C: Counter mode (when stopped)
– 89 –
FE from A/D
VC AVRG
register
TE, SE from A/D
RFDC from A/D
VCLC
TLC0
–
–
FE AVRG
register
TE AVRG
register
RF AVRG
register
– 90 –
–
–
–
Fig. 5-3.
FLC0
FLC1
TLC1
RFLC
–
FBIAS
register
TRVSC
register
FBON
TLC2
To FZC register
+
To FCS In register
–
To TRK/SLD In register
To RF In register
CXD2586R/-1
CXD2586R/-1
§5-6. AGCNTL (Automatic Gain Control) Function
The AGCNTL function automatically adjusts the filter internal gain in order to obtain the appropriate gain with
the servo loop. AGCNTL not only copes with the sensitivity variation of the actuator and photo diode, etc., but
also obtains the optimal gain for each disc.
The AGCNTL command is sent when each servo is turned on. During AGCNTL operation, if the upper 8 bits of
the serial command are 38 (Hex), the completion of AGCNTL operation can be confirmed through the SENS
pin. (See the Timing Chart 5-4 and the Description of SENS Signals.)
Setting D9 and D8 of $38 to 1 set FCS (focus) and TRK (tracking) respectively to AGCNTL operation.
Note) During AGCNTL operation, each servo filter gain must be normal, and the anti-shock circuit (described
hereafter) must be disabled.
XLAT
Max. 11.4µs
SENS
(= AGOK)
AGCNTL termination
Timing Chart 5-4.
Coefficient K13 changes for AGF (focus AGCNTL) and coefficients K23 and K07 changes for AGT (tracking
AGCNTL) due to AGCNTL.
These coefficients change from 01 to 7F (Hex), and they must also be set within this range when written
externally.
After AGCNTL operation has terminated, these coefficient values can be confirmed by reading them out from
the SENS pin with the serial readout function (described hereafter).
AGCNTL related setting
The following settings can be changed with $35, $36 and $37.
FG6 to FG0; AGF convergence gain setting, effective setting range: 00 to 57 (Hex)
TG6 to TG0; AGT convergence gain setting, effective setting range: 00 to 57 (Hex)
AGS;
Self-stop on/off
AGJ;
Convergence completion judgment time
AGGF;
Internally generated sine wave amplitude (AGF)
AGGT;
Internally generated sine wave amplitude (AGT)
AGV1;
AGCNTL sensitivity 1 (during high sensitivity adjustment)
AGV2;
AGCNTL sensitivity 2 (during low sensitivity adjustment)
AGHS;
High sensitivity adjustment on/off
AGHT;
High sensitivity adjustment time
Note) Converging servo loop gain values can be changed with the FG6 to 0 and TG6 to 0 setting values. In
addition, these setting values must be within the effective setting range. The default settings aim for
0dB at 1kHz. However, since convergence values vary according to the characteristics of each
constituent element of the servo loop, FG and TG values should be set as necessary.
– 91 –
CXD2586R/-1
AGCNTL and default operation have two stages.
In the first stage, high sensitivity adjustment is performed for a certain period of time (select 256/128ms with
AGHT), and the AGCNTL coefficient approaches the appropriate value roughly. The sensitivity at this time can
be selected from two types with AGV1.
In the second stage, the AGCNTL coefficient approaches the appropriate value finely with relatively low
sensitivity. The sensitivity for the second stage can be selected from two types with AGV2. In the second stage
of default operation, when the AGCNTL coefficient reaches the appropriate value and stops changing, the
CXD2586R/-1 confirms that the AGCNTL coefficient has not changed for a certain period of time (select
63/31ms with AGHJ), and then terminates AGCNTL operation. (Self-stop mode)
This self-stop mode can be canceled by setting AGS to 0.
In addition, the first stage is omitted for AGCNTL operation when AGHS is set to 0.
An example of AGCNTL coefficient transitions during AGCNTL operation and the relationship between the
various settings are shown in Fig. 5-5.
Initial value
Slope AGV1
AGCNTL
coefficient value
Slope AGV2
Convergence value
AGHT
AGJ
AGCNTL
start
AGCNTL
completion
SENS
Fig. 5-5.
– 92 –
CXD2586R/-1
§5-7. FCS Servo and FCS Search (Focus Search)
The FCS servo is controlled by the 8-bit serial command $0X. (See Table 5-6.)
Register
name
Command
FOCUS
CONTROL
0
D23 to D20
0 0 0 0
D19 to D16
1 0 ∗ ∗
FOCUS SERVO ON (FOCUS GAIN NORMAL)
1 1 ∗ ∗
FOCUS SERVO ON (FOCUS GAIN DOWN)
0 ∗ 0 ∗
FOCUS SERVO OFF, 0V OUT
0 ∗ 1 ∗
FOCUS SERVO OFF, FOCUS SEARCH VOLTAGE OUT
0 ∗ 1 0
FOCUS SEARCH VOLTAGE DOWN
0 ∗ 1 1
FOCUS SEARCH VOLTAGE UP
∗: Don’t care
Table 5-6.
FCS Search
FCS search is required in the course of turning on the FCS servo.
Fig. 5-7 shows the signals for sending commands $00 → $02 → $03 and performing only FCS search.
Fig. 5-8 shows the signals for sending $08 (FCS on) after that.
$00 $02 $03
$00 $02 $03
0
FCSDRV
FCSDRV
RF
RF
FOK
FOK
FZC comparator level
FE
FE
0
FZC
0
FZC
Fig. 5-7.
Fig. 5-8.
– 93 –
$08
CXD2586R/-1
§5-8. TRK (Tracking) and SLD (Sled) Servo Control
TRK and SLD servo is controlled by the 8-bit command $2X. (See Table 5-9.)
When the upper 4 bits of the serial command are 2 (Hex), TZC is output from the SENS pin.
Register
name
2
Command
TRACKING
MODE
D23 to D20
0 0 1 0
D19 to D16
0 0 ∗ ∗
TRACKING SERVO OFF
0 1 ∗ ∗
TRACKING SERVO ON
1 0 ∗ ∗
FORWARD TRACK JUMP
1 1 ∗ ∗
REVERSE TRACK JUMP
∗ ∗ 0 0
SLED SERVO OFF
∗ ∗ 0 1
SLED SERVO ON
∗ ∗ 1 0
FORWARD SLED MOVE
∗ ∗ 1 1
REVERSE SLED MOVE
∗: Don’t care
Table 5-9.
TRK Servo
The TRK JUMP (track jump) height can be set with the 6 bits D13 to D8 of $36.
In addition, when the TRK servo is on and D17 of $1 is set to 1, the TRK servo filter assumes gain-up status.
The TRK servo filter also assumes gain-up status when vibration detection is performed with the LOCK signal
low and the anti-shock circuit (described hereafter) enabled.
The gain-up filter used when TRK has assumed gain-up status has two types of structures which can be
selected by setting D16 of $1. (See Table 5-17.)
SLD Servo
The SLD MOV (sled move) output, composed of a basic value from the 6 bits D13 to D8 of $37, is determined
by multiplying this value by × 1, × 2, × 3, or × 4 magnification set using D17 and D16 when D19 = D18 = 0 is
set with $3. (See Table 5-10.)
SLD MOV must be performed continuously for 50 µs or more. In addition, if the LOCK input signal goes low
when the SLD servo is on, the SLD servo turns off.
Note) When the LOCK signal is low, the TRK servo is set gain-up status and the SLD servo is turned off, by
the default. This is disabled by setting D6 (LKSW) of $38 to 1.
Register
name
3
Command
SELECT
D23 to D20
0 0 1 1
D19 to D16
0 0 0 0
SLED KICK LEVEL (basic value × ±1)
0 0 0 1
SLED KICK LEVEL (basic value × ±2)
0 0 1 0
SLED KICK LEVEL (basic value × ±3)
0 0 1 1
SLED KICK LEVEL (basic value × ±4)
Table 5-10.
– 94 –
CXD2586R/-1
§5-9. MIRR and DFCT Signal Generation
The RF signal obtained from the RFDC pin is sampled at approximately 1.4MHz and loaded. The MIRR and
DFCT signals are generated from this RF signal.
MIRR Signal Generation
The loaded RF signal is applied to peak hold and bottom hold circuits.
An envelope is generated from the waveforms generated in these circuits, and the MIRR comparator level is
generated from the average of these envelope waveforms.
The MIRR signal is generated by comparing this MIRR comparator level with the waveform generated by
subtracting the bottom hold value from the peak hold value. (See Fig. 5-11.)
RF
Peak Hold
Bottom Hold
MIRR Comp
(Mirror comparator level)
Peak Hold
–Bottom Hold
H
MIRR
L
Fig. 5-11.
DFCT Signal Generation
The loaded RF signal is input to two peak hold circuits with different time constants, and the DFCT signal is
generated by comparing the difference between these two peak hold waveforms with the DFCT comparator
level. (See Fig. 5-12.)
The DFCT comparator level can be selected from four values using D13 and D12 of $3B.
RF
Peak Hold1
Peak Hold2
Peak Hold2
–Peak Hold1
SDF
(Defect comparator level)
H
DFCT
L
Fig. 5-12.
– 95 –
CXD2586R/-1
§5-10. DFCT Countermeasure Circuit
The DFCT countermeasure circuit performs operations to maintain the directionality of the servo so that the
servo does not become easily dislocated due to scratches or defects on discs.
Specifically, these operations are achieved by performing scratch and defect detection with the DFCT signal
generation circuit, and when DFCT goes high, applying the low frequency component of the error signal before
DFCT went high to the FCS and TRK servo filter inputs. (See Fig. 5-13.)
In addition, these operations are activated by the default. They can be disabled by setting D7 (DFSW) of $38
to 1 or by inputting high level to the DFSW pin.
Hold Filter
Error signal
Hold register
EN
Input register
DFCT
Servo Filter
Fig. 5-13.
§5-11. Anti-Shock Circuit
When vibrations are produced in the CD player, this circuit forces the TRK filter to assume gain-up status so
that the servo does not become easily dislocated. This circuit is for systems which require vibration
countermeasures.
Concretely, vibrations are detected using an internal anti-shock filter and comparator circuit, and the gain is
increased. (See Fig. 5-14.) The comparator level is fixed to 1/16 of the maximum comparator input amplitude.
However, the comparator level is practically variable by the anti-shock filter output coefficient K35.
This function can be turned on and off by D19 of $1 when the brake circuit (described hereafter) is off. (See
Table 5-17.)
This circuit can also support an external vibration detection circuit, and can also set the TRK servo filter to
gain-up status by inputting high level to the ATSK pin.
When the serial command is $1, vibration detection can be monitored from the SENS pin.
ATSK
TE
Anti Shock
Filter
SENS
Comparator
TRK Gain Up
Filter
TRK
PWM Gen
TRK Gain Normal
Filter
Fig. 5-14.
– 96 –
CXD2586R/-1
§5-12. Brake Circuit
Immediately after a long distance track jump it tends to be hard for the actuator to settle and for the servo to
turn on.
The brake circuit prevents these phenomenon.
In principle, this circuit cuts unnecessary portions of the tracking drive and works it as the brake by utilizing the
180° offset in the RF envelope and tracking error phase relationship which occurs when the actuator traverses
the track in the radial direction from the inner track to the outer track and vice versa. (See Figs. 5-15 and 5-16.)
Concretely, this operation is achieved by masking the tracking drive using the TRKCNCL signal generated by
loading the MIRR signal at the edge of the TZC (Tracking Zero Cross) signal.
The brake circuit can be turned on and off by D18 of $1. (See Fig. 5-17.)
Inner track
Outer track
Outer track
FWD REV Servo ON
JMP JMP
REV FWD Servo ON
JMP JMP
TRK
DRV
TRK
DRV
RF
Trace
RF
Trace
MIRR
MIRR
TE
0
TE
TZC
Edge
TZC
Edge
TRKCNCL
TRKCNCL
TRK
DRV
TRK
DRV
0
SENS
TZC out
0
0
SENS
TZC out
Fig. 5-15.
Register
name
1
Inner track
Command
TRACKING
CONTROL
D23 to D20
0 0 0 1
Fig. 5-16.
D19 to D16
1 0 ∗ ∗
ANTI SHOCK ON
0 ∗ ∗ ∗
ANTI SHOCK OFF
∗ 1 ∗ ∗
BRAKE ON
∗ 0 ∗ ∗
BRAKE OFF
∗ ∗ 0 ∗
TRACKING GAIN NORMAL
∗ ∗ 1 ∗
TRACKING GAIN UP
∗ ∗ ∗ 1
TRACKING GAIN UP FILTER SELECT 1
∗ ∗ ∗ 0
TRACKING GAIN UP FILTER SELECT 2
∗: Don’t care
Fig. 5-17.
– 97 –
CXD2586R/-1
§5-13. COUT Signal
The COUT signal is output to count the number of tracks during traverse, etc. It is basically generated by
loading the MIRR signal at both edges of the TZC signal. However, the used TZC signal can be selected and
there are two types of output methods according to the COUT signal application.
for 1-track jumps, etc.
Fast phase COUT signal with a fast phase TZC signal.
for High-speed traverse
Reliable COUT signal with a delayed phase TZC signal.
This is because some time is required to generate the MIRR signal, and it is necessary to delay the TZC signal
in accordance with the MIRR signal delay during high-speed traverse.
The COUT signal output method is switched with D16 when D19 = D18 = 1 and D17 = 0 are set with $3.
(When D16 = 1, for delayed phase and high-speed traverse.) In addition, the TZC signal delay can be selected
from two values with D14 of $36.
§5-14. Serial Readout Circuit
The following measurement and adjustment results can be read out from the SENS pin by inputting the
readout clock to the SCLK pin by $39. (See Fig. 5-18, Table 5-19 and the Description of SENS Signals.)
Specified commands
$390C
VC AVRG measurement result
$3908
FE AVRG measurement result
$3904
TE AVRG measurement result
$391F
RF AVRG measurement result
$3953
FCS AGCNTL coefficient result
$3963
TRK AGCNTL coefficient result
$391C
TRVSC adjustment result
$391D
FBIAS register value
XLAT
tSPW
tDLS
•••
SCLK
1/fSCLK
Serial Read Out Data
(SENS)
•••
MSB
Fig. 5-18.
Item
Symbol
SCLK frequency
fSCLK
SCLK pulse width
tSPW
tDLS
Delay time
Min.
Typ.
Max.
Unit
1
MHz
500
ns
15
µs
Table 5-19.
During readout, the upper 8 bits of the serial data must be 39 (Hex).
– 98 –
LSB
CXD2586R/-1
§5-15. Writing the Coefficient RAM
The coefficient RAM can be rewritten by $34. All coefficients have default values in the built-in ROM, and
transfer from the ROM to the RAM is completed approximately 40µs after the XRST pin rises. (The coefficient
RAM cannot be rewritten during this period.)
After that, the characteristics of each built-in filter can be finely adjusted by rewriting the data for each address
of the coefficient RAM.
The coefficient rewrite command is comprised of 24 bits, with D14 to D8 of $34 as the address (D15 = 0) and
D7 to D0 as data.
§5-16. PWM Output
FCS, TRK and SLD outputs are output as PWM waveforms.
In particular, FCS and TRK permit accurate drive by using a double oversampling noise shaper.
Timing Chart 5-20 and Figs. 5-21 and 5-22 show examples of output waveforms and drive circuits.
MCK
(5.6448MHz)
↑ ↑ ↑ ↑ ↑ ↑ ↑
Output value +A
Output value –A
Output value 0
64tMCK
64tMCK
64tMCK
SLD
SFON
SFDR
1tMCK
AtMCK
SRON
1tMCK
SRDR
AtMCK
FCS/TRK
32tMCK
32tMCK
32tMCK
32tMCK
FFON/
TFON
FFDR/
TFDR
FRON/
TRON
FRDR/
TRDR
1tMCK
A tMCK
2
1tMCK
A tMCK
2
1tMCK
1tMCK
A tMCK
2
A tMCK
2
The ON signal (FON and RON) is active low.
tMCK =
1
≈ 180ns
5.6448MHz
Timing Chart 5-20.
– 99 –
32tMCK
32tMCK
CXD2586R/-1
Example of Driver Circuits
VDD
FON
RON
DRV+
DRV–
RDR
FDR
GND
Fig. 5-21. PWM Bridge Drive Circuit
VCC
22k
22k
DRV
RDR
FDR
22k
22k
VEE
Fig. 5-22. Operational Amplifier Drive Circuit
– 100 –
CXD2586R/-1
§5-17. DIRC Input Pin
The $2 command register can be changed by operating the DIRC input pin.
Using the DIRC pin allows serial data transfer to be simplified during TRKJMP.
Fig. 5-23 shows $2 command register changes produced by DIRC pin changes.
In addition, Timing Chart 5-24 shows DIRC-based operations during TRKJMP.
High level must be input to the DIRC pin when the XRST pin rises from low to high.
DIRC
TRK
SLD
Q3
Q2
Servo status
Q3
Q2
Servo status
Q3
Q2
Servo status
0
0
OFF
1
1
REV JMP
0
1
ON
0
1
ON
1
0
FWD JMP
0
1
ON
1
0
FWD JMP
1
1
REV JMP
0
1
ON
1
1
REV JMP
1
0
FWD JMP
0
1
ON
Q1
Q0
Servo status
Q1
Q0
Servo status
Q1
Q0
Servo status
0
0
OFF
0
0
OFF
0
1
ON
0
1
ON
0
1
ON
0
1
ON
1
0
FWD MOV
1
0
FWD MOV
1
0
FWD MOV
1
1
REV MOV
1
1
REV MOV
1
1
REV MOV
Q3, Q2, Q1 and Q0 correspond to D19, D18, D17 and D16 of $2.
Fig. 5-23.
$28 latch
$2C latch
XLAT
DIRC
ON
FWD JUMP
OFF
REV JUMP
OFF
ON
TRK SERVO
ON
OFF
SLD SERVO
ON
OFF
Timing Chart 5-24.
– 101 –
CXD2586R/-1
§5-18. Servo Status Changes Produced by the LOCK Signal
When the LOCK signal becomes low, the TRK servo assumes the gain-up status and the SLD servo turns off
in order to prevent SLD free-running.
Setting D6 (LKSW) of $38 to 1 deactivates this function.
In other words, neither the TRK servo nor the SLD servo change even when the LOCK signal becomes low.
This enables microcomputer control.
§5-19. Description of Commands and Data Sets
The following description contains portions which convert internal voltages into the values when they are
output externally and describe them as input conversion or output conversion.
Input conversion converts these voltages into the voltages entering input pins before A/D conversion.
Output conversion converts PWM output values into analog voltage values.
Both types of conversion are calculated at VDD = 5.0V. If this voltage changes, the conversion values also
change proportionally. (Voltage conversion = VDDX/5; VDDX: used supply voltage)
– 102 –
CXD2586R/-1
$34
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
0
KA6
KA5
KA4
KA3
KA2
KA1
KA0
KD7
KD6
KD5
KD4
KD3
KD2
KD1
KD0
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
When D15 = 0
KA6 to KA0: Coefficient address
KD7 to KD0: Coefficient data
D15
D14
D13
D12
D11
D10
1
1
1
1
1
0
FBL9 FBL8 FBL7 FBL6 FBL5 FBL4 FBL3 FBL2 FBL1
—
When D15 = D14 = D13 = D12 = D11 = 1 ($34F)
D10 = 0
FBIAS LIMIT register write
FBL9 to FBL1: Data; data compared with FB9 to 1, FBL9 = MSB.
When using the FBIAS register in counter mode, counter operation stops when the
value of FB9 to 1 matches FBL9 to 1.
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
1
1
1
1
0
1
FB9
FB8
FB7
FB6
FB5
FB4
FB3
FB2
FB1
—
When D15 = D14 = D13 = D12 = 1. ($34F)
D11 = 0, D10 = 1
FBIAS register write
FB9 to FB1: Data; FB9 is MSB two's complement data.
For FE input conversion, FB9 to FB1 = 011111111 corresponds to approximately +1V
and FB9 to FB1 = 100000000 to –1V respectively. (when the supply voltage = 5V)
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
1
1
1
1
0
0
TV9
TV8
TV7
TV6
TV5
TV4
TV3
TV2
TV1
TV0
When D15 = D14 = D13 = D12 = 1. ($34F)
D11 = 0, D10 = 1
TRVSC register write
TV9 to TV0: Data; TV9 is MSB two's complement data.
For TE input conversion, TV9 to TV0 = 0011111111 corresponds to approximately +1V
and TV9 to TV0 = 1100000000 to –1V respectively. (when the supply voltage = 5V)
Note) • When the TRVSC register is read out, the data length is 9 bits. At this time, data corresponding to
each bit of TV8 to TV0 during external write are read out.
• When reading out internally measured values and then writing these values externally, set TV9 the
same as TV8.
– 103 –
CXD2586R/-1
$35
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
FT1
FT0
FS5
FS4
FS3
FS2
FS1
FS0
FTZ
FG6
FG5
FG4
FG3
FG2
FG1
FG0
FT1, FT0, FTZ:
Focus search-up speed
Default value: 010 (3.36V/s)
Focus drive output conversion
FS5 to FS0:
FT1
FT0
FTZ
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
0
0
0
1
1
1
1
Focus search speed
6.73 V/s
3.36
2.24
1.68
8.97
5.38
4.49
3.85
Focus search limit voltage
Default value: 011000 (±1.875V)
Focus drive output conversion
AGF convergence gain setting value
Default value: 0101101
FG6 to FG0:
$36
D15
0
D14
D13
D12
D11
D10
D9
D8
DTZC TJ5
TJ4
TJ3
TJ2
TJ1
TJ0 SFJP TG6
DTZC:
TJ5 to TJ0:
SFJP:
TG6 to TG0:
D7
D6
D5
D4
D3
D2
D1
D0
TG5
TG4
TG3
TG2
TG1
TG0
DTZC delay (8.5/4.25µs)
Default value: 0 (4.25µs)
Track jump voltage
Default value: 001110 (≈ ±1.09V)
Tracking drive output conversion
Surf jump mode on/off
TRK PWM output is made by adding the tracking filter output and TJReg (TJ5 to 0), by
setting D7 to 1 (on).
AGT convergence gain setting value
Default value: 0101110
– 104 –
CXD2586R/-1
$37
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
FZSH FZSL SM5 SM4 SM3 SM2 SM1 SM0 AGS AGJ AGGF AGGT AGV1 AGV2 AGHS AGHT
FZSH, FZSL: FZC (Focus Zero Cross) slice level
Default value:01 (±250mV); FE input conversion
SM5 to SM0:
AGS:
AGJ:
AGGF:
AGGT:
FZSH
FZSL
0
0
1
1
0
1
0
1
Slice level
+500mV
+250
+125
+62.5
Sled move voltage
Default value: 010000 (≈ ±1.25V)
Sled drive output conversion
AGCNTL self-stop on/off
Default value: 1 (on)
AGCNTL convergence completion judgment time during low sensitivity adjustment (31/63ms)
Default value: 0 (63ms)
Focus AGCNTL internally generated sine wave amplitude (small/large)
Default value: 1 (large)
Tracking AGCNTL internally generated sine wave amplitude (small/large)
Default value: 1 (large)
FE/TE input conversion
AGV1:
AGV2:
AGHS:
AGHT:
AGGF
0 (small)
1 (large)
63mV
125
AGGT
0 (small)
1 (large)
125mV
250
AGCNTL convergence sensitivity during high sensitivity adjustment; high/low
Default value: 1 (high)
AGCNTL convergence sensitivity during low sensitivity adjustment; high/low
Default value: 0 (low)
AGCNTL high sensitivity adjustment on/off
Default value: 1 (on)
AGCNTL high sensitivity adjustment time (128/256ms)
Default value: 0 (256ms)
– 105 –
CXD2586R/-1
$38
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
VCLM VCLC FLM FLC0 RFLM RFLC AGF AGT DFSW LKSW TBLM TCLM FLC1 TLC2 TLC1 TLC0
VCLM:
VCLC:
FLM:
FLC0:
RFLM:
RFLC:
AGF:
AGT:
DFSW:
LKSW:
TBLM:
TCLM:
FLC1:
TLC2:
TLC1:
TLC0:
VC level measurement (on/off)
VC level compensation for FCS In register (on/off)
Focus zero level measurement (on/off)
Focus zero level compensation for FZC register (on/off)
RF zero level measurement (on/off)
RF zero level compensation (on/off)
Focus automatic gain adjustment (on/off)
Tracking automatic gain adjustment (on/off)
Defect disable switch (on/off)
Setting this switch to 1 (on) disables the defect countermeasure circuit.
Lock switch (on/off)
Setting this switch to 1 disables the sled free-running prevention circuit.
Traverse center measurement (on/off)
Tracking zero level measurement (on/off)
Focus zero level compensation for FCS In register (on/off)
Traverse center compensation (on/off)
Tracking zero level compensation (on/off)
VC level compensation for TRK/SLD In register (on/off)
Note) Commands marked with are accepted every 2.9ms.
All commands are on when set to 1.
– 106 –
CXD2586R/-1
$39
D15
D14
D13
D12
D11
D10
D9
D8
DAC SD6
SD5
SD4
SD3
SD2
SD1
SD0
DAC:
SD6 to SD0:
SD6
1
0
Serial data readout DAC mode (on/off)
Serial readout data select
SD5
Readout data
Address = coefficient RAM data for (SD5 to SD0)
1
Address = Data RAM data for (SD4 to SD0)
SD4
0
Readout data length
8 bits
16 bits
SD3 to SD0
1
1
1
1
1
0
0
1
1
1
1
0
0
1
1
0
0
1
1
1
0
1
0
1
0
RF AVRG register
RFDC input signal
FBIAS register
TRVSC register
RFDC envelope (bottom)
RFDC envelope (peak)
8 bits
8 bits
9 bits
9 bits
8 bits
8 bits
0
1
1
0
0
0
0
0
1
0
1
0
0
0
0
∗
∗
∗
1
1
0
0
∗
∗
∗
1
0
1
0
VC AVRG register
FE AVRG register
TE AVRG register
FE input signal
TE input signal
SE input signal
VC input signal
9 bits
9 bits
9 bits
8 bits
8 bits
8 bits
8 bits
0
Note) Coefficients K40 to K4F cannot be read out.
∗: Don’t care
See the description for SRO1 and SRO0 of $3F concerning readout methods for the above data.
– 107 –
CXD2586R/-1
$3A
D15
0
D14
D13
D12
D11
D10
FBON FBSS FBUP FBV1 FBV0
D9
0
D8
D7
D6
D5
D4
D3
D2
D1
D0
TJD0 FPS1 FPS0 TPS1 TPS0 CEIT SJHD INBK MTI0
FBON:
FBIAS (focus bias) register addition (on/off)
The FBIAS register value is added to the signal loaded into the FCS In register by setting D14
to 1 (on).
FBSS:
FBIAS (focus bias) register/counter switching
The FCS BIAS register can be used as a counter by setting D13 to 1 (on).
FBUP:
FBIAS (focus bias) counter up/down operation switching
This performs counter up/down control when FBSS = 1. The FBIAS register functions as a
down counter when D12 is set to 0, and as an up counter when set to 1.
FBV1, FBV0: FBIAS (focus bias) counter voltage switching
FCS BIAS count up steps is decided by these bits.
FBV1
FBV0
Number of steps
0
0
1
0
1
2
1
0
4
1
1
8
The counter changes once for
each sampling cycle of the focus
servo filter. When MCK is
128Fs, the sampling frequency
is 88.2kHz. When converted to
FE input, 1 step is approximately
3.9 [mV].
TJD0:
This sets the tracking servo filter data RAM to 0 when switched from track jump to servo on
only when SFJP = 1 (during surf jump operation).
FPS1, FPS0: Gain setting when transferring data from the focus filter to the PWM block.
TPS1, TPS0: Gain setting when transferring data from the tracking filter to the PWM block.
This is effective for increasing the overall gain in order to widen the servo band.
Operation when FPS1, FPS0 (TPS1, TPS0) = 00 is the same as usual (7-bit shift). However,
6dB, 12dB and 18dB can be selected independently for focus (tracking) by setting the relative
gain to 0dB when FPS1, FPS0 (TPS1, TPS0) = 00.
CEIT:
SJHD:
INBK:
MTI0:
FPS1
FPS0
0
0
0
Relative gain
TPS1
TPS0
Relative gain
0dB
0
0
0dB
1
+6dB
0
1
+6dB
1
0
+12dB
1
0
+12dB
1
1
+18dB
1
1
+18dB
The CE pin input takes over the TE pin input by setting D3 to 1 (on). This means that the
registers and filters for TE input are used for CE input.
This holds the tracking filter output at the value when surf jump starts during surf jump.
When D1 is 0 (off), the brake circuit masks the tracking filter output signal with the TRKCNCL
which is generated by taking the MIRR signal at the TZC edge. When D1 is set to 1 (on), the
tracking filter input is masked instead of the output.
The tracking filter input is masked when the MIRR signal is high by setting D0 to 1 (on).
– 108 –
CXD2586R/-1
$3B
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
SFO2 SFO1 SDF2 SDF1 MAX2 MAX1 SFOX BTF D2V2 D2V1 D1V2 D1V1 RINT
SFOX, SFO2, SFO1: FOK slice level
Default value: 011 (313mV)
RFDC input conversion
SFOX
SFO2
SFO1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Slice level
179mV
223
268
313
357
446
536
625
– 109 –
D2
D1
D0
0
0
0
CXD2586R/-1
SDF2,SDF1:
DFCT slice level
Default value: 10 (179mV)
RFDC input conversion
SDF2
SDF1
0
0
1
1
0
1
0
1
Slice level
89mV
134
179
224
MAX2, MAX1: DFCT maximum time
Default value: 00 (no timer limit)
MAX2
MAX1
0
0
1
1
0
1
0
1
DFCT maximum time
No timer limit
2.00ms
2.36
2.72
BTF:
Bottom hold double-speed count-up mode for MIRR signal generation
On/off (default: off)
On when set to 1.
D2V2, D2V1: Peak hold 2 for DFCT signal generation
Count-down speed setting
Default value: 01 (0.492V/ms, 44.1kHz)
[V/ms] unit items indicate RFDC input conversion; [kHz] unit items indicate the
operating frequency of the internal counter.
D2V2
0
0
1
1
D2V1
0
1
0
1
Count-down speed
[V/ms]
[kHz]
0.246
0.492
0.984
1.969
22.05
44.1
88.2
176.4
D1V2, D1V1: Peak hold 1 for DFCT signal generation
Count down speed setting
Default value: 01 (3.938V/ms, 352.8kHz)
[V/ms] unit items indicate RFDC input conversion; [kHz] unit items indicate the
operating frequency of the internal counter.
D1V2
0
0
1
1
RINT:
D1V1
0
1
0
1
Count-down speed
[V/ms]
[kHz]
1.969
3.938
7.875
15.75
176.4
352.8
705.6
1411.2
This initializes the initial-stage registers of the circuits which generate MIRR, DFCT and FOK.
– 110 –
CXD2586R/-1
$3E
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
F1NM F1DM F3NM F3DM T1NM T1UM T3NM T3UM DFIS TLCD RFLP
D4
D3
D2
0
0
0
D1
D0
MIRI XT1D
F1NM, F1DM: Quasi double accuracy setting for FCS servo filter first-stage
On when set to 1; default = 0.
F1NM: Gain normal
F1DM: Gain down
T1NM, T1UM: Quasi double accuracy setting for TRK servo filter first-stage
On when set to 1; default = 0.
T1NM: Gain normal
T1UM: Gain up
F3NM, F3DM: Quasi double accuracy setting for FCS servo filter third-stage
On when set to 1; default = 0.
Generally, the advance amount of the phase becomes large by partially setting the FCS servo
third-stage filter which is used as the phase compensation filter to double accuracy.
F3NM: Gain normal
F3DM: Gain down
T3NM, T3UM: Quasi double accuracy setting for TRK servo filter third-stage
On when set to 1; default = 0.
Generally, the advance amount of the phase becomes large by partially setting the TRK servo
third-stage filter which is used as the phase compensation filter to double accuracy.
T3NM: Gain normal
T3UM: Gain up
Note) Filter first- and third-stage quasi double accuracy settings can be set individually.
See FILTER Composition at the end of this specification concerning quasi double-accuracy.
DFIS:
TLCD:
RFLP:
MIRI:
XT1D:
FCS hold filter input extraction node selection
0: M05 (Data RAM address 05); default
1: M04 (Data RAM address 04)
This command masks the TLC2 command set by D2 of $38 only when FOK is low.
On when set to 1; default = 0
This command passes the signal obtained from the RFDC pin through the LPF (low pass filter)
before the built-in A/D converter.
0: LPF off; default
1: LPF on
MIRR input switching.
The MIRR signal can be input from an external source. When D1 is 0, the MIRR signal is used
internally as usual. When D1 = 1, the MIRR signal can be input from an external source
through the MIRR pin.
The clock input from FSTI can be used as the master clock for the servo block regardless of
the XTSL pin, XT2D and XT4D by setting D0 to 1.
– 111 –
CXD2586R/-1
$3F
D15
0
D14
D13
D12
AGG4 XT4D XT2D
AGG4:
D11
0
D10
D9
DRR2 DRR1 DRR0
D7
D6
D5
0
ASFG
0
D4
D3
D2
D1
D0
LPAS SRO1 SRO0 AGHF COT2
This varies the amplitude of the internally generated sine wave using the AGGF and AGGT
commands during AGC.
When AGG4 = 0, the default is used. When AGG4 = 1, the setting is as shown in the table
below.
These settings are the same
AGGF (MSB)
AGGT (LSB) TE/FE input conversion
as for both focus auto gain
0
0
31 [mV]
control and tracking auto gain
0
1
63 [mV]
control.
1
0
125 [mV]
1
XT4D, XT2D:
D8
1
250 [mV]
MCK (digital servo master clock) frequency division setting
This command forcibly sets the frequency division ratio to 1/2 or 1/4 when MCK is generated
from the signal input to the FSTI pin.
XT4D
XT2D
Frequency division ratio
0
0
1
0
1
0
According to XTSL (default)
1/2
1/4
DRR2 to DRR0: Partially clears the Data RAM values (0 write).
The following values are cleared when set to 1 (on) respectively; default = 0
DRR2: M08, M09, M0A
DRR1: M00, M01, M02
DRR0: M00, M01, M02 only when LOCK = low
Note) Set DRR1 and DRR0 for 50µs or more.
ASFG:
When vibration detection is performed during anti-shock circuit operation, FCS servo filter is
set to gain normal status.
On when set to 1; default = 0
LPAS:
Built-in analog buffer low-current consumption mode
This mode reduces the total analog buffer current consumption for the VC, TE, SE and FE
input by using a single operational amplifier.
On when set to 1; default = 0
Note) When using this mode, firstly check whether each error signal is properly A/D
converted using the SRO1 and SRO0 commands of $3F.
SRO1, SRO0:
These commands are to output various data externally continuously which have been
specified with the $39 command. (However, D15 (DAC) of $39 must be set to 1.)
Digital output can be obtained from three specified pins (SOCK, XOLT and SOUT) by setting
these commands to 1 respectively. The default is 0, 0.
The output pins for each case are shown below.
SOCK
XOLT
SOUT
SRO1 = 1
SRO0 = 1
DA13
DA12
DA14
DA10
DA09
DA11
(See the Description of Data Readout on the following page.)
AGHF:
COT2:
This halves the frequency of the internally generated sine wave during AGC.
The STZC signal is output from COUT by setting D0 to 1.
(STZC: TZC signal generated by sampling the TE signal at 700kHz)
– 112 –
CXD2586R/-1
Description of Data Readout
SOCK
(5.6448MHz)
•••
•••
•••
•••
XOLT
(88.2kHz)
SOUT
MSB
•••
LSB
MSB
16-bit register for
serial/parallel conversion
SOUT
•••
LSB
16-bit register for
latch
LSB
LSB
To the 7-segment LED
•
•
•
•
•
•
To the 7-segment LED
MSB
MSB
SOCK
CLK
CLK
Data is connected to the 7-segment
LED by 4-bits at a time. This enable
Hex display using four 7-segment LEDs.
XOLT
SOUT
Serial data input
D/A
Analog
output
SOCK
Clock input
XOLT
Latch enable input
To an oscilloscope, etc.
Offset adjustment,
gain adjustment
Waveforms can be monitored with an oscilloscope using a
serial input-type D/A converter as shown above.
– 113 –
CXD2586R/-1
§5-20. List of Servo Filter Coefficients
<Coefficient Preset Value Table (1)>
ADDRESS
DATA
K00
K01
K02
K03
K04
K05
K06
K07
K08
K09
K0A
K0B
K0C
K0D
K0E
K0F
E0
81
23
7F
6A
10
14
30
7F
46
81
1C
7F
58
82
7F
SLED INPUT GAIN
SLED LOW BOOST FILTER A-H
SLED LOW BOOST FILTER A-L
SLED LOW BOOST FILTER B-H
SLED LOW BOOST FILTER B-L
SLED OUTPUT GAIN
FOCUS INPUT GAIN
SLED AUTO GAIN
FOCUS HIGH CUT FILTER A
FOCUS HIGH CUT FILTER B
FOCUS LOW BOOST FILTER A-H
FOCUS LOW BOOST FILTER A-L
FOCUS LOW BOOST FILTER B-H
FOCUS LOW BOOST FILTER B-L
FOCUS PHASE COMPENSATE FILTER A
FOCUS DEFECT HOLD GAIN
K10
K11
K12
K13
K14
K15
K16
K17
K18
K19
K1A
K1B
K1C
K1D
K1E
K1F
4E
32
20
30
80
77
80
77
00
F1
7F
3B
81
44
7F
5E
FOCUS PHASE COMPENSATE FILTER B
FOCUS OUTPUT GAIN
ANTI SHOCK INPUT GAIN
FOCUS AUTO GAIN
HPTZC / Auto Gain HIGH PASS FILTER A
HPTZC / Auto Gain HIGH PASS FILTER B
ANTI SHOCK HIGH PASS FILTER A
HPTZC / Auto Gain LOW PASS FILTER B
Fix∗
TRACKING INPUT GAIN
TRACKING HIGH CUT FILTER A
TRACKING HIGH CUT FILTER B
TRACKING LOW BOOST FILTER A-H
TRACKING LOW BOOST FILTER A-L
TRACKING LOW BOOST FILTER B-H
TRACKING LOW BOOST FILTER B-L
K20
K21
K22
K23
K24
K25
K26
K27
K28
K29
K2A
K2B
K2C
K2D
K2E
K2F
82
44
18
30
7F
46
81
3A
7F
66
82
44
4E
1B
00
00
TRACKING PHASE COMPENSATE FILTER A
TRACKING PHASE COMPENSATE FILTER B
TRACKING OUTPUT GAIN
TRACKING AUTO GAIN
FOCUS GAIN DOWN HIGH CUT FILTER A
FOCUS GAIN DOWN HIGH CUT FILTER B
FOCUS GAIN DOWN LOW BOOST FILTER A-H
FOCUS GAIN DOWN LOW BOOST FILTER A-L
FOCUS GAIN DOWN LOW BOOST FILTER B-H
FOCUS GAIN DOWN LOW BOOST FILTER B-L
FOCUS GAIN DOWN PHASE COMPENSATE FILTER A
FOCUS GAIN DOWN DEFECT HOLD GAIN
FOCUS GAIN DOWN PHASE COMPENSATE FILTER B
FOCUS GAIN DOWN OUTPUT GAIN
NOT USED
NOT USED
CONTENTS
– 114 –
CXD2586R/-1
<Coefficient ROM Preset Value Table (2)>
ADDRESS
DATA
K30
K31
K32
K33
K34
K35
K36
K37
K38
K39
K3A
K3B
K3C
K3D
K3E
K3F
80
66
00
7F
6E
20
7F
3B
80
44
7F
77
86
0D
57
00
Fix∗
ANTI SHOCK LOW PASS FILTER B
NOT USED
ANTI SHOCK HIGH PASS FILTER B-H
ANTI SHOCK HIGH PASS FILTER B-L
ANTI SHOCK FILTER COMPARATE GAIN
TRACKING GAIN UP2 HIGH CUT FILTER A
TRACKING GAIN UP2 HIGH CUT FILTER B
TRACKING GAIN UP2 LOW BOOST FILTER A-H
TRACKING GAIN UP2 LOW BOOST FILTER A-L
TRACKING GAIN UP2 LOW BOOST FILTER B-H
TRACKING GAIN UP2 LOW BOOST FILTER B-L
TRACKING GAIN UP PHASE COMPENSATE FILTER A
TRACKING GAIN UP PHASE COMPENSATE FILTER B
TRACKING GAIN UP OUTPUT GAIN
NOT USED
K40
K41
K42
K43
K44
K45
K46
K47
K48
K49
K4A
K4B
K4C
K4D
K4E
K4F
04
7F
7F
79
17
6D
00
00
02
7F
7F
79
17
54
00
00
TRACKING HOLD FILTER INPUT GAIN
TRACKING HOLD FILTER A-H
TRACKING HOLD FILTER A-L
TRACKING HOLD FILTER B-H
TRACKING HOLD FILTER B-L
TRACKING HOLD FILTER OUTPUT GAIN
NOT USED
NOT USED
FOCUS HOLD FILTER INPUT GAIN
FOCUS HOLD FILTER A-H
FOCUS HOLD FILTER A-L
FOCUS HOLD FILTER B-H
FOCUS HOLD FILTER B-L
FOCUS HOLD FILTER OUTPUT GAIN
NOT USED
NOT USED
CONTENTS
∗ Fix indicates that normal preset values should be used.
– 115 –
CXD2586R/-1
§5-21. FILTER Composition
The internal filter composition is shown below.
K ∗ ∗ and M ∗ ∗ indicate coefficient RAM and Data RAM address values respectively.
FCS Servo Gain Normal; fs = 88.2kHz
FCS
Hold Reg 2
FCS
In Reg
DFCT
2–1
K06
AGFON
Sin ROM
K06
K0F
M03
M04
Z–1
FCS
AUTO Gain
M05
Z–1
K08
FCS
Hold Reg 1
M06
Z–1
K09
K0A
K0C
2–7
K11
M07
K0E
K10
27
2–7
FCS PWM
K0D
K0B
K13
Z–1
FCS SRCH
Note) Set the MSB bit of the K0B and K0D coefficients to 0.
FCS Servo Gain Down; fs = 88.2kHz
FCS
Hold Reg 2
FCS
In Reg
DFCT
2–1
K06
K2B
M03
M04
Z–1
M05
Z–1
K24
K25
Z–1
K28
K26
2–7
K27
FCS
Hold Reg 1
FCS
AUTO Gain
M06
K2D
M07
K13
Z–1
K2A
K2C
27
2–7
FCS PWM
K29
FCS SRCH
Note) Set the MSB bit of the K27 and K29 coefficients to 0.
– 116 –
CXD2586R/-1
TRK Servo Gain Normal; fs = 88.2kHz
TRK
Hold Reg
TRK
In Reg
DFCT
2–1
K19
AGTON
Sin ROM
K19
TRK
AUTO Gain
M0B
M0C
M0D
M0E
Z–1
Z–1
Z–1
Z–1
K1A
K1B
K1C
K1E
2–7
K1D
K20
K21
K22
M0F
K23
27
2–7
TRK PWM
K1F
TRK JMP
Note) Set the MSB bit of the K1D and K1F coefficients to 0.
TRK Servo Gain Up 1; fs = 88.2kHz
TRK
Hold Reg
TRK
In Reg
DFCT
2–1
K19
TRK
AUTO Gain
M0B
M0C
M0E
Z–1
Z–1
Z–1
K3E
M0F
27
K23
TRK PWM
TRK JMP
K1A
K1B
K3C
K3D
– 117 –
CXD2586R/-1
TRK Servo Gain Up 2; fs = 88.2kHz
TRK
Hold Reg
TRK
In Reg
DFCT
2–1
K19
TRK
AUTO Gain
M0B
M0C
M0D
M0E
Z–1
Z–1
Z–1
Z–1
K36
K37
K3A
K38
2–7
K3C
K3D
M0F
K3E
27
2–7
K39
K23
TRK PWM
K3B
TRK JMP
Note) Set the MSB bit of the K39 and K3B coefficients to 0.
SLD Servo; fs = 345Hz
TRK
AUTO Gain
2–1
SLD
In Reg
K00
M00
M01
Z–1
Z–1
K05
M02
27
K07
SLD PWM
SLD MOV
K01
K03
2–7
K02
2–7
K04
Note) Set the MSB bit of the K02 and K04 coefficients to 0.
HPTZC/Auto Gain; fs = 88.2kHz
FCS
In Reg
TRK
In Reg
Sin ROM
2–1
Slice
TZC Reg
AGFON
2–1
AGTON
AGFON
M08
M09
Z–1
M0A
Z–1
K14
K15
– 118 –
Z–1
K17
Slice
AUTO Gain
Reg
CXD2586R/-1
Anti Shock; fs = 88.2kHz
TRK
In Reg
2–1
K12
M08
M09
M0A
Z–1
Z–1
Z–1
K31
K16
K35
Comp
Anti Shock
Reg
K33
2–7
K34
Note) Set the MSB bit of the K34 coefficient to 0.
The comparator level is 1/16 the maximum amplitude of the comparator input.
AVRG; fs = 88.2kHz
2–1
2–7
M08
VC, TE, FE,
RFDC
AVRG Reg
Z–1
TRK Hold; fs = 345Hz
SLD
In Reg
2–1
K40
M18
M19
Z–1
Z–1
K41
K45
TRK
Hold Reg
K43
2–7
2–7
K42
K44
Note) Set the MSB bit of the K42 and K44 coefficients to 0.
FCS Hold; fs = 345Hz
FCS
Hold Reg 1
K48
M10
M11
Z–1
Z–1
K49
K4D
FCS
Hold Reg 2
K4B
2–7
2–7
K4A
K4C
Note) Set the MSB bit of the K4A and K4C coefficients to 0.
– 119 –
CXD2586R/-1
FCS Servo Gain Normal; fs = 88.2kHz, during quasi double accuracy (Ex.: $3EAXX0)
FCS
Hold Reg 2
DFCT
2–1
FCS
In Reg
K06
AGFON
Sin ROM
K06
M03
M04
Z–1
M05
Z–1
∗
M06
Z–1
K0A
2–7
K08
M07
K13
∗
7FH
2–7
K11
Z–1
∗
81H
FCS
AUTO Gain
FCS
Hold Reg 1
K0F
K0C
2–7
K09
80H
2–7
K0B
K10
27
2–7
K0D
FCS PWM
K0E
FCS SRCH
∗ 81H, 7FH and 80H are each Hex display 8-bit fixed values when set to quasi double accuracy.
Note) Set the MSB bit of the K0B and K0D coefficients during normal operation, and of the K08, K09
and K0E coefficients during quasi double accuracy to 0.
FCS Servo Gain Down; fs = 88.2kHz, during quasi double accuracy (Ex.: $3E5XX0)
FCS
Hold Reg 2
FCS
In Reg
DFCT
2–1
K06
K2B
M03
M04
Z–1
M05
Z–1
∗
K24
K2D
M07
K13
Z–1
∗
7FH
2–7
M06
Z–1
∗
81H
FCS
AUTO Gain
FCS
Hold Reg 1
K26
2–7
K28
2–7
K25
K27
80H
2–7
K2C
27
2–7
K29
FCS PWM
K2A
FCS SRCH
∗ 81H, 7FH and 80H are each Hex display 8-bit fixed values when set to quasi double accuracy.
Note) Set the MSB bit of the K27 and K29 coefficients during normal operation, and of the K24, K25
and K2A coefficients during quasi double accuracy to 0.
– 120 –
CXD2586R/-1
TRK Servo Gain Normal; fs = 88.2kHz, during quasi double accuracy (Ex.: $3EXAX0)
TRK
Hold Reg
DFCT
2–1
TRK
In Reg
K19
AGTON
Sin ROM
K19
TRK
AUTO Gain
M0B
M0C
M0D
M0E
Z–1
Z–1
Z–1
Z–1
∗
∗
81H
K1C
2–7
K1A
M0F
K23
∗
7FH
2–7
K22
K1E
2–7
K1B
K1D
80H
2–7
K21
27
2–7
K1F
TRK PWM
K20
TRK JMP
∗ 81H, 7FH and 80H are each Hex display 8-bit fixed values when set to quasi double accuracy.
Note) Set the MSB bit of the K1D and K1F coefficients during normal operation, and of the K1A, K1B
and K20 coefficients during quasi double accuracy to 0.
TRK Servo Gain up 1; fs = 88.2kHz, during quasi double accuracy (Ex.: $3EX5X0)
TRK
Hold Reg
TRK
In Reg
DFCT
2–1
K19
TRK
AUTO Gain
M0B
M0C
M0E
Z–1
Z–1
Z–1
∗
∗
81H
2–7
K1A
∗
7FH
80H
K1B
K3C
2–7
K3E
M0F
27
K23
TRK PWM
TRK JMP
K3D
2–7
∗ 81H, 7FH and 80H are each Hex display 8-bit fixed values when set to quasi double accuracy.
Note) Set the MSB bit of the K1A, K1B and K3C coefficients during quasi double accuracy to 0.
– 121 –
CXD2586R/-1
TRK Servo Gain up 2; fs = 88.2kHz, during quasi double accuracy (Ex.: $3EX5X0)
TRK
Hold Reg
TRK
In Reg
DFCT
2–1
K19
TRK
AUTO Gain
M0B
M0C
M0D
M0E
Z–1
Z–1
Z–1
Z–1
∗
∗
81H
K36
M0F
K23
∗
7FH
2–7
K3E
K38
2–7
K3A
2–7
K37
K39
80H
2–7
K3D
27
2–7
K3B
TRK PWM
K3C
TRK JMP
∗ 81H, 7FH and 80H are each Hex display 8-bit fixed values when set to quasi double accuracy.
Note) Set the MSB bit of the K39 and K3B coefficients during normal operation, and of the K36, K37
and K3C coefficients during quasi double accuracy to 0.
– 122 –
CXD2586R/-1
§5-22. TRACKING and FOCUS Frequency Response
TRACKING frequency response
40
180°
NORMAL
GAIN UP
30
G
20
0°
φ
10
φ-Phase [degree]
G-Gain [dB]
90°
–90°
0
–10
2.1
10
100
–180°
20K
1K
f-Frequency [Hz]
FOCUS frequency response
40
180°
NORMAL
GAIN DOWN
30
20
G
0°
10
φ
–90°
0
–10
2.1
10
100
f-Frequency [Hz]
– 123 –
1K
–180°
20K
φ-Phase [degree]
G-Gain [dB]
90°
VCC
VC
CE
TE
FE
FZC
RFO
GND
ADIO
V16M
FSW
XLAT
WFCK
WFCK
DA15
SQSO
EXCK
EXCK
LRCKI
GFS
SBSO
SBSO
DA16
SQSO
SCOR
SENS
PSSL
LRCK
MUTE
NC.
ASYE
SCLK
XRST
DVDD1
PWMI
DIRC
NC.
VDD
SCLK
DFSW
ASYO
GND
ATSK
ASYI
AVDD1
XLAT
RFAC
DATA
BIAS
CLOK
AVSS1
DVDD2
FILI
COUT
COUT
CLTV
NC.
PCO
FOK
VC
XTSL 72
DAS0 70
DAS1 71
DTS5 66
DTS3 64
DTS2 63
DTS1 62
SRON
SRDR
SFON
116
117
118 TFDR
119 TRON
DVDD3
TES3
TES2
AVSS2
RFC
144 TE
143 CE
2
1
142 RFDC
141
140 ADIO
139
138 IGEN
137 AVDD2
136 V16M
135 VCKI
134 PDO
133 NC.
132
131
130 DVSS3
129 TEST
128 VCOI
127 VCOO
126
125 FFON
3
7
6
5
4
8
FFDR
124 FRDR
123 FRON
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
C2PO
DA06 37
GND
MNT3
Application circuits shown are typical examples
illustrating the operation of the devices. Sony cannot
assume responsibility for any problems arising out of
the use of these circuits or for any infringement of third
party patent and other right due to same.
XRAOF
DA05 38
DA04 39
MNT2
MNT1
DA02 41
DA03 40
MNT0
DA01 42
DVSS1 43
NC. 44
AVSS41 45
AVDD4 46
AOUT2 47
AIN2 48
LOUT2 49
AVSS42 50
AVDD5 51
XTLO 52
XTLI 53
AVSS5 54
AVSS31 55
LOUT1 56
AIN1 57
AOUT1 58
AVDD3 59
121 TFON
122
NC. 61
AVSS32 60
120 TRDR
DTS4 65
DTS6 67
114 SFDR
115
XWO 69
FSW
FE
SE
PDO
CLOK
SCOR
PCMDI
DTS7 68
TESTA
VPCO2
VPCO1
LDON
MIRR
MIRR
VCTL
FD
DFCT
DFCT
FILO
TD
SQCK
SQCK
WDCK
WDCK
TG
DVSS2
DA14
SOUT
FG
XRST
DOUT
DOUT
DA13
SOCK
GND
FOK
C16M
C16M
DA12
XOLT
SPDL
SENS
MD2
NC.
113 SSTP
MDS
GTOP
SLED
LDON
C4M
C4M
DA11
112 LOCK
111
FSTO
DA10
XUGF
SSTP
MON
MDP
PWMI
VC
DA07
LOCK
DATA
MUTE
BCKI
MON
110
GFS
+5V
XWO
MCLK
DA08
109 NC.
MCKO
108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73
MD2
FSTI
DA09
XPLCK
– 124 –
XRAOF
§6-1. Application Circuit
CXD2586R/-1
VC
Driver circuit
CXD2586R/-1
Package Outline
Unit: mm
LQFP-144P-L01
144PIN LQFP (PLASTIC)
22.0 ± 0.2
20.0 ± 0.1
1.7 MAX
73
108
109
72
B
A
37
144
36
1
0.22 ± 0.05
0.5
0.1
S
0.1
S
M
S
0.1 ± 0.05
(21.0)
0.22 ± 0.05
DETAIL A
(0.125)
0.145 ± 0.05
0.5 ± 0.15
0° to 10°
(0.2)
PACKAGE STRUCTURE
DETAIL B
SONY CODE
LQFP-144P-L01
EIAJ CODE
LQFP144-P-2020-A
JEDEC CODE
PACKAGE MATERIAL
EPOXY RESIN
LEAD TREATMENT
SOLDER PLATING
LEAD MATERIAL
42 / COPPER ALLOY
PACKAGE WEIGHT
1.3 g
LQFP-144P-L021
144PIN LQFP(PLASTIC)
22.0 } 0.2
20.0 } 0.1
1.7 MAX
73
108
72
109
B
A
144
37
1
36
0.5
0.22 ± 0.05
0.1
M
0.1
S
S
DETAIL A
(0.2)
(0.125)
0.22 ± 0.05
0.145 ± 0.05
0° to 10°
0.5 ± 0.15 (21.0)
0.1 ± 0.05
DETAIL B
PACKAGE STRUCTURE
SONY CODE
EIAJ CODE
JEDEC CODE
LQFP-144P-L021
LQFP144-P-2020
PACKAGE MATERIAL
EPOXY RESIN
LEAD TREATMENT
SOLDER PLATING
LEAD MATERIAL
COPPER ALLOY
PACKAGE WEIGHT
1.3g
– 125 –
S
CXD2586R/-1
LQFP-144P-L022
144PIN LQFP(PLASTIC)
22.0 } 0.2
20.0 } 0.1
1.7 MAX
73
108
72
109
B
A
144
37
1
36
0.5
0.22 ± 0.05
0.1
M
0.1
S
S
(0.125)
(0.2)
DETAIL A
0.145 ± 0.05
0° to 10°
0.22 ± 0.05
0.5 } 0.15
0.1 ± 0.05
(21.0)
S
DETAIL B
PACKAGE STRUCTURE
SONY CODE
LQFP-144P-L022
LQFP144-P-2020
EIAJ CODE
JEDEC CODE
PACKAGE MATERIAL
EPOXY RESIN
LEAD TREATMENT
SOLDER PLATING
LEAD MATERIAL
42 / COPPER ALLOY
PACKAGE WEIGHT
1.3g
LQFP-144P-L081
144PIN LQFP(PLASTIC)
22.0 } 0.2
1.7 MAX
20.0 } 0.1
73
108
109
72
B
A
37
144
1
36
0.5
DETAIL A
SONY CODE
EIAJ CODE
JEDEC CODE
(21.0)
M
S
(0.2)
(0.15)
DETAIL B
LQFP-144P-L081
LQFP144-P-2020
0.1
S
0.15 ± 0.05
0° to 10°
0.1
0.22 ± 0.05
0.5 ± 0.2
0.1 ± 0.05
0.22 ± 0.05
PACKAGE STRUCTURE
PACKAGE MATERIAL
EPOXY RESIN
LEAD TREATMENT
SOLDER PLATING
LEAD MATERIAL
COPPER ALLOY
PACKAGE WEIGHT
1.3g
– 126 –
S
CXD2586R/-1
LQFP-144P-L141
144PIN LQFP(PLASTIC)
22.0 ± 0.2
20.0 ± 0.1
1.7 MAX
108
73
109
72
B
A
37
144
36
1
0.22 ± 0.05
0.5
DETAIL A
0.1
(21.0)
0.22 ± 0.05
(0.2)
(0.15)
0.15 ± 0.05
0° to 10°
S
M
S
0.5 } 0.2
0.1 ± 0.05
0.1
DETAIL B
PACKAGE STRUCTURE
SONY CODE
EIAJ CODE
JEDEC CODE
LQFP-144P-L141
LQFP144-P-2020
PACKAGE MATERIAL
EPOXY RESIN
LEAD TREATMENT
SOLDER PLATING
LEAD MATERIAL
COPPER ALLOY
PACKAGE WEIGHT
1.3g
– 127 –
S