CXD2585Q CD Digital Signal Processor with Built-in Digital Servo For the availability of this product, please contact the sales office. Description The CXD2585Q is a digital signal processor LSI for CD players. This LSI incorporates a digital servo. 80 pin QFP (Plastic) Features • All digital signal processings during playback are performed with a single chip • Highly integrated mounting possible due to a builtin RAM Digital Signal Processor (DSP) Block • Playback mode supporting CAV (Constant Angular Velocity) • Frame jitter free • 0.5× to 4× continuous playback possible • Allows relative rotational velocity readout • Wide capture range playback mode • Spindle rotational velocity following method • Supports 1× to 4× playback variable pitch playback • Bit clock, which strobes the EFM signal, is generated by the digital PLL. • EFM data demodulation • Enhanced EFM frame sync signal protection • Refined super strategy-based powerful error correction C1: double correction, C2: quadruple correction Supported during 4× playback • Noise reduction during track jumps • Auto zero-cross mute • Subcode demodulation and Sub-Q data error detection • Digital spindle servo • 16-bit traverse counter • Asymmetry correction circuit • CPU interface on serial bus • Error correction monitor signal, etc. output from a new CPU interface • Servo auto sequencer • Fine search performs track jumps with high accuracy • Digital audio interface output • Digital level meter, peak meter • Bilingual supported • VCO control mode • CD TEXT data demodulation Digital Servo (DSSP) Block • Microcomputer software-based flexible servo control • Offset cancel function for servo error signal • Auto gain control function for servo loop • E:F balance, focus bias adjustment function • Surf jump function supporting micro two-axis • Tracking filter: 6 stages Focus filter: 5 stages Applications CD players Structure Silicon gate CMOS IC Absolute Maximum Ratings • Supply voltage VDD –0.3 to +7.0 • Input voltage VI –0.3 to +7.0 (VSS – 0.3 to VDD + 0.3) • Output voltage VO –0.3 to +7.0 • Storage temperature Tstg –40 to +125 • Supply voltage difference VSS – AVSS –0.3 to +0.3 VDD – AVDD –0.3 to +0.3 V V V V °C V V Recommended Operating Conditions 2.7 to 5.5 V • Supply voltage VDD • Operating temperature Topr –20 to +75 °C Note) The VDD for the CXD2585Q varies according to the playback speed. Playback speed VDD [V] CD-DSP block 4× speed 4.75 to 5.25 2× speed 3.0 to 5.5 1× speed 2.7 to 5.5 Input/Output Capacitance • Input capacitance CI • Output capacitance CO Note) Measurement conditions 12 (Max.) pF 12 (Max.) pF VDD = VI = 0V fM = 1MHz Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E97748-PS CXD2585Q 71 72 69 59 60 58 MUTE BCK PCMD LRCK WDCK 11 13 68 10 C2PO WFCK EMPH GFS XUGF VCTL VPCO V16M XTSL XTAO XTAI Block Diagram 17 14 65 66 67 3 37 TES1 FSTO 27 C4M 16 36 TEST Clock Generator EFM demodurator RFAC 50 ASYI Error Corrector 2 XRST D/A Interface 49 ASYO 48 Asymmetry Corrector ASYE 62 32K RAM BIAS 57 Digital OUT 63 MD2 64 DOUT XPCK 12 Sub Code Processor FILO 53 FILI 54 Digital PLL PCO 55 CLTV 52 MDP 25 LOCK 24 Digital CLV PWMI 23 SENS 7 DATA 4 XLAT 5 CLOK 6 SCOR 15 SBSO 79 CPU Interface EXCK 80 Servo Auto Sequencer SCSY 78 SQSO 76 SQCK 77 Signal processor block Servo block 73 SOUT 74 SOCK 75 XOLT SERVO Interface 8 SCLK 19 COUT 26 SSTP 9 MIRR DFCT FOK RFDC 43 ATSK 20 MIRR 21 DFCT 22 FOK CE 42 SERVO DSP TE 41 SE 40 OPAmp Analog SW A/D Converter FE 39 VC 38 PWM GENERATOR FOCUS SERVO FOCUS PWM GENERATOR TRACKING SERVO TRACKING PWM GENERATOR SLED SERVO SLED PWM GENERATOR IGEN 46 ADIO 44 –2– 33 FFDR 34 FRDR 31 TFDR 32 TRDR 29 SFDR 30 SRDR CXD2585Q TE CE RFDC ADIO AVSS0 IGEN AVDD0 ASYO RFAC ASYI AVSS1 CLTV FILO FILI AVDD1 PCO BIAS VCTL V16M VPCO Pin Configuration 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 DVDD2 61 40 SE ASYE 62 39 FE MD2 63 38 VC DOUT 64 37 TES1 LRCK 65 36 TEST PCMD 66 35 DVSS1 BCK 67 34 FRDR EMPH 68 33 FFDR XTSL 69 32 TRDR DVSS2 70 31 TFDR XTAI 71 30 SRDR XTAO 72 29 SFDR SOUT 73 28 DVDD1 SOCK 74 27 FSTO XOLT 75 26 SSTP SQSO 76 25 MDP ATSK MIRR SCLK COUT SENS –3– DVSS0 9 10 11 12 13 14 15 16 17 18 19 20 C4M 8 WDCK 7 C2PO 6 SCOR 5 GFS 4 XUGF 3 XPCK 2 WFCK 1 XLAT 21 DFCT CLOK 22 FOK EXCK 80 DATA SBSO 79 MUTE 23 PWMI XRST 24 LOCK SCSY 78 DVDD0 SQCK 77 CXD2585Q Pin Description Pin No. Symbol I/O Description Digital power supply. 1 DVDD0 — 2 XRST I System reset. Reset when low. 3 MUTE I Mute input (low: off, high: on) 4 DATA I Serial data input from CPU. 5 XLAT I Latch input from CPU. Serial data is latched at the falling edge. 6 CLOK I Serial data transfer clock input from CPU. 7 SENS O 8 SCLK I 9 ATSK I/O 1, 0 Anti-shock input/output. 10 WFCK O 1, 0 WFCK output. 11 XUGF O 1, 0 XUGF output. MNT0 or RFCK is output by switching with the command. 12 XPCK O 1, 0 XPCK output. MNT1 is output by switching with the command. 13 GFS O 1, 0 GFS output. MNT2 or XROF is output by switching with the command. 14 C2PO O 1, 0 G2PO output. MNT3 or GTOP is output by switching with the command. 15 SCOR O 1, 0 Outputs a high signal when either subcode sync S0 or S1 is detected. 16 C4M O 1, 0 4.2336MHz output. 1/4 frequency division output for V16M in CAV-W mode or variable pitch mode. 17 WDCK O 1, 0 Word clock output. f = 2Fs. GRSCOR is output by the command switching. 18 DVSS0 — — 19 COUT I/O 1, 0 Track count signal I/O. 20 MIRR I/O 1, 0 Mirror signal I/O. 21 DFCT I/O 1, 0 Detect signal I/O. 22 FOK I/O 1, 0 Focus OK signal I/O. 23 PWMI I 24 LOCK I/O 1, 0 25 MDP O 1, Z, 0 26 SSTP I 27 FSTO O 1, 0 28 DVDD1 — — 29 SFDR O 1, 0 Sled drive output. 30 SRDR O 1, 0 Sled drive output. 31 TFDR O 1, 0 Tracking drive output. 32 TRDR O 1, 0 Tracking drive output. 33 FFDR O 1, 0 Focus drive output. 34 FRDR O 1, 0 Focus drive output. 35 DVSS1 — — 1, 0 SENS output to CPU. SENS serial data readout clock input. Digital GND. Spindle motor external control input. GFS is sampled at 460Hz; when GFS is high, this pin outputs a high signal. If GFS is low eight consecutive samples, this pin outputs low. Input when LKIN = 1. Spindle motor servo control output. Disc innermost track detection signal input. 2/3 frequency division output for XTAI pin. Digital power supply. Digital GND. –4– CXD2585Q Pin No. Symbol 36 TEST I Test. Normally, GND. 37 TES1 I Test. Normally, GND. 38 VC I Center voltage input. 39 FE I Focus error signal input. 40 SE I Sled error signal input. 41 TE I Tracking error signal input. 42 CE I Center servo analog input. 43 RFDC I RF signal input. 44 ADIO O Analog 45 AVSS0 — — 46 IGEN I 47 AVDD0 — — 48 ASYO O 1, 0 49 ASYI I Asymmetry comparator voltage input. 50 RFAC I EFM signal input. 51 AVSS1 — 52 CLTV I 53 FILO O 54 FILI I 55 PCO O 1, Z, 0 56 AVDD1 — — 57 BIAS I Asymmetry circuit constant current input. 58 VCTL I Wide-band EFM PLL VCO2 control voltage input. 59 V16M I/O 1, 0 60 VPCO O 1, Z, 0 61 DVDD2 — — 62 ASYE I Asymmetry circuit on/off (low = off, high = on). 63 MD2 I Digital Out on/off control (low = off, high = on). 64 DOUT O 1, 0 Digital Out output. 65 LRCK O 1, 0 D/A interface. LR clock output. f = Fs 66 PCMD O 1, 0 D/A interface. Serial data output (two's complement, MSB first). 67 BCK O 1, 0 D/A interface. Bit clock output. 68 EMPH O 1, 0 Outputs a high signal when the playback disc has emphasis, and a low signal when there is no emphasis. 69 XTSL I 70 DVSS2 — I/O Description Test. No connected. Analog GND. Constant current input for operational amplifier. — Analog power supply. EFM full-swing output. (low = Vss, high = VDD) Analog GND. Multiplier VCO1 control voltage input. Analog Master PLL filter output (slave = digital PLL). Master PLL filter input. Master PLL charge pump output. Analog power supply. Wide-band EFM PLL VCO2 oscillation output. Serves as wide-band EFM PLL clock input by switching with the command. Wide-band EFM PLL charge pump output. Digital power supply. Crystal selection input. Low when the crystal is 16.9344MHz; high when it is 33.8688MHz. — Digital GND. –5– CXD2585Q Pin No. Symbol 71 XTAI I Crystal oscillation circuit input. When the master clock is input externally, input it from this pin. 72 XTAO O Crystal oscillation circuit output. 73 SOUT O 1, 0 Serial data output in servo block. 74 SOCK O 1, 0 Serial data readout clock output in servo block. 75 XOLT O 1, 0 Serial data latch output in servo block. 76 SQSO O 1, 0 Sub-Q 80-bit, PCM peak or level data outputs. CD TEXT data output. 77 SQCK I SQSO readout clock input. 78 SCSY I GRSCOR resynchronization input. 79 SBSO O 80 EXCK I I/O 1, 0 Description Sub-Q P to W serial output. SBSO readout clock input. Notes) • PCMD is a MSB first, two's complement output. • GTOP is used to monitor the frame sync protection status. (High: sync protection window released.) • XUGF is the frame sync obtained from the EFM signal, and is negative pulse. It is the signal before sync protection. • XPCK is the inverse of the EFM PLL clock. The PLL is designed so that the falling edge and the EFM signal transition point coincide. • The GFS signal goes high when the frame sync and the insertion protection timing match. • RFCK is derived from the crystal accuracy, and has a cycle of 136µs. (during normal speed) • C2PO represents the data error status. • XROF is generated when the 32K RAM exceeds the ±28F jitter margin. Combination of Monitor Pin Outputs Command bit Output data MTSL1 MTSL0 0 0 XUGF XPCK GFS C2PO 0 1 MNT0 MNT1 MNT2 MNT3 1 0 RFCK XPCK XROF GTOP –6– CXD2585Q Electrical Characteristics 1. DC Characteristics (VDD = AVDD = 5.0V ± 5%, Vss = AVss = 0V, Topr = –20 to +75°C) Item Input voltage (1) High level input voltage VIH (1) Low level input voltage Input voltage (2) Input voltage (3) Output voltage (1) Conditions VIL (1) Max. High level input voltage VIH (2) Schmitt input Low level input voltage VIL (2) Input voltage VIN (3) Analog input High level output voltage VOH (1) IOH = –2mA High level output voltage VOH (2) IOH = –6mA Unit V 0.3VDD Low level output voltage VOL (2) IOL = 4mA Output voltage (3) Typ. 0.7VDD Low level output voltage VOL (1) IOL = 4mA Output voltage (2) Min. ∗1, ∗9 V V 0.8VDD Applicable pins ∗2, ∗10 0.2VDD V VSS VDD V ∗3, ∗7, ∗8 VDD – 0.8 VDD V ∗4 VSS 0.4 V VDD – 0.8 VDD V VSS 0.4 V VDD V High level output voltage VOH (3) IOH = –0.28mA VDD – 0.5 ∗5 ∗6 VOL (3) IOL = 0.36mA VSS 0.4 V Input leak current (1) ILI (1) VIN = VSS or VDD –10 10 µA ∗1, ∗2 Input leak current (2) ILI (2) VIN = VSS or VDD –40 40 µA ∗9, ∗10 Input leak current (3) ILI (3) VI = 1.5 to 3.5V –20 20 µA ∗7 Input leak current (4) ILI (4) VI = 0 to 5.0V –40 600 µA ∗8 Low level output voltag Applicable pins ∗1 MUTE, DATA, XLAT, SSTP, TEST, TES1, MD2, XTSL, SCSY ∗2 SQCK, XRST, CLOK, ASYE ∗3 ASYI, RFAC, CLTV, FILI, VCTL ∗4 SQSO, SBSO, SENS, ATSK, WFCK, XUGF, XPCK, GFS, C2PO, SCOR, C4M, WDCK, COUT, MIRR, DFCT, FOK, LOCK, FSTO, SFDR, SRDR, TFDR, TRDR, FFDR, FRDR, ASYO, V16M, DOUT, LRCK, PCMD, BCK, EMPH, SOUT, SOCK, XOLT ∗5 MDP, PCO, VPCO ∗6 FILO ∗7 VC, FE, SE, TE, CE ∗8 RFDC ∗9 PWMI, EXCK, ATSK, COUT, MIRR, DFCT, FOK, LOCK, V16M ∗10 SCLK, FSTO –7– CXD2585Q 2. AC Characteristics (1) XTAI pin (a) When using self-excited oscillation (Topr = –20 to +75°C, VDD = AVDD = 5.0V ± 5%) Item Symbol Oscillation frequency fMAX Min. Typ. 7 Max. Unit 34 MHz (b) When inputting pulses to XTAI pin (Topr = –20 to +75°C, VDD = AVDD = 5.0V ± 5%) Item Symbol Min. Typ. Max. Unit High level pulse width tWHX 13 500 ns Low level pulse width tWLX 13 500 ns Pulse cycle tCX 26 1000 ns Input high level VIHX VDD – 1.0 Input low level VILX 0.8 V Rise time, fall time tR, tF 10 ns V tCX tWLX tWHX VIHX VIHX × 0.9 XTAI VDD/2 VIHX × 0.1 VILX tR tF (c) When inputting sine waves to XTAI pin via a capacitor (Topr = –20 to +75°C, VDD = AVDD = 5.0V ± 5%) Item Input amplitude Symbol Min. VI 2.0 Typ. Max. Unit VDD + 0.3 Vp-p –8– CXD2585Q (2) CLOK, DATA, XLAT, SQCK and EXCK pins (VDD = AVDD = 5.0V ± 5%, VSS = AVSS = 0V, Topr = –20 to +75°C) Item Symbol Min. Typ. Max. Unit 0.65 MHz Clock frequency fCK Clock pulse width tWCK 750 ns Setup time tSU 300 ns Hold time tH 300 ns Delay time tD 300 ns Latch pulse width tWL 750 ns EXCK SQCK frequency fT EXCK SQCK pulse width tWT COUT frequency (for input) ∗ fT COUT pulse width (for input) ∗ tWT 0.65 ns 750 65 1/fCK tWCK tWCK CLOK DATA tSU tH tD tWL EXCK SQCK COUT tWT tWT 1/fT SBSO SQSO tSU kHz µs 7.5 ∗ Only when $44 and $45 are executed. XLAT MHz tH –9– CXD2585Q (3) SCLK pin XLAT tDLS tSPW ••• SCLK 1/fSCLK Serial Read Out Data (SENS) Item ••• MSB Symbol Min. Typ. Max. Unit 16 MHz SCLK frequency fSCLK SCLK pulse width tSPW 31.3 ns Delay time tDLS 15 µs (4) COUT, MIRR and DFCT pins Operating frequency LSB (VDD = AVDD = 5.0V ± 5%, VSS = AVSS = 0V, Topr = –20 to +75°C) Signal Symbol Min. Typ. Max. Unit Conditions COUT maximum operating frequency fCOUT 40 kHz ∗1 MIRR maximum operating frequency fMIRR 40 kHz ∗2 DFCT maximum operating frequency fDFCTH 5 kHz ∗3 ∗1 When using a high-speed traverse TZC. ∗2 B A When the RF signal continuously satisfies the following conditions during the above traverse. • A = 0.12VDD to 0.26VDD B • ≤ 25% A+B ∗3 During complete RF signal omission. When settings related to DFCT signal generation are Typ. – 10 – CXD2585Q Contents [1] CPU Interface § 1-1. CPU Interface Timing .................................................................................................................... § 1-2. CPU Interface Command Table .................................................................................................... § 1-3. CPU Command Presets ................................................................................................................ § 1-4. Description of SENS Signals ......................................................................................................... 12 12 23 29 [2] Subcode Interface § 2-1. P to W Subcode Readout .............................................................................................................. 53 § 2-2. 80-bit Sub-Q Readout.................................................................................................................... 53 [3] Description of Modes § 3-1. CLV-N Mode.................................................................................................................................. § 3-2. CLV-W Mode ................................................................................................................................. § 3-3. CAV-W Mode................................................................................................................................. § 3-4. VCO-C mode ................................................................................................................................. 60 60 60 61 [4] Description of Other Functions § 4-1. Channel Clock Regeneration by Digital PLL Circuit ...................................................................... § 4-2. Frame Sync Protection .................................................................................................................. § 4-3. Error Correction ............................................................................................................................. § 4-4. DA Interface................................................................................................................................... § 4-5. Digital Out...................................................................................................................................... § 4-6. Servo Auto Sequence.................................................................................................................... § 4-7. Digital CLV..................................................................................................................................... § 4-8. Playback Speed............................................................................................................................. § 4-9. Asymmetry Correction ................................................................................................................... § 4-10. CD TEXT Data Demodulation ....................................................................................................... 64 66 66 67 69 70 78 79 80 81 [5] Description of Servo Signal Processing System Functions and Commands § 5-1. General Description of Servo Signal Processing System.............................................................. 83 § 5-2. Digital Servo Block Master Clock (MCK) ....................................................................................... 84 § 5-3. DC Offset Cancel [AVRG Measurement and Compensation] ....................................................... 85 § 5-4. E: F Balance Adjustment Function ................................................................................................ 86 § 5-5. FCS Bias Adjustment Function...................................................................................................... 86 § 5-6. AGCNTL Function ......................................................................................................................... 88 § 5-7. FCS Servo and FCS Search ......................................................................................................... 90 § 5-8. TRK and SLD Servo Control ......................................................................................................... 91 § 5-9. MIRR and DFCT Signal Generation .............................................................................................. 92 § 5-10. DFCT Countermeasure Circuit ...................................................................................................... 93 § 5-11. Anti-Shock Circuit .......................................................................................................................... 93 § 5-12. Brake Circuit .................................................................................................................................. 94 § 5-13. COUT Signal ................................................................................................................................. 95 § 5-14. Serial Readout Circuit.................................................................................................................... 95 § 5-15. Writing to Coefficient RAM ............................................................................................................ 96 § 5-16. PWM Output .................................................................................................................................. 96 § 5-17. Servo Status Changes Produced by LOCK Signal........................................................................ 97 § 5-18. Description of Commands and Data Sets ..................................................................................... 97 § 5-19. List of Servo Filter Coefficients...................................................................................................... 117 § 5-20. Filter Composition.......................................................................................................................... 119 § 5-21. TRACKING and FOCUS Frequency Response ............................................................................ 125 [6] Application Circuit .................................................................................................................................. 126 Explanation of abbreviations AVRG: AGCNTL: FCS: TRK: SLD: DFCT: Average Auto gain control Focus Tracking Sled Defect – 11 – CXD2585Q [1] CPU Interface § 1-1. CPU Interface Timing • CPU interface This interface uses DATA, CLOK and XLAT to set the modes. The interface timing chart is shown below. 750ns or more CLOK DATA D0 D1 D18 D19 D20 D21 D22 D23 750ns or more XLAT Registers Valid • The internal registers are initialized by a reset when XRST = 0. § 1-2. CPU Interface Command Table Total bit length for each register Register Total bit length 0 to 2 8 bits 3 8 to 24 bits 4 to 6 16 bits 7 20 bits 8 28 bits 9 28 bits A 28 bits B 24 bits C 28 bits D 20 bits E 20 bits – 12 – 1 FOCUS CONTROL 0 TRACKING CONTROL Command Register 0001 0000 – 13 – — — — — — — — 0 — — 1 — — 1 0 1 — — — — — — — 0 — — — — 0 1 — — 1 1 — 0 0 — 0 1 — 0 — — — — — — — — — — — — 0 — 0 1 — — — 1 1 — — — — 0 1 0 D15 D16 D17 Data 1 D18 D23 to D20 D19 Address Command Table ($0X to 1X) — — — — — — — — — — — — — — — — — — — — — — — — — — — — D13 D14 Data 2 — — — — — — — — — — — — — — D12 — — — — — — — — — — — — — — D11 — — — — — — — — — — — — — — D10 — — — — — — — — — — — — — — D9 Data 3 — — — — — — — — — — — — — — D8 — — — — — — — — — — — — — — D7 — — — — — — — — — — — — — — D6 — — — — — — — — — — — — — — D5 Data 4 — — — — — — — — — — — — — — D4 — — — — — — — — — — — — — — D3 — — — — — — — — — — — — — — D2 — — — — — — — — — — — — — — D1 Data 5 — — — — — — — — — — — — — — D0 —: Don't care TRACKING GAIN UP FILTER SELECT 2 TRACKING GAIN UP FILTER SELECT 1 TRACKING GAIN UP TRACKING GAIN NORMAL BRAKE OFF BRAKE ON ANTI SHOCK OFF ANTI SHOCK ON FOCUS SEACH VOLTAGE UP FOCUS SEARCH VOLTAGE DOWN FOCUS SERVO OFF, FOCUS SEARCH VOLTAGE OUT FOCUS SERVO OFF, 0V OUT FOCUS SERVO ON (FOCUS GAIN DOWN) FOCUS SERVO ON (FOCUS GAIN NORMAL) CXD2585Q – 14 – 3 SELECT Command TRACKING MODE 2 Register Command Register 0011 0 0 0 0 0 0 0 D18 0 D23 to D20 D19 — — — — — — 1 1 — 0 1 — 1 0 Address 0010 0 D18 1 1 1 0 0 D17 1 0 1 0 D16 Data 1 1 0 1 — — 1 — — 0 — — 0 — — 0 D16 D17 Data 1 0 D23 to D20 D19 Address Command Table ($2X to 3X) — — — — D15 — — — — — — — — D15 — — — — — — — — D13 — — — — D14 — — — — D13 Data 2 — — — — — — — — D14 Data 2 — — — — D12 — — — — — — — — D12 — — — — D11 — — — — — — — — D11 — — — — — — — — D9 — — — — D10 — — — — D9 Data 3 — — — — — — — — D10 Data 3 — — — — D8 — — — — — — — — D8 — — — — D7 — — — — — — — — D7 — — — — — — — — D5 — — — — D6 — — — — D5 Data 4 — — — — — — — — D6 Data 4 — — — — D4 — — — — — — — — D4 — — — — D3 — — — — — — — — D3 — — — — — — — — D1 — — — — D2 — — — — D1 Data 5 — — — — — — — — D2 Data 5 — — — — D0 — — — — — — — — D0 —: Don't care SLED KICK LEVEL (±4 × basic value) SLED KICK LEVEL (±3 × basic value) SLED KICK LEVEL (±2 × basic value) SLED KICK LEVEL (±1 × basic value) (Default) REVERSE SLED MOVE FORWARD SLED MOVE SLED SERVO ON SLED SERVO OFF REVERSE TRACK JUMP FORWARD TRACK JUMP TRACKING SERVO ON TRACKING SERVO OFF CXD2585Q 3 Register SELECT Command Address 2 Address 3 0011 0100 0000 0 0 1 1 1 0 0 0 0 0 – 15 – 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 D10 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 D9 Address 4 0 D23 to D20 D19 to D16 D15 to D12 D11 Address 1 Command Table ($340X) 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 D8 KRAM DATA (K08) FOCUS HIGH CUT FILTER A KRAM DATA (K09) FOCUS HIGH CUT FILTER B KRAM DATA (K0A) FOCUS LOW BOOST FILTER A-H KRAM DATA (K0B) FOCUS LOW BOOST FILTER A-L KRAM DATA (K0C) FOCUS LOW BOOST FILTER B-H KRAM DATA (K0D) FOCUS LOW BOOST FILTER B-L KRAM DATA (K0E) FOCUS PHASE COMPENSATE FILTER A KRAM DATA (K0F) FOCUS DEFECT HOLD GAIN KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KRAM DATA (K06) FOCUS INPUT GAIN KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KRAM DATA (K05) SLED OUTPUT GAIN KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KRAM DATA (K07) SLED AUTO GAIN KRAM DATA (K04) SLED LOW BOOST FILTER B-L KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KRAM DATA (K03) SLED LOW BOOST FILTER B-H D0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 D1 KRAM DATA (K02) SLED LOW BOOST FILTER A-L D2 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 D3 KRAM DATA (K01) SLED LOW BOOST FILTER A-H D4 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 D5 KRAM DATA (K00) SLED INPUT GAIN D6 Data 2 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 D7 Data 1 CXD2585Q 3 Register SELECT Command Address 2 Address 3 0011 0100 0001 0 0 1 1 1 0 0 0 0 0 – 16 – 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 D10 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 D9 Address 4 0 D23 to D20 D19 to D16 D15 to D12 D11 Address 1 Command Table ($341X) 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 D8 D6 D5 D4 D3 D2 D1 Data 2 D0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 D7 Data 1 KRAM DATA (K1F) TRACKING LOW BOOST FILTER B-L KRAM DATA (K1E) TRACKING LOW BOOST FILTER B-H KRAM DATA (K1D) TRACKING LOW BOOST FILTER A-L KRAM DATA (K1C) TRACKING LOW BOOST FILTER A-H KRAM DATA (K1B) TRACKING HIGH CUT FILTER B KRAM DATA (K1A) TRACKING HIGH CUT FILTER A KRAM DATA (K19) TRACKING INPUT GAIN KRAM DATA (K18) FIX KRAM DATA (K17) HPTZC / AUTO GAIN LOW PASS FILTER B KRAM DATA (K16) ANTI SHOCK HIGH PASS FILTER A KRAM DATA (K15) HPTZC / AUTO GAIN HIGH PASS FILTER B KRAM DATA (K14) HPTZC / AUTO GAIN HIGH PASS FILTER A KRAM DATA (K13) FOCUS AUTO GAIN KRAM DATA (K12) ANTI SHOCK INPUT GAIN KRAM DATA (K11) FOCUS OUTPUT GAIN KRAM DATA (K10) FOCUS PHASE COMPENSATE FILTER B CXD2585Q 3 Register SELECT Command Address 2 Address 3 0011 0100 0010 0 0 1 1 1 0 0 0 0 0 – 17 – 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 D10 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 D9 Address 4 0 D23 to D20 D19 to D16 D15 to D12 D11 Address 1 Command Table ($342X) 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 D8 D6 D5 D4 D3 D2 D1 Data 2 D0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 D7 Data 1 KRAM DATA (K2F) NOT USED KRAM DATA (K2E) NOT USED KRAM DATA (K2D) FOCUS GAIN DOWN OUTPUT GAIN KRAM DATA (K2C) FOCUS GAIN DOWN PHASE COMPENSATE FILTER B KRAM DATA (K2B) FOCUS GAIN DOWN DEFECT HOLD GAIN KRAM DATA (K2A) FOCUS GAIN DOWN PHASE COMPENSATE FILTER A KRAM DATA (K29) FOCUS GAIN DOWN LOW BOOST FILTER B-L KRAM DATA (K28) FOCUS GAIN DOWN LOW BOOST FILTER B-H KRAM DATA (K27) FOCUS GAIN DOWN LOW BOOST FILTER A-L KRAM DATA (K26) FOCUS GAIN DOWN LOW BOOST FILTER A-H KRAM DATA (K25) FOCUS GAIN DOWN HIGH CUT FILTER B KRAM DATA (K24) FOCUS GAIN DOWN HIGH CUT FILTER A KRAM DATA (K23) TRACKING AUTO GAIN KRAM DATA (K22) TRACKING OUTPUT GAIN KRAM DATA (K21) TRACKING PHASE COMPENSATE FILTER B KRAM DATA (K20) TRACKING PHASE COMPENSATE FILTER A CXD2585Q 3 Register SELECT Command Address 2 Address 3 0011 0100 0011 0 0 1 1 1 0 0 0 0 0 – 18 – 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 D10 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 D9 Address 4 0 D23 to D20 D19 to D16 D15 to D12 D11 Address 1 Command Table ($343X) 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 D8 D6 D5 D4 D3 D2 D1 Data 2 D0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 D7 Data 1 KRAM DATA (K3F) NOT USED KRAM DATA (K3E) TRACKING GAIN UP OUTPUT GAIN KRAM DATA (K3D) TRACKING GAIN UP PHASE COMPENSATE FILTER B KRAM DATA (K3C) TRACKING GAIN UP PHASE COMPENSATE FILTER A KRAM DATA (K3B) TRACKING GAIN UP2 LOW BOOST FILTER B-L KRAM DATA (K3A) TRACKING GAIN UP2 LOW BOOST FILTER B-H KRAM DATA (K39) TRACKING GAIN UP2 LOW BOOST FILTER A-L KRAM DATA (K38) TRACKING GAIN UP2 LOW BOOST FILTER A-H KRAM DATA (K37) TRACKING GAIN UP2 HIGH CUT FILTER B KRAM DATA (K36) TRACKING GAIN UP2 HIGH CUT FILTER A KRAM DATA (K35) ANTI SHOCK FILTER COMPARATE GAIN KRAM DATA (K34) ANTI SHOCK HIGH PASS FILTER B-L KRAM DATA (K33) ANTI SHOCK HIGH PASS FILTER B-H KRAM DATA (K32) NOT USED KRAM DATA (K31) ANTI SHOCK LOW PASS FILTER B KRAM DATA (K30) SLED INPUT GAIN (when TGup2 is accessed with SFSK = 1) CXD2585Q 3 Register SELECT Command Address 2 Address 3 0011 0100 0100 0 0 1 1 1 0 0 0 0 0 – 19 – 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 D10 1 0 1 0 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 0 1 1 0 0 1 1 1 0 0 1 D8 D9 Address 4 0 D23 to D20 D19 to D16 D15 to D12 D11 Address 1 Command Table ($344X) D6 D5 D4 D3 D2 D1 Data 2 D0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KRAM DATA (K4F) NOT USED KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KRAM DATA (K4E) NOT USED KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KRAM DATA (K4D) FOCUS HOLD FILTER OUTPUT GAIN KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KRAM DATA (K4C) FOCUS HOLD FILTER B-L KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KRAM DATA (K4B) FOCUS HOLD FILTER B-H KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KRAM DATA (K4A) FOCUS HOLD FILTER A-L KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KRAM DATA (K49) FOCUS HOLD FILTER A-H KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KRAM DATA (K48) FOCUS HOLD FILTER INPUT GAIN KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KRAM DATA (K47) NOT USED KRAM DATA (K46) KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 TRACKING HOLD INPUT GAIN (when TGup2 is accessed with THSK = 1) KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KRAM DATA (K45) TRACKING HOLD FILTER OUTPUT GAIN KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KRAM DATA (K44) TRACKING HOLD FILTER B-L KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KRAM DATA (K43) TRACKING HOLD FILTER B-H KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KRAM DATA (K42) TRACKING HOLD FILTER A-L KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KRAM DATA (K41) TRACKING HOLD FILTER A-H KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KRAM DATA (K40) TRACKING HOLD FILTER INPUT GAIN D7 Data 1 CXD2585Q 3 Register SELECT Command 0011 0 D23 to D20 D19 1 D18 Address 1 Command Table ($348X to 34FX) 0 D17 0 D16 0 0 1 1 1 1 1 1 1 1 0 1 0 1 0 D12 Address 2 1 0 0 1 0 D13 1 1 1 1 D15 D14 D13 D12 D14 D15 Address 2 D7 0 D8 D7 0 0 D6 0 0 D4 0 0 D3 0 0 D2 0 0 D1 Data 3 FB8 TV8 FB9 TV9 0 0 – 20 – TV7 FB7 TV6 FB6 0 0 D0 Booster Surf Brake PGFS, PFOK, RFAC 0 0 D5 D4 0 0 D3 0 0 0 0 D2 D1 Data 3 0 0 TV5 TV4 FB5 FB4 TV3 FB3 TV2 TV1 FB2 FB1 TV0 — — D0 0 0 —: Don't care Traverse Center Data FCS Bias Data FCS Bias Limit HBST HBST LB1S LB1S LB2S LB2S Booster 1 0 1 0 1 0 0 0 D5 Data 2 0 0 0 0 0 D6 Data 2 FBL9 FBL8 FBL7 FBL6 FBL5 FBL4 FBL3 FBL2 FBL1 D9 1 0 1 0 0 Data 1 0 0 0 D10 0 0 D11 0 0 THB FHB TLB1 FLB1 TLB2 ON ON ON ON ON 0 0 D8 SFBK SFBK 1 2 D9 0 D10 PGFS PGFS RFOK RFOK 1 0 0 1 D11 Data 1 CXD2585Q 3 Register SELECT Command 0011 0 1 1 1 1 1 1 1 1 1 0 0 1 1 1 0 0 1 0 1 1 D18 0 D23 to D20 D19 Address Command Table ($35X to 3FX) – 21 – 1 1 0 0 1 1 0 0 1 1 0 D17 1 0 1 0 1 0 1 0 1 0 1 D16 TJ4 D10 D9 D8 TJ3 TJ2 TJ1 D6 D5 D4 D3 D2 D1 Data 4 D0 FTZ FG6 FG5 FG4 FG3 FG2 FG1 FG0 D7 Data 3 TJ0 SFJP TG6 TG5 TG4 TG3 TG2 TG1 TG0 FS3 FS2 FS1 FS0 D11 Data 2 TRK jump, AGT FCS search, AGF FBON FBSS FBUP FBV1 FBV0 0 0 0 0 TJD0 FPS1 FPS0 TPS1 TPS0 0 0 0 0 TLD2 TLD1 TLD0 0 0 0 0 AGC4 XT4D XT2D 0 DRR2 DRR1 DRR0 0 0 0 0 0 Serial data read out 0 0 0 0 0 0 0 0 0 SLD filter TZC, Cout, Bottom, Mirr Mirr, DFCT, FOK SJHD INBK MTI0 FCS Bias, Gain, Surf jump/brake 0 0 0 AGHF ASOT Clock, others LKIN COIN MDFI MIRI XT1D Filter 0 ASFG FTQ LPAS 0 0 BTS1 BTS0 MRC1 MRC0 F1NM F1DM F3NM F3DM TINM TIUM T3NM T3UM DF1S TLCD SFID SFSK THID THSK COSS COTS CETZ CETF COT2 COT1 MOT2 SFO2 SFO1 SDF2 SDF1 MAX2 MAX1 SFOX BTF D2V2 D2V1 D1V2 D1V1 RINT 0 DAC SD6 SD5 SD4 SD3 SD2 SD1 SD0 VCLM VCLC FLM FLC0 RFLM RFLC AGF AGT DFSW LKSW TBLM TCLM FLC1 TLC2 TLC1 TLC0 DC measure, cancel FZSH FZSL SM5 SM4 SM3 SM2 SM1 SM0 AGS AGJ AGGF AGGT AGV1 AGV2 AGHS AGHT FZC, AGC, SLD move FT1 TDZC DTZC TJ5 D13 D12 FS4 D14 FT0 FS5 D15 Data 1 CXD2585Q 0 0 1 1 1 0 0 1 1 1 1 1 1 1 Sled KICK, BRAKE (D), KICK (F) Auto sequence (N) track jump count setting MODE specification Function specification Audio CTRL Traverse monitor counter setting Spindle servo coefficient setting CLV CTRL SPD mode 6 7 8 9 A B – 22 – C D E 0 0 1 1 1 0 Blind (A, E), Brake (B), Overflow (C, G) 5 1 0 D26 D27 1 0 0 1 1 0 0 1 1 0 0 D25 Address Auto sequence Command 4 Register Command Table ($4X to EX) 0 1 0 1 0 1 0 1 0 1 0 D24 SD2 TR2 AS2 D22 1024 KF2 0 MT2 D18 512 KF1 0 MT1 D17 KF0 0 MT0 D16 0 0 LSSL D15 VARI USE 4096 ATT 1 2048 1024 PCT1 PCT2 512 0 BiliGL BiliGL FLFC MAIN SUB 256 SOC2 1 128 0 0 CM3 0 CM2 TB CM1 TP VP7 VP6 VP5 CM0 EPWM SPDC ICAP CLVS Gain VP3 SFSL VC2C VP4 Gain Gain Gain Gain Gain Gain PCC1 PCC0 SFP3 MDP1 MDP0 MDS1 MDS0 DCLV1 DCLV0 8192 Mute DSPB ASEQ ON/OFF ON/OFF 32768 16384 VARI ON 1 KSL3 2048 KF3 0 MT3 D19 VCO VCO CD- DOUT DOUT WSEL ASHS SOCT0 SEL1 SEL2 ROM Mute Mute-F 4096 SD0 TR0 AS0 D20 128 8192 SD1 TR1 AS1 D21 Data 2 256 32768 16384 SD3 TR3 AS3 D23 Data 1 VP1 SFP1 32 0 0 KSL1 32 0 0 0 D13 8 0 1 0 8 — — — D11 4 1 0 0 4 — — — D10 1 0 0 THRU XVCO2 2 — — — D9 Data 4 1 0 1 0 1 — — — D8 VP0 0 Gain Gain CAV1 CAV0 INV VPCO 0 —: Don't care 0 VP CTL0 VP CTL1 SFP0 SRP3 SRP2 SRP1 SRP0 16 0 0 KSL0 16 0 0 0 D12 HIFC LPWR VPON VP2 SFP2 64 0 0 KSL2 64 0 0 0 D14 Data 3 CXD2585Q 1 0 0 1 1 0 1 0 1 0 1 1 Function specification Audio CTRL Traverse monitor counter setting Spindle servo coefficient setting 9 A B C Data 1 – 23 – 0010 TRACKING MODE Command 2 Register SELECT 0001 TRACKING CONTROL 1 3 0000 FOCUS CONTROL 0 0011 0 D18 0 0 0 D18 0 1 D18 0 1 0 D16 0 D17 0 D17 0 D16 0 D16 Data 1 0 0 0 D17 Data 1 Address 1 0 D23 to D20 D19 0011 D23 to D20 D19 Address 0 0 0 D23 to D20 D19 Command Register Address Command Preset Table ($0X to 34X) § 1-3. CPU Command Presets 1 0 0 0 Address MODE specification Command 8 Register Command Table ($4X to EX) cont. 0 D15 — D15 — — — D15 — — — — D13 D14 D13 Address 2 — D14 Data 2 — — — D12 — D12 — — — D12 Data 3 D13 Data 2 D14 Data 2 D11 — D11 — — — D11 — — — D9 — D9 D9 D5 D4 D3 D2 D1 D0 0 0 0 0 0 MTSL1 MTSL0 0 0 — 0 0 — 0 0 — 0 0 — 0 0 SCOR SCSY SOCT1 TXON TXOUT OUTLI OUTL0 SEL D6 Data 6 D8 — D8 — — — D8 D7 — D7 — — — D7 — — — D5 — D5 D6 D5 Data 1 — D6 Data 4 — — — D6 Data 4 D4 — D4 — — — D4 D3 — D3 — — — D3 — — — D1 — D0 D2 D0 Data 2 — D2 Data 5 — — — D2 Data 5 D0 — D0 — — — D0 —: Don't care KRAM DATA ($3400XX to $344fXX) SLED KICK LEVEL (±1 × basic value) (Default) TRACKING SERVO OFF SLED SERVO OFF TRACKING GAIN UP FILTER SELECT 1 FOCUS SERVO OFF, 0V OUT —: Don't care EDC7 EDC6 EDC5 EDC4 EDC3 EDC2 EDC1 EDC0 0 0 0 ERC4 D7 Data 5 See "Coefficient ROM Preset Values Table". D10 Address 3 — D10 Data 3 — — — D10 Data 3 Data 4 CXD2585Q 3 Register SELECT Command 0011 0 D23 to D20 D19 1 D18 Address 1 0 D17 Command Preset Table ($348X to 34FX) 0 D16 0 0 1 1 1 1 1 1 1 1 0 1 0 1 0 D12 Address 2 1 0 0 1 0 D13 1 1 1 1 D15 D14 D13 D12 D14 D15 Address 2 1 0 0 0 1 0 D10 0 0 0 0 0 D10 D11 0 0 0 0 0 D11 0 0 0 0 0 D8 – 24 – 0 0 0 D9 0 0 0 D8 Data 1 0 0 0 0 0 D9 Data 1 0 0 0 D7 0 0 0 0 0 D7 0 0 0 0 0 D5 0 0 0 D6 0 0 0 D5 Data 2 0 0 0 0 0 D6 Data 2 0 0 0 D4 0 0 0 0 0 D4 0 0 0 D3 0 0 0 0 0 D3 0 0 0 0 0 D1 0 0 0 D2 0 0 0 D1 Data 3 0 0 0 0 0 D2 Data 3 0 0 0 D0 0 0 0 0 0 D0 Traverse Center Data FCS Bias Data FCS Bias Limit Booster Booster Surf Brake PGFS, PFOK, RFAC CXD2585Q 3 Register SELECT Command 0011 0 1 1 1 1 1 1 1 1 1 0 0 1 1 1 0 0 1 0 1 1 D18 0 D23 to D20 D19 Address Command Preset Table ($35X to 3FX) – 25 – 1 1 0 0 1 1 0 0 1 1 0 D17 1 0 1 0 1 0 1 0 1 0 1 D16 0 0 0 0 1 0 0 0 0 0 0 D15 0 0 0 0 1 0 0 0 1 0 1 D14 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 D13 D12 Data 1 0 0 0 0 0 0 0 0 0 1 1 D11 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 D9 D10 Data 2 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 D7 D8 0 0 0 0 1 0 0 0 0 0 0 D6 0 0 0 0 0 0 0 0 1 1 1 D5 Data 3 0 0 0 0 1 0 0 0 1 0 0 D4 0 0 0 0 0 0 0 0 1 1 1 D3 0 0 0 0 0 0 0 0 0 1 1 D2 0 0 0 0 0 0 0 0 1 1 0 D1 Data 4 0 0 0 0 0 0 0 0 0 0 1 D0 Clock, others Filter SLD filter TZC, Cout, Bottom, Mirr Mirr, DFCT, FOK FCS Bias, Gain, Surf jump/brake Serial data read out DC measure, cancel FZC, AGC, SLD move TRK jump, AGT FCS search, AGF CXD2585Q – 26 – 1 SPD mode E Address 1 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 MODE specification Function specification Audio CTRL Traverse monitor counter setting Spindle servo coefficient setting 8 9 A B C 1 1 1 0 0 0 0 1 1 1 1 D26 0 1 0 1 0 1 0 1 0 1 0 D24 Data 1 1 0 0 1 1 0 0 1 1 0 0 D25 Address Command Register 1 CLV CTRL D 1 Audio CTRL A 1 1 Function specification 9 Spindle servo coefficient setting 1 MODE specification 8 C 0 Auto sequence (N) track jump count setting 7 1 0 Sled KICK, BRAKE (D), KICK (F) 6 Traverse monitor counter setting 0 Blind (A, E), Brake (B), Overflow (C, G) 5 B 0 Auto sequence 4 D27 Command Register Command Preset Table ($4X to EX) 0 0 0 0 0 0 0 0 1 1 0 D22 Data 2 0 0 0 0 0 1 0 0 0 0 0 D23 0 0 0 0 1 1 0 0 1 1 0 D20 Data 3 0 0 0 0 1 0 0 0 1 0 0 D21 Data 1 0 0 0 0 0 0 0 0 0 0 0 D18 Data 4 0 0 0 0 0 0 0 0 0 0 0 D19 0 0 0 0 0 D7 0 0 0 0 0 0 0 0 0 0 0 D17 Data 2 0 0 0 0 0 0 0 0 D5 0 0 D6 0 0 1 0 0 0 0 0 0 0 0 D15 Data 5 0 0 0 1 0 1 0 1 0 0 0 D16 0 0 — 0 — 0 0 0 0 0 0 D2 0 — 0 0 0 D1 0 0 0 0 0 1 0 0 — — — D11 Data 6 0 0 0 0 0 0 0 0 0 0 0 D12 0 0 D3 0 0 0 0 0 0 0 0 0 0 0 D13 0 0 D4 0 0 1 0 0 0 0 0 0 0 0 D14 Data 3 0 — 0 0 0 D0 0 0 0 0 1 0 0 0 — — — D10 0 0 1 0 0 1 0 0 — — — D8 —: Don't care 0 0 1 0 0 0 0 0 — — — D9 Data 4 CXD2585Q CXD2585Q <Coefficient ROM Preset Values Table (1)> ADDRESS DATA K00 K01 K02 K03 K04 K05 K06 K07 K08 K09 K0A K0B K0C K0D K0E K0F E0 81 23 7F 6A 10 14 30 7F 46 81 1C 7F 58 82 7F SLED INPUT GAIN SLED LOW BOOST FILTER A-H SLED LOW BOOST FILTER A-L SLED LOW BOOST FILTER B-H SLED LOW BOOST FILTER B-L SLED OUTPUT GAIN FOCUS INPUT GAIN SLED AUTO GAIN FOCUS HIGH CUT FILTER A FOCUS HIGH CUT FILTER B FOCUS LOW BOOST FILTER A-H FOCUS LOW BOOST FILTER A-L FOCUS LOW BOOST FILTER B-H FOCUS LOW BOOST FILTER B-L FOCUS PHASE COMPENSATE FILTER A FOCUS DEFECT HOLD GAIN K10 K11 K12 K13 K14 K15 K16 K17 K18 K19 K1A K1B K1C K1D K1E K1F 4E 32 20 30 80 77 80 77 00 F1 7F 3B 81 44 7F 5E FOCUS PHASE COMPENSATE FILTER B FOCUS OUTPUT GAIN ANTI SHOCK INPUT GAIN FOCUS AUTO GAIN HPTZC / Auto Gain HIGH PASS FILTER A HPTZC / Auto Gain HIGH PASS FILTER B ANTI SHOCK HIGH PASS FILTER A HPTZC / Auto Gain LOW PASS FILTER B Fix∗ TRACKING INPUT GAIN TRACKING HIGH CUT FILTER A TRACKING HIGH CUT FILTER B TRACKING LOW BOOST FILTER A-H TRACKING LOW BOOST FILTER A-L TRACKING LOW BOOST FILTER B-H TRACKING LOW BOOST FILTER B-L K20 K21 K22 K23 K24 K25 K26 K27 K28 K29 K2A K2B K2C K2D K2E K2F 82 44 18 30 7F 46 81 3A 7F 66 82 44 4E 1B 00 00 TRACKING PHASE COMPENSATE FILTER A TRACKING PHASE COMPENSATE FILTER B TRACKING OUTPUT GAIN TRACKING AUTO GAIN FOCUS GAIN DOWN HIGH CUT FILTER A FOCUS GAIN DOWN HIGH CUT FILTER B FOCUS GAIN DOWN LOW BOOST FILTER A-H FOCUS GAIN DOWN LOW BOOST FILTER A-L FOCUS GAIN DOWN LOW BOOST FILTER B-H FOCUS GAIN DOWN LOW BOOST FILTER B-L FOCUS GAIN DOWN PHASE COMPENSATE FILTER A FOCUS GAIN DOWN DEFECT HOLD GAIN FOCUS GAIN DOWN PHASE COMPENSATE FILTER B FOCUS GAIN DOWN OUTPUT GAIN NOT USED NOT USED CONTENTS ∗ Fix indicates that normal preset values should be used. – 27 – CXD2585Q <Coefficient ROM Preset Values Table (2)> ADDRESS DATA K30 K31 K32 K33 K34 K35 K36 K37 K38 K39 K3A K3B K3C K3D K3E K3F 80 66 00 7F 6E 20 7F 3B 80 44 7F 77 86 0D 57 00 SLED INPUT GAIN (Only when TRK Gain Up2 is accessed with SFSK = 1.) ANTI SHOCK LOW PASS FILTER B NOT USED ANTI SHOCK HIGH PASS FILTER B-H ANTI SHOCK HIGH PASS FILTER B-L ANTI SHOCK FILTER COMPARATE GAIN TRACKING GAIN UP2 HIGH CUT FILTER A TRACKING GAIN UP2 HIGH CUT FILTER B TRACKING GAIN UP2 LOW BOOST FILTER A-H TRACKING GAIN UP2 LOW BOOST FILTER A-L TRACKING GAIN UP2 LOW BOOST FILTER B-H TRACKING GAIN UP2 LOW BOOST FILTER B-L TRACKING GAIN UP PHASE COMPENSATE FILTER A TRACKING GAIN UP PHASE COMPENSATE FILTER B TRACKING GAIN UP OUTPUT GAIN NOT USED K40 K41 K42 K43 K44 K45 K46 04 7F 7F 79 17 6D 00 K47 K48 K49 K4A K4B K4C K4D K4E K4F 00 02 7F 7F 79 17 54 00 00 TRACKING HOLD FILTER INPUT GAIN TRACKING HOLD FILTER A-H TRACKING HOLD FILTER A-L TRACKING HOLD FILTER B-H TRACKING HOLD FILTER B-L TRACKING HOLD FILTER OUTPUT GAIN TRACKING HOLD FILTER INPUT GAIN (Only when TRK Gain Up2 is accessed with THSK = 1.) NOT USED FOCUS HOLD FILTER INPUT GAIN FOCUS HOLD FILTER A-H FOCUS HOLD FILTER A-L FOCUS HOLD FILTER B-H FOCUS HOLD FILTER B-L FOCUS HOLD FILTER OUTPUT GAIN NOT USED NOT USED CONTENTS – 28 – CXD2585Q § 1-4. Description of SENS Signals SENS output Microcomputer serial register (latching not required) ASEQ = 0 ASEQ = 1 Output data length $0X Z FZC — $1X Z AS — $2X Z TZC — $30 to 37 Z — $38 Z SSTP AGOK∗ $38 Z XAVEBSY∗ — $3904 Z TE Avrg Reg. 9 bits $3908 Z FE Avrg Reg. 9 bits $390C Z VC Avrg Reg. 9 bits $391C Z TRVSC Reg. 9 bits $391D Z FB Reg. 9 bits $391F Z RFDC Avrg Reg. 8 bits $3A Z FBIAS Count STOP — $3B to 3F Z SSTP — $4X Z XBUSY — $5X Z FOK — $6X Z 0 — $AX GFS GFS — $BX COMP COMP — $CX COUT COUT — $EX OV64 OV64 — Z 0 — $7X, 8X, 9X, DX, FX — ∗ $38 outputs AGOK during AGT and AGF command settings, and XAVEBSY during AVRG measurement. SSTP is output in all other cases. – 29 – CXD2585Q Description of SENS Signals SENS output Z The SENS pin is high impedance. XBUSY Low while the auto sequencer is in operation, high when operation terminates. FOK Outputs the same signal as the FOK pin. High for "focus OK". GFS High when the regenerated frame sync is obtained with the correct timing. COMP Counts the number of tracks set with Reg.B. High when Reg.B is latched, low when the initial Reg.B number is counted through COUT. COUT Counts the number of tracks set with Reg.B. High when Reg.B is latched, toggles each time the Reg.B number is counted through COUT. While $44 and $45 are being executed, toggles with each COUT 8-count instead of the Reg.B number. OV64 Low when the EFM signal is lengthened by 64 channel clock pulses or more after passing through the sync detection filter. – 30 – CXD2585Q The meaning of the data for each address is explained below. $4X commands Register name 4 AS3 Data 1 Data 2 Data 3 Command MAX timer value Timer range AS2 Command AS1 AS0 MT3 MT2 MT1 MT0 LSSL 0 0 AS3 AS2 AS1 AS0 Cancel 0 0 0 0 Fine Search 0 1 0 RXF Focus-On 0 1 1 1 1 Track Jump 1 0 0 RXF 10 Track Jump 1 0 1 RXF 2N Track Jump 1 1 0 RXF M Track Move 1 1 1 RXF 0 RXF = 0 Forward RXF = 1 Reverse • When the Focus-on command ($47) is canceled, $02 is sent and the auto sequence is interrupted. • When the Track jump commands ($44 to $45, $48 to $4D) are canceled, $25 is sent and the auto sequence is interrupted. MAX timer value Timer range MT3 MT2 MT1 MT0 LSSL 0 0 0 23.2ms 11.6ms 5.8ms 2.9ms 0 0 0 0 1.49s 0.74s 0.37s 0.18s 1 0 0 0 • To disable the MAX timer, set the MAX timer value to 0. $5X commands Timer TR3 TR2 TR1 TR0 Blind (A, E), Overflow (C, G) 0.18ms 0.09ms 0.045ms 0.022ms Brake (B) 0.36ms 0.18ms 0.09ms 0.045ms – 31 – CXD2585Q $6X commands Register name 6 SD3 Data 1 Data 2 KICK (D) KICK (F) SD2 SD1 SD0 Timer KF3 KF2 KF1 KF0 SD3 SD2 SD1 SD0 When executing KICK (D) $44 or $45 23.2ms 11.6ms 5.8ms 2.9ms When executing KICK (D) $4C or $4D 11.6ms 5.8ms 2.9ms 1.45ms Timer KICK (F) KF3 KF2 KF1 KF0 0.72ms 0.36ms 0.18ms 0.09ms $7X commands Auto sequencer track jump count setting Command Auto sequence track jump count setting Data 1 Data 2 Data 3 Data 4 D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 215 214 213 212 211 210 29 28 27 26 25 24 23 22 21 20 This command is used to set N when a 2N-track jump is executed, to set M when an M-track move is executed and to set the jump count when fine search is executed for auto sequencer. • The maximum track count is 65,535, but note that with a 2N-track jump the maximum track jump count depends on the mechanical limitations of the optical system. • When the track jump count is from 0 to 15, the COUT signal is counted for 2N-track jumps and M-track moves; when the count is 16 or over, the MIRR signal is counted. For fine search, the COUT signal is counted. – 32 – CXD2585Q $8X commands MODE specification Data 2 Data 1 Command D23 D22 D21 D20 D19 D18 D17 D16 VCO VCO CD- DOUT DOUT WSEL ASHS SOCT0 SEL1 SEL2 ROM Mute Mute-F Command bit C2PO timing Processing CDROM = 1 1-3 CDROM mode; average value interpolation and pre-value hold are not performed. CDROM = 0 1-3 Audio mode; average value interpolation and pre-value hold are performed. Processing Command bit DOUT Mute = 1 When Digital Out is on (MD2 pin = 1), DOUT output is muted. DOUT Mute = 0 When Digital Out is on, DOUT output is not muted. Processing Command bit D. out Mute F = 1 When Digital Out is on (MD2 pin = 1), DA output is muted. D. out Mute F = 0 DA output mute is not affected when Digital Out is either on or off. DA output for 48-bit slot MD2 Other mute conditions∗ 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 1 0 0 1 – ∞dB 1 0 1 0 0dB 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 DOUT Mute D.out Mute F DOUT output 0dB OFF – ∞dB 0dB – ∞dB 0dB – ∞dB ∗ See mute conditions (1), (2), and (4) to (6) under $AX commands for other mute conditions. – 33 – CXD2585Q Sync protection window width Command bit Application WSEL = 1 ±26 channel clock Anti-rolling is enhanced. WSEL = 0 ±6 channel clock Sync window protection is enhanced. ∗ In normal-speed playback, channel clock = 4.3218MHz. Command bit Function ASHS = 0 The command transfer rate to DSSP block from auto sequencer is set to normal speed. ASHS = 1 The command transfer rate to DSSP block from auto sequencer is set to half speed. ∗ See "§ 4-8. Playback Speed" for settings. Command bit Processing SOCT0 SOCT1 0 — Sub-Q is output from the SQSO pin. 1 0 Each signal is output from the SQSO pin. Input the readout clock to SQCK. (See Timing Chart 2-4.) 1 1 The error rate is output from the SQSO pin. Input the readout clock to SQCK. (See Timing Chart 2-6.) —: Don't care Data 2 Command D19 MODE specification D18 D17 Data 3 D16 VCO VCO ASHS SOCT0 SEL1 SEL2 D15 D14 D13 D12 KSL3 KSL2 KSL1 KSL0 See the previous page. Command bit Processing VCOSEL1 = 0 Multiplier PLL VCO1 is set to normal speed. VCOSEL1 = 1 Multiplier PLL VCO1 is set to approximately twice the normal speed. Command bit Processing KSL3 KSL2 0 0 Output of multiplier PLL VCO1 is 1/1 frequency-divided. 0 1 Output of multiplier PLL VCO1 is 1/2 frequency-divided. 1 0 Output of multiplier PLL VCO1 is 1/4 frequency-divided. 1 1 Output of multiplier PLL VCO1 is 1/8 frequency-divided. – 34 – CXD2585Q Command bit Processing VCOSEL2 = 0 Wide-band PLL VCO2 is set to normal speed. VCOSEL2 = 1 Wide-band PLL VCO2 is set to approximately twice the normal speed. Command bit Processing KSL1 KSL0 0 0 Output of wide-band PLL VCO2 is 1/1 frequency-divided. 0 1 Output of wide-band PLL VCO2 is 1/2 frequency-divided. 1 0 Output of wide-band PLL VCO2 is 1/4 frequency-divided. 1 1 Output of wide-band PLL VCO2 is 1/8 frequency-divided. Command Data 4 Data 5 D11 D10 D9 D8 D7 0 0 VCO2 THRU 0 ERC4 Mode specification D6 D5 Data 6 D4 D3 D2 D1 D0 SCOR SCSY SOCT1 TXON TXOUT OUTL1 OUTL0 SEL Command bit Processing VCO2 THRU = 0 V16M is output. VCO2 THRU = 1 The wide-band EFM PLL clock can be input from the V16M pin. ∗ These bits select the internal or external connection for the VCO2 used in CAV-W or variable pitch mode. Command bit Processing ERC4 = 0 C2 error double correction is performed when DSPB = 1. ERC4 = 1 C2 error quadruple correction is performed even when DSPB = 1. Command bit Processing SCOR SEL = 0 WDCK signal is output. SCOR SEL = 1 GRSCOR (protected SCOR) is output. ∗ Used when outputting GRSCOR from the WDCK pin. – 35 – CXD2585Q Command bit Processing SCSY = 0 No processing. SCSY = 1 GRSCOR (protected SCOR) synchronization is applied again. ∗ Used to resynchronize GRSCOR. The rising edge signal of this commnd bit is used internally. Therefore, when resynchronizing GRSCOR, first return the setting to 0 and then set to 1. GRSCOR achieves the crystal accuracy by removing the jitter components included in the SCOR signal. This signal is synchronized with PCMDATA. The resynchronization conditions are when GTOP = high or when the SCSY pin = high. (same as when SCSY = 1 is sent by the $8X command.) Command bit Processing TXON = 0 When CD TEXT data is not demodulated, set TXON to 0. TXON = 1 When CD TEXT data is demodulated, set TXON to 1. ∗ See "$4-10. CD TEXT Data Demodulation" Command bit Processing TXOUT = 0 Various signals except for CD TEXT is output from the SQSO pin. TXOUT = 1 CD TEXT data is output from the SQSO pin. ∗ See "$4-10. CD TEXT Data Demodulation" Command bit Processing OUTL1 = 0 WFCK, XPCK C4M, WDCK and FSTO are output. V16M is output when VCO2 THRU = 0. OUTL1 = 1 WFCK, XPCK C4M, WDCK and FSTO outputs are set to low. The V16M output is low when VCO2 THRU = 0. Command bit Processing OUTL0 = 0 PCMD, BCK, LRCK and EMPH are output. OUTL0 = 1 PCMD, BCK, LRCK and EMPH outputs are low. – 36 – CXD2585Q $9X commands Command Function specification Data 2 Data 1 D23 1 D22 D21 DSPB A.SEQ ON-OFF ON-OFF D20 D19 D18 D17 D16 1 BiliGL MAIN BiliGL SUB FLFC 1 Processing Command bit DSPB = 0 Normal-speed playback, C2 error quadruple correction. DSPB = 1 Double-speed playback, C2 error double correction. (quadruple correction when ERC4 = 1) FLFC is normally 0. FLFC is 1 in CAV-W mode, for any playback speed. Command bit BiliGL MAIN = 0 BiliGL MAIN = 1 BiliGL SUB = 0 STEREO MAIN BiliGL SUB = 1 SUB Mute Definition of bilingual capable MAIN, SUB and STEREO The left channel input is output to the left and right channels for MAIN. The right channel input is output to the left and right channels for SUB. The left and right channel inputs are output to the left and right channels for STEREO. – 37 – CXD2585Q $AX commands Data 1 Command Audio CTRL Data 2 D23 D22 D21 D20 D19 D18 D17 D16 VARI ON VARI USE Mute ATT PCT1 PCT2 0 SOC2 Command bit Processing VARION = 0 Variable pitch mode is turned off. (The crystal is the reference to the internal clock.) VARION = 1 Variable pitch mode is turned on. (The VCO2 is the reference to the internal clock.) Command bit Processing VARIUSE = 0 When the variable pitch mode is not used, set VARIUSE to 0 . VARIUSE = 1 When the variable pitch mode is used, set VARIUSE to 1. ∗ See "$DX commands" for the variable range and the usage example of the variable pitch. Command bit Command bit Meaning Mute = 0 Mute off if other mute conditions are not set. Mute = 1 Mute on. Peak register reset. Meaning ATT = 0 Attenuation off. ATT = 1 –12dB Mute conditions (1) When register A mute = 1. (2) When Mute pin = 1. (3) When register 8 D.out Mute F = 1 and the Digital Out is on (MD2 pin = 1). (4) When GFS stays low for over 35 ms (during normal-speed). (5) When register 9 BiliGL MAIN = Sub = 1. (6) When register A PCT1 = 1 and PCT2 = 0. (1) to (4) perform zero-cross muting with a 1ms time limit. Command bit Meaning PCM Gain ECC error correction ability PCT1 PCT2 0 0 Normal mode × 0dB C1: double; C2: quadruple 0 1 Level meter mode × 0dB C1: double; C2: quadruple 1 0 Peak meter mode Mute C1: double; C2: double 1 1 Normal mode × 0dB C1: double; C2: double Description of level meter mode (see Timing Chart 1-4.) • When the LSI is set to this mode, it performs digital level meter functions. • When the 96-bit clock is input to SQCK, 96 bits of data are output to SQSO. The initial 80 bits are Sub-Q data (see § 2. Subcode Interface). The last 16 bits are LSB first, which are 15-bit PCM data (absolute values) and an L/R flag. The L/R flag is high when the 15-bit PCM data is from the left channel and low when the data is from the right channel. • The PCM data is reset and the L/R flag is reversed after one readout. Then maximum value measuring continues until the next readout. – 38 – CXD2585Q Description of peak meter mode (see Timing Chart 1-5.) • When the LSI is set to this mode, the maximum PCM data value is detected regardless of if it comes from the left or right channel. The 96-bit clock must be input to SQCK to read out this data. • When the 96-bit clock is input, 96 bits of data are output to SQSO and the value is set in the LSI internal register again. In other words, the PCM maximum value detection register is not reset by the readout. • To reset the PCM maximum value register to zero, set PCT1 = PCT2 = 0 or set the $AX mute. • The Sub-Q absolute time is automatically controlled in this mode. In other words, after the maximum value is generated, the absolute time for CRC to become OK is retained in the memory. Normal operation is conducted for the relative time. • The final bit (L/R flag) of the 96-bit data is normally 0. • The pre-value hold and average value interpolation data are fixed to level (– ∞) for this mode. Command bit Processing SOC2 = 0 The SENS signal is output from the SENS pin as usual. SOC2 = 1 The SQSO pin signal is output from the SENS pin. SENS output switching • This command enables the SQSO pin signal to be output from the SENS pin. When SOC2 = 0, SENS output is performed as usual. When SOC2 = 1, the SQSO pin signal is output from the SENS pin. At this time, the readout clock is input to the SCLK pin. Note) SOC2 should be switched when SQCK = SCLK = high. $BX commands This command sets the traverse monitor count. Data 1 Command Data 2 Data 3 Data 4 D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 Traverse monitor count setting 215 214 213 212 211 210 29 28 27 26 25 24 23 22 21 20 • When the set number of tracks are counted during fine search, the sled control for the traverse cycle control goes off. • The traverse monitor count is set to monitor the traverse status from the SENS output as COMP and COUT. This command sets the monitor output switching. Data 5 Command Traverse monitor count setting D7 D6 0 0 Command bit D5 D4 MTSL1 MTSL0 Output data MTSL1 MTSL0 0 0 XUGF XPCK GFS C2PO 0 1 MINT0 MNT1 MNT2 MNT3 1 0 RFCK XPCK XROF GTOP – 39 – CXD2585Q $CX commands Data 1 Command D23 D21 D22 Data 2 D20 D19 D18 D17 D16 Gain Gain Gain Gain Gain Gain Spindle servo PCC1 PCC0 coefficient setting MDP1 MDP0 MDS1 MDS0 DCLV1 DCLV0 Gain CLVS CLV CTRL ($DX) • CLVS mode gain setting: GCLVS Gain MDS1 Gain MDS0 Gain CLVS GCLVS 0 0 0 –12dB 0 0 1 –6dB 0 1 0 –6dB 0 1 1 0dB 1 0 0 0dB 1 0 1 +6dB • CLVP mode gain setting: GMDP : GMDS Gain MDP1 Gain MDP0 GMDP Gain MDS1 Gain MDS0 GMDS 0 0 –6dB 0 0 –6dB 0 1 0dB 0 1 0dB 1 0 +6dB 1 0 +6dB • DCLV overall gain setting: GDCLV Gain DCLV1 Gain DCLV0 GDCLV 0 0 0dB 0 1 +6dB 1 0 +12dB Command bit Processing PCC1 PCC0 0 0 The VPCO signal is output. 0 1 The VPCO pin output is high impedance. 1 0 The VPCO pin output is low. 1 1 The VPCO pin output is high. • This command controls the VPCO pin signal. The VPCO output can be controlled with this setting. – 40 – CXD2585Q Command Data 3 D15 D14 D13 Data 4 D12 D11 D10 D9 D8 Spindle servo SFP3 SFP2 SFP1 SFP0 SRP3 SRP2 SRP1 SRP0 coefficient setting Command bit SFP3 to 0 Processing Sets the frame sync forward protection times. The setting range is 1 to F (Hex). Command bit SRP3 to 0 Processing Sets the frame sync backward protection times. The setting range is 1 to F (Hex). ∗ See § 4-2. Frame Sync Protection regarding frame sync protection. • The CXD2585Q can serially output the 40 bits (10 BCD codes) of error monitor data selected by EDC0 to 7 from the SQSO pin and monitor this data using a microcomputer. The C1 and C2 error rate settings are sent one at a time by the $C commands by setting $8 commands SOCT0 and SOCT1 = 1. Then, the data can be read out from the SQSO pin by sending 40 SQCK pulses. $CX commands Command Data 5 D7 D6 D5 Data 6 D4 D3 D2 D1 D0 Spindle servo EDC7 EDC6 EDC5 EDC4 EDC3 EDC2 EDC1 EDC0 coefficient setting – 41 – CXD2585Q Error monitor commands Command bit Processing EDC7 = 0 EDC6 The [No C1 errors, pointer set] count is output when 0. EDC5 The [One C1 error corrected, pointer reset] count is output when 0. EDC4 The [No C1 errors, pointer set] count is output when 0. EDC3 The [One C1 error corrected, pointer set] count is output when 0. EDC2 The [Two C1 errors corrected, pointer set] count is output when 0. EDC1 The [C1 correction impossible, pointer set] count is output when 0. 7350 frame count cycle mode∗1 when 1. 73500 frame count cycle mode∗2 when 0. EDC0 EDC7 = 1 EDC6 The [No C2 errors, pointer reset] count is output when 0. EDC5 The [One C2 error corrected, pointer reset] count is output when 0. EDC4 The [Two C2 errors corrected, pointer reset] count is output when 0. EDC3 The [Three C2 errors corrected, pointer reset] count is output when 0. EDC2 The [Four C2 errors corrected, pointer reset] count is output when 0. EDC1 The [C2 correction impossible, pointer copy] count is output when 0. EDC0 The [C2 correction impossible, pointer set] count is output when 0. ∗1 The number selected by C1 (EDC1 to 6) and C2 (EDC0 to 6) is added to C1 and C2 and output every 7350 frames. ∗2 The number selected by C1 (EDC1 to 6) and C2 (EDC0 to 6) is added to C1 and C2 and output every 73500 frames. $DX commands Command CLV CTRL Data 1 D23 D22 D21 D20 0 TB TP Gain CLVS See "$CX commands". Command bit Description TB = 0 Bottom hold at a cycle of RFCK/32 in CLVS mode. TB = 1 Bottom hold at a cycle of RFCK/16 in CLVS mode. TP = 0 Peak hold at a cycle of RFCK/4 in CLVS mode. TP = 1 Peak hold at a cycle of RFCK/2 in CLVS mode. – 42 – CXD2585Q Data 2 Command CLV CTRL Data 3 Data 4 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 VP7 VP6 VP5 VP4 VP3 VP2 VP1 VP0 VP CTL1 VP CTL0 0 0 The settings are as follows in CAV-W mode. Command bit Processing VP0 to 7 The spindle rotational velocity is set. Command bit Processing VPCTL1 VPCTL0 0 0 The setting of VP0 to 7 is multiplied by 1. 0 1 The setting of VP0 to 7 is multiplied by 2. 1 0 The setting of VP0 to 7 is multiplied by 3. 1 1 The setting of VP0 to 7 is multiplied by 4. ∗ The above setting should be 0, 0 except for the CAV-W operating mode. The rotational velocity R of the spindle can be expressed with the following equation. R: Relative velocity at normal speed = 1 256 – n R= ×l n: VP0 to 7 setting value 32 l: Multiple set by VPCTL0, 1 Command bit Description VP0 to 7 = F0 (H) Playback at 1/2 (1) × speed … … Playback at 1 (2) × speed VP0 to 7 = E0 (H) … … Playback at (4) × speed VP0 to 7 = C0 (H) Notes) 1. Values when crystal is 16.9344MHz and XTSL is low or when crystal is 33.8688MHz and XTSL is high. 2. The values in parentheses are for when DSPB is 1. 4 R – Relative velocity [Multiple] 3.5 3 2.5 2 DS 1.5 PB =1 B=0 DSP 1 0.5 F0 E0 VP0 to VP7 setting value [HEX] D0 – 43 – C0 CXD2585Q The setting in variable pitch mode is as shown below. Command bit Processing VPCTL1 to 0, VP7 to 0 The pitch of variable pitch mode is set. The setting of the pitch can be expressed with the equation below. P= –n 10 [%] P: Setting value of pitch n: Setting value for VPCTL1, VPCTL0 and VP7 to VP0 (two's complementary, VPCTL1 is sign bit) Command bit VPCTL1 1 1 0 0 VPCTL0 0 1 0 1 Setting value of pitch [%] Example of command setting 00 (H) +51.2 $D60080 : : : FF (H) +25.7 $D6FF80 00 (H) +25.6 $D600C0 : : : FF (H) +0.1 $D6FFC0 00 (H) 0.0 $D60000 : : : FF (H) –25.5 $D6FF00 00 (H) –25.6 $D60040 : : : FF (H) –48.7 $D6E740 VP7 to 0 The setting range of the pitch is –48.7 to +51.2%. The pitch setting for + side should be within the playback speed of the recommended operating conditions. The following is the example of the command in variable pitch mode. $A4XXXXX (Sets to use variable pitch mode) $ACXXXXX (Variable pitch mode is turned on. The VCO2 is the reference to the internal clock.) $D60A00 (The pitch is set to +1.0%) $D60000 (The pitch is set to 0.0%) $A4XXXXX (Variable pitch mode is turned off. The crystal is the reference to the internal clock.) – 44 – CXD2585Q $EX commands Data 1 Command SPD mode Data 2 D23 D22 D21 D20 CM3 CM2 CM1 CM0 EPWM SPDC ICAP Command bit D19 D18 Data 3 D17 D16 D15 SFSL VC2C D14 D13 D12 HIFC LPWR VPON Description Mode CM3 CM2 CM1 CM0 0 0 0 0 STOP Spindle stop mode.∗1 1 0 0 0 KICK Spindle forward rotation mode.∗1 1 0 1 0 BRAKE Spindle reverse rotation mode. Valid only when LPWR = 0 in any mode.∗1 1 1 1 0 CLVS Rough servo mode. When the RF-PLL circuit isn't locked, this mode is used to pull the disc rotations within the RFPLL capture range. 1 1 1 1 CLVP PLL servo mode. 0 1 1 0 CLVA Automatic CLVS/CLVP switching mode. Used for normal playback. ∗1 See Timing Charts 1-6 to 1-12. Command bit EPWM SPDC ICAP SFSL VC2C HIFC LPWR VPON Mode INV VPCO Description 0 0 0 0 0 0 0 0 0 CLV-N Crystal reference CLV servo. 0 0 0 0 1 1 0 0 0 CLV-W 0 1 1 0 0 1 0 1 0 CAV-W Spindle control with VP0 to 7. 1 0 1 0 0 1 0 1 0 CAV-W 0 0 0 0 0 1 0 1 1 Used for playback in CLV-W mode.∗2 Spindle control with the external PWM. VCO-C VCO control∗3 ∗2 Figs. 3-1 and 3-2 show the control flow with the microcomputer software in CLV-W mode. ∗3 Fig. 3-3 shows the control flow with the microcomputer software in VCO-C mode. – 45 – CXD2585Q Mode LPWR CLV-N 0 0 CLV-W 1 0 CAV-W 1 Command Timing chart KICK 1-6 (a) BRAKE 1-6 (b) STOP 1-6 (c) KICK 1-7 (a) BRAKE 1-7 (b) STOP 1-7 (c) KICK 1-8 (a) BRAKE 1-8 (b) STOP 1-8 (c) KICK 1-9 (a) BRAKE 1-9 (b) STOP 1-9 (c) KICK 1-10 (a) BRAKE 1-10 (b) STOP 1-10 (c) Mode LPWR Timing chart CLV-N 0 1-11 0 1-12 1 1-13 0 1-14 (EPWM = 0) 1 1-15 (EPWM = 0) 0 1-16 (EPWM = 1) 1 1-17 (EPWM = 1) CLV-W CAV-W Data 4 Command SPD mode D11 D10 D9 D8 Gain CAV1 Gain CAV0 0 0 Gain CAV1 Gain CAV0 0 0 0dB 0 1 –6dB 1 0 –12dB 1 1 –18dB Gain • This sets the gain when controlling the spindle with the phase comparator in CAV-W mode. – 46 – – 47 – C2PO CDROM = 1 C2PO CDROM = 0 WDCK LRCK Timing Chart 1-3 C2 Pointer for lower 8bits Rch C2 Pointer C2 Pointer for upper 8bits Rch 16bit C2 Pointer C2 Pointer for lower 8bits Lch C2 Pointer C2 Pointer for upper 8bits Lch 16bit C2 Pointer If C2 Pointer = 1, data is NG 48 bit slot CXD2585Q – 48 – SQSO SQCK WFCK SQSO CRCF SQCK Timing Chart 1-4 2 L/R 2 3 Sub Q Data See "Sub Code Interface" 3 96 bit data Hold section 1 96 clock pulses 1 D0 CRCF 81 D2 1 Level Meter Timing 16 bit 96 clock pulses D1 Peak data of this section 80 D4 D5 D6 R/L 2 3 CRCF 15-bit peak-data Absolute value display, LSB first D3 750ns to 120µs D13 D14 L/R Peak data L/R flag 96 CXD2585Q SQCK WFCK – 49 – 96 clock pulses Measurement CRCF Timing Chart 1-5 1 2 3 Peak Meter Timing Measurement CRCF 96 clock pulses 1 2 3 Measurement CRCF CXD2585Q CXD2585Q Timing Chart 1-6 CLV-N mode LPWR = 0 KICK MDP BRAKE STOP Z H MDP Z MDP L (a) KICK (b) BRAKE Z (c) STOP Timing Chart 1-7 CLV-W mode (when following the spindle rotational velocity) LPWR = 0 KICK MDP BRAKE STOP Z H MDP Z (a) KICK MDP L (b) BRAKE Z (c) STOP Timing Chart 1-8 CLV-W mode (when following the spindle rotational velocity) LPWR = 1 KICK MDP H BRAKE MDP Z Z (a) KICK STOP MDP Z (b) BRAKE (c) STOP BRAKE STOP Timing Chart 1-9 CAV-W mode LPWR = 0 KICK MDP H MDP (a) KICK L MDP Z (b) BRAKE (c) STOP BRAKE STOP Timing Chart 1-10 CAV-W mode LPWR = 1 KICK MDP H (a) KICK MDP Z (b) BRAKE – 50 – MDP Z (c) STOP CXD2585Q Timing Chart 1-11 CLV-N mode LPWR = 0 n · 236 (ns) n = 0 to 31 Acceleration MDP Z 132kHz 7.6µs Deceleration Timing Chart 1-12 CLV-W mode LPWR = 0 Acceleration MDP Z 264kHz 3.8µs Deceleration Timing Chart 1-13 CLV-W mode LPWR = 1 Acceleration MDP Z 264kHz 3.8µs The BRAKE pulse is masked when LPWR = 1. Timing Chart 1-14 CAV-W mode EPWM = LPWR = 0 Acceleration MDP Z 264kHz 3.8µs Deceleration Timing Chart 1-15 CAV-W mode EPWM = LPWR = 1 Acceleration MDP Z 264kHz 3.8µs The BRAKE pulse is masked when LPWR = 1. – 51 – CXD2585Q Timing Chart 1-16 CAV-W mode EPWM = 1, LPWR = 0 H PWMI L Acceleration H MDP L Deceleration Timing Chart 1-17 CAV-W mode EPWM = LPWR = 1 H PWMI L Acceleration H MDP Z The BRAKE pulse is masked when LPWR = 1. – 52 – CXD2585Q [2] Subcode Interface There are two methods for reading out a subcode externally. The 8-bit subcodes P to W can be read out from SBSO by inputting EXCK. Sub-Q can be read out after checking CRC of the 80 bits in the subcode frame. Sub-Q can be read out from the SQSO pin by inputting 80 clock pulses to the SQCK pin when SCOR comes correctly and CRCF is high. § 2-1. P to W Subcode Readout Data can be read out by inputting EXCK immediately after WFCK falls. (See Timing Chart 2-1.) § 2-2. 80-bit Sub-Q Readout Fig. 2-2 shows the peripheral block of the 80-bit Sub-Q register. • First, Sub-Q, regenerated at one bit per frame, is input to the 80-bit serial/parallel register and the CRC check circuit. • 96-bit Sub-Q is input, and if the CRC is OK, it is output to SQSO with CRCF = 1. In addition, 80 bits are loaded into the parallel/serial register. When SQSO goes high after SCOR is output, the CPU determines that new data (which passed the CRC check) has been loaded. • When the 80-bit data is loaded, the order of the MSB and LSB is inverted within each byte. As a result, although the sequence of the bytes is the same, the bits within the bytes are now ordered LSB first. • Once the 80-bit data load is confirmed, SQCK is input so that the data can be read. The SQCK input is detected, and the retriggerable monostable multivibrator is reset while the input is low. • The retriggerable monostable multivibrator has a time constant from 270 to 400µs. When the duration when SQCK is high is less than this time constant, the monostable multivibrator is kept reset; during this interval, the serial/parallel register is not loaded into the parallel/serial register. • While the monostable multivibrator is being reset, data cannot be loaded in the peak detection parallel/serial register or the 80-bit parallel/serial register. In other words, while reading out with a clock cycle shorter than this time constant, the register will not be rewritten by CRCOK and others. • The previously mentioned peak detection register can be connected to the shift-in of the 80-bit parallel/serial register. For ring control 1, input and output are shorted during peak meter and level meter modes. For ring control 2, input and output are shorted during peak meter mode. This is because the register is reset with each readout in level meter mode, and to prevent readout destruction in peak meter mode. As a result, the 96-bit clock must be input in peak meter mode. • The absolute time after peak is stored in the memory in peak meter mode. (See Timing Chart 2-3.) • The high and low intervals for SQCK should be between 750ns and 120µs. – 53 – CXD2585Q Timing Chart 2-1 Internal PLL clock 4.3218 ± ∆MHz WFCK SCOR EXCK 750ns max SBSO S0 · S1 Q R WFCK SCOR EXCK SBSO S0·S1 Q R S T U V W S0·S1 Same P1 Q R S T U V W P1 Same Subcode P.Q.R.S.T.U.V.W Read Timing – 54 – P2 P3 SUBQ Block Diagram 2-2 SI LD LD 8 (ASEC) 8 (AMIN) – 55 – CRCC LD SO 8 Peak detection 16 16 bit P/S register Monostable multivibrator LD 80 bit P/S Register 8 80 bit S/P Register LOAD CONTROL SUBQ Ring control 1 LD Order Inversion ABS time load control for peak value H G F E D C B A A B C D E F G H SIN (AFRAM) LD SI 8 8 LD Ring control 2 SHIFT 8 SHIFT 8 CRCF Mix LD 8 ADDRS CTRL SQCK SO SQSO CXD2585Q – 56 – SQSO SQCK SQCK SQSO SCOR WFCK Timing Chart 2-3 CRCF Monostable Multivibrator (Internal) CRCF1 1 2 3 2 1 ADR1 94 ADR2 ADR3 CTL0 270 to 400µs when SQCK = high. Register load forbidder CRCF1 Determined by mode 93 92 91 80 or 96 Clock 750ns to 120µs 300ns max ADR0 3 95 CTL1 96 CTL2 97 CTL3 CRCF2 98 CXD2585Q PER0 PER1 PER2 Internal signal latch PER3 PER4 PER5 PER6 PER7 C1F0 750ns or more C1F1 C1F2 C2F0 C2F2 FOK Description C2F1 GFS LOCK EMPH ALOCK – 57 – C1F1 0 0 1 1 0 0 1 1 C1F2 0 0 0 0 1 1 1 1 1 0 1 0 1 0 1 0 C1F0 C1 correction impossible; C1 pointer set Two C1 errors corrected; C1 pointer set One C1 error corrected; C1 pointer set No C1 errors; C1 pointer set — — One C1 error corrected; C1 pointer reset No C1 errors; C1 pointer reset Description C2F1 0 0 1 1 0 0 1 1 C2F2 0 0 0 0 1 1 1 1 1 0 1 0 1 0 1 0 C2F0 C2 correction impossible; C2 pointer set C2 correction impossible; C1 pointer copy — Four C2 errors corrected; C2 pointer reset Three C2 errors corrected; C2 pointer reset Two C2 errors corrected; C2 pointer reset One C2 error corrected; C2 pointer reset No C2 errors; C2 pointer reset Description Used in CAV-W mode. The result obtained by measuring the rotational velocity of the disc. (See Timing Chart 2-5.) VF0 = LSB, VF9 = MSB. VF0 to 9 VF9 GFS is sampled at 460Hz; when GFS is high eight consecutive samples, this pin outputs a high signal. If GFS is low eight consecutive samples, this pin outputs low. VF8 ALOCK VF7 High when the playback disc has emphasis. VF6 EMPH VF5 GFS is sampled at 460Hz; when GFS is high, this pin outputs a high signal. If GFS is low eight consecutive samples, this pin outputs low. VF4 LOCK VF3 High when the frame sync and the insertion protection timing match. VF2 GFS VF1 Focus OK. VF0 FOK PER0 to 7 RF jitter amount (used to adjust the focus bias). 8-bit binary data in PER0 = LSB, PER7 = MSB. Signal SQSO SQCK XLAT Set SQCK high during this interval. Example: $802000 latch Timing Chart 2-4 CXD2585Q CXD2585Q Timing Chart 2-5 Measurement interval (approximately 3.8µs) Reference window (132.2kHz) Measurement pulse (V16M/2) Measurement counter Load m VF0 to 9 The relative velocity of the disc can be obtained with the following equation. R= (m + 1) (R: Relative velocity, m: Measurement results) 32 VF0 to 9 is the result obtained by counting V16M/2 pulses while the reference signal (132.2kHz) generated from XTAL (XTAI, XTAO) (384Fs) is high. This value is 31 when the disc is rotating at normal speed and 63 when it is rotating at double speed (when DSPB is low). – 58 – SQSO SQCK XLAT Timing Chart 2-6 C1 MSB 19 – 59 – 0 7 3 C1 error rate 18 17 16 15 14 13 12 11 10 9 8 7 6 5 5 4 3 2 0 1 0 7 8 3 C2 error rate 0 19 18 17 16 15 14 13 12 11 10 9 7 6 5 5 4 3 2 0 1 0 CXD2585Q CXD2585Q [3] Description of Modes This LSI has three basic operating modes using a combination of spindle control and the PLL. The operations for each mode are described below. § 3-1. CLV-N Mode This mode is compatible with the CXD2510Q, and operation is the same as for conventional control. The PLL capture range is ±150kHz. § 3-2. CLV-W Mode This is the wide capture range mode. This mode allows the PLL to follow the rotational velocity of the disc. This rotational following control has two types: using the built-in VCO2 or providing an external VCO. The spindle is the same CLV servo as for the conventional series. Operation using the built-in VCO2 is described below. (When using an external VCO, input the signal from the VPCO pin to the low-pass filter, use the output from the low-pass filter as the control voltage for the external VCO, and input the oscillation from the VCO to the V16M pin.) When starting to rotate the disc and/or speeding up to the lock range from the condition where the disc is stopped, CAV-W mode should be used. Specifically, first send $E665X to set CAV-W mode and kick the disc, then send $E60CX to set CLV-W mode if ALOCK is high, which can be read out serially from the SQSO pin. CLV-W mode can be used while ALOCK is high. The microcomputer monitors the serial data output, and must return the operation to the speed adjusting state (CAV-W mode) when ALOCK becomes low. The control flow according to the microcomputer software in CLV-W mode is shown in Fig. 3-2. In CLV-W mode (normal), low power consumption is achieved by setting LPWR to high. Control was formerly performed by applying acceleration and deceleration pulses to the spindle motor. However, when LPWR is set high, deceleration pulses are not output, thereby achieving low power consumption mode. Note) The capture range for this mode is theoretically up to the signal processing limit. § 3-3. CAV-W Mode This is CAV mode. In this mode, the external clock is fixed and it is possible to control the spindle to the desired rotational velocity. The rotational velocity is determined by the VP0 to VP7 setting values or the external PWM. When controlling the spindle with VP0 to VP7, setting CAV-W mode with the $E665X command and controlling VP0 to VP7 with the $DX commands allows the rotational velocity to be varied from low speed to 4× speed. (See "$DX commands".) Also, when controlling the spindle with the external PWM, the PWMI pin is binary input which becomes KICK during high intervals and BRAKE during low intervals. The microcomputer can know the rotational velocity using V16M. The reference frequency for the velocity measurement is a signal of 132.3kHz obtained by dividing XTAL (XTAI, XTAO) (384Fs) by 128. The velocity is obtained by counting the half of V16M pulses while the reference is high, and the result is output from the new CPU interface as 10 bits (VP0 to VP9). These measurement results are 31 when the disc is rotating at normal speed or 127 when it is rotating at 4× speed. These values match those of the 256 - n for control with VP0 to VP7. (See Table 2-5 and Fig. 2-6.) In CAV-W mode, the spindle is set to the desired rotational velocity and the operation speed for the entire system follows this rotational velocity. Therefore, the cycles for the Fs system clock, PCM data and others output from this LSI change according to the rotational velocity of the disc. Note) The capture range for this mode is theoretically up to the signal processing limit. Note) Set FLFC to 1 for this mode – 60 – CXD2585Q § 3-4. VCO-C Mode This is VCO control mode. In this mode, the V16M oscillation frequency can be controlled by setting $D commands VP0 to VP7 and VPCTL0, 1. The V16M oscillation frequency can be expressed by the following equation. V16M = l (256 – n) 32 n: VP0 to 7 setting value l: VPCTL0, 1 setting value The VCO1 oscillation frequency is determined by V16M. The VCO1 frequency can be expressed by the following equation. • When DSPB = 0 VCO1 = V16M × 49 24 • When DSPB = 1 VCO1 = V16M × 49 16 – 61 – CXD2585Q CAV-W CLV-W Operation mode Rotational velocity CLVS CLVP Spindle mode Target speed KICK Time LOCK ALOCK Fig. 3-1. Disc Stop to Regular Playback in CLV-W Mode CLV-W Mode CLV-W MODE START KICK $E8000 Mute OFF $A00XXXX CAV-W $E665X (CLVA) NO ALOCK = H ? YES CLV-W $E60CX (CLVA) (WFCK PLL) YES ALOCK = L ? NO Fig. 3-2. CLV-W Mode Flow Chart – 62 – CXD2585Q VCO-C Mode Access START R? (How many minutes of absolute time?) n? (Calculate n) Transfer $E00510 What is the ultimate speed multiple? Calculate VP0 to VP7. Switch to VCO control mode. EPWM = SPDC = ICAP = SFSL = VC2C = LPWR = 0 HIFC = VPON = 1 Transfer $DX XX Transfer VP0 to VP7. ( corresponds to VP0 to VP7.) Track Jump Subroutine Transfer $E66500 Switch to normal-speed playback mode. EPWM = SFSL = VC2C = LPWR = 0 SPDC = ICAP = HIFC = VPON = 1 Access END Fig. 3-3. Access Flow Chart Using VCO Control – 63 – CXD2585Q [4] Description of other functions § 4-1. Channel Clock Regeneration by Digital PLL Circuit • The channel clock is necessary for demodulating the EFM signal regenerated by the optical system. Assuming T as the channel clock cycle, the EFM signal is modulated in an integer multiple of T from 3T to 11T. In order to read the information in the EFM signal, this integer value must be read correctly. As a result, T, that is the channel clock, is necessary. In an actual player, a PLL is necessary for regenerating the channel clock because the fluctuation in the spindle rotation alters the width of the EFM signal pulses. The block diagram of this PLL is shown in Fig. 4-1. The CXD2585Q has a built-in three-stage PLL. • The first-stage PLL is a wide-band PLL. When using the internal VCO2, an external LPF is necessary; when not using the internal VCO2, external LPF and VCO are necessary. The output of this first-stage PLL is used as a reference for all clocks within the LSI. • The second-stage PLL regenerates the high-frequency clock needed by the third-stage digital PLL. • The third-stage PLL is a digital PLL that regenerates the actual channel clock. • The digital PLL in CLV-N mode has a secondary loop, and is controlled by the primary loop (phase) and the secondary loop (frequency). When FLFC = 1, the secondary loop can be turned off. High frequency components such as 3T and 4T may contain deviations. In such cases, turning the secondary loop off yields better playability. However, in this case the capture range becomes ±50kHz. • A new digital PLL has been provided for CLV-W mode to follow the rotational velocity of the disc in addition to the conventional secondary loop. – 64 – CXD2585Q Block Diagram 4-1 CLV-W CAV-W Selector Spindle rotation information Clock input 1/32 XTAI XTSL 1/2 1/l 1/n Phase comparator 1/2 VPCO CLV-N CLV-W /CLV-N CAV-W l = 1, 2, 3, 4 (VPCTL0, 1) LPF n = 1 to 256 (VP7 to 0) VCOSEL2 Microcomputer control 1/K (KSL1, 0) VCTL VCO2 V16M 2/1 MUX VPON 1/N Phase comparator 1/M PCO FILI FILO 1/K (KSL3, 2) CLTV VCO1 VCOSEL1 Digital PLL RFPLL – 65 – CXD2585Q § 4-2. Frame sync protection • In normal speed playback, a frame sync is recorded approximately every 136µs (7.35kHz). This signal is used as a reference to recognize the data within a frame. Conversely, if the frame sync cannot be recognized, the data is processed as error data because the data cannot be recognized. As a result, recognizing the frame sync properly is extremely important for improving playability. • In the CXD2585Q, window protection and forward protection/backward protection have been adopted for frame sync protection. These functions achieve very powerful frame sync protection. There are two window widths; one for cases where a rotational disturbance affects the player and the other for cases where there is no rotational disturbance (WSEL = 0/1). In addition, the forward protection counter is set to 13∗, and the backward protection counter to 3∗. Concretely, when the frame sync is being played back normally and then cannot be detected due to scratches, a maximum of 13 frames are inserted. If the frame sync cannot be detected for 13 frames or more, the window opens to resynchronize the frame sync. In addition, immediately after the window opens and the resynchronization is executed, if a proper frame sync cannot be detected within 3 frames, the window opens immediately. ∗ Default values. These values can be set as desired by $C commands SFP0 to SFP3 and SRP0 to SRP3. § 4-3. Error Correction • In the CD format, one 8-bit data contains two error correction codes, C1 and C2. For C1 correction, the code is created with 28-byte information and 4-byte C1 parity. For C2 correction, the code is created with 24-byte information and 4-byte parity. Both C1 and C2 are Reed Solomon codes with a minimum distance of 5. • The CXD2585Q uses refined super strategy to achieve double correction for C1 and quadruple correction for C2. • In addition, to prevent C2 miscorrection, a C1 pointer is attached to data after C1 correction according to the C1 error status, the playback status of the EFM signal, and the operating status of the player. • The correction status can be monitored externally. See Table 4-2. • When the C2 pointer is high, the data in question was uncorrectable. Either the pre-value was held or an average value interpolation was made for the data. MNT3 MNT2 MNT1 MNT0 0 0 0 0 No C1 errors; C1 pointer reset 0 0 0 1 One C1 error corrected; C1 pointer reset 0 0 1 0 — 0 0 1 1 — 0 1 0 0 No C1 errors; C1 pointer set 0 1 0 1 One C1 error corrected; C1 pointer set 0 1 1 0 Two C1 errors corrected; C1 pointer set 0 1 1 1 C1 correction impossible; C1 pointer set 1 0 0 0 No C2 errors; C2 pointer reset 1 0 0 1 One C2 error corrected; C2 pointer reset 1 0 1 0 Two C2 errors corrected; C2 pointer reset 1 0 1 1 Three C2 errors corrected; C2 pointer reset 1 1 0 0 Four C2 errors corrected; C2 pointer reset 1 1 0 1 1 1 1 0 C2 correction impossible; C1 pointer copy 1 1 1 1 C2 correction impossible; C2 pointer set Description — Table 4-2. – 66 – CXD2585Q Timing Chart 4-3 Normal-speed PB 400 to 500ns RFCK t = Dependent on error condition MNT3 C1 correction C2 correction MNT2 MNT1 MNT0 Strobe Strobe § 4-4. DA Interface • The CXD2585Q supports the 48-bit slot interface as the DA interface. 48-bit slot interface This interface includes 48 cycles of the bit clock within one LRCK cycle, and is MSB first. When LRCK is high, the data is for the left channel. – 67 – R0 1 2 – 68 – DA16 WDCK DA15 (4.23M) LRCK (88.2K) R0 1 2 3 4 5 Lch MSB (15) Lch MSB (15) 48bit slot Double-Speed Playback DA16 WDCK DA15 (2.12M) LRCK (44.1K) 48bit slot Normal-Speed Playback PSSL = L Timing Chart 4-4 6 7 8 9 L14 10 L13 11 L12 12 L0 24 L11 L9 Rch MSB L10 L8 L7 L6 L5 L4 L3 L2 L1 L0 24 Rch MSB CXD2585Q CXD2585Q § 4-5. Digital Out There are three Digital Out: the type 1 format for broadcasting stations, the type 2 form 1 format for home use, and the type 2 form 2 format for the manufacture of software. The CXD2585Q supports type 2 form 1. The channel status clock accuracy is automatically set to level II when using the crystal clock and to level III in CAV-W mode or variable pitch mode. In addition, Sub-Q data which are matched twice in succession after a CRC check are input to the first four bits (bits 0 to 3). DOUT is output when the crystal is 34MHz and DSPB is set to 1 with XTSL high in CLV-N or CLV-W mode. Therefore, set MD2 to 0 and turn DOUT off. Digital Out C bit 0 2 3 From sub Q 0 ID0 16 1 0 4 5 6 7 8 9 10 11 12 13 14 15 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/1 0 0 ID1 COPY Emph 0 0 0 32 48 0 176 bit0 to 3 Sub-Q control bits that matched twice with CRCOK bit29 VPON or VARION: 1 X'tal: 0 Table 4-5. – 69 – CXD2585Q § 4-6. Servo Auto Sequence This function performs a series of controls, including auto focus and track jumps. When the auto sequence command is received from the CPU, auto focus, 1-track jump, 2N-track jump, fine search and M-track move are executed automatically. The servo block operates according to the built-in program during the auto sequence execution (when XBUSY = low), so that commands from the CPU, that is $0, 1, 2 and 3 commands, are not accepted. ($4 to E commands are accepted.) In addition, when using the auto sequence, turn the A.SEQ of register 9 on. When CLOK goes from low to high while XBUSY is low, XBUSY does not become high for a maximum of 100µs after that point. This is to prevent the transfer of erroneous data to the servo when XBUSY changes from low to high by the monostable multivibrator, which is reset by CLOK being low (when XBUSY is low). In addition, a MAX timer is built into this LSI as a countermeasure against abnormal operation due to external disturbances, etc. When the auto sequence command is sent from the CPU, this command assumes a $4XY format, in which X specifies the command and Y sets the MAX timer value and timer range. If the executed auto sequence command does not terminate within the set timer value, the auto sequence is interrupted (like $40). See [1] "$4X commands" concerning the timer value and range. Also, the MAX timer is invalidated by inputting $4X0. Although this command is explained in the format of $4X in the following command descriptions, the timer value and timer range are actually sent together from the CPU. (a) Auto focus ($47) Focus search-up is performed, FOK and FZC are checked, and the focus servo is turned on. If $47 is received from the CPU, the focus servo is turned on according to Fig. 4-6. The auto focus starts with focus search-up, and note that the pickup should be lowered beforehand (focus search-down). In addition, blind E of register 5 is used to eliminate FZC chattering. Concretely, the focus servo is turned on at the falling edge of FZC after FZC has been continuously high for a longer time than E. (b) Track jump 1, 10 and 2N-track jumps are performed respectively. Always use this when the focus, tracking, and sled servos are on. Note that tracking gain-up and braking-on ($17) should be sent beforehand because they are not involved in this sequence. • 1-track jump When $48 ($49 for REV) is received from the CPU, a FWD (REV) 1-track jump is performed in accordance with Fig. 4-7. Set blind A and brake B with register 5. • 10-track jump When $4A ($4B for REV) is received from the CPU, a FWD (REV) 10-track jump is performed an accordance with Fig. 4-8. The principal difference from the 1-track jump is to kick the sled. In addition, after kicking the actuator, when 5 tracks have been counted through COUT, the brake is applied to the actuator. Then, when the actuator speed is found to have slowed up enough (determined by the COUT cycle becoming longer than the overflow C set with register 5), the tracking and sled servos are turned on. – 70 – CXD2585Q • 2N-track jump When $4C ($4D for REV) is received from the CPU, a FWD (REV) 2N-track jump is performed in accordance with Fig. 4-9. The track jump count N is set with register 7. Although N can be set to 216 tracks, note that the setting is actually limited by the actuator. COUT is used for counting the number of jumps when N is less than 16, and MIRR is used with N is 16 or more. Although the 2N-track jump basically follows the same sequence as the 10-track jump, the one difference is that after the tracking servo is turned on, the sled continues to move only for "D", set with register 6. • Fine search When $44 ($45 for REV) is received from the CPU, a FWD (REV) fine search (N-track jump) is performed in accordance with Fig. 4-10. The differences from a 2N-track jump are that a higher precision is achieved by controlling the traverse speed, and a longer distance jump is achieved by controlling the sled. The track jump count is set with register 7. N can be set to 216 tracks. After kicking the actuator and sled, the traverse speed is controlled based on the overflow G. Set kick D and F with register 6 and overflow G with register 5. Also, sled speed control during traverse can be turned off by causing COMP to fall. Set the number of tracks during which COMP falls with register B. After N tracks have been counted through COUT, the brake is applied to the actuator and sled. (This is performed by turning on the tracking servo for the actuator, and by kicking the sled in the opposite direction during the time for kick D set with register 6.) Then, the tracking and sled servos are turned on. Set overflow G to the speed required to slow up just before the track jump terminates. (The speed should be such that it will come on-track when the tracking servo turns on at the termination of the track jump.) For example, set the target track count N – α for the traverse monitor counter which is set with register B, and COMP will be monitored. When the falling edge of this COMP is detected, overflow G can be reset. • M-track move When $4E ($4F for REV) is received from the CPU, a FWD (REV) M-track move is performed in accordance with Fig. 4-11. M can be set to 216 tracks. Like the 2N-track jump, COUT is used for counting the number of moves when M is less than 16, and MIRR is used when M is 16 or more. The M-track move is executed by moving only the sled, and is therefore suited for moving across several thousand to several ten-thousand tracks. In addition, the track and sled servos are turned off after M tracks have been counted through COUT or MIRR unlike for the other jumps. Transfer $25 from the microcomputer after the actuator has stabilized. – 71 – CXD2585Q Auto focus Focus search up FOK = H NO YES FZC = H NO YES FZC = L Check whether FZC is continuously high for the period of time E set with register 5. NO YES Focus servo ON END Fig. 4-6-(a). Auto Focus Flow Chart $47 Latch XLAT FOK FZC BUSY Command for DSSP Blind E $03 Fig. 4-6-(b). Auto Focus Timing Chart – 72 – $08 CXD2585Q 1 Track Track FWD kick sled servo OFF (REV kick for REV jump) WAIT (Blind A) COUT = NO YES Track REV kick (FWD kick for REV jump) WAIT (Brake B) Track, sled servo ON END Fig. 4-7-(a). 1-Track Jump Flow Chart $48 (REV = $49) Latch XLAT COUT BUSY Brake B Blind A Command for DSSP $2C ($28) $28 ($2C) Fig. 4-7-(b). 1-Track Jump Timing Chart – 73 – $25 CXD2585Q 10 Track Track, sled FWD kick WAIT (Blind A) (Counts COUT × 5) COUT = 5 ? NO YES Track, REV kick Checks whether the COUT cycle is longer than overflow C. C = Overflow ? NO YES Track, sled servo ON END Fig. 4-8-(a). 10-Track Jump Flow Chart $4A (REV = $4B) Latch XLAT COUT BUSY Blind A COUT 5 count Overflow C Command for DSSP $2E ($2B) $2A ($2F) Fig. 4-8-(b). 10-Track Jump Timing Chart – 74 – $25 CXD2585Q 2N Track Track, sled FWD kick WAIT (Blind A) COUT (MIRR) = N NO Counts COUT for the first 16 times and MIRR for more times. YES Track REV kick C = Overflow NO YES Track servo ON WAIT (Kick D) Sled servo ON END Fig. 4-9-(a). 2N-Track Jump Flow Chart $4C (REV = $4D) Latch XLAT COUT (MIRR) BUSY Blind A Command for DSSP $2A ($2F) COUT (MIRR) N count Overflow C $2E ($2B) $26 ($27) Fig. 4-9-(b). 2N-Track Jump Timing Chart – 75 – Kick D $25 CXD2585Q Fine Search Track Servo ON Sled FWD Kick WAIT (Kick D) Track Sled FWD Kick WAIT (Kick F) Traverse Speed Ctrl (Overflow G) COUT = N? NO YES Track Servo ON Sled REV Kick WAIT (Kick D) Track Sled Servo ON END Fig. 4-10-(a). Fine Search Flow Chart $44 (REV = $45) latch XLAT COUT BUSY Command for DSSP Kick D $26 ($27) Kick F Traverse Speed Control (Overflow G) & COUT N count $2A ($2F) Kick D $27 ($26) $25 Fig. 4-10-(b). Fine Search Timing Chart – 76 – CXD2585Q M Track Move Track Servo OFF Sled FWD Kick WAIT (Blind A) Counts COUT for M < 16. Counts MIRR for M ≥ 16. COUT (MIRR) = M NO YES Track, Sled Servo OFF END Fig. 4-11-(a). M-Track Move Flow Chart $4E (REV = $4F) Latch XLAT COUT (MIRR) BUSY Blind A Command for DSSP COUT (MIRR) M count $20 $22 ($23) Fig. 4-11-(b). M-Track Move Timing Chart – 77 – CXD2585Q § 4-7. Digital CLV Fig. 4-12 shows the block diagram. Digital CLV outputs MDS error and MDP error signals with PWM, with the sampling frequency increased up to 130kHz during normal-speed playback in CLVS, CLVP and other modes. In addition, the digital spindle servo gain is variable. Digital CLV CLVS U/D MDS Error MDP Error Measure Measure Over Sampling Filter-1 2/1 MUX CLV P/S Gain MDP Gain MDS 1/2 Mux Gain DCLV Over Sampling Filter-2 CLV P/S Noise Shape Modulation KICK, BRAKE, STOP PWMI LPWR Mode Select MDP CLVS U/D: Up/down signal from CLVS servo MDS error: Frequency error for CLVP servo MDP error: Phase error for CLVP servo PWMI: Spindle drive signal from the microcomputer for CAV servo Fig. 4-12. Block Diagram – 78 – CXD2585Q § 4-8. Playback Speed In the CXD2585Q, the following playback modes can be selected through different combinations of XTAI, XTSL pin, double-speed command (DSPB), VCO1 selection command (VCOSEL1), VCO1 frequency division commands (KSL3, KSL2) and command transfer rate selector (ASHS) in CLV-N or CLV-W mode. Mode XTAI XTSL DSPB VCOSEL1∗1 ASHS Playback speed 1 768Fs 1 0 0/1 0 1× C1: double; C2: quadruple 2 768Fs 1 1 0/1 0 2× C1: double; C2: double 3 768Fs 0 0 1 1 2× C1: double; C2: quadruple 4 768Fs 0 1 1 1 4× C1: double; C2: double 5 384Fs 0 0 0/1 0 1× C1: double; C2: quadruple 6 384Fs 0 1 0/1 0 2× C1: double; C2: double 7 384Fs 1 1 0/1 0 1× C1: double; C2: double Error correction∗2 ∗1 Actually, the optimal value should be used together with KSL3 and KSL2. ∗2 When $8 ERC4 = 1, C2 is for quadruple correction with DSPB = 1. The playback speed can be varied by setting VP0 to VP7 in CAV-W mode. See "[3] Description of Modes" for details. – 79 – CXD2585Q § 4-9. Asymmetry Correction Fig. 4-13 shows the block diagram and circuit example. ASYE ASYO R1 RFAC R1 R2 R1 ASYI R1 BIAS R1 R2 Fig. 4-15. Asymmetry Correction Application Circuit – 80 – = 2 5 CXD2585Q §4-10. CD TEXT Data Demodulation • In order to demodulate the CD TEXT data, set the command $8 Data 6 D3 TXON to 1. During TXON = 1, connect EXCK to low and do not use the data output from SBSO because the CD TEXT demodulation circuit uses EXCK and the SBSO pin exclusively. It requires 26.7ms (max.) to demodulate the CD TEXT data correctly after TXON is set to 1. • The CD TEXT data is output by switching the SQSO pin with the command. The CD TEXT data output is enabled by setting the command $8 Data 6 D2 TXOUT to 1. To read data, the readout clock should be input to SQCK. • The readable data are the CRC counting results for the each pack and the CD TEXT data (16 bytes) except for CRC data. • When the CD TEXT data is read, the order of the MSB and LSB is inverted within each byte. As a result, although the sequence of the bytes is the same, the bits within the bytes are now ordered LSB first. • Data which can be stored in the LSI is 1 packet (4 packs). TXON CD TEXT Decoder EXCK SBSO Subcode Decoder SQCK SQSO TXOUT Fig. 4-14. Block Diagram of CD TEXT Demodulation Circuit – 81 – – 82 – TXOUT (command) SQCK SQSO TXOUT (command) SQCK SQSO SCOR 4 3 2 1 CRC CRC CRC CRC CRC Data CRCF 0 0 80 Clock Subcode Q Data 0 0 R2 W1 V1 U1 S1 Pack2 16Byte R1 U3 LSB T3 520 Clock MSB Pack1 16Byte T1 ID1 (Pack1) 0 4bit Fig. 4-15. CD TEXT Data Timing Chart S2 LSB CRC 4bit S3 U2 Pack4 16Byte R3 W2 V2 ID2 (Pack1) Pack3 16Byte LSB T2 W4 MSB V4 U4 T4 ID3 (Pack1) CRCF S4 CXD2585Q CXD2585Q [5] Description of Servo Signal Processing System Functions and Commands §5-1. General Description of Servo Signal Processing System (VDD: Supply voltage) Focus servo Sampling rate: 88.2kHz (when MCK = 128Fs) Input range: 0.3VDD to 0.7VDD Output format: 7-bit PWM Other: Offset cancel Focus bias adjustment Focus search Gain-down function Defect countermeasure Auto gain control Tracking servo Sampling rate: Input range: Output format: Other: Sled servo Sampling rate: Input range: Output format: Other: 88.2kHz (when MCK = 128Fs) 0.3VDD to 0.7VDD 7-bit PWM Offset cancel E:F balance adjustment Track jump Gain-up function Defect countermeasure Drive cancel Auto gain control Vibration countermeasure 345Hz (when MCK = 128Fs) 0.3VDD to 0.7VDD 7-bit PWM Sled move FOK, MIRR, DFCT signal generation RF signal sampling rate: 1.4MHz (when MCK = 128Fs) Input range: 0.43VDD to VDD Other: RF zero level automatic measurement – 83 – CXD2585Q §5-2. Digital Servo Block Master Clock (MCK) The clock with the 2/3 frequency of the crystal is supplied to the digital servo block. XT4D and XT2D are $3F commands, and XT1D is $3E command. (Default = 0) The digital servo block is designed with an MCK frequency of 5.6448MHz (128Fs) as typical. Mode XTAI FSTO XTSL XT4D XT2D XT1D Frequency division ratio MCK 1 384Fs 256Fs ∗ ∗ ∗ 1 1 256Fs 2 384Fs 256Fs ∗ ∗ 1 0 1/2 128Fs 3 384Fs 256Fs 0 0 0 0 1/2 128Fs 4 768Fs 512Fs ∗ ∗ ∗ 1 1 512Fs 5 768Fs 512Fs ∗ ∗ 1 0 1/2 256Fs 6 768Fs 512Fs ∗ 1 0 0 1/4 128Fs 7 768Fs 512Fs 1 0 0 0 1/4 128Fs Fs = 44.1kHz, ∗: Don’t care Table 5-1. – 84 – CXD2585Q § 5-3. DC Offset Cancel [AVRG (Average) Measurement and Compensation] (See Fig. 5-3.) The CXD2585Q can measure the average of RFDC, VC, FE and TE and compensate these signals using the measurement results to control the servo effectively. This AVRG measurement and compensation is necessary to initialize the CXD2585Q, and is able to cancel the DC offset. AVRG measurement takes the levels applied to the VC, FE, RFDC and TE pins as the digital average of 256 samples, and then loads these values into each AVRG register. The AVRG measurement commands are D15 (VCLM), D13 (FLM), D11 (RFLM) and D4 (TLM) of $38. Measurement is on when the respective command is set to 1. AVRG measurement requires approximately 2.9ms to 5.8ms (when MCK = 128Fs) after the command is received. The completion of AVRG measurement operation can be monitored by the SENS pin. (See Timing Chart 5-2.) Monitoring requires that the upper 8 bits of the command register are 38 (Hex). XLAT 2.9 to 5.8ms SENS ( = XAVEBSY) AVRG measurement completed Max. 1µs Timing Chart 5-2. <Measurement> VC AVRG: The VC DC offset (VC AVRG) which is the center voltage for the system is measured and used to compensate the FE, TE and SE signals. FE AVRG: The FE DC offset (FE AVRG) is measured and used to compensate the FE and FZC signals. TE AVRG: The TE DC offset (TE AVRG) is measured and used to compensate the TE and SE signals. RF AVRG: The RF DC offset (RF AVRG) is measured and used to compensate the RFDC signal. <Compensation> RFLC: (RF signal – RF AVRG) is input to the RF In register. "00" is input when the RF signal is lower than RF AVRG. TLC0: (TE signal – VC AVRG) is input to the TRK In register. TLC1: (TE signal – TE AVRG) is input to the TRK In register. VCLC: (FE signal – VC AVRG) is input to the FCS In register. FLC1: (FE signal – FE AVRG) is input to the FCS In register. FLC0: (FE signal – FE AVRG) is input to the FZC register. Two methods of canceling the DC offset are assumed for the CXD2585Q. These methods are shown in Figs. 5-3a and 5-3b. An example of AVRG measurement and compensation commands is shown below. $38 08 00 (RF AVRG measurement) $38 20 00 (FE AVRG measurement) $38 00 10 (TE AVRG measurement) $38 14 0A (Compensation on [RFLC, FLC0, FLC1, TLC1], corresponds to Fig. 5-3a.) See the description of $38 for these commands. – 85 – CXD2585Q § 5-4. E:F Balance Adjustment Function (See Fig. 5-3.) When the disc is rotated with the laser on, and with the FCS (focus) servo on via FCS Search (focus search), the traverse waveform appears in the TE signal due to disc eccentricity. In this condition, the low-frequency component can be extracted from the TE signal using the built-in TRK hold filter by setting D5 (TBLM) of $38 to 1. The extracted low-frequency component is loaded into the TRVSC register as a digital value, and the TRVSC register value is established when TBLM returns to "0". Next, setting D2 (TLC2) of $38 to 1 compensates the values obtained from the TE and SE input pins with the TRVSC register value (subtraction), allowing the E:F balance offset to be adjusted. (See Fig. 5-3.) § 5-5. FCS Bias (Focus Bias) Adjustment Function The FBIAS register value can be added to the FCS servo filter input by setting D14 (FBON) of $3A to 1. (See Fig. 5-3.) When D11 = 0 and D10 = 1 is set by $34F, the FBIAS register value can be written using the 9-bit value of D9 to D1 (D9: MSB). In addition, the RF jitter can be monitored by setting the $8 command SOCT to 1. (See "DSP Block Timing Chart".) The FBIAS register can be used as a counter by setting D13 (FBSS) of $3A to 1. The FBIAS register functions as an up counter when D12 (FBUP) of $3A = 1, and as a down counter when D12 (FBUP) of $3A = 0. The number of up and down steps can be changed by setting D11 and D10 (FBV1 and FBV0) of $3A. When using the FBIAS register as a counter, the counter stops when the value set beforehand in FBL9 to FBL1 of $34 matches the FCSBIAS value. Also, if the upper 8 bits of the command register are $3A at this time, SENS goes to high and the counter stop can be monitored. A B C FBIAS setting value (FB9 to FB1) LIMIT value (FBL9 to FBL1) Here, assume the FBIAS setting value FB9 to FB1 and the FBIAS LIMIT value FBL9 to FBL1 are set in status A. For example, if command registers FBUP = 0, FBV1 = 0, FBV0 = 0 and FBSS = 1 are set from this status, down count starts from status A and approaches the set LIMIT value. When the LIMIT value is reached and the FBIAS value matches FBL9 to FBL1, the counter stops and the SENS pin goes to high. Note that the up/down counter counts at each sampling cycle of the focus servo filter. The number of steps by which the count value changes can be selected from 1, 2, 4 or 8 steps by FBV1 and FBV0. When converted to FE input, 1 step corresponds to 1/512 × VDD × 0.4. A: Register mode B: Counter mode C: Counter mode (when stopped) SENS pin – 86 – CXD2585Q RFDC from A/D To RF In register – RF AVRG register RFLC SE from A/D Tp SLD In register – TLC1 · TLD1 TLC2 · TLD2 – To TRK In register TE from A/D – TE AVRG register – TRVSC register TLC1 TLC2 FE from A/D To FCS In register – FE AVRG register FLC1 FBIAS register + FBON FLC0 To FZC register – Fig. 5-3a. RFDC from A/D To RF In register – RF AVRG register RFLC SE from A/D To SLD In register TLC0 · TLD0 – TLC2 · TLD2 – To TRK In register TE from A/D – – TLC0 TRVSC register VC AVRG register TLC2 VCLC FE from A/D To FCS In register – FE AVRG register FBIAS register FLC0 – Fig. 5-3b. – 87 – + FBON To FZC register CXD2585Q § 5-6. AGCNTL (Automatic Gain Control) Function The AGCNTL function automatically adjusts the filter internal gain in order to obtain the appropriate servo loop gain. AGCNTL not only copes with the sensitivity variation of the actuator and photo diode, etc., but also obtains the optimal gain for each disc. The AGCNTL command is sent when each servo is turned on. During AGCNTL operation, if the upper 8 bits of the command register are 38 (Hex), the completion of AGCNTL operation can be confirmed by monitoring the SENS pin. (See Timing Chart 5-4 and "Description of SENS Signals".) Setting D9 and D8 of $38 to 1 set FCS (focus) and TRK (tracking) respectively to AGCNTL operation. Note) During AGCNTL operation, each servo filter gain must be normal, and the anti-shock circuit (described hereafter) must be disabled. XLAT Max. 11.4µs SENS ( = AGOK) AGCNTL completion Timing Chart 5-4. Coefficient K13 changes for AGF (focus AGCNTL) and coefficients K23 and K07 change for AGT (tracking AGCNTL) due to AGCNTL. These coefficients change from 01 to 7F (Hex), and they must also be set within this range when written externally. After AGCNTL operation has completed, these coefficient values can be confirmed by reading them out from the SENS pin with the serial readout function (described hereafter). AGCNTL related settings The following settings can be changed with $35, $36 and $37. FG6 to FG0; AGF convergence gain setting, effective setting range: 00 to 57 (Hex) TG6 to TG0; AGT convergence gain setting, effective setting range: 00 to 57 (Hex) AGS; Self-stop on/off AGJ; Convergence completion judgment time AGGF; Internally generated sine wave amplitude (AGF) AGGT; Internally generated sine wave amplitude (AGT) AGV1; AGCNTL sensitivity 1 (during rough adjustment) AGV2; AGCNTL sensitivity 2 (during fine adjustment) AGHS; Rough adjustment on/off AGHT; Fine adjustment time Note) Converging servo loop gain values can be changed with the FG6 to FG0 and TG6 to TG0 setting values. In addition, these setting values must be within the effective setting range. The default settings aim for 0dB at 1kHz. However, since convergence values vary according to the characteristics of each constituent element of the servo loop, FG and TG values should be set as necessary. – 88 – CXD2585Q AGCNTL and default operation have two stages. In the first stage, rough adjustment is performed with high sensitivity for a certain period of time (select 256/128ms with AGHT, when MCK = 128Fs), and the AGCNTL coefficient approaches the appropriate value. The sensitivity at this time can be selected from two types with AGV1. In the second stage, the AGCNTL coefficient is finely adjusted with relatively low sensitivity to further approach the appropriate value. The sensitivity for the second stage can be selected from two types with AGV2. In the second stage of default operation, when the AGCNTL coefficient reaches the appropriate value and stops changing, the CXD2585Q confirms that the AGCNTL coefficient has not changed for a certain period of time (select 63/31ms with AGHJ, when MCK = 128Fs), and then completes AGCNTL operation. (Self stop mode) This self-stop mode can be canceled by setting AGS to 0. In addition, the first stage is omitted for AGCNTL operation when AGHS is set to 0. An example of AGCNTL coefficient transitions during AGCNTL operation with various settings is shown in Fig. 5-5. Initial value Slope AGV1 AGCNTL coefficient value Slope AGV2 Convergence value AGHT AGJ AGCNTL start AGCNTL completion SENS Fig. 5-5. Note) Fig. 5-5 shows the case where the AGCNTL coefficient converges from the initial value to a smaller value. – 89 – CXD2585Q § 5-7. FCS Servo and FCS Search (Focus Search) The FCS servo is controlled by the 8-bit serial command $0X. (See Table 5-6.) Register name Command FOCUS CONTROL 0 D23 to D20 0 0 0 0 D19 to D16 1 0 ∗ ∗ FOCUS SERVO ON (FOCUS GAIN NORMAL) 1 1 ∗ ∗ FOCUS SERVO ON (FOCUS GAIN DOWN) 0 ∗ 0 ∗ FOCUS SERVO OFF, 0V OUT 0 ∗ 1 ∗ FOCUS SERVO OFF, FOCUS SEARCH VOLTAGE OUT 0 ∗ 1 0 FOCUS SEARCH VOLTAGE DOWN 0 ∗ 1 1 FOCUS SEARCH VOLTAGE UP ∗: Don't care Table 5-6. FCS Search FCS search is required in the course of turning on the FCS servo. Fig. 5-7 shows the signals for sending commands $00 → $02 → $03 and performing only FCS search operation. Fig. 5-8 shows the signals for sending $08 (FCS on) after that. $00 $02 $03 $00 $02 $03 0 FCSDRV FCSDRV RF RF FOK FOK FZC comparator level FE FE 0 FZC 0 FZC Fig. 5-7. Fig. 5-8. – 90 – $08 CXD2585Q § 5-8. TRK (Tracking) and SLD (Sled) Servo Control The TRK and SLD servos are controlled by the 8-bit command $2X. (See Table 5-9.) When the upper 4 bits of the serial data are 2 (Hex), TZC is output to the SENS pin. Register name 2 Command D23 to D20 TRACKING MODE 0 0 1 0 D19 to D16 0 0 ∗ ∗ TRACKING SERVO OFF 0 1 ∗ ∗ TRACKING SERVO ON 1 0 ∗ ∗ FORWARD TRACK JUMP 1 1 ∗ ∗ REVERSE TRACK JUMP ∗ ∗ 0 0 SLED SERVO OFF ∗ ∗ 0 1 SLED SERVO ON ∗ ∗ 1 0 FORWARD SLED MOVE ∗ ∗ 1 1 REVERSE SLED MOVE Table 5-9. ∗: Don't care TRK Servo The TRK JUMP (track jump) level can be set with 6 bits (D13 to D8) of $36. In addition, when the TRK servo is on and D17 of $1 is set to 1, the TRK servo filter switches to gain-up mode. The filter also switches to gain-up mode when the LOCK signal goes low or when vibration is detected with the anti-shock circuit (described hereafter) enabled. The CXD2585Q has 2 types of gain-up filter structures in TRK gain-up mode which can be selected by setting D16 of $1. (See Table 5-17.) SLD Servo The SLD MOV (sled move) output, composed of a basic value from 6 bits (D13 to D8) of $37, is determined by multiplying this value by 1×, 2×, 3×, or 4× magnification set using D17 and D16 when D18 = D19 = 0 is set with $3. (See Table 5-10.) SLD MOV must be performed continuously for 50µs or more. In addition, if the LOCK input signal goes low when the SLD servo is on, the SLD servo turns off. Note) When the LOCK signal is low, the TRK servo switches to gain-up mode and the SLD servo is turned off. These operations are disabled by setting D6 (LKSW) of $38 to 1. Register name 3 Command SELECT D23 to D20 0 0 1 1 D19 to D16 0 0 0 0 SLED KICK LEVEL (basic value × ±1) 0 0 0 1 SLED KICK LEVEL (basic value × ±2) 0 0 1 0 SLED KICK LEVEL (basic value × ±3) 0 0 1 1 SLED KICK LEVEL (basic value × ±4) Table 5-10. – 91 – CXD2585Q § 5-9. MIRR and DFCT Signal Generation The RF signal obtained from the RFDC pin is sampled at approximately 1.4MHz (when MCK = 128Fs) and loaded. The MIRR and DFCT signals are generated from this RF signal. MIRR Signal Generation The loaded RF signal is applied to peak hold and bottom hold circuits. An envelope is generated from the waveforms generated in these circuits, and the MIRR comparator level is generated from the average of this envelope waveform. The MIRR signal is generated by comparing the waveform generated by subtracting the bottom hold value from the peak hold value with this MIRR comparator level. (See Fig. 5-11.) The bottom hold speed and mirror sensitivity can be selected from 4 values using D7 and D6, and D5 and D4, respectively, of $3C. RF Peak Hold Bottom Hold Peak Hold – Bottom Hold MIRR Comp (Mirror comparator level) H MIRR L Fig. 5-11. DFCT Signal Generation The loaded RF signal is input to two peak hold circuits with different time constants, and the DFCT signal is generated by comparing the difference between these two peak hold waveforms with the DFCT comparator level. (See Fig. 5-12.) The DFCT comparator level can be selected from four values using D13 and D12 of $3B. RF Peak Hold1 Peak Hold2 Peak Hold2 – Peak Hold1 SDF (Defect comparator level) H DFCT L Fig. 5-12. – 92 – CXD2585Q § 5-10. DFCT Countermeasure Circuit The DFCT countermeasure circuit maintains the directionality of the servo so that the servo does not become easily dislocated due to scratches or defects on discs. Specifically, these operations are achieved by detecting scratches and defects with the DFCT signal generation circuit, and when DFCT goes high, applying the low frequency component of the error signal before DFCT went high to the FCS and TRK servo filter inputs. (See Fig. 5-13.) In addition, these operations are activated by the default. They can be disabled by setting D7 (DFSW) of $38 to 1. Hold Filter Error signal Input register Hold register EN DFCT Servo Filter Fig. 5-13. § 5-11. Anti-Shock Circuit When vibrations occur in the CD player, this circuit forces the TRK filter to switch to gain-up mode so that the servo does not become easily dislocated. This circuit is for systems which require vibration countermeasures. Concretely, vibrations are detected using an internal anti-shock filter and comparator circuit, and the gain is increased. (See Fig. 5-14.) The comparator level is fixed to 1/16 of the maximum comparator input amplitude. However, the comparator level is practically variable by adjusting the value of the anti-shock filter output coefficient K35. This function can be turned on and off by D19 of $1 when the brake circuit (described hereafter) is off. (See Table 5-17.) This circuit can also support an external vibration detection circuit, and can set the TRK servo filter to gain-up mode by inputting high level to the ATSK pin. When the upper 4 bits of the command register are 1 (Hex), vibration detection can be monitored from the SENS pin. It also can be monitored from the ATSK pin by setting the ASOT command of $3F to 0. ATSK TE Anti Shock Filter SENS Comparator TRK Gain Up Filter TRK PWM Gen TRK Gain Normal Filter Fig. 5-14. – 93 – CXD2585Q § 5-12. Brake Circuit Immediately after a long distance track jump it tends to be hard for the actuator to settle and for the servo to turn on. The brake circuit prevents these phenomenon. In principle, the brake circuit uses the tracking drive as a brake by cutting the unnecessary portions utilizing the 180° offset in the RF envelope and tracking error phase relationship which occurs when the actuator traverses the track in the radial direction from the inner track to the outer track and vice versa. (See Figs. 5-15 and 5-16.) Concretely, this operation is achieved by masking the tracking drive using the TRKCNCL signal generated by loading the MIRR signal at the edge of the TZC (Tracking Zero Cross) signal. The brake circuit can be turned on and off by D18 of $1. (See Fig. 5-17.) In addition, the low frequency for the tracking drive after masking can be boosted. (SFBK1, 2 of $34B) Inner track Outer track Outer track FWD REV Servo ON JMP JMP REV FWD Servo ON JMP JMP TRK DRV TRK DRV RF Trace RF Trace MIRR MIRR TE 0 TE TZC Edge TZC Edge TRKCNCL TRKCNCL TRK DRV (SFBK OFF) 0 TRK DRV (SFBK ON) 0 0 TRK DRV (SFBK OFF) 0 TRK DRV (SFBK ON) 0 SENS TZC out SENS TZC out Fig. 5-15. Register name 1 Inner track Command TRACKING CONTROL D23 to D20 0 0 0 1 Fig. 5-16. D19 to D16 1 0 ∗ ∗ ANTI SHOCK ON 0 ∗ ∗ ∗ ANTI SHOCK OFF ∗ 1 ∗ ∗ BRAKE ON ∗ 0 ∗ ∗ BRAKE OFF ∗ ∗ 0 ∗ TRACKING GAIN NORMAL ∗ ∗ 1 ∗ TRACKING GAIN UP ∗ ∗ ∗ 1 TRACKING GAIN UP FILTER SELECT 1 ∗ ∗ ∗ 0 TRACKING GAIN UP FILTER SELECT 2 ∗: Don't care Table 5-17. – 94 – CXD2585Q § 5-13. COUT Signal The COUT signal is output to count the number of tracks during traverse, etc. It is basically generated by loading the MIRR signal at both edges of the TZC signal. The used TZC signal can be selected from among three different phases according to the COUT signal application. • HPTZC: For 1-track jumps Fast phase COUT signal generation with a fast phase TZC signal. (The TZC phase is advanced by a cutoff 1kHz digital HPF; when MCK = 128Fs.) • STZC: For COUT generation when MIRR is externally input and for applications other than COUT generation. This is generated by sampling the TE signal at 700kHz. (when MCK = 128Fs) • DTZC: For high-speed traverse Reliable COUT signal generation with a delayed phase STZC signal. Since it takes some time to generate the MIRR signal, it is necessary to delay the TZC signal in accordance with the MIRR signal delay during high-speed traverse. The COUT signal output method is switched with D15 and D14 of $3C. When D15 = 1: STZC When D15 = 0 and D14 = 0: HPTZC When D15 = 0 and D14 = 1: DTZC When DTZC is selected, the delay can be selected from two values with D14 of $36. § 5-14. Serial Readout Circuit The following measurement and adjustment results can be read out from the SENS pin by inputting the readout clock to the SCLK pin by $39. (See Fig. 5-18, Table 5-19 and "Description of SENS Signals".) Specified commands $390C: VC AVRG measurement result $3908: FE AVRG measurement result $3904: TE AVRG measurement result $391F: RF AVRG measurement result XLAT tDLS $3953: $3963: $391C: $391D: FCS AGCNTL coefficient result TRK AGCNTL coefficient result TRVSC adjustment result FBIAS register value tSPW ••• SCLK 1/fSCLK Serial Readout Data (SENS pin) MSB LSB ••• Fig. 5-18. Item Symbol SCLK frequency fSCLK SCLK pulse width tSPW tDLS Delay time Min. Typ. Max. Unit 16 MHz 31.3 ns 15 µs Table 5-19. During readout, the upper 8 bits of the command register must be 39 (Hex). – 95 – CXD2585Q § 5-15. Writing to Coefficient RAM The coefficient RAM can be rewritten by $34. All coefficients have default values in the built-in ROM, and transfer from the ROM to the RAM is completed approximately 40µs (when MCK = 128Fs) after the XRST pin rises. (The coefficient RAM cannot be rewritten during this period.) After that, the characteristics of each built-in filter can be finely adjusted by rewriting the data for each address of the coefficient RAM. The coefficient rewrite command is comprised of 24 bits, with D14 to D8 of $34 as the address (D15 = 0) and D7 to D0 as data. Coefficient rewriting is completed 11.3µs (when MCK = 128Fs) after the command is received. When rewriting multiple coefficients, be sure to wait 11.3µs (when MCK = 128Fs) before sending the next rewrite command. § 5-16. PWM Output FCS, TRK and SLD PWM format outputs are described below. In particular, FCS and TRK use a double oversampling noise shaper. Timing Chart 5-20 and Fig. 5-21 show examples of output waveforms and drive circuits. MCK (5.6448MHz) ↑ ↑ ↑ ↑ ↑ ↑ ↑ Output value +A Output value –A Output value 0 64tMCK 64tMCK 64tMCK SLD SFDR AtMCK SRDR AtMCK FCS/TRK 32tMCK FFDR/ TFDR FRDR/ TRDR tMCK = A tMCK 2 32tMCK 32tMCK 32tMCK A tMCK 2 A tMCK 2 1 ≈180ns 5.6448MHz A tMCK 2 Timing Chart 5-20. VCC R R DRV RDR FDR R R VEE Fig. 5-21. Drive Circuit – 96 – 32tMCK 32tMCK CXD2585Q § 5-17. Servo Status Changes Produced by LOCK Signal When the LOCK signal becomes low, the TRK servo switches to the gain-up mode and the SLD servo turns off in order to prevent SLD free-running. Setting D6 (LKSW) of $38 to 1 deactivates this function. In other words, neither the TRK servo nor the SLD servo change even when the LOCK signal becomes low. This enables microcomputer control. § 5-18. Description of Commands and Data Sets $34 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 KA6 KA5 KA4 KA3 KA2 KA1 KA0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 0 0 When D15 = 0. KA6 to KA0: Coefficient address KD7 to KD0: Coefficient data $348 (preset: $348 000) D15 D14 D13 D12 1 0 0 0 D11 PGFS1 PGFS0 PFOK1 PFOK0 These commands set the GFS pin hold time. The hold time is inversely proportional to the playback speed. PGFS1 PGFS0 Processing 0 0 High when the frame sync is of the correct timing, low when not the correct timing. 0 1 High when the frame sync is of the correct timing, low when continuously not the correct timing for 2ms or longer. 1 0 High when the frame sync is of the correct timing, low when continuously not the correct timing for 4ms or longer. 1 1 High when the frame sync is the correct timing, low when continuously not the correct timing for 8ms or longer. These commands set the FOK hold time. See $3B for the FOK slice level. These are the values when MCK = 128Fs, and the hold time is inversely proportional to the MCK setting. PFOK1 PFOK0 Processing 0 0 High when the RFDC value is higher than the FOK slice level, low when lower than the FOK slice level. 0 1 High when the RFDC value is higher than the FOK slice level, low when continuously lower than the FOK slice level for 4.35ms or more. 1 0 High when the RFDC value is higher than the FOK slice level, low when continuously lower than the FOK slice level for 10.16ms or more. 1 1 High when the RFDC value is higher than the FOK slice level, low when continuously lower than the FOK slice level for 21.77ms or more. – 97 – CXD2585Q $34B (preset: $34B 000) D15 D14 D13 D12 1 0 1 1 D11 D10 SFBK1 SFBK2 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 0 0 0 0 D2 D1 D0 The low frequency can be boosted for brake operation. See § 5-12 for brake operation. SFBK1: When 1, brake operation is performed by setting the LowBooster-1 input to 0. This is valid only when TLB1ON = 1. The preset is 0. SFBK2: When 1, brake operation is performed by setting the LowBooster-2 input to 0. This is valid only when TLB2ON = 1. The preset is 0. $34C (preset: $34C 000) D15 1 D14 1 D13 0 D12 D11 D10 0 THB ON FHB ON D9 D8 D7 TLB1 FLB1 TLB2 ON ON ON D6 0 D5 D4 D3 HBST1 HBST0 LB1S1 LB1S0 LB2S1 LB2S0 These commands turn on the boost function. (See § 5-20. Filter Composition.) There are five boosters (three for the TRK filter and two for the FCS filter) which can be turned on and off independently. THBON: When 1, the high frequency is boosted for the TRK filter. Preset when 0. FHBON: When 1, the high frequency is boosted for the FCS filter. Preset when 0. TLB1ON: When 1, the low frequency is boosted for the TRK filter. Preset when 0. FLB1ON: When 1, the low frequency is boosted for the FCS filter. Preset when 0. TLB2ON: When 1, the low frequency is boosted for the TRK filter. Preset when 0. The difference between TLB1ON and TLB2ON is the position where the low frequency is boosted. For TLB1ON, the low frequency is boosted before the TRK jump, and for TLB2ON, after the TRK jump. The following commands set the boosters. (See § 5-20. Filter Composition.) HBST1, HBST0: TRK and FCS HighBooster setting. HighBooster has the configuration shown in Fig. 5-24a, and can select three different combinations of coefficients BK1, BK2 and BK3. (See Table 5-25a.) An example of characteristics is shown in Fig. 5-26a. These characteristics are the same for both the TRK and FCS filters. The sampling frequency is 88.2kHz (when MCK = 128Fs). LB1S1, LB1S0: TRK and FCS LowBooster-1 setting. LowBooster-1 has the configuration shown in Fig. 5-24b, and can select three different combinations of coefficients BK4, BK5 and BK6. (See Table 5-25b.) An example of characteristics is shown in Fig. 5-26b. These characteristics are the same for both the TRK and FCS filters. The sampling frequency is 88.2kHz (when MCK = 128Fs). LB2S1, LB2S0: TRK LowBooster-2 setting. LowBooster-2 has the configuration shown in Fig. 5-24c, and can select three different combinations of coefficients BK7, BK8 and BK9. (See Table 5-25c.) An example of characteristics is shown in Fig. 5-26c. This booster is used exclusively for the TRK filter. The sampling frequency is 88.2kHz (when MCK = 128Fs). Note) Fs = 44.1kHz – 98 – CXD2585Q HighBooster setting BK3 Z–1 HBST1 HBST0 0 1 1 — 0 1 Z–1 BK1 BK2 Fig. 5-24a. LB1S1 Z–1 BK3 –120/128 –124/128 –126/128 96/128 112/128 120/128 2 2 2 BK5 0 1 1 LowBooster-1 setting LB1S0 Z–1 — 0 1 BK4 BK5 BK6 –255/256 –511/512 –1023/1024 1023/1024 2047/2048 4095/4096 1/4 1/4 1/4 Table 5-25b. Fig. 5-24b. LB2S1 BK9 Z–1 BK8 0 1 1 Fig. 5-24c. LowBooster-2 setting LB2S0 Z–1 BK7 BK2 Table 5-25a. BK6 BK4 BK1 — 0 1 BK7 BK8 BK9 –255/256 –511/512 –1023/1024 1023/1024 2047/2048 4095/4096 1/4 1/4 1/4 Table 5-25c. – 99 – CXD2585Q 15 12 9 3 2 1 6 Gain [dB] 3 0 –3 –6 –9 –12 –15 1 10 100 1k 10k 1k 10k Frequency [Hz] +90 +72 3 2 1 Phase [degree] +36 0 –36 –72 –90 1 10 100 Frequency [Hz] Fig. 5-26a. Servo HighBooster Characteristics [FCS, TRK] (MCK = 128Fs) 1 HBST1 = 0 2 HBST1 = 1, HBST0 = 0 – 100 – 3 HBST1 = 1, HBST0 = 1 CXD2585Q 15 12 9 6 Gain [dB] 3 2 3 1 0 –3 –6 –9 –12 –15 1 10 100 1k 10k 1k 10k Frequency [Hz] +90 +72 Phase [degree] +36 3 2 1 0 –36 –72 –90 1 10 100 Frequency [Hz] Fig. 5-26b. Servo LowBooster1 Characteristics [FCS, TRK] (MCK = 128Fs) 1 LB1S1 = 0 2 LB1S1 = 1, LB1S0 = 0 – 101 – 3 LB1S1 = 1, LB1S0 = 1 CXD2585Q 15 12 9 6 Gain [dB] 3 2 3 1 0 –3 –6 –9 –12 –15 1 10 100 1k 10k 1k 10k Frequency [Hz] +90 +72 Phase [degree] +36 3 2 1 0 –36 –72 –90 1 10 100 Frequency [Hz] Fig. 5-26c. Servo LowBooster2 Characteristics [FCS, TRK] (MCK = 128Fs) 1 LB2S1 = 0 2 LB2S1 = 1, LB2S0 = 0 – 102 – 3 LB2S1 = 1, LB2S0 = 1 CXD2585Q $34F D15 D14 D13 D12 D11 D10 1 1 1 1 1 0 D9 D8 D7 D6 D5 D4 D3 D2 D1 FBL9 FBL8 FBL7 FBL6 FBL5 FBL4 FBL3 FBL2 FBL1 D0 — When D15 = D14 = D13 = D12 = D11 = 1 ($34F) D10 = 0 FBIAS LIMIT register write FBL9 to FBL1: Data; data compared with FB9 to FB1, FBL9 = MSB. When using the FBIAS register in counter mode, counter operation stops when the value of FB9 to FB1 matches with FBL9 to FBL1. D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 1 1 1 1 0 1 FB9 FB8 FB7 FB6 FB5 FB4 FB3 FB2 FB1 — When D15 = D14 = D13 = D12 = 1 ($34F) D11 = 0, D10 = 1 FBIAS register write FB9 to FB1: Data; two's complement data, FB9 = MSB. For FE input conversion, FB9 to FB1 = 011111111 corresponds to 255/256 × VDD/5 and FB9 to FB1 = 100000000 to –256/256 × VDD/5 respectively. (VDD: supply voltage) D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 1 1 1 1 0 0 TV9 TV8 TV7 TV6 TV5 TV4 TV3 TV2 TV1 TV0 When D15 = D14 = D13 = D12 = 1 ($34F) D11 = 0, D10 = 0 TRVSC register write TV9 to TV0: Data; two's complement data, TV9 = MSB. For TE input conversion, TV9 to TV0 = 0011111111 corresponds to 255/256 × VDD/5 and TV9 to TV0 = 1100000000 to –256/256 × VDD/5 respectively. (VDD: supply voltage) Note) • When the TRVSC register is read out, the data length is 9 bits. At this time, data corresponding to each bit TV8 to TV0 during external write are read out. • When reading out internally measured values and then writing these values externally, set TV9 the same as TV8. – 103 – CXD2585Q $35 (preset: $35 58 2D) D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 FT1 FT0 FS5 FS4 FS3 FS2 FS1 FS0 FTZ FG6 FG5 FG4 FG3 FG2 FG1 FG0 FT1, FT0, FTZ: Focus search-up speed Default value: 010 (0.673 × VDD V/s) Focus drive output conversion ∗ FT1 FT0 FTZ 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 0 0 0 1 1 1 1 Focus search speed [V/s] 1.35 × VDD 0.673 × VDD 0.449 × VDD 0.336 × VDD 1.79 × VDD 1.08 × VDD 0.897 × VDD 0.769 × VDD ∗: preset, VDD: PWM driver supply voltage FS5 to FS0: Default value: Focus search limit voltage 011000 (±24/64 × VDD, VDD: PWM driver supply voltage) FG6 to FG0: Focus drive output conversion AGF convergence gain setting value Default value: 0101101 $36 (preset: $36 0E 2E) D15 D14 D13 D12 D11 D10 D9 D8 TDZC DTZC TJ5 TJ4 TJ3 TJ2 TJ1 TJ0 SFJP TG6 TDZC: DTZC: TJ5 to TJ0: SFJP: TG6 to TG0: D7 D6 D5 D4 D3 D2 D1 D0 TG5 TG4 TG3 TG2 TG1 TG0 Selects the TZC signal for generating the TRKCNCL signal during brake circuit operation. TDZC = 0: The edge of the HPTZC or STZC signal, whichever has the faster phase, is used. TDZC = 1: The edge of the HPTZC or STZC signal or the tracking drive signal zero-cross, whichever has the fastest phase, is used. (See § 5-12.) DTZC delay (8.5/4.25µs, when MCK = 128Fs) Default value: 0 (4.25µs) Track jump voltage Default value: 001110 (≈ ±14/64 × VDD, VDD: PWM driver supply voltage) Tracking drive output conversion Surf jump mode on/off The tracking PWM output is generated by adding the tracking filter output and TJReg (TJ5 to 0), by setting D7 to 1 (on) AGT convergence gain setting value Default value: 0101110 – 104 – CXD2585Q $37 (preset: $37 50 BA) D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 FZSH FZSL SM5 SM4 SM3 SM2 SM1 SM0 AGS AGJ AGGF AGGT AGV1 AGV2 AGHS AGHT FZSH, FZSL: FZC (Focus Zero Cross) slice level Default value: 01 (1/8 × VDD × 0.4, VDD: supply voltage); FE input conversion ∗ FZSH FZSL Slice level 0 0 1 1 0 1 0 1 1/4 × VDD × 0.4 1/8 × VDD × 0.4 1/16 × VDD × 0.4 1/32 × VDD × 0.4 ∗: preset SM5 to SM0: AGS: AGJ: AGGF: AGGT: Sled move voltage Default value: 010000 (≈ ±16/64 × VDD, VDD: PWM driver supply voltage) Sled drive output conversion AGCNTL self-stop on/off Default value: 1 (on) AGCNTL convergence completion judgment time during low sensitivity adjustment (31/63ms, when MCK = 128Fs) Default value: 0 (63ms) Focus AGCNTL internally generated sine wave amplitude (small/large) Default value: 1 (large) Tracking AGCNTL internally generated sine wave amplitude (small/large) Default value: 1 (large) FE/TE input conversion AGGF 0 (small) 1/32 × VDD × 0.4 1 (large)∗ 1/16 × VDD × 0.4 AGGT 0 (small) 1/16 × VDD × 0.4 1 (large)∗ 1/8 × VDD × 0.4 ∗: preset AGV1: AGV2: AGHS: AGHT: AGCNTL convergence sensitivity during high sensitivity adjustment; high/low Default value: 1 (high) AGCNTL convergence sensitivity during low sensitivity adjustment; high/low Default value: 0 (low) AGCNTL high sensitivity adjustment on/off Default value: 1 (on) AGCNTL high sensitivity adjustment time (128/256ms, when MCK = 128Fs) Default value: 0 (256ms) – 105 – CXD2585Q $38 (preset: $38 00 00) D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 VCLM VCLC FLM FLC0 RFLM RFLC AGF AGT DFSW LKSW TBLM TCLM FLC1 TLC2 TLC1 TLC0 ∗VCLM: VC level measurement (on/off) VCLC: VC level compensation for FCS In register (on/off) ∗FLM: Focus zero level measurement (on/off) FLC0: Focus zero level compensation for FZC register (on/off) ∗RFLM: RF zero level measurement (on/off) RFLC: RF zero level compensation (on/off) AGF: Focus auto gain adjustment (on/off) AGT: Tracking auto gain adjustment (on/off) DFSW: Defect disable switch (on/off) Setting this switch to 1 (on) disables the defect countermeasure circuit. LKSW: Lock switch (on/off) Setting this switch to 1 (on) disables the sled free-running prevention circuit. TBLM: Traverse center measurement (on/off) ∗TCLM: Tracking zero level measurement (on/off) FLC1: Focus zero level compensation for FCS In register (on/off) TLC2: Traverse center compensation (on/off) TLC1: Tracking zero level compensation (on/off) TLC0: VC level compensation for TRK/SLD In register (on/off) Note) Commands marked with ∗ are accepted every 2.9ms. (when MCK = 128Fs) All commands are on when 1. – 106 – CXD2585Q $39 D15 D14 D13 D12 D11 D10 D9 D8 DAC SD6 SD5 SD4 SD3 SD2 SD1 SD0 DAC: SD6 to SD0: SD6 1 0 Serial data readout DAC mode (on/off) Serial readout data select SD5 Readout data Coefficient RAM data for address = SD5 to SD0 1 Data RAM data for address = SD4 to SD0 SD4 1 0 0 0 Readout data length 8 bits 16 bits SD3 to SD0 1 1 1 1 0 0 0 1 1 1 1 0 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 RF AVRG register RFDC input signal FBIAS register TRVSC register RFDC envelope (bottom) RFDC envelope (peak) RFDC envelope (peak) – (bottom) 8 bits 8 bits 9 bits 9 bits 8 bits 8 bits 8 bits $399F $399E $399D $399C $3993 $3992 $3991 1 1 0 0 0 0 0 1 0 1 0 0 0 0 ∗ ∗ ∗ 1 1 0 0 ∗ ∗ ∗ 1 0 1 0 VC AVRG register FE AVRG register TE AVRG register FE input signal TE input signal SE input signal VC input signal 9 bits 9 bits 9 bits 8 bits 8 bits 8 bits 8 bits $398C $3988 $3984 $3983 $3982 $3981 $3980 ∗: Don't care Note) Coefficients K40 to K4F cannot be read out. See the Description for Data Readout concerning readout methods for the above data. – 107 – CXD2585Q $3A (preset: $3A 00 00) D15 0 D14 D13 D12 D11 D10 FBON FBSS FBUP FBV1 FBV0 FBON: FBSS: FBUP: FBV1, FBV0: ∗ D9 0 D8 D7 D6 D5 TJD0 FPS1 FPS0 TPS1 TPS0 FPS1, FPS0: TPS1, TPS0: ∗ D3 0 D2 D1 D0 SJHD INBK MTI0 FBIAS (focus bias) register addition (on/off) The FBIAS register value is added to the signal loaded into the FCS In register by setting FBON = 1 (on). FBIAS (focus bias) register/counter switching FBSS = 0: register, FBSS = 1: counter. FBIAS (focus bias) counter up/down operation switching This performs counter up/down control when FBSS = 1. FBUP = 0: down counter, FBUP = 1: up counter. FBIAS (focus bias) counter voltage switching The number of FCS BIAS count-up/-down steps per cycle is decided by these bits. FBV1 FBV0 Number of steps per cycle 0 0 1 0 1 2 1 0 4 1 1 8 ∗: preset TJD0: D4 The counter changes once for each sampling cycle of the focus servo filter. When MCK is 128Fs, the sampling frequency is 88.2kHz. When converted to FE input, 1 step is approximately 1/29 × VDD × 0.4, VDD = supply voltage. This sets the tracking servo filter data RAM to 0 when switched from track jump to servo on only when SFJP = 1 (during surf jump operation). Gain setting when transferring data from the focus filter to the PWM block. Gain setting when transferring data from the tracking filter to the PWM block. These are effective for increasing the overall gain in order to widen the servo band. Operation when FPS1, FPS0 (TPS1, TPS0) = 00 is the same as usual (7-bit shift). However, 6dB, 12dB and 18dB can be selected independently for focus and tracking by setting the relative gain to 0dB when FPS1, FPS0 (TPS1, TPS0) = 00. FPS1 FPS0 Relative gain TPS1 TPS0 Relative gain 0 0 0dB 0 0 0dB 0 1 +6dB 0 1 +6dB 1 0 +12dB 1 0 +12dB 1 1 +18dB 1 1 +18dB ∗ ∗: preset SJHD: INBK: MTI0: This holds the tracking filter output at the value when surf jump starts during surf jump. When INBK = 0 (off), the brake circuit masks the tracking drive signal with TRKCNCL which is generated by fetching the MIRR signal at the TZC edge. When INBK = 1 (on), the tracking filter input is masked instead of the drive output. The tracking filter input is masked when the MIRR signal is high by setting MTI0 = 1 (on). – 108 – CXD2585Q $3B (preset: $3B E0 50) D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 SFO2 SFO1 SDF2 SDF1 MAX2 MAX1 SFOX BTF D2V2 D2V1 D1V2 D1V1 RINT SFOX, SFO2, SFO1: FOK slice level Default value: 011 (28/256 × VDD × 0.57, VDD = supply voltage) RFDC input conversion ∗ SFOX SFO2 SFO1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Slice level 16/256 × VDD × 0.57 20/256 × VDD × 0.57 24/256 × VDD × 0.57 28/256 × VDD × 0.57 32/256 × VDD × 0.57 40/256 × VDD × 0.57 48/256 × VDD × 0.57 56/256 × VDD × 0.57 ∗: preset SDF2, SDF1: DFCT slice level Default value: 10 (0.0313 × VDD × 1.14V) RFDC input conversion ∗ SDF2 SDF1 0 0 1 1 0 1 0 1 Slice level 0.0156 × VDD × 1.14 0.0234 × VDD × 1.14 0.0313 × VDD × 1.14 0.0391 × VDD × 1.14 ∗: preset, VDD: supply voltage MAX2, MAX1: DFCT maximum time (MCK = 128Fs) Default value: 00 (no timer limit) ∗ MAX2 MAX1 0 0 1 1 0 1 0 1 DFCT maximum time No timer limit 2.00ms 2.36 2.72 ∗: preset BTF: Bottom hold double-speed count-up mode for MIRR signal generation On/off (default: off) On when set to 1. – 109 – D2 D1 D0 0 0 0 CXD2585Q D2V2, D2V1: ∗ Peak hold 2 for DFCT signal generation Count-down speed setting Default value: 01 (0.086 × VDD × 1.14V/ms, 44.1kHz) [V/ms] unit items indicate RFDC input conversion; [kHz] unit items indicate the operating frequency of the internal counter. D2V2 D2V1 0 0 1 1 0 1 0 1 Count-down speed [V/ms] [kHz] 0.0431 × VDD × 1.14 0.0861 × VDD × 1.14 0.172 × VDD × 1.14 0.344 × VDD × 1.14 22.05 44.1 88.2 176.4 ∗: preset, VDD: supply voltage D1V2, D1V1: Peak hold 1 for DFCT signal generation Count-down speed setting Default value: 01 (0.688 × VDD × 1.14V/ms, 352.8kHz) [V/ms] unit items indicate RFDC input conversion; [kHz] unit items indicate the operating frequency of the internal counter. ∗ D1V2 D2V1 0 0 1 1 0 1 0 1 Count-down speed [V/ms] [kHz] 0.344 × VDD × 1.14 0.688 × VDD × 1.14 1.38 × VDD × 1.14 2.75 × VDD × 1.14 176.4 352.8 705.6 1411.2 ∗: preset, VDD: supply voltage RINT: This initializes the initial-state registers of the circuits which generate MIRR, DFCT and FOK. – 110 – CXD2585Q $3C (preset: $3C 00 80) D15 D14 D13 D12 D11 D10 D9 COSS COTS CETZ CETF COT2 COT1 MOT2 D8 0 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 BTS1 BTS0 MRC1 MRC0 COSS, COTS: This selects the TZC signal used when generating the COUT signal. Preset = HPTZC. COSS COTS 1 0 0 — 0 1 ∗ TZC STZC HPTZC DTZC ∗: preset, —: don't care STZC is the TZC generated by sampling the TE signal at 700kHz. (when MCK = 128Fs) DTZC is the delayed phase STZC. (The delay time can be selected by D14 of $36.) HPTZC is the fast phase TZC passed through a HPF with a cut-off frequency of 1kHz. See § 5-13. CETZ: The input from the TE pin normally enters the TRK filter and is used to generate the TZC signal. However, the input from the CE pin can also be used. This function is for the center error servo. When 0, the TZC signal is generated by using the signal input to the TE pin. When 1, the TZC signal is generated by using the signal input to the CE pin. When 0, the signal input to the TE pin is input to the TRK servo filter. When 1, the signal input to the CE pin is input to the TRK servo filter. CETF: These commands output the TZC signal. COT2, COT1: This outputs the TZC signal from the COUT pin. COT2 COT1 1 0 0 — 1 0 ∗ COUT pin output STZC HPTZC COUT ∗: preset, —: don't care MOT2: The STZC signal is output from the MIRR pin by setting MOT2 to 1. These commands set the MIRR signal generation circuit. BTS1, BTS0: This sets the count-up speed for the bottom hold value of the MIRR generation circuit. The time per step is approximately 708ns (when MCK = 128Fs). The preset value is BTS1 = 1, BTS0 = 0 like the CXD2586R. This is valid only when BTF of $3B is 0. MRC1, MRC0: This sets the minimum pulse width for masking the MIRR signal of the MIRR generation circuit. As noted in § 5-9, the MIRR signal is generated by comparing the waveform obtained by subtracting the bottom hold value from the peak hold value with the MIRR comparator level. Strictly speaking, however, for MIRR to become high, these levels must be compared continuously for a certain time. This sets that time. The preset value is MRC1 = 0, MRC0 = 0 like the CXD2586R. BTS1 BTS0 ∗ 0 0 1 1 0 1 0 1 Number of count-up steps per cycle 1 2 4 8 MRC1 MRC0 0 0 1 1 0 1 0 1 Setting time [µs] 5.669∗ 11.338 22.675 45.351 ∗: preset (when MCK = 128Fs) – 111 – CXD2585Q $3D (preset: $3D 00 00) D15 D14 D13 D12 SFID SFSK THID THSK SFID: D11 0 D10 D9 D8 TLD2 TLD1 TLD0 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 0 0 SLED servo filter input can be obtained not from SLD in Reg, but from M0D, which is the TRK filter second-stage output. When the low frequency component of the tracking error signal obtained from the RF amplifier is attenuated, the low frequency can be amplified and input to the SLD servo filter. Only during TRK servo gain up2 operation, coefficient K30 is used instead of K00. Normally, the DC gain between the TE input pin and M0D changes for TRK filter gain normal and gain up2, creating a difference in the DC level at M0D. In this case, the DC level of the signal transmitted to M00 can be kept uniform by adjusting the K30 value even during the above switching. TRK hold filter input can be obtained not from SLD in Reg, but from M0D, which is the TRK filter second-stage output. When signals other than the tracking error signal from the RF amplifier are input to the SE input pin, the signal transmitted from the TE pin can be obtained as the TRK hold filter input. Only during TRK servo gain up2 operation, coefficient K46 is used instead of K40. Normally, the DC gain between the TE input pin and M0D changes for TRK filter gain normal and gain up2, creating a difference in the DC level at M0D. In this case, the DC level of the signal transmitted to M18 can be kept uniform by adjusting the K46 value even during the above switching. SFSK: THID: THSK: ∗ See § 5-21. Filter Composition regarding the SFID, SFSK, THID and THSK commands. TLD0 to 2: This turns on and off SLD filter correction independently of the TRK filter. See $38 (TLC0 to 2) and Fig. 5-3. Traverse center correction ∗ TLC2 TLD2 0 — OFF OFF 0 ON ON 1 ON OFF 1 TLC1 TLD1 TRK filter Tracking zero level correction TRK filter ∗ 0 1 TLC0 0 1 SLD filter — OFF OFF 0 ON ON 1 ON OFF TLD0 VC level correction TRK filter ∗ SLD filter SLD filter — OFF OFF 0 ON ON 1 ON OFF ∗: preset, —: don't care – 112 – CXD2585Q • Input coefficient sign inversion when SFID = 1 and THID = 1 The preset coefficients for the TRK filter are negative for input and positive for output. With this, the CXD2585Q outputs the servo drives which have the reversed phase to the error inputs.. Negative input coefficient TE TRK Filter K19 Negative input coefficient SE Positive output coefficient SLD Filter K00 Positive input coefficient TRK Hold K40 Positive output coefficient ∗ K22 K05 Positive output coefficient TRK Hold Filter K45 When SFID = 1, the TRK filter negative input coefficient is applied to the SLD filter, so invert the SLD input coefficient (K00) sign. (For example, inverting the sign for coefficient K00: E0Hex results in 60Hex.) For the same reason, when THID = 1, invert the TRK hold input coefficient (K40) sign. Negative input coefficient K19 TE Positive output coefficient TRK Filter ∗ K22 MOD Positive input coefficient K00 SE Positive output coefficient SLD Filter Negative input coefficient TRK Hold K40 K05 Positive output coefficient TRK Hold Filter ∗ for TRK servo gain normal See § 5-21. Filter Composition. – 113 – K45 CXD2585Q $3E (preset: $3E 00 00) D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 F1NM F1DM F3NM F3DM T1NM T1UM T3NM T3UM DFIS TLCD D5 0 D4 D3 D2 D1 D0 LKIN COIN MDFI MIRI XT1D F1NM, F1DM: Quasi double accuracy setting for FCS servo filter first-stage On when 1; default when 0. F1NM: Gain normal F1DM: Gain down T1NM, T1UM: Quasi double accuracy setting for TRK servo filter first-stage On when 1; default when 0. T1NM: Gain normal T1UM: Gain up F3NM, F3DM: Quasi double accuracy setting for FCS servo filter third-stage On when 1; default when 0. Generally, the advance amount of the phase becomes large by partially setting the FCS servo third-stage filter which is used as the phase compensation filter to double accuracy. F3NM: Gain normal F3DM: Gain down T3NM, T3UM: Quasi double accuracy setting for TRK servo filter third-stage On when 1; default when 0. Generally, the advance amount of the phase becomes large by partially setting the TRK servo third-stage filter which is used as the phase compensation filter to double accuracy. T3NM: Gain normal T3UM: Gain up Note) Filter first- and third-stage quasi double accuracy settings can be set individually. See § 5-20 Filter Composition at the end of this specification concerning quasi double accuracy. DFIS: FCS hold filter input extraction node selection 0: M05 (Data RAM address 05); default 1: M04 (Data RAM address 04) This command masks the TLC2 command set by D2 of $38 only when FOK is low. On when 1; default when 0 When 0, the internally generated LOCK signal is output to the LOCK pin. (default) When 1, the LOCK signal can be input from an external source to the LOCK pin. When 0, the internally generated COUT signal is output to the COUT pin. (default) When 1, the COUT signal can be input from an external source to the COUT pin. TLCD: LKIN: COIN: The MIRR, DFCT and FOK signals can also be input from an external source. MDFI: When 0, the MIRR, DFCT and FOK signals are generated internally. (default) When 1, the MIRR, DFCT and FOK signals can be input from an external source through the MIRR, DFCT and FOK pins. MIRI: When 0, the MIRR signal is generated internally. (default) When 1, the MIRR signal can be input from an external source through the MIRR pin. ∗ MDFI MIRI 0 0 MIRR, DFCT and FOK are all generated internally. 0 1 MIRR only is input from an external source. 1 — MIRR, DFCT and FOK are all input from an external source. ∗: preset, —: don't care XT1D: When XT1D = 1, the input to the servo master clock can be used without dividing its frequency. This command takes precedence over the XTSL pin, XT2D and XT4D. See the description of $3F for XT2D and XT4D. – 114 – CXD2585Q $3F (preset: $3F 00 00) D15 0 D14 D13 D12 D11 AGG4 XT4D XT2D AGG4: D10 0 D9 D8 D7 DRR2 DRR1 DRR0 0 D6 D5 D4 ASFG FTQ LPAS D3 D2 D1 D0 0 0 AGHF 0 This varies the amplitude of the internally generated sine wave using the AGGF and AGGT commands during AGC. When AGG4 = 0, the default is used. When AGG4 = 1, the setting is as shown in the table below. Sine wave amplitude AGG4 AGGF AGGT 0 1 XT4D, XT2D: TE input conversion FE input conversion 0 — 1/36 × VDD × 0.4 — 1 — 1/16 × VDD × 0.4 — — 0 — — 1 — 0 0 1/64 × VDD × 0.4 0 1 1/32 × VDD × 0.4 1 0 1/16 × VDD × 0.4 1 1 1/8 × VDD × 0.4 See $37 for AGGF and AGGT. The presets are AGG4 = 0, AGGF = 1 and AGGT = 1. ∗: preset, —: don't care 1/16 × VDD × 0.4 1/8 × VDD × 0.4∗ MCK (digital servo master clock) frequency division setting This command forcibly sets the frequency division ratio to 1/4, 1/2 or 1/1 when MCK is generated. See the description of $3E for XT1D. Also, see the decription of §5-2. Digital Servo Block Master Clock (MCK). ∗ XT1D XT2D XT4D Frequency division ratio 0 0 0 According to XTSL 1 — — 1/1 0 1 — 1/2 0 0 1 1/4 ∗: preset, —: don't care DRR2 to DRR0: Partially clears the Data RAM values (0 write). The following values are cleared when 1 (on) respectively; default = 0 DRR2: M08, M09, M0A DRR1: M00, M01, M02 DRR0: M00, M01, M02 only when LOCK = low Note) Set DRR1 and DRR0 on for 50µs or more. ASFG: When vibration detection is performed during anti-shock circuit operation, the FCS servo filter is forcibly set to gain normal status. On when 1; default when 0 LPAS: Built-in analog buffer low-current consumption mode This mode reduces the total analog buffer current consumption for the VC, TE, SE and FE input analog buffers by using a single operational amplifier. On when 1; default when 0 Note) When using this mode, first check whether each error signal is properly A/D converted using the data readout and the like. AGHF: This halves the frequency of the internally generated sine wave during AGC. FTQ: The slope of the output during focus search is 1/4 of the conventional output slope. On when 1; default when 0 . ASOT: The anti-shock signal, which is internally detected, is output from the ATSK pin. Output when set to 1; default = 0 Vibration detection when a high signal is output for the anti-shock signal output. – 115 – CXD2585Q Description of Data Readout SOCK (5.6448MHz) ··· ··· ··· ··· XOLT (88.2kHz) SOUT MSB ··· LSB MSB 16-bit register for serial/parallel conversion SOUT ··· LSB 16-bit register for latch LSB LSB To the 7-segment LED • • • • • • To the 7-segment LED MSB MSB SOCK CLK CLK Data is connected to the 7-segment LED by 4bits at a time. This enables Hex display using four 7-segment LEDs. XOLT SOUT Serial data input Analog output D/A SOCK Clock input XOLT Latch enable input To an oscilloscope, etc. Offset adjustment, gain adjustment Waveforms can be monitored with an oscilloscope using a serial input-type D/A converter as shown above. – 116 – CXD2585Q § 5-19. List of Servo Filter Coefficients <Coefficient Preset Value Table (1)> ADDRESS DATA K00 K01 K02 K03 K04 K05 K06 K07 K08 K09 K0A K0B K0C K0D K0E K0F E0 81 23 7F 6A 10 14 30 7F 46 81 1C 7F 58 82 7F SLED INPUT GAIN SLED LOW BOOST FILTER A-H SLED LOW BOOST FILTER A-L SLED LOW BOOST FILTER B-H SLED LOW BOOST FILTER B-L SLED OUTPUT GAIN FOCUS INPUT GAIN SLED AUTO GAIN FOCUS HIGH CUT FILTER A FOCUS HIGH CUT FILTER B FOCUS LOW BOOST FILTER A-H FOCUS LOW BOOST FILTER A-L FOCUS LOW BOOST FILTER B-H FOCUS LOW BOOST FILTER B-L FOCUS PHASE COMPENSATE FILTER A FOCUS DEFECT HOLD GAIN K10 K11 K12 K13 K14 K15 K16 K17 K18 K19 K1A K1B K1C K1D K1E K1F 4E 32 20 30 80 77 80 77 00 F1 7F 3B 81 44 7F 5E FOCUS PHASE COMPENSATE FILTER B FOCUS OUTPUT GAIN ANTI SHOCK INPUT GAIN FOCUS AUTO GAIN HPTZC / Auto Gain HIGH PASS FILTER A HPTZC / Auto Gain HIGH PASS FILTER B ANTI SHOCK HIGH PASS FILTER A HPTZC / Auto Gain LOW PASS FILTER B Fix∗ TRACKING INPUT GAIN TRACKING HIGH CUT FILTER A TRACKING HIGH CUT FILTER B TRACKING LOW BOOST FILTER A-H TRACKING LOW BOOST FILTER A-L TRACKING LOW BOOST FILTER B-H TRACKING LOW BOOST FILTER B-L K20 K21 K22 K23 K24 K25 K26 K27 K28 K29 K2A K2B K2C K2D K2E K2F 82 44 18 30 7F 46 81 3A 7F 66 82 44 4E 1B 00 00 TRACKING PHASE COMPENSATE FILTER A TRACKING PHASE COMPENSATE FILTER B TRACKING OUTPUT GAIN TRACKING AUTO GAIN FOCUS GAIN DOWN HIGH CUT FILTER A FOCUS GAIN DOWN HIGH CUT FILTER B FOCUS GAIN DOWN LOW BOOST FILTER A-H FOCUS GAIN DOWN LOW BOOST FILTER A-L FOCUS GAIN DOWN LOW BOOST FILTER B-H FOCUS GAIN DOWN LOW BOOST FILTER B-L FOCUS GAIN DOWN PHASE COMPENSATE FILTER A FOCUS GAIN DOWN DEFECT HOLD GAIN FOCUS GAIN DOWN PHASE COMPENSATE FILTER B FOCUS GAIN DOWN OUTPUT GAIN NOT USED NOT USED CONTENTS ∗ Fix indicates that normal preset values should be used. – 117 – CXD2585Q <Coefficient Preset Value Table (2)> ADDRESS DATA K30 K31 K32 K33 K34 K35 K36 K37 K38 K39 K3A K3B K3C K3D K3E K3F 80 66 00 7F 6E 20 7F 3B 80 44 7F 77 86 0D 57 00 SLED INPUT GAIN (Only when TRK Gain Up2 is accessed with SFSK = 1.) ANTI SHOCK LOW PASS FILTER B NOT USED ANTI SHOCK HIGH PASS FILTER B-H ANTI SHOCK HIGH PASS FILTER B-L ANTI SHOCK FILTER COMPARATE GAIN TRACKING GAIN UP2 HIGH CUT FILTER A TRACKING GAIN UP2 HIGH CUT FILTER B TRACKING GAIN UP2 LOW BOOST FILTER A-H TRACKING GAIN UP2 LOW BOOST FILTER A-L TRACKING GAIN UP2 LOW BOOST FILTER B-H TRACKING GAIN UP2 LOW BOOST FILTER B-L TRACKING GAIN UP PHASE COMPENSATE FILTER A TRACKING GAIN UP PHASE COMPENSATE FILTER B TRACKING GAIN UP OUTPUT GAIN NOT USED K40 K41 K42 K43 K44 K45 K46 04 7F 7F 79 17 6D 00 K47 K48 K49 K4A K4B K4C K4D K4E K4F 00 02 7F 7F 79 17 54 00 00 TRACKING HOLD FILTER INPUT GAIN TRACKING HOLD FILTER A-H TRACKING HOLD FILTER A-L TRACKING HOLD FILTER B-H TRACKING HOLD FILTER B-L TRACKING HOLD FILTER OUTPUT GAIN TRACKING HOLD FILTER INPUT GAIN (Only when TRK Gain Up2 is accessed with THSK = 1.) NOT USED FOCUS HOLD FILTER INPUT GAIN FOCUS HOLD FILTER A-H FOCUS HOLD FILTER A-L FOCUS HOLD FILTER B-H FOCUS HOLD FILTER B-L FOCUS HOLD FILTER OUTPUT GAIN NOT USED NOT USED CONTENTS – 118 – 2–1 AGFON DFCT K06 K06 Z–1 K08 M03 FCS In Reg FCS Hold Reg2 2–1 DFCT K06 Z–1 K24 M03 FCS Servo Gain Down fs = 88.2kHz Sin ROM FCS In Reg FCS Hold Reg2 FCS Servo Gain Normal fs = 88.2kHz K25 Z–1 2–7 2–7 K0D K0C Z–1 K0E M05 K0F FCS Hold Reg 1 – 119 – 2–7 2–7 K29 K28 K2A FCS Hold Reg 1 Z–1 FPS1, 0 BK1 BK2 Z–1 BK3 BK6 Z–1 Note) Set the MSB bit of the K27 and K29 coefficients to 0. K27 K26 Z–1 M05 K28 Note) Set the MSB bit of the K0B and K0D coefficients to 0. K0B K0A M04 K09 Z–1 M04 § 5-20. Filter Composition The internal filter composition is shown below. K∗∗ and M∗∗ indicate coefficient RAM and Data RAM address values respectively. BK4 Z–1 M06 K2C K10 Z–1 M06 BK5 K2D K11 K13 FCS SRCH M07 Z–1 K13 FSC AUTO Gain M07 FCS AUTO Gain 27 PWM CXD2585Q AGTON 2–1 DFCT K19 K19 Z–1 K1A M0B 2–1 DFCT K19 Z–1 K1A M0B – 120 – TRK In Reg TRK Hold Reg 2–1 K19 DFCT Z–1 Z–1 TPS1, 0 K36 M0B TRK Servo Gain Up 2 fs = 88.2kHz TRK In Reg TRK Hold Reg TRK Servo Gain Up 1 fs = 88.2kHz Sin ROM TRK In Reg TRK Hold Reg BK1 TRK Servo Gain Normal fs = 88.2kHz BK2 K37 K1B K1B K3C Z–1 Z–1 2–7 K1F K1E K20 2–7 2–7 K3B K3A Z–1 K3C M0D K3D Z–1 M0E K3E BK3 BK6 Z–1 BK4 BK5 Z–1 TRK JMP Note) Set the MSB bit of the K39 and K3B coefficients to 0. K39 K38 M0C Z–1 2–7 M0D Z–1 Note) Set the MSB bit of the K1D and K1F coefficients to 0. K1D K1C M0C Z–1 M0C SLD Servo TRK Hold BK9 K3D Z–1 M0E K21 Z–1 M0E BK7 Z–1 K3E K22 K23 K23 M0F BK8 K23 Z–1 TRK AUTO Gain M0F TRK AUTO Gain M0F TRK AUTO Gain 27 PWM CXD2585Q K06 K06 Z–1 K08 81H M03 ∗ 2–7 2–7 K09 ∗ 7FH Z–1 K0B K0A M04 2–7 2 –7 K0D K0C Z–1 K0E 80H M05 K0F ∗ 2–7 FCS Hold Reg 1 K10 – 121 – 2–1 K11 K06 Z–1 K24 81H M03 ∗ 2–7 2–7 ∗ K25 7FH Z–1 K27 K26 M04 2–7 2–7 K29 K28 Z–1 K2A 80H M05 K2B ∗ 2–7 FCS Hold Reg 1 K2C Z–1 M06 K2D fixed values when set to quasi double accuracy. Z–1 FPS1, 0 BK1 BK2 Z–1 BK3 BK6 Z–1 BK4 BK5 K13 FCS SRCH M07 FCS AUTO Gain K13 FCS AUTO Gain M07 Z–1 Note) Set the MSB bit of the K27 and K29 coefficients during normal operation, and of the K24, K25 and K2A coefficients during quasi double accuracy to 0. DFCT ∗ 81H, 7FH and 80H are each Hex display 8-bit FCS In Reg FCS Hold Reg 2 Z–1 M06 Note) Set the MSB bit of the K0B and K0D coefficients during normal operation, and of the K0B, K09 and K0E coefficients during quasi double accuracy to 0. AGFON 2–1 DFCT FCS Servo Gain Normal fs = 88.2kHz, during quasi double accuracy (Ex.: $3E5XX0) Sin ROM FCS In Reg FCS Hold Reg 2 FCS Servo Gain Normal fs = 88.2kHz, during quasi double accuracy (Ex.: $3EAXX0) 27 PWM CXD2585Q 2–1 AGTON DFCT Z–1 K1A 81H M0B ∗ 2–7 2–7 K1B ∗ 7FH Z–1 K1D K1C M0C 2–7 2–7 K1F K1E Z–1 K20 80H M0D ∗ 2–7 2–1 DFCT Z–1 K1A 81H M0B ∗ 2–7 2–7 K1B 7FH ∗ Z–1 K3C 80H M0C ∗ 2–7 Z–1 M0E K3D Note) Set the MSB bit of the K1A, K1B and K3C coefficients during quasi double accuracy to 0. K19 – 122 – 2–1 DFCT K22 M0F K23 Z–1 K36 81H M0B ∗ 2–7 2–7 K37 ∗ 7FH Z–1 K39 K38 M0C 2–7 2–7 K3B K3A Z–1 K3C 80H M0D ∗ 2–7 K3D Z–1 M0E K3E K3E K23 M0F K23 TRK AUTO Gain M0F TRK AUTO Gain Z–1 TPS1, 0 BK1 BK2 Z–1 BK3 BK6 Z–1 BK4 Note) Set the MSB bit of the K39 and K3B coefficients during normal operation, and of the K36, K37 and K3C coefficients during quasi double accuracy to 0. K19 ∗ 81H, 7FH and 80H are each Hex display 8-bit fixed values when set to quasi double accuracy. TRK In Reg TRK Hold Reg TRK Servo Gain up2 fs = 88.2kHz, during quasi double accuracy (Ex.: $3EX5X0) TRK In Reg TRK Hold Reg K21 Z–1 M0E TRK AUTO Gain Note) Set the MSB bit of the K1D and K1F coefficients during normal operation, and of the K1A, K1B and K20 coefficients during quasi double accuracy to 0. K19 K19 TRK Servo Gain up1 fs = 88.2kHz, during quasi double accuracy (Ex.: $3EX5X0) Sin ROM TRK In Reg TRK Hold Reg TRK Servo Gain Normal fs = 88.2kHz, during quasi double accuracy (Ex.: $3EXAX0) BK5 Z–1 27 TRK JMP BK9 Z–1 BK7 BK8 Z–1 PWM CXD2585Q CXD2585Q SLD Servo fs = 345Hz TRK SERVO FILTER Second-stage output K30 M0D SLD In Reg 2–1 TRK AUTO Gain SFSK (only when TGUP2 is used.) SFID M00 M01 Z–1 Z–1 K00 K05 M02 2–7 K07 PWM SLD MOV K01 K03 2–7 2–7 K02 K04 Note) Set the MSB bit of the K02 and K04 coefficients to 0. HPTZC/Auto Gain fs = 88.2kHz FCS In Reg TRK In Reg Sin ROM 2–1 Slice TZC Reg AGFON M08 2–1 AGTON AGFON M09 Z–1 M0A Z–1 K14 K15 – 123 – Z–1 K17 Slice AUTO Gain Reg CXD2585Q Anti Shock fs = 88.2kHz TRK In Reg 2–1 K12 M08 M09 M0A Z–1 Z–1 Z–1 K31 K35 Comp Anti Shock Reg K33 K16 2–7 K34 Note) Set the MSB bit of the K34 coefficient to 0. The comparator level is 1/16 the maximum amplitude of the comparator input. AVRG fs = 88.2kHz 2–1 2–7 M08 VC, TE, FE, RFDC AVRG Reg Z–1 TRK Hold fs = 345Hz TRK SERVO FILTER Second-stage output K46 M0D SLD In Reg THSK (only when TGUP2 is used.) THID 2–1 M18 M19 Z–1 Z–1 K40 K41 K45 TRK Hold Reg K43 2–7 2–7 K42 K44 Note) Set the MSB bit of the K42 and K44 coefficients to 0. FCS Hold fs = 345Hz FCS Hold Reg 1 K48 M10 M11 Z–1 Z–1 K49 K4D FCS Hold Reg 2 K4B 2–7 K4A 2–7 K4C Note) Set the MSB bit of the K4A and K4C coefficients to 0. – 124 – CXD2585Q § 5-21. TRACKING and FOCUS Frequency Response TRACKING frequency response 180° 40 NORMAL GAIN UP 30 G 20 0° φ 10 φ – Phase [degree] G – Gain [dB] 90° –90° 0 –10 2.1 10 100 –180° 20k 1k f – Frequency [Hz] When using the preset coefficients with the boost function off. FOCUS frequency response 40 180° NORMAL GAIN DOWN 30 20 G 0° 10 φ –90° 0 –10 2.1 10 100 1k –180° 20k f – Frequency [Hz] When using the preset coefficients with the boost function off. – 125 – φ – Phase [degree] G – Gain [dB] 90° AVDD0 IGEN ASYO RFAC ASYI AVss1 CLTV FILO PCO FILI AVDD1 VCTL BIAS V16M VPCO V16M SE 40 FE 39 ADIO VC 38 AVss0 63 MD2 RFDC 61 DVDD2 62 ASYE TE 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 CE XPCK GFS XUGF ATSK WFCK SCLK XOLT SBSO 74 SOCK 75 XOLT SOCK 80 EXCK 79 SBSO 78 SCSY 2 1 77 SQCK 76 SQSO 73 SOUT 72 XTAO SOUT 7 6 5 4 3 8 SFDR 29 DFCT 21 FOK 22 PWMI 23 LOCK 24 MDP 25 SSTP 26 FSTO 27 DVDD1 28 9 10 11 12 13 14 15 16 17 18 19 20 WFCK XRST SRDR 30 TFDR 31 XUGF 71 XTAI XPCK MUTE 70 DVss2 C2PO SCCY XRST MUTE DATA XLAT CLOK SENS SCLK GFS SCOR FOK PWMI LDON VDD GND DATA FFDR 33 C4M XLAT TRDR 32 EMPH WDCK DVDD0 SQSO SQCK MIRR MIRR CLOK 69 XTSL FRDR 34 BCK COUT – 126 – SENS 68 EMPH 66 PCMD 67 BCK PCMD DVss1 35 TES1 37 SCOR TEST 36 C2PO 65 LRCK C4M 64 DOUT DVss0 LRCK WDCK DOUT COUT [6] Application Circuit DFCT LOCK FSTO +5V SSTP SLED SPDL GND Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. Driver Circuit FG TD TG FD LDON Vcc GND RFO FZC FE TE CE VC CXD2585Q CXD2585Q Package Outline Unit: mm 80PIN QFP (PLASTIC) + 0.35 1.5 – 0.15 + 0.1 0.127 – 0.05 16.0 ± 0.4 + 0.4 14.0 – 0.1 60 0.1 41 40 80 21 (15.0) 61 + 0.15 0.3 – 0.1 20 ± 0.12 M 0° to 10° 0.5 ± 0.2 1 0.65 + 0.15 0.1 – 0.1 PACKAGE STRUCTURE PACKAGE MATERIAL EPOXY RESIN SONY CODE QFP-80P-L03 LEAD TREATMENT SOLDER PLATING EIAJ CODE LQFP080-P-1414 LEAD MATERIAL 42/COPPER ALLOY PACKAGE MASS 0.6g JEDEC CODE – 127 –