SONY CXD2548

CXD2548R
CD Digital Signal Processor with Built-in Digital Servo and DAC
For the availability of this product, please contact the sales office.
Description
The CXD2548R is a digital signal processor LSI for
CD players. This LSI incorporates a digital servo,
digital filter, zero detection circuit, 1-bit DAC and
analog low-pass filter on a single chip.
112 pin LQFP (Plastic)
Features
• All digital signal processing during playback is
performed with a single chip
• Highly integrated mounting possible due to a builtin RAM
Digital Signal Processor (DSP) Block
• Playback mode which supports CAV (Constant
Angular Velocity)
• Frame jitter free
• 0.5 × to 2.5 × continuous playback possible
• Allows relative rotational velocity readout
• Supports spindle external control
• Wide capture range playback mode
• Spindle rotational velocity following method
• Supports normal-speed, double-speed playback
• 16K RAM
• EFM data demodulation
• Enhanced EFM frame sync signal protection
• SEC strategy-based error correction
• Subcode demodulation and Sub Q data error
detection
• Digital spindle servo
• 16-bit traverse counter
• Asymmetry compensation circuit
• CPU interface on serial bus
• Error correction monitor signal, etc. output from a
new CPU interface
• Servo auto sequencer
• Digital audio interface outputs
• Digital level meter, peak meter
Digital Servo (DSSP) Block
• Microcomputer software-based flexible servo control
• Offset cancel function for servo error signal
• Auto gain control function for servo loop
• E:F balance, focus bias adjustment functions
• Surf jump function supporting micro two-axis
Digital Filter, DAC and Analog Low-Pass Filter Blocks
• Digital de-emphasis
• Digital attenuation
• Zero detection function
• 8Fs oversampling digital filter
• S/N: 100dB or more (master clock: 384Fs, typ.)
• THD + N: 0.007% or more (master clock: 384Fs,
typ.)
• Rejection band attenuation: –60dB or more
Applications
CD players
Structure
Silicon gate CMOS IC
Absolute Maximum Ratings
–0.3 to +7.0
V
• Supply voltage
VDD
• Input voltage
VI
–0.3 to +7.0
V
(VSS – 0.3V to VDD + 0.3)
• Output voltage
VO
–0.3 to +7.0
V
• Storage temperature Tstg
–40 to +125 °C
• Supply voltage difference
VSS – AVSS –0.3 to +0.3
V
VDD – AVDD –0.3 to +0.3
V
Recommended Operating Conditions
–3.4 to +5.25 V
• Supply voltage
VDDNote)
• Operating temperature Topr
–20 to +75 °C
Note) The VDD (Min.) for the CXD2548R varies
according to the playback speed selection.
VDD (min.) [V]
Playback
speed
CD-DSP block DAC block DSSP block
2×
3.4V
4.5V
3.4V
1×
3.4V
3.4V
3.4V
1 ×∗1
3.4V
3.4V
∗1 When the internal operation of the CD-DSP side
is set to double-speed mode and the crystal
oscillation frequency is halved, normal-speed
playback results.
I/O Capacitance
• Input pin
• Output pin
CI
CO
12 (Max.)
12 (Max.)
pF
pF
Note) Measurement conditions VDD = VI = 0V
fM = 1MHz
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E96404-PS
CXD2548R
Block Diagram
CKOUT
4
XTAO
104
XTAI
103
LMUT2(CH2)
3
RMUT1(CH1)
2
SYSM
1
4
98
104
99
Digital Filter
+
1 bit DAC
103
3
100
109
2
108
1
107
AOUT1
AIN1
LOUT1
AOUT2
AIN2
LOUT2
98
99
100
109
108
107
EMPHI
BCKI
90
LRCKI
PCMDI
90 92 88 94
DOUT
92
88
94
91
89
87
85
26
25
BCK
PCMD
LRCK
WDCK
C2PO
RFCK
33
33
91
15
89
85
27
Digital
OUT
D/A
Interface
87
77
Digital
CLV
26
79
25
17
TES0
29
30
31
MNT0
MNT1
MNT3
78
29
30
Error
Corrector
8
16K
RAM
9
31
7
50
52
53
51
39
40
83
XTAO 104
XTAI
103
FSTO
81
C4M
84
ACDT
16
RFAC
50
ASYI
52
ASYO
53
BIAS
51
Clock
Generator
13
LOCK
MDS
MDP
PWMI
SQCK
SQSO
EXCK
SBSO
SCOR
XLON
SPOA
CLOK
XLAT
DATA
15
27
77
78
79
17
8
9
7
6
28
18
19
14
13
12
10
SENS
10
Digital
PLL
Servo
Interface
36
MIRR
35
DFCT
76
FOK
37
DFCT
MIRR
COUT
FOK
36
35
76
37
SERVO DSP
A/D
CONVERTER
Asymmetry
Corector
FOCUS SERVO
TRACKING SERVO
OpAmp
A Sw
SLED SERVO
PWM GENERATOR
23 45 46 44 48
FOCUS PWM
GENERATOR
TRACKING PWM
GENERATOR
SLED PWM
GENERATOR
59 57 56 55 54 58 60 61
23 45 46 44 48
ADIO
16
Servo
Auto
SEquencer
41
CE
84
XTSL
14
12
OSC
RFC
83
CPU
Interface
XROF
42
VC
40
VPCO2
43
FE
39
VCKI
VPCO1
19
Sub Code
Processor
21
TE
41
22
SE
42
VCTL
V16M
EFM
demodurator
24
RFDC
43
GTOP
18
CLTV
21
XUGF
28
93
FILI
22
GFS
20
PCO
24
EMPH
FILO
93
6
XPCK
20
WFCK
XRST
59 57 56 55 54 58 60 61
–2–
69
70
71
72
73
74
SFDR
SRDR
TFDR
TRDR
FFDR
FRDR
69
70
71
72
73
74
CXD2548R
TE
CE
RFDC
RFC
ADIO
AVSS3
IGEN
AVDD3
TES2
TES3
VSS2
TEST
SFDR
SRDR
TFDR
TRDR
FRDR
FFDR
VDD2
COUT
LOCK
MDS
SSTP
MDP
FSTO
FSTI
XTSL
C4M
Pin Configuration
84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57
WDCK 85
56 SE
VDD3 86
55 FE
LRCK 87
54 VC
LRCKI 88
53 ASYO
PCMD 89
52 ASYI
PCMDI 90
51 BIAS
BCK 91
50 RFAC
BCKI 92
49 AVDD4
EMPH 93
48 CLTV
EMPHI 94
47 AVSS4
VSS3 95
46 FILI
AVSS1 96
45 FILO
AVDD1 97
44 PCO
AOUT1 98
43 VCTL
AIN1 99
42 V16M
LOUT1 100
41 VCKI
AVSS1 101
40 VPCO2
XVDD 102
39 VPCO1
XTAI 103
38 VDD1
XTAO 104
37 FOK
XVSS 105
36 DFCT
AVSS2 106
35 MIRR
LOUT2 107
34 ATSK
AIN2 108
33 DOUT
32 VSS1
AOUT2 109
AVDD2 110
31 MNT3
AVSS2 111
30 MNT1
–3–
XROF
SCOR
C2PO
RFCK
GFS
XPCK
XUGF
GTOP
WFCK
XLON
SPOA
PWMI
ACDT
XRST
CLOK
XLAT
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
SCLK
VDD0
SBSO
8
DATA
LMUT2
7
SENS
6
SQSO
5
EXCK
4
SQCK
3
CKOUT
2
RMUT1
29 MNT0
1
SYSM
VSS0 112
CXD2548R
Pin Description
Pin
No.
Symbol
Description
I/O
System mute input. (high = on, low = off)
1
SYSM
I
2
RMUT1
O
1, 0
R ch zero detection output. (high = on, low = off)
3
LMUT2
O
1, 0
L ch zero detection output. (high = on, low = off)
4
CKOUT
O
1, 0
DAC master clock frequency division output. Either the clock input from
XTAI × 1, × 1/2 or × 1/4, or low output is selected and output.
5
VDD0
6
SBSO
O
7
EXCK
I
SBSO readout clock input.
8
SQCK
I
SQSO readout clock input.
9
SQSO
O
1, 0
Sub Q 80-bit and PCM peak and level data 16-bit output.
10
SENS
O
1, 0
SENS output to CPU.
11
SCLK
I
SENS serial data readout clock input.
12
DATA
I
Serial data input from CPU.
13
XLAT
I
Latch input from CPU. Serial data is latched at the falling edge.
14
CLOK
I
Serial data transfer clock input from CPU.
15
XRST
I
System reset. Reset when low.
16
ACDT
O
17
PWMI
I
18
XLON
O
19
SPOA
I
20
WFCK
O
1, 0
WFCK (Write Flame Clock) output.
21
GTOP
O
1, 0
GTOP output.
22
XUGF
O
1, 0
XUGF output.
23
XPCK
O
1, 0
XPLCK output.
24
GFS
O
1, 0
GFS output.
25
RFCK
O
1, 0
RFCK output.
26
C2PO
O
1, 0
C2PO output.
27
XROF
O
1, 0
XRAOF output.
28
SCOR
O
1, 0
Outputs a high signal when either subcode sync S0 or S1 is detected.
29
MNT0
O
1, 0
MNT0 output.
30
MNT1
O
1, 0
MNT1 output.
31
MNT3
O
1, 0
MNT3 output.
32
Vss1
33
DOUT
O
34
ATSK
I
35
MIRR
O
1, 0
Mirror signal output.
36
DFCT
O
1, 0
Defect signal output.
Digital power supply.
1, 0
1, 0
Sub P to W serial output.
Normally not used. Leave open.
Spindle motor external control input.
1, 0
Microcomputer extension interface (output).
Microcomputer extension interface (input A).
Digital GND.
1, 0
Digital Out output pin.
Anti-shock pin.
–4–
CXD2548R
Pin
No.
Symbol
Description
I/O
37
FOK
O
38
VDD1
39
VPCO1
O
1, Z, 0
Wide-band EFM PLL charge pump output.
40
VPCO2
O
1, Z, 0
Wide-band EFM PLL VCO2 charge pump output.
41
VCKI
I
42
V16M
O
43
VCTL
I
44
PCO
O
1, Z, 0
Master PLL charge pump output.
45
FILO
O
Analog
Master PLL filter output (slave = digital PLL).
46
FILI
I
47
AVss4
48
CLTV
49
AVDD4
50
RFAC
I
EFM signal input.
51
BIAS
I
Asymmetry circuit constant current input.
52
ASYI
I
Asymmetry comparator voltage input.
53
ASYO
O
54
VC
I
Center voltage input.
55
FE
I
Focus error signal input.
56
SE
I
Sled error signal input.
57
TE
I
Tracking error signal input.
58
CE
I
Center error signal input.
59
RFDC
I
RF signal input. Input range: 2.15 to 5.0V. (when DVDD = AVDD = 5.0V)
60
RFC
I
Connects an RF signal LPF time-constant capacitor.
61
ADIO
O
Operational amplifier output.
62
AVss3
63
IGEN
64
AVDD3
65
TES2
I
Test pin. Normally fixed to low.
66
TES3
I
Test pin. Normally fixed to low.
67
Vss2
68
TEST
I
69
SFDR
O
1, 0
Sled drive output.
70
SRDR
O
1, 0
Sled drive output.
71
TFDR
O
1, 0
Tracking drive output.
72
TRDR
O
1, 0
Tracking drive output.
73
FFDR
O
1, 0
Focus drive output.
1, 0
Focus OK signal output.
Digital power supply.
Wide-band EFM PLL VCO2 oscillation input.
1, 0
Wide-band EFM PLL VCO2 oscillation output.
Wide-band EFM PLL VCO2 control input.
Master PLL filter input.
Analog GND.
I
Master VCO control voltage input.
Analog power supply.
1, 0
EFM full-swing output (low = VSS, high = VDD).
Analog GND.
I
Connects an operational amplifier current source reference resistor.
Analog power supply.
Digital GND.
Test pin. Normally fixed to low.
–5–
CXD2548R
Pin
No.
Symbol
Description
I/O
O
1, 0
74
FRDR
75
VDD2
76
COUT
O
1, 0
Track count signal output.
77
LOCK
O
1, 0
GFS is sampled at 460Hz; when GFS is high, this pin outputs a high signal.
If GFS is low eight consecutive samples, this pin outputs low.
78
MDS
O
1, 0
Spindle motor servo control output.
79
MDP
O
1, 0
Spindle motor servo control output.
80
SSTP
I
81
FSTO
O
82
FSTI
I
Digital servo reference clock input.
83
XTSL
I
Crystal selection input. Low when the crystal is 16.9344MHz; high when the
crystal is 33.8688MHz.
84
C4M
O
1, 0
4.2336MHz output.
85
WDCK
O
1, 0
D/A interface. Word clock f = 2Fs
86
VDD3
87
LRCK
O
88
LRCKI
I
89
PCMD
O
90
PCMDI
I
91
BCK
O
92
BCKI
I
93
EMPH
O
94
EMPHI
I
95
Vss3
Digital GND.
96
AVss1
L ch, analog GND.
97
AVDD1
L ch, analog power supply.
98
AOUT1
O
99
AIN1
I
100
LOUT1
O
101
AVss1
L ch, analog GND.
102
XVDD
Master clock analog power supply.
103
XTAI
I
104
XTAO
O
105
XVss
Master clock analog GND.
106
AVss2
R ch, analog GND.
107
LOUT2
O
108
AIN2
I
109
AOUT2
O
Focus drive output.
Digital power supply.
Disc innermost track detection signal input.
1, 0
2/3-frequency division output for Pins 103 and 104.
Digital power supply.
1, 0
D/A interface. LR clock f = Fs
LR clock input to DAC (48-bit slot).
1, 0
D/A interface. Serial data. (two's complement, MSB first)
Audio data input to DAC (48-bit slot).
1, 0
D/A interface. Bit clock.
Bit clock input to DAC (48-bit slot).
1, 0
Outputs a high signal when the playback disc has emphasis, and a low
signal when there is no emphasis.
DAC de-emphasis ON/OFF. (high = on, low = off)
Analog
L ch, analog output.
L ch, operational amplifier input.
Analog
L ch, LINE output.
Master clock 16.9344MHz crystal oscillation circuit input, or 33.8688MHz input.
1, 0
Analog
Master clock 16.9344MHz crystal oscillation circuit output.
R ch, LINE output.
R ch, operational amplifier input.
Analog
R ch, analog output.
–6–
CXD2548R
Pin
No.
Symbol
Description
I/O
110
AVDD2
R ch, analog power supply.
111
AVss2
R ch, analog GND.
112
Vss0
Digital GND.
Notes) • PCMD is a MSB first, two's complement output.
• GTOP is used to monitor the frame sync protection status. (High: sync protection window released.)
• XUGF is the frame sync obtained from the EFM signal, and negative pulse. It is the signal before
sync protection.
• XPLCK is the inverse of the EFM PLL clock. The PLL is designed so that the falling edge and the
EFM signal transition point coincide.
• The GFS signal goes high when the frame sync and the insertion timing match.
• RFCK is derived from the crystal accuracy, and has a cycle of 136µs (during normal speed).
• C2PO represents the data error status.
• XRAOF is generated when the 16K RAM exceeds the ±4F jitter margin.
–7–
CXD2548R
Electrical Characteristics
1. DC Characteristics
(VDD = AVDD = 5.0V ± 5%, Vss = AVss = 0V, Topr = –20 to +75°C)
Item
Input voltage (1)
Input voltage (2)
Conditions
High level input voltage
VIH (1)
Low level input voltage
VIL (1)
High level input voltage
VIH (2)
Low level input voltage
VIL (2)
Input voltage (3) Input voltage
VIN (3)
Min.
Typ.
Max.
0.7VDD
V
0.3VDD
Schmitt input
Unit Applicable pins
0.8VDD
∗1
V
V
0.2VDD
V
∗2
Analog input
Vss
VDD
V
∗3, 7, 8, 10
VDD – 0.8
VDD
V
∗4
0
0.4
V
VDD – 0.8
VDD
V
0
0.4
V
Output
voltage (1)
High level output voltage VOH(1)
IOH = –4mA
Low level output voltage VOL(1)
IOL = 4mA
Output
voltage (2)
High level output voltage VOH(2)
IOH = –2mA
Low level output voltage VOL (2)
IOL = 4mA
Output
voltage (3)
High level output voltage VOH(3)
IOH = –0.28mA VDD – 0.5
VDD
V
Low level output voltage VOL (3)
IOL = 0.36mA
0
0.4
V
∗5
∗6
Input leak current (1)
ILI (1)
VI = 0 to 5.5V
–10
10
µA
∗1, 2
Input leak current (2)
ILI (2)
VI = 1.5 to 3.5V
–20
20
µA
∗7
Input leak current (3)
ILI (3)
VI = 0 to 5.0V
–40
600
µA
∗8
Tri-state pin
output leak current
ILO
VO = 0 to 5.5V
–5
5
µA
∗9
Applicable pins
∗1 XTSL, DATA, XLAT, TEST, TES2, TES3, SSTP, ATSK, PWMI, SYSM, EMPHI, PCMDI
∗2 CLOK, XRST, EXCK, SQCK, VCKI, LRCKI, BCKI, SPOA, SCLK
∗3 CLTV, FILI, RFAC, VCTL, AIN1, AIN2, ASYI
∗4 MDP, PCO, PDO, VPCO1, VPCO2
∗5 ASYO, DOUT, FSTO, C4M, SBSO, SQSO, SCOR, EMPH, LOCK, WDCK, SENS, MDS, MNT0, MNT1,
MNT3, WFCK, V16M, CKOUT, LMUT2, RMUT1, XLON, LRCK, PCMD, BCK, GTOP, XUGF, XPCK, GFS,
RFCK, C2PO, XRAOF, MIRR, DFCT, COUT, FFDR, FRDR, TFDR, TRDR, SFDR, SRDR
∗6 FILO
∗7 TE, SE, FE, CE, VC
∗8 RFDC
∗9 SENS, MDS, MDP, PDO, PCO, VPCO1, VPCO2
∗10 RFC
–8–
CXD2548R
2. AC Characteristics
(1) XTAI pin
(a) When using self-excited oscillation
(Topr = –20 to +75°C, VDD = AVDD = 5.0V ± 5%)
Item
Oscillation
frequency
Symbol
Min.
Typ.
7
fMAX
Max.
Unit
34
MHz
(b) When inputting pulses to XTAI pin
(Topr = –20 to +75°C, VDD = AVDD = 5.0V ± 5%)
Item
Symbol
Min.
Typ.
Max.
Unit
High level pulse
width
tWHX
13
500
ns
Low level pulse
width
tWLX
13
500
ns
Pulse cycle
tCK
26
1,000
ns
Input high level
VIHX
VDD – 1.0
Input low level
VILX
0.8
V
Rise time, fall
time
tR, tF
10
ns
V
tCX
tWLX
tWHX
VIHX
VIHX × 0.9
VDD/2
XTLI
VIHX × 0.1
VILX
tR
tF
(c) When inputting sine waves to XTLI pin via a capacitor
(Topr = –20 to +75°C, VDD = AVDD = 5.0V ± 5%)
Item
Input amplitude
Symbol
Min.
VI
2.0
Typ.
Max.
Unit
VDD + 0.3 Vp-p
–9–
CXD2548R
(2) CLOK, DATA, XLAT, SQCK, and EXCK pins
(VDD = AVDD = 5.0V ± 5%, VSS = AVSS = 0V, Topr = –20 to +75°C)
Item
Clock frequency
fCK
Clock pulse width
Latch pulse width
tWCK
tSU
tH
tD
tWL
EXCK, SQCK frequency
fT
Setup time
Hold time
Delay time
Min.
Symbol
Typ.
Max.
Unit
0.65
MHz
750
ns
300
ns
300
ns
300
ns
750
ns
0.65∗1
MHz
750∗1
EXCK, SQCK pulse width fWT
ns
1/fCK
tWCK
tWCK
CLK
DATA
XLT
tSU
tH
tD
tWL
EXCK
SQCK
tWT
tWT
1/fT
SUBQ
SQCK
tSU
tH
∗1 In quasi double-speed playback mode, except when SQSO is Sub Q Read, the SQCL maximum operating
frequency is 300kHz and its minimum pulse width is 1.5µs.
(3) BCKI, LRCKI and PCMDI pins (VDD = AVDD = 5.0V ± 5%, VSS = AVSS = 0V, Topr = –20 to +75°C)
Item
Symbol Conditions
BCK pulse width
tW
tSU
tH
tSU
DATAL, R setup time
DATAL, R hold time
LRCK setup time
Min.
Typ.
Unit
94
ns
18
ns
18
ns
18
ns
tW(BCKI) tW(BCKI)
BCKI
Max.
VDD/2
VDD/2
tSU
tH
(PCMDI) (PCMDI)
PCMDI
tSU
(LRCKI)
LRCKI
– 10 –
CXD2548R
(4) SCLK pin
XLAT
tDLS
tSPW
···
SCLK
1/fSCLK
Serial Read Out Data
(SENS)
Item
Symbol
SCLK frequency
fSCLK
SCLK pulse width
tSPW
tDLS
Delay time
···
MSB
Min.
Typ.
Max.
Unit
1
MHz
500
ns
15
µs
LSB
(5) COUT, MIRR and DFCT pins
Operating frequency (VDD = AVDD = 5.0V ± 5%, VSS = AVSS = 0V, Topr = –20 to +75°C)
Item
Symbol
Min.
Typ.
Max.
Unit
Conditions
COUT maximum
operating frequency
fCOUT
40
kHz
∗1
MIRR maximum
operating frequency
fMIRR
40
kHz
∗2
DFCT maximum
operating frequency
fDFCTH
5
kHz
∗3
∗1 When using a high-speed traverse TZC
∗2
B
A
When the RF signal continuously satisfies the following conditions during the above traverse.
• A = 0.6 to 1.3V
•
B
= 25% or less
A+B
∗3 During complete RF signal omission
When settings related to DFCT signal generation are Typ.
– 11 –
CXD2548R
1-bit DAC and LPF Block Analog Characteristics
Analog characteristics (VDD = AVDD = 5.0V, VSS = AVSS = 0V, Ta = 25°C)
Item
Symbol
Total harmonic
distortion
THD
Signal-to-noise
ratio
S/N
Typ.
Max.
384Fs
0.0050
0.0070
768Fs
0.0045
0.0065
Min.
Crystal
Conditions
1kHz, 0dB data
1kHz, 0dB data
(Using A-weighting filter)
384Fs
96
100
768Fs
96
100
Fs = 44.1kHz in all cases.
The total harmonic distortion and signal-to-noise ratio measurement circuits are shown below.
12k
AOUT1 (2)
680p
12k
12k
SHIBASOKU (AM51A)
AIN1 (2)
150p
LOUT1 (2)
Audio Analyzer
22µ
100k
LPF external circuit diagram
768Fs/384Fs
TEST DISC
DATA
RF
Rch
A
Lch
B
Audio Analyzer
CXD2548R
Block diagram of analog characteristics measurement
– 12 –
Unit
%
dB
CXD2548R
(VDD = AVDD = 5.0V, VSS = AVSS = 0V, Topr = –20 to +75°C)
Item
Symbol
Output voltage
VOUT
Load resistance
RL
Min.
Typ.
1.15∗
8
∗ When a sine wave of 1kHz and 0dB is output.
Applicable pins
∗1 LOUT1, LOUT2
– 13 –
Max.
Unit
Applicable pins
Vrms
∗1
kΩ
∗1
CXD2548R
Contents
[1] CPU Interface
§1-1. CPU Interface Timing ...................................................................................................................... 15
§1-2. CPU Interface Command Table . ..................................................................................................... 16
§1-3. CPU Command Presets .................................................................................................................. 25
§1-4. Description of SENS Signals ........................................................................................................... 30
[2] Description of CD Signal Processing and DAC System Commands and Subcode Interface
§2-1. Description of Commands and Data Sets ....................................................................................... 31
§2-2. Subcode Interface ........................................................................................................................... 50
[3] Description of Other CD Signal Processing and DAC System Functions
§3-1. Description of DSP Operating Modes ............................................................................................. 55
(a)
CLV-N Mode .................................................................................................................................... 55
(b)
CLV-W Mode ................................................................................................................................... 55
(c)
CAV-W Mode .................................................................................................................................. 55
§3-2. Frame Sync Protection .................................................................................................................... 57
§3-3. Error Correction ............................................................................................................................... 57
§3-4. DA Interface .................................................................................................................................... 58
§3-5. Digital Out ........................................................................................................................................ 60
§3-6. Servo Auto Sequence ..................................................................................................................... 60
§3-7. Asymmetry Compensation .............................................................................................................. 67
§3-8. Channel Clock Regeneration by the Digital PLL Circuit .................................................................. 68
§3-9. Digital CLV ...................................................................................................................................... 70
§3-10. 1-bit DAC Block ............................................................................................................................... 71
§3-11. LPF Block ........................................................................................................................................ 73
§3-12. Setting the Playback Speed for the CD-DSP and 1-bit DAC Blocks ............................................... 74
[4] Description of Servo Signal Processing System Functions and Commands
§4-1. General Description of the Servo Signal Processing System ......................................................... 75
§4-2. Digital Servo Block Master Clock (MCK) ......................................................................................... 76
§4-3. AVRG Measurement and Compensation ........................................................................................ 76
§4-4. E:F Balance Adjustment Function ................................................................................................... 78
§4-5. FCS Bias Adjustment Function ....................................................................................................... 78
§4-6. AGCNTL Function ........................................................................................................................... 80
§4-7. FCS Servo and FCS Search ........................................................................................................... 82
§4-8. TRK and SLD Servo Control ........................................................................................................... 83
§4-9. MIRR and DFCT Signal Generation ................................................................................................ 84
§4-10. DFCT Countermeasure Circuit ........................................................................................................ 85
§4-11. Anti-Shock Circuit ............................................................................................................................ 85
§4-12. Brake Circuit .................................................................................................................................... 86
§4-13. COUT Signal ................................................................................................................................... 87
§4-14. Serial Readout Circuit ..................................................................................................................... 87
§4-15. Writing the Coefficient RAM ............................................................................................................ 88
§4-16. PWM Output .................................................................................................................................... 88
§4-17. Servo Status Changes Produced by the LOCK Signal ................................................................... 90
§4-18. Description of Commands and Data Sets ........................................................................................ 90
§4-19. List of Servo Filter Coefficients ...................................................................................................... 102
§4-20. FILTER Composition ..................................................................................................................... 104
§4-21. TRACKING and FOCUS Frequency Response ............................................................................ 111
[5] Application Circuit
§5-1. Application Circuit .......................................................................................................................... 112
Explanation of abbreviations
AVRG:
AGCNTL:
FCS:
TRK:
SLD:
DFCT:
Average
auto gain control
Focus
Tracking
Sled
Defect
– 14 –
CXD2548R
[1] CPU Interface
§1-1. CPU Interface Timing
• CPU Interface
This interface uses DATA, CLOK, and XLAT to set the modes.
The interface timing chart is shown below.
750ns or more
CLOK
DATA
(Example)
D18
D19
D20
D21
D22
D23
750ns or more
XLAT
Valid
Registers
• The internal registers are initialized by a reset when XRST = 0.
Note) Be sure to set SQCK to high when XLAT is low.
– 15 –
TRACKING
CONTROL
FOCUS
CONTROL
0
1
Command
Register
0001
0000
—
– 16 –
—
—
—
—
—
—
—
—
—
—
1
0
—
0
1
—
—
—
—
—
—
—
—
—
—
—
—
0
—
—
—
—
1
—
—
—
—
—
—
—
0
—
—
—
—
—
0
1
—
—
1
—
0
1
0
—
1
—
0
—
—
—
1
—
0
—
—
—
0
—
0
—
—
—
—
1
—
—
—
—
1
D14
D15
D16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
D13
Data 2
D17
0
D18
Data 1
1
D23 to D20 D19
Address
Command Table ($0X to 1X)
§1-2. CPU Interface Command Table
—
—
—
—
—
—
—
—
—
—
—
—
—
—
D12
—
—
—
—
—
—
—
—
—
—
—
—
—
—
D11
—
—
—
—
—
—
—
—
—
—
—
—
—
—
D10
—
—
—
—
—
—
—
—
—
—
—
—
—
—
D9
Data 3
—
—
—
—
—
—
—
—
—
—
—
—
—
—
D8
—
—
—
—
—
—
—
—
—
—
—
—
—
—
D7
—
—
—
—
—
—
—
—
—
—
—
—
—
—
D6
—
—
—
—
—
—
—
—
—
—
—
—
—
—
D5
Data 4
—
—
—
—
—
—
—
—
—
—
—
—
—
—
D4
—
—
—
—
—
—
—
—
—
—
—
—
—
—
D3
—
—
—
—
—
—
—
—
—
—
—
—
—
—
D2
—
—
—
—
—
—
—
—
—
—
—
—
—
—
D1
Data 5
—
—
—
—
—
—
—
—
—
—
—
—
—
—
D0
—: Don’t care
TRACKING GAIN UP
FILTER SELECT 2
TRACKING GAIN UP
FILTER SELECT 1
TRACKING GAIN UP
TRACKING GAIN
NORMAL
BRAKE OFF
BRAKE ON
ANTI SHOCK OFF
ANTI SHOCK ON
FOCUS SEARCH
VOLTAGE UP
FOCUS SEARCH
VOLTAGE DOWN
FOCUS SERVO OFF,
FOCUS SEARCH
VOLTAGE OUT
FOCUS SERVO OFF,
0V OUT
FOCUS SERVO ON
(FOCUS GAIN
DOWN)
FOCUS SERVO ON
(FOCUS GAIN
NORMAL)
CXD2548R
– 17 –
3
SELECT
Command
TRACKING
MODE
2
Register
Command
Register
0011
0
0
0
0
0
0
0
D18
0
D23 to D20 D19
—
1
0
1
1
1
1
0
0
0
0
1
D16
D17
Data 1
1
1
—
—
—
0
—
—
0
—
—
—
—
D15
—
—
—
—
—
—
—
1
1
0
—
—
—
0
1
—
—
—
—
1
0
—
—
—
—
0
0
Address
0010
D15
D16
D17
Data 1
D18
D23 to D20 D19
Address
Command Table ($2X to 3X)
—
—
—
—
—
—
—
—
D13
—
—
—
—
D14
—
—
—
—
D13
Data 2
—
—
—
—
—
—
—
—
D14
Data 2
—
—
—
—
D12
—
—
—
—
—
—
—
—
D12
—
—
—
—
D11
—
—
—
—
—
—
—
—
D11
—
—
—
—
—
—
—
—
D9
—
—
—
—
D10
—
—
—
—
D9
Data 3
—
—
—
—
—
—
—
—
D10
Data 3
—
—
—
—
D8
—
—
—
—
—
—
—
—
D8
—
—
—
—
D7
—
—
—
—
—
—
—
—
D7
—
—
—
—
—
—
—
—
D5
—
—
—
—
D6
—
—
—
—
D5
Data 4
—
—
—
—
—
—
—
—
D6
Data 4
—
—
—
—
D4
—
—
—
—
—
—
—
—
D4
—
—
—
—
D3
—
—
—
—
—
—
—
—
D3
—
—
—
—
—
—
—
—
D1
—
—
—
—
D2
—
—
—
—
D1
Data 5
—
—
—
—
—
—
—
—
D2
Data 5
—
—
—
—
D0
—
—
—
—
—
—
—
—
D0
—: Don’t care
SLED KICK LEVEL
(±4 × basic value)
SLED KICK LEVEL
(±3 × basic value)
SLED KICK LEVEL
(±2 × basic value)
SLED KICK LEVEL
(±1 × basic value) (Default)
REVERSE SLED MOVE
FORWARD SLED MOVE
SLED SERVO ON
SLED SERVO OFF
REVERSE TRACK JUMP
FORWARD TRACK JUMP
TRACKING SERVO ON
TRACKING SERVO OFF
CXD2548R
3
Register
SELECT
Command
Address 2
Address 3
0011
0100
0000
0
0
1
1
1
0
0
0
0
0
– 18 –
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
D10
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
D9
Address 4
0
D23 to D20 D19 to D16 D15 to D12 D11
Address 1
Command Table ($340X)
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
D8
D6
D5
D4
D3
D2
D1
Data 2
D0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
D7
Data 1
KRAM DATA (K0F)
FOCUS DEFECT HOLD GAIN
KRAM DATA (K0E)
FOCUS PHASE COMPENSATE FILTER A
KRAM DATA (K0D)
FOCUS LOW BOOST FILTER B-L
KRAM DATA (K0C)
FOCUS LOW BOOST FILTER B-H
KRAM DATA (K0B)
FOCUS LOW BOOST FILTER A-L
KRAM DATA (K0A)
FOCUS LOW BOOST FILTER A-H
KRAM DATA (K09)
FOCUS HIGH CUT FILTER B
KRAM DATA (K08)
FOCUS HIGH CUT FILTER A
KRAM DATA (K07)
SLED AUTO GAIN
KRAM DATA (K06)
FOCUS INPUT GAIN
KRAM DATA (K05)
SLED OUTPUT GAIN
KRAM DATA (K04)
SLED LOW BOOST FILTER B-L
KRAM DATA (K03)
SLED LOW BOOST FILTER B-H
KRAM DATA (K02)
SLED LOW BOOST FILTER A-L
KRAM DATA (K01)
SLED LOW BOOST FILTER A-H
KRAM DATA (K00)
SLED INPUT GAIN
CXD2548R
3
Register
SELECT
Command
Address 2
Address 3
0011
0100
0001
0
0
1
1
1
0
0
0
0
0
– 19 –
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
D10
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
D9
Address 4
0
D23 to D20 D19 to D16 D15 to D12 D11
Address 1
Command Table ($341X)
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
D8
D6
D5
D4
D3
D2
D1
Data 2
D0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
D7
Data 1
KRAM DATA (K1F)
TRACKING LOW BOOST FILTER B-L
KRAM DATA (K1E)
TRACKING LOW BOOST FILTER B-H
KRAM DATA (K1D)
TRACKING LOW BOOST FILTER A-L
KRAM DATA (K1C)
TRACKING LOW BOOST FILTER A-H
KRAM DATA (K1B)
TRACKING HIGH CUT FILTER B
KRAM DATA (K1A)
TRACKING HIGH CUT FILTER A
KRAM DATA (K19)
TRACKING INPUT GAIN
KRAM DATA (K18)
FIX
KRAM DATA (K17)
HPTZC / AUTO GAIN LOW PASS FILTER B
KRAM DATA (K16)
ANTI SHOCK HIGH PASS FILTER A
KRAM DATA (K15)
HPTZC / AUTO GAIN HIGH PASS FILTER B
KRAM DATA (K14)
HPTZC / AUTO GAIN HIGH PASS FILTER A
KRAM DATA (K13)
FOCUS AUTO GAIN
KRAM DATA (K12)
ANTI SHOCK INPUT GAIN
KRAM DATA (K11)
FOCUS OUTPUT GAIN
KRAM DATA (K10)
FOCUS PHASE COMPENSATE FILTER B
CXD2548R
3
Register
SELECT
Command
Address 2
Address 3
0011
0100
0010
0
0
1
1
1
0
0
0
0
0
– 20 –
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
D10
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
D9
Address 4
0
D23 to D20 D19 to D16 D15 to D12 D11
Address 1
Command Table ($342X)
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
D8
D6
D5
D4
D3
D2
D1
Data 2
D0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
D7
Data 1
KRAM DATA (K2F)
NOT USED
KRAM DATA (K2E)
NOT USED
KRAM DATA (K2D)
FOCUS GAIN DOWN OUTPUT GAIN
KRAM DATA (K2C)
FOCUS GAIN DOWN PHASE COMPENSATE FILTER B
KRAM DATA (K2B)
FOCUS GAIN DOWN DEFECT HOLD GAIN
KRAM DATA (K2A)
FOCUS GAIN DOWN PHASE COMPENSATE FILTER A
KRAM DATA (K29)
FOCUS GAIN DOWN LOW BOOST FILTER B-L
KRAM DATA (K28)
FOCUS GAIN DOWN LOW BOOST FILTER B-H
KRAM DATA (K27)
FOCUS GAIN DOWN LOW BOOST FILTER A-L
KRAM DATA (K26)
FOCUS GAIN DOWN LOW BOOST FILTER A-H
KRAM DATA (K25)
FOCUS GAIN DOWN HIGH CUT FILTER B
KRAM DATA (K24)
FOCUS GAIN DOWN HIGH CUT FILTER A
KRAM DATA (K23)
TRACKING AUTO GAIN
KRAM DATA (K22)
TRACKING OUTPUT GAIN
KRAM DATA (K21)
TRACKING PHASE COMPENSATE FILTER B
KRAM DATA (K20)
TRACKING PHASE COMPENSATE FILTER A
CXD2548R
3
Register
SELECT
Command
Address 2
Address 3
0011
0100
0011
0
0
1
1
1
0
0
0
0
0
– 21 –
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
D10
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
D9
Address 4
0
D23 to D20 D19 to D16 D15 to D12 D11
Address 1
Command Table ($343X)
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
D8
D6
D5
D4
D3
D2
D1
Data 2
D0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
D7
Data 1
KRAM DATA (K3F)
NOT USED
KRAM DATA (K3E)
TRACKING GAIN UP OUTPUT GAIN
KRAM DATA (K3D)
TRACKING GAIN UP PHASE COMPENSATE FILTER B
KRAM DATA (K3C)
TRACKING GAIN UP PHASE COMPENSATE FILTER A
KRAM DATA (K3B)
TRACKING GAIN UP2 LOW BOOST FILTER B-L
KRAM DATA (K3A)
TRACKING GAIN UP2 LOW BOOST FILTER B-H
KRAM DATA (K39)
TRACKING GAIN UP2 LOW BOOST FILTER A-L
KRAM DATA (K38)
TRACKING GAIN UP2 LOW BOOST FILTER A-H
KRAM DATA (K37)
TRACKING GAIN UP2 HIGH CUT FILTER B
KRAM DATA (K36)
TRACKING GAIN UP2 HIGH CUT FILTER A
KRAM DATA (K35)
ANTI SHOCK FILTER COMPARATE GAIN
KRAM DATA (K34)
ANTI SHOCK HIGH PASS FILTER B-L
KRAM DATA (K33)
ANTI SHOCK HIGH PASS FILTER B-H
KRAM DATA (K32)
NOT USED
KRAM DATA (K31)
ANTI SHOCK LOW PASS FILTER B
KRAM DATA (K30)
FIX
CXD2548R
3
Register
SELECT
Command
Address 2
Address 3
0011
0100
0100
0
0
1
1
1
0
0
0
0
0
– 22 –
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
D10
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
D9
Address 4
0
D23 to D20 D19 to D16 D15 to D12 D11
Address 1
Command Table ($344X)
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
D8
D6
D5
D4
D3
D2
D1
Data 2
D0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
D7
Data 1
KRAM DATA (K4F)
NOT USED
KRAM DATA (K4E)
NOT USED
KRAM DATA (K4D)
FOCUS HOLD FILTER OUTPUT GAIN
KRAM DATA (K4C)
FOCUS HOLD FILTER B-L
KRAM DATA (K4B)
FOCUS HOLD FILTER B-H
KRAM DATA (K4A)
FOCUS HOLD FILTER A-L
KRAM DATA (K49)
FOCUS HOLD FILTER A-H
KRAM DATA (K48)
FOCUS HOLD FILTER INPUT GAIN
KRAM DATA (K47)
NOT USED
KRAM DATA (K46)
NOT USED
KRAM DATA (K45)
TRACKING HOLD FILTER OUTPUT GAIN
KRAM DATA (K44)
TRACKING HOLD FILTER B-L
KRAM DATA (K43)
TRACKING HOLD FILTER B-H
KRAM DATA (K42)
TRACKING HOLD FILTER A-L
KRAM DATA (K41)
TRACKING HOLD FILTER A-H
KRAM DATA (K40)
TRACKING HOLD FILTER INPUT GAIN
CXD2548R
3
Register
SELECT
Command
0
1
0
– 23 –
0011
1
1
1
1
1
D18
1
1
D17
0
0
Address
1
D23 to D20 D19
0011
1
1
1
0
1
D17
1
0
1
D18
0
0
1
Address
0
1
1
0
0
1
1
0
1
0
1
0
D23 to D20 D19
0011
D17
D18
Address
0
0
1
1
D17
D18
0
D23 to D20 D19
0011
0
D23 to D20 D19
Command Table ($34FX to 3FX)
1
0
D16
1
0
D16
1
0
1
0
1
0
1
D16
0
0
0
D16
1
1
1
D13
D9
D6
D5
D4
D3
D2
D1
TJ1
TV5
FB5
D4
D3
TV3
FB3
D2
D1
Data 4
TV2 TV1
FB2 FB1
D0
TV0
—
TRVSC DATA
FOCUS BIAS DATA
DTZC/TRACK JUMP
VOLTAGE/AUTO GAIN
D5
TV4
FB4
TJ0 SFJP TG6 TG5 TG4 TG3 TG2 TG1 TG0
D6
Data 3
TV6
FB6
FOCUS BIAS LIMIT
FOCUS SEARCH SPEED/
VOLTAGE/AUTO GAIN
D7
TV7
FB7
—
D0
FBON FBSS FBUP FBV1 FBV0
0
0
0
0
0
—
—
D13
D14
D13
Data 1
—
—
D14
D12
—
—
D12
D11
—
—
D11
—
—
D9
D10
D9
Data 2
—
—
D10
Data 2
D8
—
—
D8
D7
—
—
D7
—
—
D5
D6
D5
Data 3
—
—
D6
Data 3
0
AGG4 XT4D XT2D
0
DRR2 DRR1 DRR0
0
ASFG
0
F1NM F1DM F3NM F3DM T1NM T1UM T3NM T3UM DFIS TLCD RFLP
D15
—
—
D15
Data 1
0
0
0
SERIAL DATA READ
MODE/SELECT
0
D3
—
—
D3
LPAS SRO1
0
D4
—
—
D4
0
—
—
D1
0
0
D2
D0
—
—
D0
0
AGHF COT2 Others
—: Don’t care
TZC for COUT SLCT
DTZC
TZC for COUT SLCT
HPTZC (Default)
Operation for MIRR/
DFCT/FOK
MIRI XT1D Filter
D1
Data 4
—
—
D2
Data 4
0
TJD0 FPS1 FPS0 TPS1 TPS0 CEIT SJHD INBK MTI0 FOCUS BIAS
0
SFO2 SFO1 SDF2 SDF1 MAX2 MAX1 SFOX BTF D2V2 D2V1 D1V2 D1V1 RINT
0
DAC SD6 SD5 SD4 SD3 SD2 SD1 SD0
LEVEL/AUTO GAIN/
DFSW/ (Initialize)
TJ2
D7
FTZ FG6 FG5 FG4 FG3 FG2 FG1 FG0
D8
TV9 TV8
FB9 FB8
FS2 FS1 FS0
D10
D8
FBL9 FBL8 FBL7 FBL6 FBL5 FBL4 FBL3 FBL2 FBL1
D9
Data 2
0
1
0
D10
Data 3
VCLM VCLC FLM FLC0 RFLM RFLC AGF AGT DFSW LKSW TBLM TCLM FLC1 TLC2 TLC1 TLC0
TJ3
FS3
D11
0
0
1
D11
Data 2
FZSL/SLED MOVE/
Voltage/AUTO GAIN
TJ4
FS5 FS4
FT0
DTZC TJ5
D13
D12
1
1
1
D12
D14
Data 1
1
1
1
D14
Data 1
FZSH FZSL SM5 SM4 SM3 SM2 SM1 SM0 AGS AGJ AGGF AGGT AGV1 AGV2 AGHS AGHT
0
FT1
D15
1
1
1
D15
Address
CXD2548R
1
1
0
0
0
1
1
Blind (A, E),
Overflow (C)
Brake (B)
Kick (D)
Auto sequence
(N) track jump
count
Mode
specification
Function
specification
5
6
7
8
9
– 24 –
1
1
1
1
1
1
1
Serial bus
CTRL
Spindle servo
coefficient
setting
CLV CTRL
CLV MODE
B
C
D
E
0
1
Audio CTRL
A
0
0
0
1
1
0
Auto sequence
4
D26
1
0
0
1
1
0
0
1
1
0
0
D25
Address
D27
Command
Register
name
Command Table ($4X to EX)
D22
D21
D20
—
—
—
D19
—
—
—
D18
—
—
—
D17
0
Mute ATT
SL0 CPUSR
0
16
—
—
—
D12
0
—
—
—
—
0
—
1
2
—
—
—
D9
—
0
1
—
—
—
D8
—
—
—
—
—
—
D7
—
—
—
—
—
—
D6
—
—
—
—
—
—
D5
Data 5
—
—
—
—
—
—
D4
—
—
—
—
—
—
D3
—
—
—
—
CM3 CM2 CM1 CM0 EPWM SPDC ICAP SFSL VC2C HIFC LPWR VPON
0
—
—
—
Gain Gain
FCSW
CAV1 CAV0
—
—
—
0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 FMUT
—
—
—
0
4
—
—
—
D10
Data 4
MCSL CKOSL1 CKOSL0 ZDPL ZMUT
0
8
—
—
—
D11
Gain
VP7 VP6 VP5 VP4 VP3 VP2 VP1 VP0
CLVS
—
32
—
—
—
D13
DCLV
TB
PWM MD
TP
0
OPSL EMPH SMUT
—
64
—
—
—
D14
VCO
KSL3 KSL2 KSL1 KSL0
SEL2
128
—
—
—
D15
—
—
—
0
0
SOCT
256
—
—
—
D16
Data 3
—
—
—
0
0
0
0
DSPB
ON/OFF
0
0
VCO
DOUT DOUT
WSEL
SEL1
Mute ON/OFF
Gain Gain Gain Gain
MDP1 MDP0 MDS1 MDS0
SL1
0
0
CDROM
32768 16384 8192 4096 2048 1024 512
11.6ms 5.8ms 2.9ms 1.45ms
0.36ms 0.18ms 0.09ms 0.05ms
0.18ms 0.09ms 0.05ms 0.02ms
AS3 AS2 AS1 AS0
D23
Data 2
1
0
1
0
1
0
1
0
1
0
D24
Data 1
—
—
—
—
0
—
—
—
—
—
—
D2
—
—
—
—
0
—
—
—
—
—
—
D0
—: Don’t care
—
—
—
—
0
—
—
—
—
—
—
D1
Data 6
CXD2548R
Command
Register
SELECT
0010
TRACKING
MODE
2
3
0001
TRACKING
CONTROL
1
0
0
0
– 25 –
0011
0
D18
0
0
0
D18
0
1
D18
0
1
0
D16
0
D17
0
D17
0
D16
0
D16
Data 1
0
0
0
D17
Data 1
Address 1
0
D23 to D20 D19
0011
D23 to D20 D19
Address
0000
FOCUS
CONTROL
0
D23 to D20 D19
Command
Register
Address
Command Preset Table ($0X to 34X)
§1-3. CPU Command Presets
0
D15
—
D15
—
—
—
D15
—
—
—
D13
—
D13
D14
D13
Address 2
—
D14
Data 2
—
—
—
D14
Data 2
D12
—
D12
—
—
—
D12
D11
—
D11
—
—
—
D11
—
—
—
D9
—
D9
D9
D8
—
D8
—
—
—
D8
D7
—
D7
—
—
—
D7
—
—
—
D5
—
D5
D6
D5
Data 1
—
D6
Data 4
—
—
—
D6
Data 4
D4
—
D4
—
—
—
D4
See "Coefficient ROM Preset Values Table".
D10
Address 3
—
D10
Data 3
—
—
—
D10
Data 3
D3
—
D3
—
—
—
D3
—
—
—
D1
—
D0
D2
D0
Data 2
—
D2
Data 5
—
—
—
D2
Data 5
D0
—
D0
—
—
—
D0
—: Don’t care
KRAM DATA
($3400XX to $344fXX)
SLED KICK LEVEL
(±1 × basic value) (Default)
TRACKING SERVO OFF
SLED SERVO OFF
TRACKING GAIN UP
FILTER SELECT 1
FOCUS SERVO OFF,
0V OUT
CXD2548R
3
Register
SELECT
Command
0
1
0
– 26 –
0011
1
1
1
1
D18
1
1
D17
0
1
Address
1
D23 to D20 D19
0011
D17
1
0
1
D18
1
0
1
Address
0
0
1
0
1
1
0
0
1
1
0
1
0
1
0
D23 to D20 D19
0011
D17
D18
Address
0
0
1
1
D17
D18
0
D23 to D20 D19
0011
0
D23 to D20 D19
Address 1
Command Preset Table ($34FX to 3FX)
1
0
D16
0
D16
1
0
1
0
1
0
1
D16
0
0
0
D16
1
1
1
D13
—
D13
1
0
0
0
0
0
0
D13
0
0
0
0
0
0
D13
D14
Data 1
—
D14
Data 1
1
0
0
0
1
0
1
D14
Data 1
1
1
1
D14
D15
—
D15
1
0
0
0
0
0
0
D15
1
1
1
D15
0
0
D12
—
D12
0
0
0
0
1
0
1
D12
1
1
1
D12
Address 2
0
0
D11
—
D11
0
0
0
0
0
1
1
D11
0
0
1
D11
0
0
0
D9
0
0
0
0
0
1
0
D9
—
D9
0
0
0
0
D9
D10
Data 2
—
D10
Data 2
0
0
0
0
0
1
0
D10
Data 2
0
1
0
D10
0
0
D8
—
D8
0
0
0
0
0
0
0
D8
0
0
0
D8
Data 1
0
0
D7
—
D7
0
0
0
0
1
0
0
D7
0
0
0
D7
0
0
0
D5
0
0
0
0
1
1
1
D5
—
D5
0
0
0
0
D5
D6
Data 3
—
D6
Data 3
1
0
0
0
0
0
0
D6
Data 3
0
0
0
D6
Data 2
0
0
D4
—
D4
1
0
0
0
1
0
0
D4
0
0
0
D4
0
0
D3
—
D3
0
0
0
0
1
1
1
D3
0
0
0
D3
0
0
0
D1
0
0
0
0
1
1
0
D1
—
D1
0
0
D2
0
0
D1
Data 4
—
D2
Data 4
0
0
0
0
0
1
1
D2
Data 4
0
0
0
D2
Data 3
0
0
D0
—
D0
0
0
0
0
0
0
1
D0
0
0
0
D0
Others
Filter
—: Don’t care
TZC for COUT SLCT
HPTZC (Default)
Operation for MIRR/
DFCT/FOK
FOCUS BIAS
SERIAL DATA READ
MODE/SELECT
LEVEL/AUTO GAIN/
DFSW/ (Initialize)
FZSL/SLED MOVE/
Voltage/AUTO GAIN
DTZC/TRACK JUMP
VOLTAGE AUTO GAIN
FOCUS SEARCH SPEED/
VOLTAGE AUTO GAIN
TRVSC DATA
FOCUS BIAS DATA
FOCUS BIAS LIMIT
CXD2548R
1
1
0
0
0
1
1
Blind (A, E),
Overflow (C)
Brake (B)
Kick (D)
Auto sequence
(N) track jump
count
Mode
specification
Function
specification
5
6
7
8
9
– 27 –
1
1
1
1
1
1
1
Serial bus
CTRL
Spindle servo
coefficient
setting
CLV CTRL
CLV MODE
B
C
D
E
0
1
Audio CTRL
A
0
0
0
1
1
0
Auto sequence
4
D26
1
0
0
1
1
0
0
1
1
0
0
D25
Address
D27
Command
Register
name
0
1
0
1
0
1
0
1
0
1
0
D24
Command Preset Table ($4X to EX)
0
0
0
0
0
0
0
0
0
0
0
D23
0
0
1
0
0
0
0
0
1
1
0
D22
0
0
1
1
0
0
0
0
1
0
0
D21
Data 1
0
0
0
0
0
0
0
0
1
1
0
D20
0
1
—
—
0
0
0
0
—
—
—
D19
0
1
—
—
0
0
0
0
—
—
—
D18
0
1
—
—
0
0
0
0
—
—
—
D17
Data 2
0
0
—
—
0
0
0
1
—
—
—
D16
0
0
—
—
0
0
0
0
—
—
—
D15
0
0
—
—
0
0
0
0
—
—
—
D14
0
0
—
—
0
0
1
0
—
—
—
D13
Data 3
0
0
—
—
0
0
0
0
—
—
—
D12
0
—
—
—
0
0
0
0
—
—
—
D11
0
—
—
—
0
0
0
0
—
—
—
D10
0
—
—
—
0
—
1
0
—
—
—
D9
Data 4
0
—
—
—
0
—
0
0
—
—
—
D8
—
—
—
—
0
—
—
—
—
—
—
D7
—
—
—
—
0
—
—
—
—
—
—
D6
—
—
—
—
0
—
—
—
—
—
—
D5
Data 5
—
—
—
—
0
—
—
—
—
—
—
D4
—
—
—
—
0
—
—
—
—
—
—
D3
—
—
—
—
0
—
—
—
—
—
—
D2
—
—
—
—
0
—
—
—
—
—
—
D0
—: Don’t care
—
—
—
—
0
—
—
—
—
—
—
D1
Data 6
CXD2548R
CXD2548R
<Coefficient ROM Preset Values Table (1)>
ADDRESS
DATA
K00
K01
K02
K03
K04
K05
K06
K07
K08
K09
K0A
K0B
K0C
K0D
K0E
K0F
E0
81
23
7F
6A
10
14
30
7F
46
81
1C
7F
58
82
7F
SLED INPUT GAIN
SLED LOW BOOST FILTER A-H
SLED LOW BOOST FILTER A-L
SLED LOW BOOST FILTER B-H
SLED LOW BOOST FILTER B-L
SLED OUTPUT GAIN
FOCUS INPUT GAIN
SLED AUTO GAIN
FOCUS HIGH CUT FILTER A
FOCUS HIGH CUT FILTER B
FOCUS LOW BOOST FILTER A-H
FOCUS LOW BOOST FILTER A-L
FOCUS LOW BOOST FILTER B-H
FOCUS LOW BOOST FILTER B-L
FOCUS PHASE COMPENSATE FILTER A
FOCUS DEFECT HOLD GAIN
K10
K11
K12
K13
K14
K15
K16
K17
K18
K19
K1A
K1B
K1C
K1D
K1E
K1F
4E
32
20
30
80
77
80
77
00
F1
7F
3B
81
44
7F
5E
FOCUS PHASE COMPENSATE FILTER B
FOCUS OUTPUT GAIN
ANTI SHOCK INPUT GAIN
FOCUS AUTO GAIN
HPTZC / Auto Gain HIGH PASS FILTER A
HPTZC / Auto Gain HIGH PASS FILTER B
ANTI SHOCK HIGH PASS FILTER A
HPTZC / Auto Gain LOW PASS FILTER B
Fix∗
TRACKING INPUT GAIN
TRACKING HIGH CUT FILTER A
TRACKING HIGH CUT FILTER B
TRACKING LOW BOOST FILTER A-H
TRACKING LOW BOOST FILTER A-L
TRACKING LOW BOOST FILTER B-H
TRACKING LOW BOOST FILTER B-L
K20
K21
K22
K23
K24
K25
K26
K27
K28
K29
K2A
K2B
K2C
K2D
K2E
K2F
82
44
18
30
7F
46
81
3A
7F
66
82
44
4E
1B
00
00
TRACKING PHASE COMPENSATE FILTER A
TRACKING PHASE COMPENSATE FILTER B
TRACKING OUTPUT GAIN
TRACKING AUTO GAIN
FOCUS GAIN DOWN HIGH CUT FILTER A
FOCUS GAIN DOWN HIGH CUT FILTER B
FOCUS GAIN DOWN LOW BOOST FILTER A-H
FOCUS GAIN DOWN LOW BOOST FILTER A-L
FOCUS GAIN DOWN LOW BOOST FILTER B-H
FOCUS GAIN DOWN LOW BOOST FILTER B-L
FOCUS GAIN DOWN PHASE COMPENSATE FILTER A
FOCUS GAIN DOWN DEFECT HOLD GAIN
FOCUS GAIN DOWN PHASE COMPENSATE FILTER B
FOCUS GAIN DOWN OUTPUT GAIN
NOT USED
NOT USED
CONTENTS
– 28 –
CXD2548R
<Coefficient ROM Preset Values Table (2)>
ADDRESS
DATA
K30
K31
K32
K33
K34
K35
K36
K37
K38
K39
K3A
K3B
K3C
K3D
K3E
K3F
80
66
00
7F
6E
20
7F
3B
80
44
7F
77
86
0D
57
00
Fix∗
ANTI SHOCK LOW PASS FILTER B
NOT USED
ANTI SHOCK HIGH PASS FILTER B-H
ANTI SHOCK HIGH PASS FILTER B-L
ANTI SHOCK FILTER COMPARATE GAIN
TRACKING GAIN UP2 HIGH CUT FILTER A
TRACKING GAIN UP2 HIGH CUT FILTER B
TRACKING GAIN UP2 LOW BOOST FILTER A-H
TRACKING GAIN UP2 LOW BOOST FILTER A-L
TRACKING GAIN UP2 LOW BOOST FILTER B-H
TRACKING GAIN UP2 LOW BOOST FILTER B-L
TRACKING GAIN UP PHASE COMPENSATE FILTER A
TRACKING GAIN UP PHASE COMPENSATE FILTER B
TRACKING GAIN UP OUTPUT GAIN
NOT USED
K40
K41
K42
K43
K44
K45
K46
K47
K48
K49
K4A
K4B
K4C
K4D
K4E
K4F
04
7F
7F
79
17
6D
00
00
02
7F
7F
79
17
54
00
00
TRACKING HOLD FILTER INPUT GAIN
TRACKING HOLD FILTER A-H
TRACKING HOLD FILTER A-L
TRACKING HOLD FILTER B-H
TRACKING HOLD FILTER B-L
TRACKING HOLD FILTER OUTPUT GAIN
NOT USED
NOT USED
FOCUS HOLD FILTER INPUT GAIN
FOCUS HOLD FILTER A-H
FOCUS HOLD FILTER A-L
FOCUS HOLD FILTER B-H
FOCUS HOLD FILTER B-L
FOCUS HOLD FILTER OUTPUT GAIN
NOT USED
NOT USED
CONTENTS
∗ Fix indicates that normal preset values should be used.
– 29 –
CXD2548R
§1-4. Description of SENS Signals
SENS output
Microcomputer serial register
(latching not required)
ASEQ = 1
Output data length
$0X
FZC
—
$1X
AS
—
$2X
TZC
—
$38
AGOK∗1
—
$38
XAVEBSY∗1
—
SSTP
—
$3900
VC In Reg.
8 bit
$3901
SLD In Reg.
8 bit
$3902
TRK In Reg.
8 bit
$3903
FCS In Reg.
8 bit
$3904
TE Avrg Reg.
9 bit
$3908
FE Avrg Reg.
9 bit
$390C
VC Avrg Reg.
9 bit
$391C
TRVSC Reg.
9 bit
$391D
FB Reg.
9 bit
$391E
RFDC In Reg.
8 bit
$391F
RFDC Avrg Reg.
8 bit
$3920 to $393F
Address 5-bit (M00 to 1F) data RAM data
16 bit
$3940 to $397F
Address 6-bit (K00 to 3F) coefficient RAM data
8 bit
$4X
XBUSY
—
$5X
FOK
—
$6X
0
—
$AX
GFS
—
$EX
OV64
—
0
—
$30 to 37, $3A to 3F
$7X, 8X, 9X, BX,
CX, DX, FX
∗1 $38 outputs AGOK during AGT and AGF command settings, and XAVEBSY during AVRG measurement.
SSTP is output in all other cases.
Note) The SENS output can be read from the SQSO pin when SOCT = 0, SL1 = 1 and SL0 = 0. (See "$BX
Commands".)
Description of SENS Signals
SENS output
XBUSY
Low while the auto sequencer is in operation, high when operation terminates.
FOK
Outputs the same signal as the FOK pin.
High for "focus OK".
GFS
High when the regenerated frame sync is obtained with the correct timing.
OV64
Low when the EFM signal is lengthened by 64 channel lock pulses or more after passing
through the sync detection filter.
– 30 –
CXD2548R
[2] Description of CD Signal Processing and DAC System Commands and Subcode Interface
2-1. Description of Commands and Data Sets
$4X commands
AS3
AS2
AS1
AS0
CANCEL
0
0
0
0
FOCUS-ON
0
1
1
1
1 TRACK JUMP
1
0
0
RXF
10 TRACK JUMP
1
0
1
RXF
2 NTRACK JUMP
1
1
0
RXF
N TRACK MOVE
1
1
1
RXF
Command
RXF = 0 FORWARD
RXF = 1 REVERSE
• When the Focus-on command ($47) is canceled, $02 is sent and the auto sequence is interrupted.
• When the Track jump/Move commands ($48 to $4F) are canceled, $25 is sent and the auto sequence is
interrupted.
$5X commands
Auto sequence timer setting
Set timers: A, E, C, B
Command
D23
D22
D21
D20
Blind (A, E), Over flow (C)
0.18ms
0.09ms
0.05ms
0.02ms
Brake (B)
0.36ms
0.18ms
0.09ms
0.05ms
e.g.) D2 = D0 = 1, D3 = D1 = 0 (Initial Reset)
A = E = C = 0.11ms
B = 0.23ms
$6X commands
Auto sequence timer setting
Set timer: D
Command
KICK (D)
D23
D22
D21
D20
11.6ms
5.8ms
2.9ms
1.45ms
e.g.) D3 = 0, D2 = D1 = D0 = 1 (Initial Reset)
D = 10.15ms
$7X commands
Auto sequence track jump/move count setting (N)
Data 1
Command
Data 2
Data 3
Data 4
D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9 D8
Auto sequence track jump
215 214 213 212 211 210
count setting
29
28
27
26
25
24
23
22
21
20
This command is used to set N when a 2N-track jump or N-track move is executed for auto sequence.
• The maximum track count is 65,535, but note that with a 2N-track jump the maximum track jump count
depends on the mechanical limitations of the optical system.
• When the track jump count is from 0 to 15, the COUT signal is counted; when the count is 16 or over, the
MIRR signal is counted.
– 31 –
CXD2548R
$8X commands
Command
Data 1
D23
D22
D21
Data 2
D20
D19
DOUT DOUT
VCO
Mode
CDROM
WSEL
Mute ON/OFF
SEL1
specification
Data 3
D18
D17
D16
D15
D14
D13
D12
0
SOCT
VCO
SEL2
KSL3
KSL2
KSL1
KSL0
See "$BX Commands".
Data 4
D11
D10
D9
D8
0
0
1
0
Command bit
C2PO timing
Processing
CDROM = 1
See Timing
Chart 1-1.
CDROM mode; average value interpolation and pre-value hold
are not performed.
CDROM = 0
See Timing
Chart 1-1.
Audio mode; average value interpolation and pre-value hold
are performed.
Command bit
Processing
DOUT Mute = 1
Digital Out output is muted. (DA output is not muted.)
DOUT Mute = 0
If other mute conditions are not set, Digital Out is not muted.
Command bit
Processing
DOUT ON/OFF = 1
Digital Out is output from the DOUT pin.
DOUT ON/OFF = 0
Digital Out is not output from the DOUT pin.
WSEL = 1
Sync protection window width
±26 channel clock∗1
Anti-rolling is enhanced.
WSEL = 0
±6 channel clock
Sync window protection is enhanced.
Command bit
Application
∗1 In normal-speed playback, channel clock = 4.3218MHz.
– 32 –
CXD2548R
Command bit
Processing
VCOSEL1
KSL3
KSL2
0
0
0
Multiplier PLL VCO1 is set to normal speed, and the output is 1/1
frequency-divided.
0
0
1
Multiplier PLL VCO1 is set to normal speed, and the output is 1/2
frequency-divided.
0
1
0
Multiplier PLL VCO1 is set to normal speed, and the output is 1/4
frequency-divided.
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
Multiplier PLL VCO1 is set to normal speed, and the output is 1/8
frequency-divided.
Multiplier PLL VCO1 is set to high speed∗1, and the output is 1/1
frequency-divided.
Multiplier PLL VCO1 is set to high speed∗1, and the output is 1/2
frequency-divided.
Multiplier PLL VCO1 is set to high speed∗1, and the output is 1/4
frequency-divided.
Multiplier PLL VCO1 is set to high speed∗1, and the output is 1/8
frequency-divided.
∗1 Approximately twice the normal speed
Command bit
Processing
VCOSEL2
KSL1
KSL0
0
0
0
Wide-band PLL VCO2 is set to normal speed, and the output is 1/1
frequency-divided.
0
0
1
Wide-band PLL VCO2 is set to normal speed, and the output is 1/2
frequency-divided.
0
1
0
Wide-band PLL VCO2 is set to normal speed, and the output is 1/4
frequency-divided.
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
Wide-band PLL VCO2 is set to normal speed, and the output is 1/8
frequency-divided.
Wide-band PLL VCO2 is set to high speed∗2, and the output is 1/1
frequency-divided.
Wide-band PLL VCO2 is set to high speed∗2, and the output is 1/2
frequency-divided.
Wide-band PLL VCO2 is set to high speed∗2, and the output is 1/4
frequency-divided.
Wide-band PLL VCO2 is set to high speed∗2, and the output is 1/8
frequency-divided.
∗2 Approximately twice the normal speed
– 33 –
– 34 –
C2PO
CDROM = 1
C2PO
CDROM = 0
WDCK
LRCK
Timing Chart 2-1
C2 Pointer for lower 8bits
Rch C2 Pointer
C2 Pointer for upper 8bits
Rch 16bit C2 Pointer
C2 Pointer for lower 8bits
Lch C2 Pointer
C2 Pointer for upper 8bits
Lch 16bit C2 Pointer
If C2 Pointer = 1,
data is NG
CXD2548R
CXD2548R
∗ Data 3 and subsequent data are DF/DAC function settings.
$9X commands
Data 1
Command
D23
D22
D21
0
DSPB
ON/OFF
0
Function
specification
Data 2
Data 3
D20 D19 to D16 D15
0
0000
0
D14
D13
Data 4
D12
D11
D10
MCSL CKOSL1 CKOSL0 ZDPL ZMUT
Processing
Command bit
DSPB = 1
Double-speed playback (CD-DSP block)
DSPB = 0
Normal-speed playback (CD-DSP block)
Processing
Command bit
MCSL = 1
DF/DAC block master clock selection. Crystal = 768Fs (33.8688MHz).
MCSL = 0
DF/DAC block master clock selection. Crystal = 384Fs (16.9344MHz).
Command bit
Processing
CKOSL1
CKOSL0
0
0
CKOUT pin output is the 1/1 frequency-divided crystal input.
0
1
CKOUT pin output is the 1/2 frequency-divided crystal input.
1
0
CKOUT pin output is the 1/4 frequency-divided crystal input.
1
1
CKOUT pin output is fixed low.
Processing
Command bit
ZDPL = 1
Mute flag (LMUT2 and RMUT1 pins) polarity setting. Muted when high.
ZDPL = 0
Mute flag (LMUT2 and RMUT1 pins) polarity setting. Muted when low.
Processing
Command bit
ZMUT = 1
Zero detection mute on.
ZMUT = 0
Zero detection mute off.
– 35 –
D9
D8
—
—
CXD2548R
∗ Data 2 and subsequent data are DF/DAC function settings.
$AX commands
Command
Data 1
Data 2
D23
D22
D21
D20
D19
D18
0
0
Mute
ATT
0
0
Audio CTRL
Data 4
D17
Data 3
D16
D15
OPSL EMPH SMUT
D14
D13
D12
0
AD9
AD8
Data 5
Data 6
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
FMUT
0
0
0
Processing
Command bit
Mute = 1
Mute on. Zero data is output from DSP.
Mute = 0
Mute off.
Processing
Command bit
ATT = 1
DSP output –12dB
ATT = 0
Attenuation off
Processing
Command bit
OPSL = 1
Set to 1 when changing the FMUT setting.
OPSL = 0
Set to 0 when not changing the FMUT setting.
Processing
Command bit
EMPH = 1
De-emphasis on.
EMPH = 0
De-emphasis off.
∗ If either the EMPHI pin or EMPH are high, de-emphasis is on.
Processing
Command bit
SMUT = 1
Soft mute on.
SMUT = 0
Soft mute off.
∗ If either the SYSM pin or SMUT are high, soft mute is on.
– 36 –
CXD2548R
Processing
Command bit
AD9 to 0
Attenuation data
The attenuation data is 10 bits, and is set as follows.
Attenuation data
Audio output
3FFh
0dB
3FEh
3FEh
:
001h
–0.0085dB
–0.017dB
000h
–∞
–60.198dB
Processing
Command bit
FMUT = 1
Forced mute on.
FMUT = 0
Forced mute off.
∗ FMUT can be set when OPSL is high.
– 37 –
– 38 –
L1
L0
Peak meter
0
0
mode D
PER1
VF1
PER2
PER0
PER1
mode C
SPOA
D1
L2
0
PER2
VF2
PER3
SL0 CPUSR
D2
VF0
PER0
SL1
D3
Data 1
mode B
mode A
SQCK
XLAT
Serial bus
CTRL
Command
$BX commands
L3
WFCK
PER3
VF3
PER4
0
D0
L4
SCOR
PER4
VF4
PER5
L5
GFS
PER5
VF5
PER6
0
0
1
1
1
1
1
1
L6
GTOP
PER6
VF6
1
0
L7
EMPH
PER7
VF7
C1F1
1
0
PER7
0
0
C1F2
R0
FOK
0
ALOCK
SL1
0
0
SOCT
R1
LOCK
C1F1
C1F1
0
1
0
1
0
1
0
1
0
SL0
0
0
C2F2
R2
R3
RFCK XRAOF
C1F2
C1F2
C2F1
C
B
A
SubQ
D
SENS
R4
C1F1
C2F1
C2F1
0
Peak meter
SubQ
mode
R5
C1F2
C2F2
C2F2
FOK
R6
C2F1
0
0
GFS
R7
C2F2
FOK
FOK
LOCK
GFS
GFS
LOCK
LOCK
EMPH ALOCK
EMPH
EMPH
VF0
VF1
VF2
VF3
VF4
VF5
VF6
VF7
The SQSO pin output is switched to the various signals by
setting the SOCT command of $8X and the SL1 and SL0
commands of $BX. Set SQCK to high at the fall of XLAT.
Modes other than Sub Q and peak meter are loaded to the
register when set at the fall of XLAT. Sub Q is loaded to
the register with each SCOR, and peak meter is loaded
during peak detection.
CXD2548R
CXD2548R
Signal
Description
PER0 to 7
RF jitter amount (used to adjust the focus bias). 8-bit binary data in PER0 = LSB, PER7 = MSB.
FOX
Focus OK
GFS
High when the frame sync and the insertion protection timing match.
LOCK
GFS is sampled at 460Hz; when GFS is high, a high signal is output. If GFS is low eight
consecutive samples, a low signal is output.
EMPH
High when the playback disc has emphasis.
ALOCK
GFS is sampled at 460Hz; when GFS is high eight consecutive samples, a high signal is
output. If GFS is low eight consecutive samples, a low signal is output.
VF0 to 7
Used during CAV-W mode. Disc rotational speed measurement results. (See Timing Chart
2-3.) VF0 = LSB, VF7 = MSB.
SPOA
SPOA pin input
WFCK
Write frame clock output
SCOR
High when either subcode sync S0 or S1 is detected.
GTOP
High when the sync protection window is open.
RFCK
Read frame clock output
XRAOF
Low when the built-in 16K RAM exceeds the ±4 frame jitter margin.
L0 to L7,
R0 to R7
Peak meter register output. Lch L0 to 7 and Rch R0 to 7 peak data. L0 and R0 are LSB.
C1F1
C1F2
0
0
1
1
C1 correction status
C2F1
C2F2
No Error
0
0
No Error
0
Single Error Correction
1
0
Single Error Correction
1
Irretrievable Error
1
1
Irretrievable Error
Processing
Command bit
CPUSR = 1
XLON pin is high.
CPUSR = 0
XLON pin is low.
– 39 –
C2 correction status
CXD2548R
Peak Meter
XLAT
SQCK
SQSO
L0
L1
L2
L3
L4
L5
L6
L7
R0
R1
R2
R3
R4
R5
R6
R7
(Peak meter)
Setting the SOCT command of $8X to 0 and the SL1 and SL0 commands of $BX to 0 and 1, respectively,
results in peak detection mode. The SQSO output is connected to the peak register. The maximum PCM data
values (absolute value, upper 8 bits) for Lch and Rch can be read from SQSO by inputting 16 clocks to SQCK.
Peak detection is not performed during SQCK input, and the peak register does not change during readout.
This SQCK input judgment uses a retriggerable monostable multivibrator with a time constant of 270µs to
400µs. The time during which SQCK input is high should be 270 µs or less. Also, peak detection is restarted
270µs to 400µs after SQCK input.
The peak detection register is reset with each readout (16 clocks input to SQCK).
The maximum value during peak detection mode is detected and held in this status until the next readout.
When switching to peak detection mode, readout should be performed one time initially to reset the peak
detection register.
Peak detection can also be performed for previous value hold and average value interpolation data.
– 40 –
CXD2548R
$CX commands
Command
D23
D22
D21
D20
Servo coefficient setting
Gain
MDP1
Gain
MDP0
Gain
MDS1
Gain
MDS0
Gain
CLVS
CLV CTRL ($DX)
• CLV mode gain setting: GCLVS
Gain
MDS1
Gain
MDS0
Gain
CLVS
GCLVS
0
0
0
–12dB
0
0
1
–6dB
0
1
0
–6dB
0
1
1
0dB
1
0
0
0dB
1
0
1
+6dB
• CLVP mode gain setting: GMDP, GMDS
Gain
MDP1
Gain
MDP0
GMDP
Gain
MDS1
Gain
MDS0
GMDS
0
0
–6dB
0
0
–6dB
0
1
0dB
0
1
0dB
1
0
+6dB
1
0
+6dB
– 41 –
CXD2548R
$DX commands
Command
CLV CTRL
Data 1
Data 2
Data 3
D23
D22
D21
D20
D19
D18
D17
D16
D15
D14
D13
D12
DCLV
PWM MD
TB
TP
Gain
CLVS
VP7
VP6
VP5
VP4
VP3
VP2
VP1
VP0
See "$CX Commands".
Command bit
Description
DCLV PWM MD = 1
Digital CLV PWM mode specified. Both MDS and MDP are used.
CLV-W and CAV-W modes can not be used.
DCLV PWM MD = 0
Digital CLV PWM mode specified. Ternary MDP values are output.
CLV-W and CAV-W modes can be used.
Description
Command bit
TB = 0
Bottom hold at a cycle of RFCK/32 in CLVS mode.
TB = 1
Bottom hold at a cycle of RFCK/16 in CLVS mode.
TP = 0
Peak hold at a cycle of RFCK/4 in CLVS mode.
TP = 1
Peak hold at a cycle of RFCK/2 in CLVS mode.
The rotational velocity R of the spindle can be
expressed with the following equation.
Command bit
Description
VP0 to 7 = F0 (H)
Playback at half (normal) speed
:
R=
to
VP0 to 7 = E0 (H)
256 – n
32
R: Relative velocity at normal speed = 1
n: VP0 to 7 setting value
Playback at normal (double) speed
Notes)
1) Values in parentheses are for when DSPB is 1.
2) Values when the crystal is 16.9344MHz and XTSL is low or when the crystal is 33.8688MHz and XTSL is
high.
3) The VP0 to 7 setting values are valid in CAV-W mode.
R – Relative velocity [times]
2
1.5
B=
1
P
DS
1
B=0
DSP
0.5
F0
VP0 to 7 setting value [HEX]
Fig. 2-1.
– 42 –
E0
CXD2548R
$EX commands
Data 1
Command
CLV mode
Data 2
D23
D22
D21
D20
CM3
CM2
CM1
CM0 EPWM SPDC ICAP
Command bit
D19
D18
Data 3
D17
D16
D15
SFSL VC2C
D14
D13
D12
HIFC LPWR VPON
Description
Mode
CM3
CM2
CM1
CM0
0
0
0
0
STOP
Spindle stop mode.∗1
1
0
0
0
KICK
Spindle forward rotation mode.∗1
1
0
1
0
BRAKE
Spindle reverse rotation mode. Valid only when LPWR = 0
in any modes.∗1
1
1
1
0
CLVS
Rough servo mode. When the RF-PLL circuit isn't locked,
this mode is used to pull the disc rotations within the RFPLL capture range.
1
1
1
1
CLVP
PLL servo mode.
0
1
1
0
CLVA
Automatic CLVS/CLVP switching mode.
Used for normal playback.
∗1 See Timing Charts 1-6 to 1-12.
Command bit
EPWM SPDC
ICAP
SFSL
VC2C
HIFC
LPWR VPON
Mode
Description
0
0
0
0
0
0
0
0
CLV-N
Crystal reference CLV servo.
0
0
0
0
1
1
0
0
CLV-W
Used for playback in CLV-W
mode.∗2
0
1
1
0
0
1
0
1
CAV-W
Spindle control with VP0 to 7.
1
0
1
0
0
1
0
1
CAV-W
Spindle control with the external
PWM.
∗2 Figs. 3-1 and 3-2 show the control flow with the microcomputer software in CLV-W mode.
– 43 –
CXD2548R
Data 4
Command
SPD mode
D11
D10
D9
Gain Gain
FCSW
CAV1 CAV0
Gain
CAV1
Gain
CAV0
Gain
0
0
0dB
0
1
–6dB
1
0
–12dB
1
1
–18dB
D8
0
• This sets the gain when controlling the spindle with the phase comparator
in CAV-W mode.
Processing
Command bit
FCSW = 0
The VPCO2 pin is not used and it is Hi-Z.
FCSW = 1
The VPCO2 pin is used and the pin signal is the same as VPCO1.
– 44 –
CXD2548R
Mode
DCLV
PWM MD
0
LPWR
0
CLV-N
1
0
0
CLV-W
0
1
0
CAV-W
0
1
Mode
CLV-N
CLV-W
CAV-W
Command
Timing chart
KICK
2-2 (a)
BRAKE
2-2 (b)
STOP
2-2 (c)
KICK
2-3 (a)
BRAKE
2-3 (b)
STOP
2-3 (c)
KICK
2-4 (a)
BRAKE
2-4 (b)
STOP
2-4 (c)
KICK
2-5 (a)
BRAKE
2-5 (b)
STOP
2-5 (c)
KICK
2-6 (a)
BRAKE
2-6 (b)
STOP
2-6 (c)
KICK
2-7 (a)
BRAKE
2-7 (b)
STOP
2-7 (c)
DCLV
PWM MD
LPWR
Timing chart
0
0
2-8
1
0
2-9
0
2-10
1
2-11
0
2-12 (EPWM = 0)
1
2-13 (EPWM = 0)
0
2-14 (EPWM = 1)
1
2-15 (EPWM = 1)
0
0
Note) CLV-W and CAV-W modes support control only by the ternary output of the MDP pin.
Therefore, set DCLV PWM MD to 0 in CLV-W and CAV-W modes.
– 45 –
CXD2548R
Timing Chart 2-2
CLV-N mode DCLV PWM MD = LPWR = 0
KICK
MDS
MDP
Z
BRAKE
MDS
Z
STOP
MDS
Z
MDP
Z
Z
H
MDP
Z
H
MON
L
H
MON
MON
(a) KICK
L
(b) BRAKE
(c) STOP
BRAKE
STOP
Timing Chart 2-3
CLV-N mode DCLV PWM MD = 1, LPWR = 0
KICK
H
MDS
MDP
H
MDS
MDP
L
H
L
MDP
L
L
H
MON
MDS
H
MON
MON
(b) BRAKE
(a) KICK
L
(c) STOP
Timing Chart 2-4
CLV-W mode (when following the spindle rotational velocity) DCLV PWM MD = LPWR = 0
KICK
Z
MDS
MDP
BRAKE
MDS
Z
MDP
Z
Z
H
MDP
Z
MON
Z
MDS
STOP
H
(a) KICK
L
H
MON
MON
(b) BRAKE
– 46 –
L
(c) STOP
CXD2548R
Timing Chart 2-5
CLV-W mode (when following the spindle rotational velocity) DCLV PWM MD = 0, LPWR = 1
KICK
Z
MDS
MDP
MON
MDS
Z
MDS
Z
MDP
Z
MDP
Z
H
Z
H
STOP
BRAKE
H
MON
(a) KICK
MON
L
(b) BRAKE
(c) STOP
BRAKE
STOP
Timing Chart 2-6
CAV-W mode DCLV PWM MD = LPWR = 0
KICK
MDS
MDP
MON
Z
H
H
MDS
Z
MDP
L
H
MON
(a) KICK
MDS
Z
MDP
Z
MON
(b) BRAKE
H
(c) STOP
Timing Chart 2-7
CAV-W mode DCLV PWM MD = 0, LPWR = 1
KICK
MDS
MDP
MON
Z
BRAKE
MDS
Z
MDS
Z
MDP
Z
MDP
Z
H
H
(a) KICK
STOP
MON
H
MON
(b) BRAKE
– 47 –
H
(c) STOP
CXD2548R
Timing Chart 2-8
CLV-N mode DCLV PWM MD = LPWR = 0
MDS
Z
n · 236 (ns) n = 0 to 31
Acceleration
MDP
Z
132kHz
7.6µs
Deceleration
Timing Chart 2-9
CLV-N mode DCLV PWM MD = 1, LPWR = 0
MDS
Acceleration
Deceleration
MDP
132kHz
n · 236 (ns) n = 0 to 31
7.6µs
Timing Chart 2-10
CLV-W mode DCLV PWM MD = LPWR = 0
Z
MDS
Acceleration
MDP
Z
264kHz
3.8µs
Deceleration
Timing Chart 2-11
CLV-W mode DCLV PWM MD = 0, LPWR = 1
Z
MDS
Acceleration
MDP
Z
264kHz
3.8µs
The BRAKE pulse is masked when LPWR = 1.
– 48 –
CXD2548R
Timing Chart 2-12
CAV-W mode EPWM = DCLV PWM MD = LPWR = 0
Acceleration
MDP
Z
264kHz
3.8µs
Deceleration
Timing Chart 2-13
CAV-W mode EPWM = 1, DCLV PWM MD = 0, LPWR = 1
Acceleration
MDP
Z
264kHz
3.8µs
The BRAKE pulse is masked when LPWR = 1.
Timing Chart 2-14
CAV-W mode EPWM = 1, DCLV PWM MD = LPWR = 0
H
PWMI
L
Acceleration
H
MDP
L
Deceleration
Timing Chart 2-15
CAV-W mode EPWM = 1, DCLV PWM MD = 0, LPWR = 1
H
PWMI
L
Acceleration
H
MDP
Z
The BRAKE pulse is masked when LPWR = 1.
Note) CLV-W and CAV-W modes support control only by the ternary output of the MDP pin. Therefore, set
DCLV PWM MD to 0 in CLV-W and CAV-W modes.
– 49 –
CXD2548R
2-2. Subcode Interface
There are two methods for reading out a subcode externally.
The 8-bit subcodes P to W can be read out from SBSO by inputting EXCK to the CXD2584R.
Sub Q can be read out after checking CRC of the 80 bits in the subcode frame.
Sub Q can be read out from the SQSO pin by inputting 80 clock pulses to the SQCK pin when SCOR comes
correctly and CRCF is high.
P to W Subcode Readout
Data can be read out by inputting EXCK immediately after WFCK falls. (See Timing Chart 2-16.)
80-bit Sub Q Readout
Fig. 2-2 shows the peripheral block of the 80-bit Sub Q register.
• First, Sub Q, regenerated at one bit per frame, is input to the 80-bit serial/parallel register and the CRC check
circuit.
• 96-bit Sub Q is input, and if the CRC is OK, it is output to SQSO with CRCF = 1. In addition, 80 bits are
loaded into the parallel/serial register.
When SQSO goes high 400µs (monostable multivibrator time constant) or more after subcode readout, the
CPU determines that new data (which passed the CRC check) has been loaded.
• When the 80-bit data is loaded, the order of the MSB and LSB is inverted within each byte. As a result,
although the sequence of the bytes is the same, the bits within the bytes are now ordered LSB first.
• Once the 80-bit data load is confirmed, SQCK is input so that the data can be read.
The SQCK input is detected, and the retriggerable monostable multivibrator is reset while the input is low.
• The retriggerable monostable multivibrator has a time constant from 270 to 400µs. When the duration when
SQCK is high is less than this time constant, the monostable multivibrator is kept reset; during this interval,
the serial/parallel register is not loaded into the parallel/serial register.
• While the monostable multivibrator is being reset, data cannot be loaded in the 80-bit parallel/serial register.
In other words, while reading out with a clock cycle shorter than this time constant, the register will not be
rewritten by CRCOK and others.
• See Timing Chart 2-17.
• The high and low intervals for SQCK should be between 750ns and 120µs.
– 50 –
CXD2548R
Timing Chart 2-16
Internal
PLL clock
4.3218 ±∆MHz
WFCK
SCOR
EXCK
400ns max
SBSO
S0 · S1
Q
R
WFCK
SCOR
EXCK
SBSO
S0·S1 Q R S T U V W S0·S1
Same
P1
Q R S T U V W
P1
Same
Sub Code P.Q.R.S.T.U.V.W Read Timing
– 51 –
P2
P3
SUBQ
SI
LD
H G F E D C B A
A B C D E F G H
SIN
Order
Inversion
– 52 –
CRCC
SUBQ
8
LD
(ASEC)
8
(AMIN)
80bit S/P Register
8
80bit S/P Register
Mono/Multi
LD
(AFRAM)
LD
SHIFT
8
8
8
8
LD
Mix
CRCF
8
SHIFT
SQSO
8
ADDRS CTRL
LD
Fig. 2-2 Block Diagram
SQCK
SO
CXD2548R
LD
LD
– 53 –
SQSO
SQCK
CRCF
Mono/multi (Internal)
SQCK
SQSO
SCOR
WFCK
Timing Chart 2-17
CRCF1
1
2
Order
Inversion
ADR1
3
2
1
94
Determined by mode
93
92
91
ADR2
ADR3
CTL0
270 to 400µs when SQCK = high.
Registere load forbidder
80 Clock
750ns to 120µs
300ns max
ADR0
3
95
L
CTL1
96
CTL2
97
CTL3
CRCF2
98
CXD2548R
CXD2548R
Timing Chart 2-18
Measurement interval (approximately 3.8µs)
Reference window
(132.2kHz)
Measurement pulse
(VCK1/2)
Measurement counter
Load
m
VF0 to 7
The relative velocity of the disc can be obtained with the following equation.
R=
m+1
(R: Relative velocity, m: Measurement results)
32
VF0 to 7 is the result obtained by counting VCKI/2 pulses while the reference signal (132.2kHz) generated
from the crystal (384Fs) is high. This count is 31 when the disc is rotating at normal speed and 63 when it is
rotating at double speed (when DSPB is low).
– 54 –
CXD2548R
[3] Description of Other CD Signal Processing and DAC System Functions
3-1. Description of DSP Operating Modes
This LSI has three basic operating modes using a combination of spindle control and the PLL. The operations
for each mode are described below.
(a) CLV-N Mode
This mode is compatible with the CXD2507AQ, and operation is the same as for the conventional control.
The PLL capture range is ±150kHz.
(b) CLV-W Mode
This is the wide capture range mode. This mode allows PLL to follow the rotational velocity of the disc. This
rotational following control has two types: using the built-in VCO2 or providing an external VCO. The spindle
is the same CLV servo as for the conventional series. Operation using the built-in VCO2 is described below.
(When using an external VCO, input the signal from the VPCO1 pin to the low-pass filter, use the output from
the low-pass filter as the control voltage for the external VCO, and input the oscillation from the VCO to the
VCKI pin.) While starting to rotate a disc and/or speeding up to the lock range from the condition that a disc
stops, CAV-W mode should be used. Concretely saying, firstly send $E665 to set CAV-W mode and kick a
disc, secondly send $E60C to set CLV-W mode if ALOCK is high, which can be read out serially from the
SQSO pin. CLV-W mode can be used while ALOCK is high. The microcomputer monitors the serial data
output, and must return the operation to the speed adjusting state (CAV-W mode) when ALOCK becomes
low. The control flow according to the microcomputer software in CLV-W mode is shown in Fig. 3-2.
In CLV-W mode (normal), low power consumption is achieved by setting LPWR to high. Control was formerly
performed by applying acceleration and deceleration pulses to the spindle motor. However, when LPWR is
set to high, deceleration pulses are not output, thereby achieving low power consumption mode.
CLV-W mode supports control only by the ternary output of the MDP pin. Therefore, when using CLV-W
mode, set DCLV PWM MD to low.
Note) The capture range for this mode is theoretically up to the signal processing limit.
(c) CAV-W Mode
This is CAV mode. In this mode the external clock is fixed and it is possible to control spindle to variable
rotational velocity. The rotational velocity is determined by the VP0 to 7 setting values or the external PWM.
When controlling the spindle with VP0 to 7, setting CAV-W mode with $E665 command and controlling VP0
to 7 with the $DX commands allows the rotational velocity to be varied from low speed to double speed. (See
"$DX Commands".) Also, when controlling the spindle with the external PWM, the PWMI pin is binary input
which becomes KICK during high intervals and BRAKE during low intervals.
The microcomputer can know the rotational velocity using V16M. And the reference for the velocity
measurement is a signal of 132.3kHz obtained by 1/128 of the crystal (384 Fs). The velocity is obtained by
counting V16M/2 pulses while the reference is high, and the result is output from the new CPU interface as 8
bits (VP0 to 7). These measurement results are 31 when the disc is rotating at normal speed or 63 when it is
rotating at double speed. These values match those of the 256 - n for control with VP0 to 7.
In CAV-W mode, the spindle is set to the desired rotational velocity and the operation speed for the entire
system follows this rotational velocity. Therefore, the cycles for the Fs system clock, PCM data and all other
output signals from this LSI change according to the rotational velocity of the disc (excluding the servo output
block).
Note) The capture range for this mode is theoretically up to the signal processing limit.
– 55 –
CXD2548R
CAV-W
CLV-W
Operation mode
Rotational velocity
CLVS
CLVP
Spindle mode
Target velocity
KICK
Time
LOCK
ALOCK
Fig. 3-1. Disc Stop to Regular Playback in CLV-W Mode
CLV-W Mode
CLV-W MODE
START
KICK
$E800
Mute OFF $A000
CAV-W $E665
(CLVA)
NO
ALOCK = H ?
YES
CLV-W $E60C
(CLVA)
(WFCK PLL)
YES
ALOCK = L ?
NO
Fig. 3-2. CLV-W Mode Flow Chart
– 56 –
CXD2548R
3-2. Frame Sync Protection
• In normal-speed playback, a frame sync is recorded approximately every 136µs (7.35kHz). This signal is
used as a reference to recognize the data within a frame. Conversely, if the frame sync cannot be
recognized, the data is processed as error data because the data cannot be recognized. As a result,
recognizing the frame sync properly is extremely important for improving playability.
• In the CXD2548R, window protection and forward protection/backward protection have been adopted for
frame sync protection. These functions achieve very powerful frame sync protection. There are two window
widths: one for cases where a rotational disturbance affects the player and the other for cases where there is
no rotational disturbance (WSEL = 0/1). In addition, the forward protection counter is fixed to 13, and the
backward protection counter to 3. Concretely, when the frame sync is being played back normally and then
cannot be detected due to scratches, a maximum of 13 frames are inserted. If frame sync cannot be detected
for 13 frames or more, the window opens to resynchronize the frame sync.
In addition, immediately after the window opens and the resynchronization is executed, if a proper frame
sync cannot be detected within 3 frames, the window opens immediately.
3-3. Error Correction
• In the CD format, one 8-bit data contains two error correction codes, C1 and C2. For C1 correction, the code
is creased with 28-byte information and 4-byte C1 parity.
For C2 correction, the code is created with 24-byte information and 4-byte C2 parity.
Both C1 and C2 are Reed Solomon codes with a minimum distance of 5.
• The CXD2548R's SEC strategy uses powerful frame sync protection and C1 and C2 error correction to
achieve high playability.
• The correction status can be monitored externally.
See Table 3-1.
• When the C2 pointer is high, the data in question was uncorrectable. Either the pre-value was held or an
average value interpolation was made for the data.
MNT3
MNT1
MNT0
Description
0
0
0
No C1 errors
0
0
1
One C1 error corrected
0
1
1
C1 correction impossible
1
0
0
No C2 errors
1
0
1
One C2 error corrected
1
1
1
C2 correction impossible
Table 3-1.
– 57 –
CXD2548R
Timing Chart 3-1
Normal-speed PB
400 to 500ns
RFCK
t = Dependent on error
condition
MNT3
C1 correction
C2 correction
MNT1
MNT0
Strobe
Strobe
3-4. DA Interface
• The CXD2548R's DA interface is as follows.
This interface includes 48 cycles of the bit clock within one LRCK cycle, and is MSB first. When LRCK is
high, the data is for the left channel.
– 58 –
R0
1
2
3
– 59 –
PCMD
WDCK
BCK
(4.23M)
LRCK
(88.2k)
R0
1
2
4
5
Lch MSB (15)
Lch MSB (15)
48bit slot Double-Speed Playback
PCMD
WDCK
BCK
(2.12M)
LRCK
(44.1k)
48bit slot Normal-Speed Playback
Timing Chart 3-2
6
7
8
9
L14
10
L13
11
L12
12
L0
24
L11
L9
Rch MSB
L10
L8
L7
L6
L5
L4
L3
L2
L1
L0
24
RMSB
CXD2548R
CXD2548R
4-5. Digital Out
There are three Digital Out: the type 1 format for broadcasting stations, the type 2 form 1 format for home
use, and the type 2 form 2 format for the manufacture of software.
The CXD2548R supports type 2 form 1.
Sub Q data which are matched twice in succession after a CRC check are input to the first four bits (bits 0 to
3) of the channel status.
Digital Out C bit
0
2
3
From sub Q
0
ID0
16
1
0
4
5
6
7
8
9
10
11
12
13
14
15
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0/1
0
0
ID1 COPY Emph
0
0
0
32
48
0
176
Bits 0 to 3 Sub Q control bits that matched twice with CRCOK
Bit 29
CAV-W: 1 Crystal: 0
Table 3-2.
3-6. Servo Auto Sequence
This function performs a series of controls, including auto focus and track jumps. When the auto sequence
command is received from the CPU, auto focus, 1-track jump, 2N-track jump and N-track move are executed
automatically.
Servo is used in an exclusive manner during the auto sequence execution (when XBUSY = low), so that
commands from the CPU are not transferred to the servo, but can be sent to the CXD2548R.
Connect the CPU and RF as shown in Fig. 3-3.
When CLOK goes from low to high while XBUSY is low, XBUSY does not become high for a maximum of
100µs after that point. This is to prevent the transfer of erroneous data to the servo when XBUSY changes
from low to high by the monostable multivibrator, which is reset by CLOK being low (when XBUSY is low).
– 60 –
CXD2548R
(a) Auto focus ($47)
Focus search-up is performed, FOK and FZC are checked, and the focus servo is turned on.
If $47 is received from the CPU, the focus servo is turned on according to Fig. 3-4. The auto focus starts with
focus search-up, and note that the pickup should be lowered beforehand (focus search down). In addition,
blind E of register 5 is used to eliminate FZC chattering. Concretely, the focus servo is turned on at the falling
edge of FZC after FZC has been continuously high for a longer time than E.
CXD2548R connection diagram when using auto sequence (example)
RF
FOK
FOK
DATA
CXD2548R
CLOK
Micro-computer
XLAT
SENS
Fig. 3-3
Auto focus
Focus search up
FOK=H
NO
YES
(Check whether FZC is continuously high
for the period of time E set with register 5.)
FZC = H
NO
YES
FZC = L
NO
YES
Focus servo ON
END
Fig. 3-4-(a). Auto Focus Flow Chart
– 61 –
CXD2548R
$47latch
XLT
FOK
SENS (FZC)
BUSY
Command for
SSP
Blind E
$08
$03
Fig. 3-4-(b). Auto Focus Timing Chart
(b) Track jump
1, 10 and 2N-track jumps are performed respectively. Always use this when the focus, tracking, and sled
servos are on. Note that tracking gain-up and braking-on should be sent beforehand because they are not
involved in this sequence.
• 1-track jump
When $48 ($49 for REV) is received from the CPU, a FWD (REV) 1-track jump is performed in accordance
with Fig. 3-5. Set blind A and brake B with register 5.
• 10-track jump
When $4A ($4B for REV) is received from the CPU, a FWD (REV) 10-track jump is performed in accordance
with Fig. 3-6. The principal difference from the 1-track jump is to kick the sled. In addition, after kicking the
actuator, when 5 tracks have been counted through COUT, the brake is applied to the actuator. Then, when
the actuator speed is found to have slowed up enough (determined by the COUT cycle becoming longer than
the overflow C set with register 5), the tracking and sled servos are turned on.
• 2N-track jump
When $4C ($4D for REV) is received from the CPU, a FWD (REV) 2N-track jump is performed in accordance
with Fig. 3-7. The track jump count N is set with register 7. Although N can be set to 216 tracks, note that the
setting is actually limited by the actuator. COUT is used for counting the number of jumps.
Although the 2N-track jump basically follows the same sequence as the 10-track jump, the one difference is
that after the tracking servo is turned on, the sled continues to move only for "D", set with register 6.
• N-track move
When $4E ($4F for REV) is received from the CPU, a FWD (REV) N-track move is performed in accordance
with Fig. 3-8. N can be set to 216 tracks. COUT is used for counting the number of jumps. The N-track move is
executed only by moving the sled, and is therefore suited for moving across several thousand to several tenthousand tracks.
– 62 –
CXD2548R
Track
(REV kick for
REV jump)
Track kick
sled servo
WAIT
(Blind A)
COUT =
NO
YES
Track REV
kick
(FWD kick for
REV jump)
WAIT
(Brake B)
Track sled
servo ON
END
Fig. 3-5-(a). 1-Track Jump Flow Chart
$48 (REV = $49) latch
XLT
COUT
BUSY
Brake B
Blind A
Command for
SSP
$28 ($2C)
$2C ($28)
Fig. 3-5-(b). 1-Track Jump Timing Chart
– 63 –
$25
CXD2548R
10 Track
Track, sled
FWD kick
WAIT
(Blind A)
COUT = 5 ?
(Counts COUT × 5)
NO
YES
Track, REV
kick
C = Over-flow ?
NO
(Check whether the COUT cycle
is longer than overflow C.)
YES
Track sled
servo ON
END
Fig. 3-6-(a). 10-Track Jump Flow Chart
$4A (REV = $4B) latch
XLT
COUT
BUSY
Blind A
COUT 5 count
Over-flow C
Command for
SSP
$2E ($2B)
$2A ($2F)
Fig. 3-6-(b). 10-Track Jump Timing Chart
– 64 –
$25
CXD2548R
2N Track
Track, sled
FWD kick
WAIT
(Blind A)
COUT (MIRR) = N
NO
Counts COUT till N < 16.
Counts MIRR till N ≥ 16.
YES
Track REV
kick
C = Over-flow
NO
YES
Track servo
ON
WAIT
(Kick D)
Sled servo
ON
END
Fig. 3-7-(a). 2N-Track Jump Flow Chart
$4C (REV = $4D) latch
XLT
COUT
(MIRR)
BUSY
Blind A
Command for
SSP
$2A ($2F)
COUT (MIRR)
N count
Over-flow C
$2E ($2B)
$26 ($27)
Fig. 3-7-(b). 2N-Track Jump Timing Chart
– 65 –
Kick D
$25
CXD2548R
N Track move
Track servo OFF
Sled FWD kick
WAIT
(Blind A)
COUT (MIRR) = N
NO
Counts COUT till N < 16.
Counts MIRR till N ≥ 16.
YES
Track, sled
servo OFF
END
Fig. 3-8-(a). N-Track Move Flow Chart
$4E (REV = $4F) latch
XLT
COUT
(MIRR)
BUSY
Blind A
Command for
SSP
COUT (MIRR) N count
$20
$22 ($23)
Fig. 3-8-(b). N-Track Move Timing Chart
– 66 –
CXD2548R
3-7. Asymmetry Compensation
Fig. 3-9 shows the block diagram and circuit example.
ASYO
R1
RF
R1
R2
R1
ASYI
R1
BIAS
R1
2
=
R2
5
Fig. 3-9. Asymmetry Compensation Application Circuit
– 67 –
CXD2548R
3-8. Channel Clock Regeneration by the Digital PLL Circuit
• The channel clock is necessary for demodulating the EFM signal regenerated by the optical system.
Assuming T as the channel clock cycle, the EFM signal is modulated in an integer multiple of T from 3T to
11T. In order to read the information in the EFM signal, this integer value must be read correctly. As a
result, T, that is the channel clock, is necessary.
In an actual player, a PLL is necessary to regenerate the channel clock because the fluctuation in the
spindle rotation alters the width of the EFM signal pulses.
The block diagram of this PLL is shown in Fig. 3-10.
The CXD2548R has a built-in three-stage PLL.
• The first-stage PLL is a wide-band PLL. When using the internal VCO2, an external LPF is necessary;
when not using the internal VCO2, external LPF and VCO are necessary.
The output of this first-stage PLL is used as a reference for all clocks within the LSI.
• The second-stage PLL regenerates the high-frequency clock needed by the third-stage digital PLL.
• The third-stage PLL is a digital PLL that regenerates the actual channel clock.
• A new digital PLL has been provided for CLV-W mode to follow the rotational speed of the disc in addition
to the conventional secondary loop.
– 68 –
CXD2548R
Block Diagram 3-10
CLV-W
CAV-W
Spindle rotation information
XTSL
1/2
Microcomputer
control
VPCO1, 2
CLV-W /CLV-N
CAV-W
LPF
1/32
1/n
n = 1 to 256
(VP7 to 0)
1/K
(KSL1, 0)
Phase comparator
1/2
Selector
OSC
CLV-N
VCOSEL2
VCO2
VCTL
V16M
2/1 MUX
VCKI
VPON
1/M
1/N
Phase comparator
X'tal
PCO
FILI
FILO
1/K
(KSL3, 2)
CLTV
VCO1
VCOSEL1
Digital PLL
RFPLL
CXD2548R
– 69 –
CXD2548R
3-9. Digital CLV
Fig. 3-11 shows the block diagram. Digital CLV outputs MDS error and MDP error with PWM, with sampling
frequency increased up to 130Hz during normal-speed playback in CLVS, CLVP and other modes.
In addition, the digital spindle servo gain is variable.
Digital CLV
CLVS U/D
MDS Error
MDP Error
Measure
Measure
Over Sampling
Filter-1
2/1 MUX
CLV P/S
Gain
MDS
Gain
MDP
1/2
MUX
CLV P/S
Over Sampling
Filter-2
Noise Shape
KICK, BRAKE, STOP
Modulation
PWMI
Mode Select
DCLVMD, LPWR
MDS
CLVS U/D:
MDS error:
MDP error:
PWMI:
MDP
Up/down signal from CLVS servo
Frequency error for CLVP servo
Phase error for CLVP servo
Spindle drive signal from the microcomputer
Fig. 3-11. Block Diagram
– 70 –
CXD2548R
3-10. 1-bit DAC Block
(a) DAC block input timing
Timing Chart 3-3 shows the DAC block input timing chart.
Audio data is not transferred from the CD signal processor block to the DAC block inside the CXD2548R.
This is to allow data to be sent to the DAC block via the audio DSP, etc.
When the data is input to the DAC block without using the audio DSP, the data must be connected outside
the LSI. In this case, EMPH, LRCK, BCK and PCMD can be connected directly with EMPHI, LRCKI, BCKI
and PCMDI.
(b) Description of DAC block functions
Zero data detection
When the condition where the lower 4 bits of the input data are DC and the remaining upper bits are all "0"
or all "1" has continued about for 300ms, zero data is detected. Zero data detection is performed
independently for the left and right channels.
Mute flag output
The LMUT and RMUT pins go active when any one of the following conditions is met.
The polarity can be selected with the ZDPL command of $9X.
• When zero data is detected
• When a high signal is input to the SYSM pin
• When the SMUT command of $AX is set
Attenuation operation
Assuming attenuation data X1, X2 and X3 (X1 > X3 > X2), the corresponding audio outputs are Y1, Y2 and
Y3 (Y1 > Y3 > Y2). First, X1 is sent, followed by X2. If X2 is sent before X1 reaches Y1 (A in the figure), X1
continues approaching Y2. Next, if X3 is sent before X1 reaches Y2 (B or C in the figure), X1 then
approaches Y3 from the value (B or C in the figure) at that point.
0dB
3FF (H)
A
Y1
B
Y3
C
Y2
–∞
000 (H)
23.2 [ms]
Soft mute
When any one of the following conditions is met, soft mute results and the input data is attenuated to "0".
• When attenuation data of 000 (high) is set
• When "Soft mute" in the operation controls for serial control is high
• When a high signal (= mute) is input to the input pin SYSM
0dB
–∞
t
23.2 [ms]
23.2 [ms]
– 71 –
1
– 72 –
PCMDI
BCKI
(4.23M)
LRCKI
(88.2k)
R0
1
2
2
3
Lch MSB (15)
Double-Speed Playback
PCMDI R0
BCKI
(2.12M)
LRCKI
(44.1k)
Normal-Speed Playback
Timing Chart 3-3
5
Lch MSB (15)
4
6
7
8
9
L13
11
L12
12
L0
24
L11
Rch MSB
L10
DAC Block Input Timing
L14
10
L9
L8
L7
L6
L5
L4
L3
L2
L1
L0
24
RMSB
CXD2548R
CXD2548R
3-11. LPF Block
The CXD2548R contains an initial-stage secondary active LPF with numerous resistors and capacitors and an
operational amplifier with reference voltage.
The resistors and capacitors are attached externally, allowing the cut-off frequency fc to be determined flexibly.
The reference voltage (VC) is (AVDD – AVSS)/2.
The LPF block application circuit is shown below.
In this circuit, the cut-off frequency is fc ≈ 40kHz.
The capacitance of the external capacitors when fc = 30kHz and 50kHz are noted below as a reference.
• When fc ≈ 30kHz:
C1 = 200pF, C2 = 910pF
• When fc ≈ 50kHz:
C1 = 120pF, C2 = 560pF
LPF Block Application Circuit
12k
AOUT1 (2)
C2
680p
12k
AIN1 (2)
Vc
C1
150p
12k
Analog out
LOUT1 (2)
Fig. 3-12. LPF External Circuit
– 73 –
CXD2548R
3-12. Setting the Playback Speed for the CD-DSP and 1-bit DAC Blocks (in CLV-N mode)
(a) CD-DSP block
In the CXD2548R, the following playback modes can be selected through different combinations of the
crystal, XTSL pin and the DSPB command of $9X.
CD-DSP block playback speed
X'tal
XTSL
DSPB
CD-DSP block playback speed
768Fs
1
0
1×
768Fs
1
1
2×
384Fs
0
0
1×
384Fs
0
1
384Fs
1
1
2×
1 ×∗1
Fs = 44.1kHz.
∗1 Low power consumption mode. The CD-DSP processing speed is halved, allowing power consumption
to be reduced.
(b) 1-bit DAC block
The operation speed for the DAC block is determined by the crystal and the MCSL command of $9X
regardless of the CD-DSP operating conditions noted above. This allows the playback modes for the DAC
and CD-DSP blocks to be set independently.
1-bit DAC block playback speed
X'tal
MCSL
DAC block playback speed
768Fs
1
1×
768Fs
0
2×
384Fs
0
1×
Fs = 44.1kHz.
– 74 –
CXD2548R
[4] Description of Servo Signal Processing System Functions and Commands
§4-1. General Description of the Servo Signal Processing System
(Voltages are the values for a 5V power supply.)
Focus servo
Sampling rate:
88.2kHz
Input range:
2.5V center ±1.0V
Output format:
7-bit PWM
Others:
Offset cancel
Focus bias adjustment
Focus search
Gain-down function
Defect countermeasure
Auto gain control
Tracking servo
Sampling rate:
Input range:
Output format:
Others:
Sled servo
Sampling rate:
Input range:
Output format:
Others:
88.2kHz
2.5V center ±1.0V
7-bit PWM
Offset cancel
E:F balance adjustment
Track jump
Gain-up function
Defect countermeasure
Drive cancel
Auto gain control
Vibration countermeasure
345Hz
2.5V center ±1.0V
7-bit PWM
Sled move
FOK, MIRR, DFCT signals generation
RF signal sampling rate:
1.4MHz
Input range:
2.15V to 5.0V
Others:
RF zero level automatic measurement
The signal input from the RFDC pin is multiplied by a factor of 0.7 and loaded
into the A/D converter.
– 75 –
CXD2548R
§4-2. Digital Servo Block Master Clock (MCK)
The FSTI pin is the reference clock input pin. The internal master clock (MCK) is generated by dividing the
frequency of the signal input to FSTI. The frequency division ratio is 1/2 or 1/4.
Table 4-1 below shows the hypothetical case where the crystal clock generated from the digital signal
processor block is 2/3 frequency-divided and input to the FSTI pin by externally connecting the FSTI pin and
the FSTO pin.
The XT4D and XT2D command settings can be made with D13 and D12 of $3F. (Default = 0)
The digital servo block is designed with an MCK frequency of 5.6448MHz.
Mode
X'tal
FSTO
FSTI
XTSL
XT4D
XT2D
Frequency division ratio
MCK frequency
1
384Fs
256Fs
256Fs
∗
0
1
1/2
128Fs
2
384Fs
256Fs
256Fs
0
0
0
1/2
128Fs
3
768Fs
512Fs
512Fs
∗
1
0
1/4
128Fs
4
768Fs
512Fs
512Fs
1
0
0
1/4
128Fs
Fs = 44.1kHz, ∗: Don't care
Table 4-1.
§4-3. AVRG (Average) Measurement and Compensation
The CXD2548R has a circuit that measures AVRG of RFDC, VC, FE, and TE and a circuit that compensates
them to control servo effectively.
AVRG measurement and compensation is necessary to initialize the CXD2548R, and is able to cancel the
offset by performing each AVRG measurement before playback operation and using these results for
compensation.
The level applied to the VC, FE, RFDC and TE pins can be measured by setting D15 (VLCM), D13 (FLM), D11
(RFLM) and D4 (TCLM) of $38 respectively to 1.
AVRG measurement consists of digitally measuring the level applied to each analog input pin by taking the
average of 256 samples, and then loading these values into the AVRG register.
AVRG measurement requires approximately 2.9ms to 5.8ms after the command is received.
During AVRG measurement, if the upper 8 bits of the serial data are 38 (Hex), the completion of AVRG
measurement operation can be confirmed through the SENS pin. (See Timing Chart 4-1.)
XLAT
2.9 to 5.8ms
SENS
(= XAVEBSY)
Max. 1µs
Completion of AVRG measurement
Timing Chart 4-1.
– 76 –
CXD2548R
<Measurement>
• VC AVRG
The offset can be canceled by measuring the VC level which is the center voltage for the system and using
that value to apply compensation to each input error signal.
• FE AVRG
The FE signal DC level is measured. In addition, compensation is applied to the FZC comparator level output
from the SENS pin during FCS SEARCH (focus search) using these measurement results.
• TE AVRG
The TE signal DC level is measured.
• RE AVRG
The MIRR, DFCT and FOK signals are generated from the RF signal. However, the FOK signal is generated
by comparing the RF signal at a certain level, so that it is necessary to establish a zero level which becomes
the comparator level reference. Therefore, the RF signal is measured before playback operation, and
compensation is applied to bring this level to the zero level.
An example of sending AVRG measurement and compensation commands is shown below.
(Example) $380800 (RF Avrg. measurement on)
$382000 (FE Avrg. measurement on)
$380010 (TE Avrg. measurement on)
$388000 (VC Avrg. measurement on)
(Complete each AVRG measurement before starting the next.)
$38140A (RFLC, FLC0, FLC1 and TLC1 commands on)
(The required compensation should be turn on together; see Fig. 4-2.)
An interval of 5.8ms or more must be maintained between each command, or the SENS pin must be monitored
to confirm that the previous command has been completed before the next AVRG command is sent.
<Compensation>
See Fig. 4-2 for the contents of each compensation below.
• RFLC
The difference by which the RF signal exceeds the RF AVRG value is input to the RF In register.
• TCL0
The value obtained by subtracting the VC AVRG value from the TE signal is input to the TRK In register.
• TCL1
The value obtained by subtracting the TE AVRG value from the TE signal is input to the TRK In register.
• VCLC
The value obtained by subtracting the VC AVRG value from the FE signal is input to the FCS In register.
• FLC1
The value obtained by subtracting the FE AVRG value from the FE signal is input to the FCS In register.
• FLC0
The value obtained by subtracting the FE AVRG value from the FE signal is input to the FZC register.
– 77 –
CXD2548R
§4-4. E:F Balance Adjustment Function
When the disc is rotated with the laser on, and with the FCS (focus) servo on via FCS Search (focus search),
the traverse waveform appears in the TE signal due to disc eccentricity.
In this condition, the low-frequency component can be extracted from the TE signal using the built-in TRK hold
filter by setting D5 (TBLM) of $38 to 1.
The extracted low-frequency component is loaded into the TRVSC register as a digital value, and the TRVSC
register value is established when TBLM returns to 0.
Next, setting D2 (TLC2) of $38 to 1 applies only the amount of compensation (subtraction) equal to the TRVSC
register value to the values obtained from the TE and SE input pins, enabling the E:F balance offset to be
adjusted. (See Fig. 4-2.)
§4-5. FCS Bias (Focus Bias) Adjustment Function
The FBIAS register value can be added to the FCS servo filter input by setting D14 (FBON) of $3A to 1. (See
Fig. 4-2.)
When the FBIAS register value is set to D11 = 0 and D10 = 1 by $34F, data can be written using the 9-bit
value of D9 to D1 (D9: MSB).
In addition, the RF jitter can be monitored by setting the SOCT and SLO commands of $B to 1. (See "DSP
Block Timing Chart".)
The FBIAS register can be used as a counter by setting D13 (FBSS) of $3A to 1. It operates as an up/down
counter. The FBIAS register functions as an up counter when D12 (FBUP) of $3A = 1, and as a down counter
when D12 (FBUP) of $3A = 0.
The number of up and down steps can be changed by setting D11 and D10 (FBV1 and FBV0) of $3A.
When using the FBIAS register as a counter, the counter stops when the value set beforehand in FBL9 to 1 of
$34 matches the FCSBIAS value. Also, if the upper 8 bits of the command register are $3A at this time, the
counter stop can be monitored through SENS.
A
B
Here, the FBIAS setting values FB9 to 1 and the
FBIAS LIMIT values FBL9 to 1 are assumed to
be set in status A. For example, if command
registers FBUP = 0, FBV1 = 0, FBV0 = 0 and
FBSS = 1 are set from this status, down count
starts from status A and approaches the set
LIMIT value. When the LIMIT value is reached
and the FBIAS value matches FBL9 to 1, the
counter stops and the SENS pin goes to high.
Note that the up/down counter changes with
each sampling cycle of the focus servo filter. The
number of steps by which the count value
changes can be selected from 1, 2, 4 or 8 steps
by FBV1 and FBV0. When converted to FE
input, 1 step corresponds to approximately 3.9
[mV].
C
FBIAS setting value
(FB9 to 1)
LIMIT value
(FBL9 to 1)
A:Register mode
B:Counter mode
C:Counter mode (when stopped)
SENS pin
Fig. 4-1.
– 78 –
FE from A/D
VC AVRG
register
TE, SE from A/D
RFDC from A/D
VCLC
TLC0
–
–
FE AVRG
register
TE AVRG
register
RF AVRG
register
– 79 –
–
–
–
Fig. 4-2.
FLC0
FLC1
TLC1
RFLC
–
FBIAS
register
TRVSC
register
FBON
TLC2
+
–
To FZC register
To FCS In register
To TRK/SLD In register
To RF In register
CXD2548R
CXD2548R
§4-6. AGCNTL (Auto Gain Control) Function
The AGCNTL function automatically adjusts the filter internal gain in order to obtain the appropriate gain with
the servo loop. AGCNTL not only copes with the sensitivity variation of the actuator and photo diode, etc., but
also obtains the optimal gain for each disc.
The AGCNTL command is sent when each servo is turned on. During AGCNTL operation, if the upper 8 bits of
the serial data are 38 (Hex), the completion of AGCNTL operation can be confirmed through the SENS pin.
(See Timing Chart 4-2 and "Description of SENS Signals".)
Setting D9 and D8 of $38 to 1 set FCS (focus) and TRK (tracking) respectively to AGCNTL operation.
Note) During AGCNTL operation, each servo filter gain must be normal, and the anti-shock circuit (described
hereafter) must be disabled.
XLAT
Max. 11.4µs
SENS
(= AGOK)
AGCNTL completion
Timing Chart 4-2.
Coefficient K13 changes for AGF (focus AGCNTL) and coefficients K23 and K07 change for AGT (tracking
AGCNTL) due to AGCNTL.
These coefficients change from 01 to 7F (Hex), and they must also be set within this range when written
externally.
After AGCNTL operation has completed, these coefficient values can be confirmed by reading them out from
the SENS pin with the serial readout function (described hereafter).
AGCNTL related setting
The following settings can be changed with $35, $36 and $37.
FG6 to FG0; AGF convergence gain setting, effective setting range: 00 to 57 (Hex)
TG6 to TG0; AGT convergence gain setting, effective setting range: 00 to 57 (Hex)
AGS;
Self-stop on/off
AGJ;
Convergence completion judgment time
AGGF;
Internally generated sine wave amplitude (AGF)
AGGT;
Internally generated sine wave amplitude (AGT)
AGV1;
AGCNTL sensitivity 1 (during high sensitivity adjustment)
AGV2;
AGCNTL sensitivity 2 (during low sensitivity adjustment)
AGHS;
High sensitivity adjustment on/off
AGHT;
High sensitivity adjustment time
Note) Converging servo loop gain values can be changed with the FG6 to 0 and TG6 to 0 setting values. In
addition, these setting values must be within the effective setting range. The default settings aim for 0
dB at 1kHz. However, since convergence values vary according to the characteristics of each
constituent element of the servo loop, FG and TG values should be set as necessary.
– 80 –
CXD2548R
AGCNTL and default operation have two stages.
In the first stage, high sensitivity adjustment is performed for a certain period of time (select 256/128ms with
AGHT), and the AGCNTL coefficient approaches the appropriate value roughly. The sensitivity at this time can
be selected from two types with AGV1.
In the second stage, the AGCNTL coefficient approaches the appropriate value finely with relatively low
sensitivity. The sensitivity for the second stage can be selected from two types with AGV2. In the second stage
of default operation, when the AGCNTL coefficient reaches the appropriate value and stops changing, the
CXD2548R confirms that the AGCNTL coefficient has not changed for a certain period of time (select 63/31ms
with AGHJ), and then completes AGCNTL operation. (Self-stop mode)
This self-stop mode can be canceled by setting AGS to 0.
In addition, the first stage is omitted for AGCNTL operation when AGHS is set to 0.
An example of AGCNTL coefficient transitions during AGCNTL operation and the relationship between the
various settings are shown in Fig. 4-3.
Initial value
Slope AGV1
AGCNTL
coefficient value
Slope AGV2
Convergence value
AGHT
AGJ
AGCNTL
Start
AGCNTL
completion
SENS
Fig. 4-3.
– 81 –
CXD2548R
§4-7. FCS Servo and FCS Search (Focus Search)
The FCS servo is controlled by the 8-bit serial command $0X. (See Table 4-2.)
Register name Command D23 to D20 D19 to D16
FOCUS
CONTROL
0
0 0 0 0
1 0 ∗ ∗
FOCUS SERVO ON (FOCUS GAIN NORMAL)
1 1 ∗ ∗
FOCUS SERVO ON (FOCUS GAIN DOWN)
0 ∗ 0 ∗
FOCUS SERVO OFF, 0V OUT
0 ∗ 1 ∗
FOCUS SERVO OFF, FOCUS SEARCH VOLTAGE OUT
0 ∗ 1 0
FOCUS SEARCH VOLTAGE DOWN
0 ∗ 1 1
FOCUS SEARCH VOLTAGE UP
∗: Don't care
Table 4-2.
FCS Search
FCS search is required in the course of turning on the FCS servo.
Fig. 4-4 shows the signals for sending commands $00 → $02 → $03 and performing only FCS search.
Fig. 4-5 shows the signals for sending $08 (FCS on) after that.
$00 $02 $03
$00 $02 $03
0
FCSDRV
FCSDRV
RF
RF
FOK
FOK
FZC comparator level
FE
FE
0
FZC
0
FZC
Fig. 4-4.
Fig. 4-5.
– 82 –
$08
CXD2548R
§4-8. TRK (Tracking) and SLD (Sled) Servo Control
TRK and SLD servo is controlled by the 8-bit command $2X. (See Table 4-3.)
When the upper 4 bits of the serial data are 2 (Hex), TZG is output from the SENS pin.
Register name Command D23 to D20 D19 to D16
2
TRACKING
MODE
0 0 1 0
0 0 ∗ ∗
TRACKING SERVO OFF
0 1 ∗ ∗
TRACKING SERVO ON
1 0 ∗ ∗
FORWARD TRACK JUMP
1 1 ∗ ∗
REVERSE TRACK JUMP
∗ ∗ 0 0
SLED SERVO OFF
∗ ∗ 0 1
SLED SERVO ON
∗ ∗ 1 0
FORWARD SLED MOVE
∗ ∗ 1 1
REVERSE SLED MOVE
∗: Don't care
Table 4-3.
TRK Servo
The TRK JUMP (track jump) height can be set with 6 bits (D13 to D8) of $36.
In addition, when the TRK servo is on and D17 of $1 is set to 1, the TRK servo filter assumes gain-up status.
The filter also assumes gain-up status when vibration detection is performed with the LOCK signal low and the
anti-shock circuit (described hereafter) enabled.
The gain-up filter used when TRK has assumed gain-up status has two types of structures which can be
selected by setting D16 of $1. (See Table 4-5.)
SLD Servo
The SLD MOV (sled move) output, composed of a basic value from 6 bits (D13 to D8) of $37, is determined by
multiplying this value by 1 ×, 2 ×, 3 ×, or 4 × magnification set using D17 and D16 when D19 = D18 = 0 is set
with $3. (See Table 4-4.)
SLD MOV must be performed continuously for 50µs or more. In addition, if the LOCK input signal goes low
when the SLD servo is on, the SLD servo turns off.
Note) When the LOCK signal is low, the TRK servo is set to gain-up status and the SLD servo is turned off by
the default. These operations are disabled by setting D6 (LKSW) of $38 to 1.
Register name Command D23 to D20 D19 to D16
3
SELECT
0 0 1 1
0 0 0 0
SLED KICK LEVEL (basic value × ±1)
0 0 0 1
SLED KICK LEVEL (basic value × ±2)
0 0 1 0
SLED KICK LEVEL (basic value × ±3)
0 0 1 1
SLED KICK LEVEL (basic value × ±4)
Table 4-4.
– 83 –
CXD2548R
§4-9. MIRR and DFCT Signal Generation
The RF signal obtained from the RFDC pin is sampled at approximately 1.4MHz and loaded. The MIRR and
DFCT signals are generated from this RF signal.
MIRR Signal Generation
The loaded RF signal is applied to peak hold and bottom hold circuits.
An envelope is generated from the waveforms generated in these circuits, and the MIRR comparator level is
generated from the average of these envelope waveforms.
The MIRR signal is generated by comparing this MIRR comparator level with the waveform generated by
subtracting the bottom hold value from the peak hold value. (See Fig. 4-6.)
RF
Peak Hold
Bottom Hold
Peak Hold
–Bottom Hold
MIRR Comp
(Mirror comparator level)
H
MIRR
L
Fig. 4-6.
DFCT Signal Generation
The loaded RF signal is input to two peak hold circuits with different time constants, and the DFCT signal is
generated by comparing the difference between these two peak hold waveforms with the DFCT comparator
level. (See Fig. 4-7.)
The DFCT comparator level can be selected from four values using D13 and D12 of $3B.
RF
Peak Hold1
Peak Hold2
Peak Hold2
–Peak Hold1
SDF
(Defect
comparator level)
H
DFCT
L
Fig. 4-7.
– 84 –
CXD2548R
§4-10. DFCT Countermeasure Circuit
The DFCT countermeasure circuit performs operations to maintain the directionality of the servo so that the
servo does not become easily dislocated due to scratches or defects on discs.
Specifically, these operations are achieved by performing scratch and defect detection with the DFCT signal
generation circuit, and when DFCT goes high, applying the low frequency component of the error signal before
DFCT went high to the FCS and TRK servo filter inputs. (See Fig. 4-8.)
In addition, these operations are activated by the default. They can be disabled by setting D7 (DFSW) of $38
to 1.
Hold Filter
Error signal
Input register
Hold register
EN
DFCT
Servo Filter
Fig. 4-8.
§4-11. Anti-Shock Circuit
When vibrations are produced in the CD player, this circuit forces the TRK filter to assume gain-up status so
that the servo does not become easily dislocated. This circuit is for systems which require vibration
countermeasures.
Concretely, vibrations are detected using an internal anti-shock filter and comparator circuit, and the gain is
increased. (See Fig. 4-9.)
The comparator level is fixed to 1/16 of the maximum comparator input amplitude. However, the comparator
level is practically variable by adjusting the anti-shock filter output coefficient K35.
This function can be turned on and off by D19 of $1 when the brake circuit (described hereafter) is off. (See
Table 4-5.)
This circuit can also support an external vibration detection circuit, and can set the TRK servo filter to gain-up
status by inputting high level to the ATSK pin.
When the serial data is $1, vibration detection can be monitored from the SENS pin.
ATSK
TE
Anti Shock
Filter
SENS
Comparator
TRK Gain Up
Filter
TRK
PWM Gen
TRK Gain Normal
Filter
Fig. 4-9.
– 85 –
CXD2548R
§4-12. Brake Circuit
Immediately after a long distance track jump it tends to be hard for the actuator to settle and for the servo to
turn on.
The brake circuit prevents these phenomenon.
In principle, this circuit cuts unnecessary portions of the tracking drive and applies the brake by utilizing the
180° offset in the RF envelope and tracking error phase relationship which occurs when the actuator traverses
the track in the radial direction from the inner track to the outer track and vice versa. (See Figs. 4-10 and 4-11.)
Concretely, this operation is achieved by masking the tracking drive using the TRKCNCL signal generated by
loading the MIRR signal at the edge of the TZC (Tracking Zero Cross) signal.
The brake circuit can be turned on and off by D18 of $1. (See Fig. 4-5.)
Inner track → Outer track
Outer track → Inner track
FWD REV Servo ON
JMP JMP
REV FWD Servo ON
JMP JMP
TRK
DRV
TRK
DRV
RF
Trace
RF
Trace
MIRR
MIRR
TE
0
TE
TZC
Edge
TZC
Edge
TRKCNCL
TRKCNCL
TRK
DRV
TRK
DRV
0
SENS
TZC out
0
0
SENS
TZC out
Fig. 4-10.
Fig. 4-11.
Register name Command D23 to D20 D19 to D16
1
TRACKING
CONTROL
0 0 0 1
1 0 ∗ ∗
ANTI SHOCK ON
0 ∗ ∗ ∗
ANTI SHOCK OFF
∗ 1 ∗ ∗
BRAKE ON
∗ 0 ∗ ∗
BRAKE OFF
∗ ∗ 0 ∗
TRACKING GAIN NORMAL
∗ ∗ 1 ∗
TRACKING GAIN UP
∗ ∗ ∗ 1
TRACKING GAIN UP FILTER SELECT 1
∗ ∗ ∗ 0
TRACKING GAIN UP FILTER SELECT 2
∗: Don't care
Fig. 4-5.
– 86 –
CXD2548R
§4-13. COUT Signal
The COUT signal is output to count the number of tracks during traverse, etc. It is basically generated by
loading the MIRR signal at both edges of the TZC signal. However, the used TZC signal can be selected and
there are two types of output methods according to the COUT signal application.
For 1-track jumps, etc.
Fast phase COUT signal generation with a fast phase TZC signal.
For High-speed traverse
Reliable COUT signal generation with a delayed phase TZC signal.
This is because some time is required to generate the MIRR signal, and it is necessary to delay the TZC signal
in accordance with the MIRR signal delay during high-speed traverse.
The COUT signal output method is switched with D16 when D19 = D18 = 1 and D17 = 0 are set with $3.
(When D16 = 1, for delayed phase and high-speed traverse.) In addition, the TZC signal delay can be selected
from two values with D14 of $36.
§4-14. Serial Readout Circuit
The following measurement and adjustment results can be read out from the SENS pin by inputting the
readout clock to the SCLK pin by $39. (See Fig. 4-12, Table 4-6 and "Description of SENS Signals".)
Specified commands
$390C VC AVRG measurement result
$3908 FE AVRG measurement result
$3904 TE AVRG measurement result
$391F RF AVRG measurement result
$3953 FCS AGCNTL coefficient result
$3963 TRK AGCNTL coefficient result
$391C TRVSC adjustment result
$391D FBIAS register value
XLAT
tSPW
tDLS
SCLK
···
1/fSCLK
Serial Read Out Data
(SENS)
MSB
LSB
···
Fig. 4-12.
Item
Symbol
SCLK frequency
fSCLK
SCLK pulse width
tSPW
tDLS
Delay time
Min.
Typ.
Max.
Unit
1
MHz
500
ns
15
µs
Table 4-6.
During readout, the upper 8 bits of the serial data must be 39 (Hex).
– 87 –
CXD2548R
§4-15. Writing the Coefficient RAM
The coefficient RAM can be rewritten by $34. All coefficients have default values in the built-in ROM, and
transfer from the ROM to the RAM is completed approximately 40µs after the XRST pin rises. (The coefficient
RAM cannot be rewritten during this period.)
After that, the characteristics of each built-in filter can be finely adjusted by rewriting the data for each address
of the coefficient RAM.
The coefficient rewrite command is comprised of 24 bits, with D14 to D8 of $34 as the address (D15 = 0) and
D7 to D0 as data.
§4-16. PWM Output
FCS, TRK and SLD outputs are output as PWM waveforms.
In particular, FCS and TRK permit accurate drive by using a double oversampling noise shaper.
Timing Chart 4-3 and Fig. 4-13 show examples of output waveforms and drive circuits.
MCK
(5.6448MHz) ↑ ↑ ↑ ↑ ↑ ↑ ↑
Output value +A
Output value –A
Output value 0
64tMCK
64tMCK
64tMCK
SLD
SFDR
AtMCK
SRDR
AtMCK
FCS/TRK
32tMCK
FFDR/
TFDR
A tMCK
2
FRDR/
TRDR
tMCK =
32tMCK
32tMCK
A tMCK
2
A tMCK
2
1
≈ 180ns
5.6448MHz
32tMCK
A tMCK
2
Timing Chart 4-3.
– 88 –
32tMCK
32tMCK
CXD2548R
Example of Drive Circuit
VCC
22k
22k
DRV
RDR
FDR
22k
22k
VEE
Fig. 4-13. Operational Amplifier Drive Circuit
– 89 –
CXD2548R
§4-17. Servo Status Changes Produced by the LOCK Signal
When the LOCK signal becomes low, the TRK servo assumes the gain-up status and the SLD servo turns off
in order to prevent SLD free-running.
Setting D6 (LKSW) of $38 to 1 deactivates this function.
In other words, neither the TRK servo nor the SLD servo change even when the LOCK signal becomes low.
This enables microcomputer control.
§4-18. Description of Commands and Data Sets
The following description contains portions which convert internal voltages into the values when they are
output externally and describe them as input conversion or output conversion.
Input conversion converts these voltages into the voltages entering input pins before A/D conversion.
Output conversion converts PWM output values into analog voltage values.
Both types of conversion are calculated at VDD = 5.0V. If this voltage changes, the conversion values also
change proportionally. (Voltage conversion = VDDX/5; VDDX: used supply voltage)
– 90 –
CXD2548R
$34
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
0
KA6
KA5
KA4
KA3
KA2
KA1
KA0
KD7
KD6
KD5
KD4
KD3
KD2
KD1
KD0
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
When D15 = 0
KA6 to KA0: Coefficient address
KD7 to KD0: Coefficient data
D15
D14
D13
D12
D11
D10
1
1
1
1
1
0
FBL9 FBL8 FBL7 FBL6 FBL5 FBL4 FBL3 FBL2 FBL1
—
When D15 = D14 = D13 = D12 = D11 = 1 ($34F)
D10 = 0
FBIAS LIMIT register write
FBL9 to FBL1: Data; data compared with FB9 to 1, FBL9 = MSB.
When using the FBIAS register in counter mode, counter operation stops when the
value of FB9 to 1 matches with FBL9 to 1.
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
1
1
1
1
0
1
FB9
FB8
FB7
FB6
FB5
FB4
FB3
FB2
FB1
—
When D15 = D14 = D13 = D12 = 1. ($34F)
D11 = 0, D10 = 1
FBIAS register write
FB9 to FB1: Data; FB9 is MSB two's complement data.
For FE input conversion, FB9 to FB1 = 011111111 corresponds to approximately +1V
and FB9 to FB1 = 100000000 to –1V respectively. (when the supply voltage = 5V)
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
1
1
1
1
0
0
TV9
TV8
TV7
TV6
TV5
TV4
TV3
TV2
TV1
TV0
When D15 = D14 = D13 = D12 = 1. ($34F)
D11 = 0, D10 = 0
TRVSC register write
TV9 to TV0: Data; TV9 is MSB two's complement data.
For TE input conversion, TV9 to TV0 = 0011111111 corresponds to approximately +1V
and TV9 to TV0 = 1100000000 to –1V respectively. (when the supply voltage = 5V)
Note) • When the TRVSC register is read out, the data length is 9 bits. At this time, data corresponding to
each bit of TV8 to TV0 during external write are read out.
• When reading out internally measured values and then writing these values externally, set TV9 the
same as TV8.
– 91 –
CXD2548R
$35
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
FT1
FT0
FS5
FS4
FS3
FS2
FS1
FS0
FTZ
FG6
FG5
FG4
FG3
FG2
FG1
FG0
D5
D4
D3
D2
D1
D0
TG5
TG4
TG3
TG2
TG1
TG0
FT1, FT0, FTZ: Focus search-up speed
Default value: 010 (3.36V/s)
Focus drive output conversion
FT1
FT0
FTZ
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
0
0
0
1
1
1
1
Focus search speed
6.73V/s
3.36
2.24
1.68
8.97
5.38
4.49
3.85
FS5 to FS0:
Focus search limit voltage
Default value: 011000 (±1.875V)
Focus drive output conversion
FG6 to FG0: AGF convergence gain setting value
Default value: 0101101
$36
D15
0
D14
D13
D12
D11
D10
D9
D8
D7
DTZC TJ5
TJ4
TJ3
TJ2
TJ1
TJ0 SFJP TG6
DTZC:
D6
DTZC delay (8.5/4.25µs)
Default value: 0 (4.25µs)
TJ5 to TJ0:
Track jump voltage
Default value: 001110 (≈ ±1.09V)
Tracking drive output conversion
SFJP:
Surf jump mode on/off
TRK PWM output is made by adding the tracking filter output and TJReg (TJ5 to 0), by setting
D7 to 1 (on).
TG6 to TG0: AGT convergence gain setting value
Default value: 0101110
– 92 –
CXD2548R
$37
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
FZSH FZSL SM5 SM4 SM3 SM2 SM1 SM0 AGS AGJ AGGF AGGT AGV1 AGV2 AGHS AGHT
FZSH, FZSL: FZC (Focus Zero Cross) slice level
Default value: 01 (±250mV); FE input conversion
FZSH
FZSL
0
0
1
1
0
1
0
1
Slice level
+500mV
+250
+125
+62.5
SM5 to SM0: Sled move voltage
Default value: 010000 (≈ ±1.25V)
Sled drive output conversion
AGS:
AGCNTL self-stop on/off
Default value: 1 (on)
AGJ:
AGCNTL convergence completion judgment time during low sensitivity adjustment (31/63ms)
Default value: 0 (63ms)
AGGF:
Focus AGCNTL internally generated sine wave amplitude (small/large)
Default value: 1 (large)
AGGT:
Tracking AGCNTL internally generated sine wave amplitude (small/large)
Default value: 1 (large)
FE/TE input conversion
AGV1:
AGV2:
AGHS:
AGHT:
AGGF
0 (small)
1 (large)
63mV
125
AGGT
0 (small)
1 (large)
125mV
250
AGCNTL convergence sensitivity during high sensitivity adjustment; high/low
Default value: 1 (high)
AGCNTL convergence sensitivity during low sensitivity adjustment; high/low
Default value: 0 (low)
AGCNTL high sensitivity adjustment on/off
Default value: 1 (on)
AGCNTL high sensitivity adjustment time (128/256ms)
Default value: 0 (256ms)
– 93 –
CXD2548R
$38
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
VCLM VCLC FLM FLC0 RFLM RFLC AGF AGT DFSW LKSW TBLM TCLM FLC1 TLC2 TLC1 TLC0
∗ VCLM:
VCLC:
∗ FLM:
FLC0:
∗ RFLM:
RFLC:
AGF:
AGT:
DFSW:
LKSW:
TBLM:
∗ TCLM:
FLC1:
TLC2:
TLC1:
TLC0:
VC level measurement (on/off)
VC level compensation for FCS In register (on/off)
Focus zero level measurement (on/off)
Focus zero level compensation for FZC register (on/off)
RF zero level measurement (on/off)
RF zero level compensation (on/off)
Focus auto gain adjustment (on/off)
Tracking auto gain adjustment (on/off)
Defect disable switch (on/off)
Setting this switch to 1 (on) disables the defect countermeasure circuit.
Lock switch (on/off)
Setting this switch to 1 disables the sled free-running prevention circuit.
Traverse center measurement (on/off)
Tracking zero level measurement (on/off)
Focus zero level compensation for FCS In register (on/off)
Traverse center compensation (on/off)
Tracking zero level compensation (on/off)
VC level compensation for TRK/SLD In register (on/off)
Note) Commands marked with ∗ are accepted every 2.9ms.
All commands are on when set to 1.
– 94 –
CXD2548R
$39
D15
D14
D13
D12
D11
D10
D9
D8
DAC SD6
SD5
SD4
SD3
SD2
SD1
SD0
DAC:
Serial data readout DAC mode (on/off)
SD6 to SD0: Serial readout data select
SD6
1
0
SD5
Readout data
Coefficient RAM data for address = SD5 to SD0
1
Data RAM data for address = SD4 to SD0
SD4
0
Readout data length
8 bit
16 bit
SD3 to SD0
1
1
1
1
1
0
0
1
1
1
1
0
0
1
1
0
0
1
1
1
0
1
0
1
0
RF AVRG register
RFDC input signal
FBIAS register
TRVSC register
RFDC envelope (bottom)
RFDC envelope (peak)
8 bit
8 bit
9 bit
9 bit
8 bit
8 bit
0
1
1
0
0
0
0
0
1
0
1
0
0
0
0
∗
∗
∗
1
1
0
0
∗
∗
∗
1
0
1
0
VC AVRG register
FE AVRG register
TE AVRG register
FE input signal
TE input signal
SE input signal
VC input signal
9 bit
9 bit
9 bit
8 bit
8 bit
8 bit
8 bit
0
Note) Coefficients K40 to K4F cannot be read out.
See the description for SRO1 of $3F concerning readout methods for the above data.
– 95 –
∗: Don't care
CXD2548R
$3A
D15
0
D14
D13
D12
D11
D10
FBON FBSS FBUP FBV1 FBV0
D9
0
D8
D7
D6
D5
D4
D3
D2
D1
D0
TJD0 FPS1 FPS0 TPS1 TPS0 CEIT SJHD INBK MTI0
FBON:
FBIAS (focus bias) register addition (on/off)
The FBIAS register value is added to the signal loaded into the FCS In register by setting D14 to
1 (on).
FBSS:
FBIAS (focus bias) register/counter switching
The FCS BIAS register can be used as a counter by setting D13 to 1 (on).
FBUP:
FBIAS (focus bias) counter up/down operation switching
This performs counter up/down control when FBSS = 1. The FBIAS register functions as a down
counter with D12 set to 0, and as an up counter when set to 1.
FBV1, FBV0: FBIAS (focus bias) counter voltage switching
FCS BIAS count-up steps is decided by these bits.
FBV1
FBV0
Number of steps
0
0
1
0
1
2
1
0
4
1
1
8
The counter changes once for each
sampling cycle of the focus servo filter.
When MCK is 128Fs, the sampling
frequency is 88.2kHz. When converted to
FE input, 1 step is approximately 3.9 [mV].
TJD0:
This sets the tracking servo filter data RAM to 0 when switched from track jump to servo on only
when SFJP = 1 (during surf jump operation).
FPS1, FPS0: Gain setting when transferring data from the focus filter to the PWM block.
TPS1, TPS0: Gain setting when transferring data from the tracking filter to the PWM block.
This is effective for increasing the overall gain in order to widen the servo band.
Operation when FPS1, FPS0 (TPS1, TPS0) = 00 is the same as usual (7-bit shift). However,
6dB, 12dB and 18dB can be selected independently for focus (tracking) by setting the relative
gain to 0dB when FPS1, FPS0 (TPS1, TPS0) = 00.
CEIT:
SJHD:
INBK:
MT10:
FPS1
FPS0
0
0
0
Relative gain
TPS1
TPS0
Relative gain
0dB
0
0
0dB
1
+6dB
0
1
+6dB
1
0
+12dB
1
0
+12dB
1
1
+18dB
1
1
+18dB
The CE pin input takes over the TE pin input by setting D3 to 1 (on). This means that the
registers and filters for TE input are used for CE input.
This holds the tracking filter output at the value when surf jump starts during surf jump.
When D2 is 0 (off), the brake circuit masks the tracking filter output signal with TRKCNCL which
is generated by taking the MIRR signal at the TZC edge. When D2 is set to 1 (on), the tracking
filter input is masked instead of the output.
The tracking filter input is masked when the MIRR signal is high by setting D1 to 1 (on).
– 96 –
CXD2548R
$3B
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
SFO2 SFO1 SDF2 SDF1 MAX2 MAX1 SFOX BTF D2V2 D2V1 D1V2 D1V1 RINT
SFOX, SFO2, SFO1: FOK slice level
Default value: 011 (313mV)
RFDC input conversion
SFOX
SFO2
SFO1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Slice level
179mV
223
268
313
357
446
536
625
– 97 –
D2
D1
D0
0
0
0
CXD2548R
SDF2, SDF1: DFCT slice level
Default value: 10 (179mV)
RFDC input conversion
SDF2
SDF1
0
0
1
1
0
1
0
1
Slice level
89mV
134
179
224
MAX2, MAX1: DFCT maximum time
Default value: 00 (no timer limit)
MAX2
MAX1
0
0
1
1
0
1
0
1
DFCT maximum time
No timer limit
2.00ms
2.36
2.72
BTF:
Bottom hold double-speed count-up mode for MIRR signal generation
On/off (default: off)
On when set to 1.
D2V2, D2V1: Peak hold 2 for DFCT signal generation
Count-down speed setting
Default value: 01 (0.492V/ms, 44.1kHz)
[V/ms] unit items indicate RFDC input conversion; [kHz] unit items indicate the
operating frequency of the internal counter.
D2V2
0
0
1
1
D2V1
0
1
0
1
Count-down speed
[V/ms]
[kHz]
0.246
0.492
0.984
1.969
22.05
44.1
88.2
176.4
D1V2, D1V1: Peak hold 1 for DFCT signal generation
Count-down speed setting
Default value: 01 (3.938V/ms, 352.8kHz)
[V/ms] unit items indicate RFDC input conversion; [kHz] unit items indicate the
operating frequency of the internal counter.
D1V2
0
0
1
1
RINT:
D1V1
0
1
0
1
Count-down speed
[V/ms]
[kHz]
1.969
3.938
7.875
15.75
176.4
352.8
705.6
1411.2
This initializes the initial-stage registers of the circuits which generate MIRR, DFCT and FOK.
– 98 –
CXD2548R
$3E
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
F1NM F1DM F3NM F3DM T1NM T1UM T3NM T3UM DFIS TLCD RFLP
D4
D3
D2
0
0
0
D1
D0
MIRI XT1D
F1NM, F1DM: Quasi double accuracy setting for FCS servo filter first-stage
On when set to 1; default = 0.
F1NM: Gain normal
F1DM: Gain down
T1NM, T1UM: Quasi double accuracy setting for TRK servo filter first-stage
On when set to 1; default = 0.
T1NM: Gain normal
T1UM: Gain up
F3NM, F3DM: Quasi double accuracy setting for FCS servo filter third-stage
On when set to 1; default = 0.
Generally, the advance amount of the phase becomes large by partially setting the FCS servo
third-stage filter which is used as the phase compensation filter to double accuracy.
F3NM: Gain normal
F3DM: Gain down
T3NM, T3UM: Quasi double accuracy setting for TRK servo filter third-stage
On when set to 1; default = 0.
Generally, the advance amount of the phase becomes large by partially setting the TRK servo
third-stage filter which is used as the phase compensation filter to double accuracy.
T3NM: Gain normal
T3UM: Gain up
Note) Filter first- and third-stage quasi double accuracy settings can be set individually.
See "FILTER Composition" at the end of this specification concerning quasi double-accuracy.
DFIS:
TLCD:
RFLP:
MIRI:
XT1D:
FCS hold filter input extraction node selection
0: M05 (Data RAM address 05); default
1: M04 (data RAM address 04)
This command masks the TLC2 command set by D2 of $38 only when FOK is low.
On when set to 1; default = 0
This command passes the signal obtained from the RFDC pin through the LPF (low-pass filter)
before the built-in A/D converter.
0: LPF off; default
1: LPF on
MIRR input switching.
The MIRR signal can be input from an external source. When D1 is 0, the MIRR signal is used
internally as usual. When D1 = 1, the MIRR signal can be input from an external source
through the MIRR pin.
The clock input from FSTI can be used as the master clock for the servo block regardless of the
XTSL pin, XT2D and XT4D by setting D0 to 1.
– 99 –
CXD2548R
$3F
D15
0
D14
D13
D12
AGG4 XT4D XT2D
AGG4:
XT4D, XT2D:
D11
D10
0
D9
D8
DRR2 DRR1 DRR0
D7
D6
D5
0
ASFG
0
D4
D3
D2
D1
D0
LPAS SRO1 SRO0 AGHF COT2
This varies the amplitude of the internally generated sine wave using the AGGF and AGGT
commands during AGC.
When AGG4 = 0, the default is used. When AGG4 = 1, the setting is as shown in the table below.
AGGF (MSB)
AGGT (LSB)
TE/FE input conversion
0
0
31 [mV]
0
1
63 [mV]
1
0
125 [mV]
1
1
250 [mV]
These settings are the same as
for both focus auto gain control
and tracking auto gain control.
MCK (digital servo master clock) frequency division setting
This command forcibly sets the frequency division ratio to 1/2 or 1/4 when MCK is generated
from the signal input to the FSTI pin.
XT4D
XT2D
Frequency division ratio
0
0
1
0
1
0
According to XTSL (default)
1/2
1/4
DRR2 to DRR0: Partially clears the Data RAM values (0 write).
The following values are cleared when set to 1 (on) respectively; default = 0
DRR2: M08, M09, M0A
DRR1: M00, M01, M02
DRR0: M00, M01, M02 only when LOCK = low
Note) Set DRR1 and DRR0 for 50µs or more.
ASFG:
When vibration detection is performed during anti-shock circuit operation, FCS servo filter is
forcibly set to gain normal status.
On when set to 1; default = 0
LPAS:
Built-in analog buffer low-current consumption mode
This mode reduces the total analog buffer current consumption for the VC, TE, SE and FE
input by using a single operational amplifier.
On when set to 1; default = 0
Note) When using this mode, firstly check whether each error signal is properly A/D converted
using the SRO1 and SRO0 commands of $3F.
SRO1, SRO0: These commands are used to output various data continuously externally which have been
specified with the $39 command. (However, D15 (DAC) of $39 must be set to 1.)
Digital output (SOCK, XOLT and SOUT) can be obtained from three specified pins by setting
these commands to 1 respectively. The default is 0, 0.
The output pins for each case are shown below.
SRO1 = 1
SOCK
XOLT
SOUT
XUGF
GFS
GTOP
(See "Description of Data Readout" on the following page.)
AGHF:
COT2:
This halves the frequency of the internally generated sine wave during AGC.
The STZC signal is output from COUT by setting D0 to 1.
(STZC: TZC signal generated by sampling the TE signal at 700kHz)
– 100 –
CXD2548R
Description of Data Readout
SOCK
(5.6448MHz)
···
···
···
···
XOLT
(88.2kHz)
SOUT
MSB
···
LSB
MSB
16-bit register for
serial/parallel
conversion
SOUT
···
LSB
16-bit register
for latch
LSB
LSB
To the 7-segment LED
•
•
•
•
•
•
To the 7-segment LED
MSB
SOCK
MSB
CLK
CLK
Data is connected to the 7-segment LED
by 4-bits at time. This enables Hex
display using four 7-segment LEDs.
XOLT
SOUT
Serial data input
D/A
Analog
output
SOCK
Clock input
XOLT
Latch enable input
To an oscilloscope, etc.
Offset adjustment,
gain adjustment
Waveforms can be monitored with an oscilloscope using a serial
input-type D/A converter as shown above.
– 101 –
CXD2548R
§4-19. List of Servo Filter Coefficients
<Coefficient Preset Value Table (1)>
ADDRESS
DATA
K00
K01
K02
K03
K04
K05
K06
K07
K08
K09
K0A
K0B
K0C
K0D
K0E
K0F
E0
81
23
7F
6A
10
14
30
7F
46
81
1C
7F
58
82
7F
SLED INPUT GAIN
SLED LOW BOOST FILTER A-H
SLED LOW BOOST FILTER A-L
SLED LOW BOOST FILTER B-H
SLED LOW BOOST FILTER B-L
SLED OUTPUT GAIN
FOCUS INPUT GAIN
SLED AUTO GAIN
FOCUS HIGH CUT FILTER A
FOCUS HIGH CUT FILTER B
FOCUS LOW BOOST FILTER A-H
FOCUS LOW BOOST FILTER A-L
FOCUS LOW BOOST FILTER B-H
FOCUS LOW BOOST FILTER B-L
FOCUS PHASE COMPENSATE FILTER A
FOCUS DEFECT HOLD GAIN
K10
K11
K12
K13
K14
K15
K16
K17
K18
K19
K1A
K1B
K1C
K1D
K1E
K1F
4E
32
20
30
80
77
80
77
00
F1
7F
3B
81
44
7F
5E
FOCUS PHASE COMPENSATE FILTER B
FOCUS OUTPUT GAIN
ANTI SHOCK INPUT GAIN
FOCUS AUTO GAIN
HPTZC / Auto Gain HIGH PASS FILTER A
HPTZC / Auto Gain HIGH PASS FILTER B
ANTI SHOCK HIGH PASS FILTER A
HPTZC / Auto Gain LOW PASS FILTER B
Fix∗
TRACKING INPUT GAIN
TRACKING HIGH CUT FILTER A
TRACKING HIGH CUT FILTER B
TRACKING LOW BOOST FILTER A-H
TRACKING LOW BOOST FILTER A-L
TRACKING LOW BOOST FILTER B-H
TRACKING LOW BOOST FILTER B-L
K20
K21
K22
K23
K24
K25
K26
K27
K28
K29
K2A
K2B
K2C
K2D
K2E
K2F
82
44
18
30
7F
46
81
3A
7F
66
82
44
4E
1B
00
00
TRACKING PHASE COMPENSATE FILTER A
TRACKING PHASE COMPENSATE FILTER B
TRACKING OUTPUT GAIN
TRACKING AUTO GAIN
FOCUS GAIN DOWN HIGH CUT FILTER A
FOCUS GAIN DOWN HIGH CUT FILTER B
FOCUS GAIN DOWN LOW BOOST FILTER A-H
FOCUS GAIN DOWN LOW BOOST FILTER A-L
FOCUS GAIN DOWN LOW BOOST FILTER B-H
FOCUS GAIN DOWN LOW BOOST FILTER B-L
FOCUS GAIN DOWN PHASE COMPENSATE FILTER A
FOCUS GAIN DOWN DEFECT HOLD GAIN
FOCUS GAIN DOWN PHASE COMPENSATE FILTER B
FOCUS GAIN DOWN OUTPUT GAIN
NOT USED
NOT USED
CONTENTS
– 102 –
CXD2548R
<Coefficient ROM Preset Value Table (2)>
ADDRESS
DATA
K30
K31
K32
K33
K34
K35
K36
K37
K38
K39
K3A
K3B
K3C
K3D
K3E
K3F
80
66
00
7F
6E
20
7F
3B
80
44
7F
77
86
0D
57
00
Fix∗
ANTI SHOCK LOW PASS FILTER B
NOT USED
ANTI SHOCK HIGH PASS FILTER B-H
ANTI SHOCK HIGH PASS FILTER B-L
ANTI SHOCK FILTER COMPARATE GAIN
TRACKING GAIN UP2 HIGH CUT FILTER A
TRACKING GAIN UP2 HIGH CUT FILTER B
TRACKING GAIN UP2 LOW BOOST FILTER A-H
TRACKING GAIN UP2 LOW BOOST FILTER A-L
TRACKING GAIN UP2 LOW BOOST FILTER B-H
TRACKING GAIN UP2 LOW BOOST FILTER B-L
TRACKING GAIN UP PHASE COMPENSATE FILTER A
TRACKING GAIN UP PHASE COMPENSATE FILTER B
TRACKING GAIN UP OUTPUT GAIN
NOT USED
K40
K41
K42
K43
K44
K45
K46
K47
K48
K49
K4A
K4B
K4C
K4D
K4E
K4F
04
7F
7F
79
17
6D
00
00
02
7F
7F
79
17
54
00
00
TRACKING HOLD FILTER INPUT GAIN
TRACKING HOLD FILTER A-H
TRACKING HOLD FILTER A-L
TRACKING HOLD FILTER B-H
TRACKING HOLD FILTER B-L
TRACKING HOLD FILTER OUTPUT GAIN
NOT USED
NOT USED
FOCUS HOLD FILTER INPUT GAIN
FOCUS HOLD FILTER A-H
FOCUS HOLD FILTER A-L
FOCUS HOLD FILTER B-H
FOCUS HOLD FILTER B-L
FOCUS HOLD FILTER OUTPUT GAIN
NOT USED
NOT USED
CONTENTS
∗ Fix indicates that normal preset values should be used.
– 103 –
CXD2548R
§4-20. FILTER Composition
The internal filter composition is shown below.
K ∗ ∗ and M ∗ ∗ indicate coefficient RAM and Data RAM address values respectively.
FCS Servo Gain Normal fs = 88.2kHz
FCS
Hold Reg 2
FCS
In Reg
DFCT
2–1
K06
AGFON
Sin ROM
K06
K0F
M03
M04
Z–1
M05
Z–1
K08
K09
FCS
AUTO Gain
FCS
Hold Reg 1
M06
Z–1
K0A
K0C
2–7
K11
M07
K0E
K10
27
2–7
FCS PWM
K0D
K0B
K13
Z–1
FCS SRCH
Note) Set the MSB bit of the K0B and K0D coefficients to 0.
FCS Servo Gain Down fs = 88.2kHz
FCS
Hold Reg 2
FCS
In Reg
DFCT
2–1
K06
K2B
M03
M04
Z–1
M05
Z–1
K24
K25
Z–1
K26
K28
2–7
K27
FCS
Hold Reg 1
FCS
AUTO Gain
M06
K2D
M07
K13
Z–1
K2A
K2C
27
2–7
FCS PWM
K29
FCS SRCH
Note) Set the MSB bit of the K27 and K29 coefficients to 0.
– 104 –
CXD2548R
TRK Servo Gain Normal fs = 88.2kHz
TRK
Hold Reg
TRK
In Reg
DFCT
2–1
K19
AGTON
Sin ROM
K19
TRK
AUTO Gain
M0B
M0C
M0D
M0E
Z–1
Z–1
Z–1
Z–1
K1A
K1B
K1C
K1E
2–7
K1D
K20
K21
K22
M0F
K23
27
2–7
TRK PWM
K1F
TRK JMP
Note) Set the MSB bit of the K1D and K1F coefficients to 0.
TRK Servo Gain Up 1 fs = 88.2kHz
TRK
Hold Reg
TRK
In Reg
DFCT
2–1
K19
TRK
AUTO Gain
M0B
M0C
M0E
Z–1
Z–1
Z–1
K3E
M0F
27
K23
TRK PWM
TRK JMP
K1A
K1B
K3C
K3D
– 105 –
CXD2548R
TRK Servo Gain Up 2 fs = 88.2kHz
TRK
Hold Reg
TRK
In Reg
DFCT
2–1
K19
TRK
AUTO Gain
M0B
M0C
M0D
M0E
Z–1
Z–1
Z–1
Z–1
K36
K37
K38
K3A
2–7
K3C
K3D
K3E
M0F
27
2–7
K39
K23
TRK PWM
K3B
TRK JMP
Note) Set the MSB bit of the K39 and K3B coefficients to 0.
SLD Servo fs = 345Hz
TRK
AUTO Gain
2–1
SLD
In Reg
K00
M00
M01
Z–1
Z–1
K05
M02
27
K07
SLD PWM
SLD MOV
K01
K03
2–7
K02
2–7
K04
Note) Set the MSB bit of the K02 and K04 coefficients to 0.
HPTZC/Auto Gain fs = 88.2kHz
FCS
In Reg
TRK
In Reg
Sin ROM
2–1
Slice
TZC Reg
AGFON
2–1
AGTON
AGFON
M08
M09
Z–1
M0A
Z–1
K14
K15
– 106 –
Z–1
K17
Slice
AUTO Gain
Reg
CXD2548R
Anti Shock fs = 88.2kHz
TRK
In Reg
2–1
K12
M08
M09
M0A
Z–1
Z–1
Z–1
K31
K16
K35
Comp
Anti Shock
Reg
K33
2–7
K34
Note) Set the MSB bit of the K34 coefficient to 0.
The comparator level is 1/16 the maximum amplitude of the comparator input.
AVRG fs = 88.2kHz
2–1
2–7
M08
VC, TE, FE,
RFDC
AVRG Reg
Z–1
TRK Hold fs = 345Hz
SLD
In Reg
2–1
K40
M18
M19
Z–1
Z–1
K41
K45
TRK
Hold Reg
K43
2–7
2–7
K42
K44
Note) Set the MSB bit of the K42 and K44 coefficients to 0.
FCS Hold fs = 345Hz
FCS
Hold Reg 1
K48
M10
M11
Z–1
Z–1
K49
K4D
FCS
Hold Reg 2
K4B
2–7
2–7
K4A
K4C
Note) Set the MSB bit of the K4A and K4C coefficients to 0.
– 107 –
CXD2548R
FCS Servo Gain Normal; fs = 88.2kHz, during quasi double accuracy (Ex.: $3EAXX0)
FCS
Hold Reg 2
DFCT
2–1
FCS
In Reg
K06
AGFON
Sin ROM
K06
M03
M04
Z–1
M05
Z–1
∗
K0A
2–7
K08
K11
M07
K13
Z–1
∗
7FH
2–7
M06
Z–1
∗
81H
FCS
AUTO Gain
FCS
Hold Reg 1
K0F
K0C
2–7
K09
80H
K10
2–7
K0B
27
2–7
K0D
FCS PWM
K0E
FCS SRCH
∗ 81H, 7FH and 80H are each Hex display 8-bit fixed values when set to quasi double accuracy.
Note) Set the MSB bit of the K0B and K0D coefficients during normal operation, and of the K08, K09
and K0E coefficients during quasi double accuracy to 0.
FCS Servo Gain Down; fs = 88.2kHz, during quasi double accuracy (Ex.: $3E5XX0)
FCS
Hold Reg 2
DFCT
2–1
FCS
In Reg
K06
M03
M04
Z–1
M05
Z–1
∗
7FH
2–7
K24
K2D
M07
K13
Z–1
∗
K26
2–7
K28
2–7
K25
M06
Z–1
∗
81H
FCS
AUTO Gain
FCS
Hold Reg 1
K2B
K27
80H
2–7
K2C
27
2–7
K29
FCS PWM
K2A
FCS SRCH
∗ 81H, 7FH and 80H are each Hex display 8-bit fixed values when set to quasi double accuracy.
Note) Set the MSB bit of the K27 and K29 coefficients during normal operation, and of the K24, K25 and
K2A coefficients during quasi double accuracy to 0.
– 108 –
CXD2548R
TRK Servo Gain Normal; fs = 88.2kHz, during quasi double accuracy (Ex.: $3EXAX0)
TRK
Hold Reg
DFCT
2–1
TRK
In Reg
K19
AGTON
Sin ROM
K19
TRK
AUTO Gain
M0B
M0C
M0D
Z–1
Z–1
Z–1
∗
K1C
K1E
2–7
K1A
M0F
K23
∗
7FH
2–7
K22
Z–1
∗
81H
M0E
2–7
K1B
K1D
80H
2–7
K21
27
2–7
K1F
TRK PWM
K20
TRK JMP
∗ 81H, 7FH and 80H are each Hex display 8-bit fixed values when set to quasi double accuracy.
Note) Set the MSB bit of the K1D and K1F coefficients during normal operation, and of the K1A, K1B
and K20 coefficients during quasi double accuracy to 0.
TRK Servo Gain up 1; fs = 88.2kHz, during quasi double accuracy (Ex.: $3EX5X0)
TRK
Hold Reg
DFCT
2–1
TRK
In Reg
K19
TRK
AUTO Gain
M0B
M0C
M0E
Z–1
Z–1
Z–1
∗
∗
81H
2–7
K1A
∗
7FH
80H
K1B
K3C
2–7
K3E
M0F
27
K23
TRK PWM
TRK JMP
K3D
2–7
∗ 81H, 7FH and 80H are each Hex display 8-bit fixed values when set to quasi double accuracy.
Note) Set the MSB bit of the K1A, K1B and K3C coefficients during quasi double accuracy to 0.
– 109 –
CXD2548R
TRK Servo Gain up 2; fs = 88.2kHz, during quasi double accuracy (Ex.: $3EX5X0)
TRK
Hold Reg
TRK
In Reg
DFCT
2–1
K19
TRK
AUTO Gain
M0B
M0C
M0D
M0E
Z–1
Z–1
Z–1
Z–1
∗
∗
81H
K36
M0F
K23
∗
7FH
2–7
K3E
K38
2–7
K3A
2–7
K37
K39
80H
2–7
K3D
27
2–7
K3B
TRK PWM
K3C
TRK JMP
∗ 81H, 7FH and 80H are each Hex display 8-bit fixed values when set to quasi double accuracy.
Note) Set the MSB bit of the K39 and K3B coefficients during normal operation, and the K36, K37 and
K3C coefficients during quasi double accuracy to 0.
– 110 –
CXD2548R
§4-21. TRACKING and FOCUS Frequency Response
TRACKING frequency response
180°
40
NORMAL
GAIN UP
30
G
20
0°
φ
10
φ – Phase [degree]
G – Gain [dB]
90°
–90°
0
–10
2.1
10
100
–180°
20K
1K
f – Frequency [Hz]
FOCUS frequency response
180°
40
NORMAL
GAIN DOWN
30
20
G
0°
10
φ
–90°
0
–10
2.1
10
100
f – Frequency [Hz]
– 111 –
1K
–180°
20K
φ – Phase [degree]
G – Gain [dB]
90°
ADIO
ADIO
IGEN
TES2
TES3
VSS2
TEST
TRDR
XLAT
TFDR
CLOK
FFDR
DATA
FRDR
VDD2
SENS
COUT
COUT
LOCK
LOCK
MDS
EXCK
SSTP
MDP
VC
FSTI
LMUT2
FSTO
CKOUT
XTSL
C4M
SE 56
99 AIN1
112 VSS0
4
CKOUT
3
LMUT2
RMUT1
2
RMUT1
SYSM
1
111 AVSS2
110 AVDD2
109 AOUT2
108 AIN2
107 LOUT2
106 AVSS2
105 XVSS
104 XTAO
103 XTAI
102 XVDD
101 AVSS1
100 LOUT1
7
6
5
PCO 44
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
MNT1 30
MNT0 29
MNT3 31
VSS1 32
DOUT 33
MNT3
MNT1
MNT0
GND
VC
FG
TD
TG
FD
LDON
VCC
GND
RFO
FZC
FE
TE
CE
VC
Application circuits shown are typical examples illustrating the operation of
the devices. Sony cannot assume responsibility for any problems arising out
of the use of these circuits or for any infringement of third party patent and
other right due to same.
DOUT
MIRR
ATSK 34
DFCT
MIRR 35
V16M
DFCT 36
FOK 37
VDD1 38
VPCO1 39
VPCO2 40
VCKI 41
V16M 42
VCTL 43
8
XLON
98 AOUT1
WFCK
97 AVDD1
FILI 46
VDD0
FILO 45
94 EMPHI
SBSO
SBSO
95 VSS3
CLTV 48
AVSS4 47
93 EMPH
XUGF
SQCK
XPLCK
SQSO
GTOP
MUTE
SQCK
SQSO
SENS
SCLK
DATA
XLAT
CLOK
XRST
PWMI
GFS
SCOR
FOK
LDON
VDD
GND
EXCK
96 AVSS1
AVDD4 49
92 BCKI
SCLK
RFAC 50
ACDT
91 BCK
90
87
XRST
C4M
BIAS 51
SFDR
PCMDI
SRDR
ASYI 52
PWMI
ASYO 53
XLON
88 LRCKI
SPOA
89 PCMD
WFCK
FE 55
XUGF
VC 54
GFS
LRCK
AVDD3
GTOP
WDCK
XROF
86 VDD3
AVSS3
XPCK
85
RFC
RFCK
RFCK
WDCK
CE
84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57
Driver Circuit
RFDC
C2PO
C2PO
+5V
SSTP
SLED
SPDL
GND
TE
SCOR
– 112 –
XRAOF
[5] Application Circuit
§5-1. Application Circuit
CXD2548R
CXD2548R
Unit: mm
112PIN LQFP(PLASTIC)
22.0 ± 0.2
1.7MAX
20.0 ± 0.1
1.4 ± 0.1
84
S
57
0.1
56
85
B
A
112
29
28
1
0.65
0.32 ± 0.05
0.13 M
S
0° — 10°
DETAIL A
(0.3)
(0.125)
0.32 ± 0.05
0.145 ± 0.03
0.6 ± 0.15
0.25
(21.0)
0.1 ± 0.05
(0.5)
Package Outline
DETAIL B
PACKAGE STRUCTURE
PACKAGE MATERIAL
EPOXY RESIN
SONY CODE
LQFP-112P-L01
LEAD TREATMENT
SOLDER PLATING
EIAJ CODE
LQFP112-P-2020
LEAD MATERIAL
COPPER ALLOY
PACKAGE WEIGHT
1.3g
JEDEC CODE
– 113 –
S