SONY CXD2720Q

CXD2720Q
Single-Chip Digital Signal Processor for Karaoke
Description
The CXD2720Q is a digital signal processor LSI for
Karaoke, suitable for use in LD/CD/CD-G/video CD
and the like.
A large capacity DRAM and AD/DA converters are
built in, and Karaoke functions such as key control,
microphone echo and voice canceling are contained
on a single chip.
Features
• 3-channel 1-bit AD converter and decimation filter
S/N ratio: 88 dB
THD + N: 0.016%
Filter pass band ripple:
less than ±0.5dB
Filter stop band attenuation: less than –41dB
(all characteristics are typical values)
• 2-channel 1-bit DA converter and oversampling
filter
S/N ratio: 98dB
THD + N: 0.006%
Filter pass band ripple:
less than ±0.2dB
Filter stop band attenuation: less than –41dB
(all characteristics are typical values)
• In addition to analog input/output, 2-channel input/
2-channel output of digital input/output are provided.
The interface also supports a variety of formats.
• 128K-bit DRAM for key control and microphone
echo processing
Functions
• Key controller pitch setting can be varied to a
maximum of ±1 octave with a precision of 14 bits
• Microphone echo delay time can be varied to a
maximum of 185ms (when Fs = 44.1kHz)
• Voice canceller supports settings other than center
by the panpot volume
• Voice parametric equalizer
• Voice pitch shifter
• Mixing function to support sound multiplexing
software
• Digital de-emphasis function
100 pin QFP (Plastic)
Structure
Silicon gate CMOS
Applications
Equipment having Karaoke function, such as
LD/CD, compact music center, video games, etc.
Absolute Maximum Ratings
•
•
•
•
•
(Ta = 25°C, VSS = 0V)
Supply voltage
VDD VSS – 0.5 to +7.0
V
Input voltage
VI VSS – 0.5 to VDD + 0.5 V
Output voltage
VO VSS – 0.5 to VDD + 0.5 V
Operating temperature
Topr
–20 to +75
°C
Storage temperature Tstg
–55 to +150
°C
Recommended Operating Conditions
• Supply voltage
VDD 4.5 to 5.5 (5.0 typ.) V
• Operating temperature
Ta
–20 to +75
°C
Input/Output Capacitance
9 (max.)
pF
• Input capacitance
CIN
• Output capacitance
COUT 11 (max.)
pF
• Input/output capacitance CI/O 11(max.)
pF
∗ Measurement conditions: VDD = VI = 0V, F = 1MHz
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E96426-ST
CXD2720Q
Block Diagram
128K bit DELAY RAM
RVDT 3
SCK
4
XLAT
5
MICRO
COMPUTER
I/F
REDY 6
TRDT
25 AO1P
DAC1
7
26 AO1N
DAC2
39 AO2N
40 AO2P
ADC1
29 AIN1
ADC2
36 AIN2
ADC3
22 AIN3
DSP
LRCK 88
BCK 87
SERIAL
DATA
I/F
SI 86
SO 12
XWO
8
CLOCK GENERATOR
/TIMING CIRCUIT
33
82
32
XTLI XTLO BFOT
NC
NC
VSS4
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
VDD2
VSS5
NC
NC
NC
NC
NC
NC
NC
NC
NC
VSS6
Pin Configuration
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
X768 81
50 NC
BFOT 82
49 NC
INVI 83
48
NC
NC 84
47
NC
NC 85
46 NC
SI 86
45
NC
BCK 87
44
NC
LRCK 88
43 VDD1
XMST 89
42 VSS3
VSS7 90
41
AVS5
NC 91
40 AO2P
NC 92
39 AO2N
NC 93
38 AVD5
NC 94
37 AVD2
NC 95
36 AIN2
NC 96
35 AVS2
NC 97
34 XVSS
NC 98
33
XTLI
–2–
AVD1
AIN1
AVS1
AVS4
AO1P
AO1N
AVD4
AIN3
AVD3
AVS3
VSS2
TST5
TRDT
TST3
REDY
TST4
XLAT
TST2
SCK
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
TST1
RVDT
8
TST0
7
XS24
6
SO
5
VDD0
4
VSS1
3
XWO
2
XRST
1
VSS0
32 XTLO
31 XVDD
AVS0
VDD3 99
AVD0 100
CXD2720Q
Pin Description
Pin
No.
Symbol
I/O
Description
1
AVS0
—
DRAM digital GND.
2
VSS0
—
Digital GND.
3
RVDT
I
Data input for microcomputer interface.
4
SCK
I
Shift clock input for microcomputer interface.
5
XLAT
I
Latch input for microcomputer interface.
6
REDY
O
Transmission enabling signal output for microcomputer interface. Transmission
prohibited when Low.
7
TRDT
O
Serial data output for microcomputer interface.
8
XWO
I
Window open input for synchronization. Normally High.
9
XRST
I
System reset input. Resets when Low.
10
VSS1
—
Digital GND.
11
VDD0
—
Digital power supply.
12
SO
O
1-sampling 2-channel serial data output.
13
XS24
I
Serial data 24-/32-bit slot selection. 24-bit slot when Low. (valid for slave mode)
14
TST0
I
Test pin. Normally set Low.
15
TST1
I
Test pin. Normally set Low.
16
TST2
I
Test pin. Normally set Low.
17
TST3
I
Test pin. Normally set Low.
18
TST4
I
Test pin. Normally set Low.
19
TST5
I
Test pin. Normally set Low.
20
VSS2
—
Digital GND.
21
AVS3
—
CH3 AD converter GND.
22
AIN3
I
23
AVD3
—
CH3 AD converter power supply.
24
AVD4
—
CH1 DA converter power supply.
25
AO1P
O
CH1 DA converter analog positive phase output.
26
AO1N
O
CH1 DA converter analog reversed phase output.
27
AVS4
—
CH1 DA converter GND.
28
AVS1
—
CH1 AD converter GND.
29
AIN1
I
CH1 AD converter analog input.
30
AVD1
—
CH1 AD converter power supply.
31
XVDD
—
Digital power supply for master clock.
32
XTLO
O
Crystal oscillator circuit output.
33
XTLI
I
Crystal oscillator circuit input.
34
XVSS
—
Digital GND for master clock.
35
AVS2
—
CH2 AD converter GND.
CH3 AD converter analog input (for microphone input).
–3–
CXD2720Q
Pin
No.
Symbol
I/O
Description
36
AIN2
I
CH2 AD converter analog input.
37
AVD2
—
CH2 AD converter power supply.
38
AVD5
—
CH2 DA converter power supply.
39
AO2N
O
CH2 DA converter analog reversed phase output.
40
AO2P
O
CH2 DA converter analog positive phase output.
41
AVS5
—
CH2 DA converter GND.
42
VSS3
—
Digital GND.
43
VDD1
—
Digital power supply.
44 to 52 NC
53
VSS4
Normally open.
—
54 to 68 NC
Digital GND.
Normally open.
69
VSS5
—
Digital GND.
70
VDD2
—
Digital power supply.
71 to 79 NC
Normally open.
80
VSS6
—
81
X768
I
Test input pin. Normally set Low.
82
BFOT
O
Clock, frequency-divider output (384fs).
83
INVI
I
Test pin. Normally set Low.
84
NC
Normally open.
85
NC
Normally open.
86
SI
87
BCK
I/O
Serial bit transmission clock for serial input/output data SI and SO.
88
LRCK
I/O
Sampling frequency clock for serial input/output data SI and SO.
89
XMST
I
90
VSS7
I
—
91 to 98 NC
Digital GND.
1-sampling 2-channel serial data input.
BCK, LRCK master/slave mode switching input. Master mode when Low.
Digital GND.
Normally open.
99
VDD3
—
Digital power supply.
100
AVD0
—
Digital power supply for DRAM.
–4–
CXD2720Q
DC Characteristics
(AVD0 to 5 = XVDD = VDD0 to 3 = 5V ± 10%, AVS0 to 5 = XVSS = VSS0 to 7 = 0V, Ta = –20 to +75°C)
Item
Input voltage (1)
Symbol
Conditions
Min.
Typ.
0.7VDD
High level VIH
Low level VIL
Input voltage (2)
∗1, ∗4, ∗5
V
∗3
0.2VDD
V
∗3
VDD
V
∗2
V
∗6, ∗7, ∗8
V
∗6, ∗7, ∗8, ∗9
V
∗10
V
∗10
V
∗11
VDD/2
V
∗11
0.8VDD
Low level VIL
Unit Applicable pins
∗1, ∗4, ∗5
V
V
0.3VDD
High level VIH
Input voltage (3)
Max.
Analog input
VSS
Output voltage High level VOH
(1)
Low level VOL
IOH = –2.0mA
VDD – 0.8
Output voltage High level VOH
(2)
Low level VOL
IOH = –6.0mA
Output voltage High level VOH
(3)
Low level VOL
IOH = –12.0mA
Input leak current (1)
II
VIH = VDD, VSS
–10
10
µA
∗1, ∗3, ∗5
Input leak current (2)
II
VIH = VDD, VSS
–40
40
µA
∗4
Output leak current
IOZ
VIH = VDD, VSS
–40
40
µA
∗8, ∗9
Feedback resistance
RFB
1M
2.5M
Ω
Resistance
between ∗5
and ∗11.
Current consumption
IDD
79
90
mA
VIN
IOL = 4.0mA
0.4
VDD – 0.8
IOL = 4.0mA
0.4
VDD/2
IOL = 12.0mA
250k
fs = 44.1kHz
∗1 RVDT, SCK, XLAT, XWO, XRST, XS24, TST0 to TST5, X768, SI, XMST
∗2 AIN1, AIN2, AIN3
∗3 INVI
∗4 During input to bidirectional pins BCK, LRCK
∗5 XTLI
∗6 During output from bidirectional pins BCK, LRCK
∗7 SO, BFOT
∗8 TRDT
∗9 REDY
∗10 AO1P, AO1N, AO2N, AO2P
∗11 XTLO
–5–
CXD2720Q
AC Characteristics
(AVD0 to 5 = XVDD = VDD0 to 3 = 5V±10%, AVS0 to 5 = XVSS = VSS0 to 7 = 0V, Ta = –20 to +75°C)
Serial Audio Interface Timing
[Slave mode]
0.7VDD
0.3VDD
BCK
tSSI
tHSI
0.7VDD
0.3VDD
SI
tDSSO
SO
tHLR
tSLR
0.7VDD
0.3VDD
LRCK
[Master mode]
BCK
tDLR
LRCK
tDMSO
SO
Item
SI setup time
SI hold time
SO delay time
LRCK setup time
LRCK hold time
LRCK delay time
SO delay time
Symbol
tSSI
tHSI
tDSSO
tSLR
tHLR
tDLR
tDMSO
Conditions
Min.
Max.
Unit
Slave mode
20
ns
Slave mode
40
ns
Slave mode, CL = 60pF
50
ns
Slave mode
20
ns
Slave mode
40
ns
Master mode, CL = 120pF
50
ns
Master mode, CL = 60pF
100
ns
–6–
CXD2720Q
Microcomputer Interface Timing
[Write]
• Transmission timing for address section, transmission mode section, data section LSB
RVDT
Address LSB
tSWL tSWH
0.7VDD
0.3VDD
Mode MSB
tDS
tDH
Data LSB
Data MSB
0.7VDD
0.3VDD
SCK
tSLP
tLSD
0.7VDD
0.3VDD
XLAT
tLWL
tLWH
REDY
• Transmission timing from data section MSB to address section and transmission mode section
RVDT
Data MSB
Address LSB
Mode MSB
0.7VDD
0.3VDD
tSS
0.7VDD
0.3VDD
SCK
tSLD
0.7VDD
0.3VDD
XLAT
tSBD
tLDR
tRLP
tBSP
REDY
[Read]
• Transmission timing for address section and transmission mode section is the same as for write.
RVDT
Address LSB
Mode MSB
tSS
0.7VDD
0.3VDD
SCK
tSLP
tRSDP
0.7VDD
0.3VDD
XLAT
tLWL
tLBD
0.7VDD
0.3VDD
REDY
tLDN
tSDD
Data LSB
TRDT
–7–
Data MSB
CXD2720Q
Item
Symbol
tDS
tDH
tSWL
tSWH
tLWL
tLWH
tSLP
tLSD
tLBD
tSBD
tBSP
tRLP
tRSDP
RVDT setup time relative to SCK rise
RVDT data hold time from SCK rise
SCK Low level width
SCK High level width
XLAT Low level width
XLAT High level width
SCK rise preceding time relative to XLAT rise
SCK rise wait time relative to XLAT rise
Delay time to REDY fall relative to XLAT rise.
Delay time to REDY fall relative to SCK rise
REDY fall preceding time relative to SCK rise
REDY rise preceding time relative to XLAT rise
REDY rise preceding time relative to SCK fall
XLAT fall wait time relative to SCK rise
XLAT fall delay time relative to REDY fall
Delay time from XLAT rise until TRDT data becomes active
Delay time from SCK rise until TRDT data becomes high-impedance
Delay time from SCK fall until TRDT data is verified
CK rise wait time for next transmission
tSLD
tLDR
tLDN
tSDF
tSDD
tSS
Note 1) t is the cycle of 1/2 the clock frequency applied to the XTLI pin. (384fs)
Note 2) REDY and TRDT pins are the values for CL = 60pF.
–8–
Min.
Max.
Unit
20
ns
1t + 20
ns
1t + 20
ns
1t + 20
ns
1t + 20
ns
1t + 20
ns
20
ns
3t + 20
ns
3t + 50
ns
4t + 50
ns
20
ns
20
ns
20
ns
3t + 20
ns
20
ns
2t + 40
3t + 80
ns
3t + 80
ns
2t + 70
ns
ns
CXD2720Q
Analog Characteristics (AVD0 to 5 = VDD0 to 3 = XVDD = 5.0V, AVS0 to 5 = VSS0 to 7 = XVSS = 0.0V, Ta = 25°C,
DSP: each function = OFF, gain = 1)
[1] ADC + DAC connection total characteristics
The measurement circuit in Figure 1-1 is used. Unless otherwise indicated, the measurement conditions are as
given below.
• Input signal ...1.0Vrms, 1kHz
• fs....................44.1kHz
• Rin .................0Ω
Item
S/N ratio
THD + N
Measurement conditions
Min.
Typ.
1.0Vrms, EIAJ (with “A” weighting filter)
80
88
1.0Vrms, EIAJ
0.016
0.5Vrms, EIAJ
0.012
Max.
Unit
dB
0.03
%
Dynamic range
EIAJ
92
dB
Channel separation
Only ADC characteristics using DAC1,
EIAJ
108
dB
Level difference between
channels
Only ADC characteristics using DAC1
0.05
dB
Rin = 0Ω
1.26
Rin = 22kΩ
2.06
Analog full-scale input level
ADC input impedance
Analog current consumption
Vrms
34.6
kΩ
21
mA
∗1 Analog input level which outputs digital full scale.
An optional analog input signal level Vin (Vrms) of 1.26Vrms or more can be set in digital full scale by the
measurement circuit external resistor Rin.
The calculation formula for external resistor Rin is:
Rin = 27.5 × Vin – 34.6 [kΩ]......(1)
However, THD + N characteristics deteriorate for full-scale output as shown in Graph 1, so use of up to 80%
(when Rin = 0Ω, 0.8 × 1.26 (Vrms) = 1.0 (Vrms) → “analog full scale”) of the analog signal level is recommended
for digital full-scale output.
In this case, the Rin calculation formula is the same as formula (1), except that Vin becomes 1.25 × Vin.
Note that this change causes the output level after ADC + DAC to change.
Most of the above specifications are measurement values for analog full scale.
–9–
CXD2720Q
[2] DAC unit characteristics
Use the measurement circuit in Figure 1-2. Unless otherwise specified, the measurement conditions are as
follows.
• Input signal ....0dB, 1kHz, 16 bit
• fs....................44.1kHz
Item
Measurement conditions
S/N ratio
Min.
EIAJ (with “A” weighting filter)
Typ.
98
Max.
Unit
dB
EIAJ (0dB)
0.006
EIAJ (–1dB)
0.004
Dynamic range
EIAJ (–60dB)
98
dB
Channel separation
EIAJ
120
dB
Level difference between
channels
EIAJ
0.05
dB
Output level
EIAJ (Measure at OUT in Figure 1-2.)
2.0
Vrms
THD + N
THD + N [%]
1.00
0.10
(Rin = 0Ω)
Digital full scale
Analog full scale
0.01
–60
–50
–40
–30
–20
–10
Analog input level [dBV]
Graph 1.
– 10 –
0
10
(1Vrms)
%
CXD2720Q
CXD2720Q
(Master mode)
150p
10µ Rin
12k
22k
39k
AINx AOxN
Vin
2.2k
8200p
2.2k
OUT
330p
1M
AOxP
820p
12k
22k
39k
150p
Figure 1-1. ADC + DAC Measurement Circuit Diagram
CXD2720Q
(Slave mode)
768fs
48fs
fs
DATA
(fs = 44.1kHz)
150p
XTLI
BCK
12k
22k
39k
LRCK AOxN
2.2k
8200p
2.2k
330p
SI
AOxP
820p
12k
22k
39k
150p
Figure 1-2. DAC Measurement Circuit Diagram
– 11 –
OUT
CXD2720Q
Description of Functions
1. Master/Slave Modes
[Relevant pins] XMST, LRCK, BCK
When connecting multiple CXD2720Qs, or when using as a pair with a D/A converter such as the CXD2558M,
one of the CXD2720Q should be in master mode to supply LRCK and BCK.
The clock applied to LRCK and BCK in slave mode must be synchronized to either the crystal oscillator clock
of the XTLI and XTLO pins or the external clock input from the XTLI pin
XMST
Mode
LRCK, BCK I/O
H
Slave mode
Input
L
Master mode
Output
Table 1-1. LRCK, BCK Mode Setting
2. Master Clock System
[Relevant pins] XTLI, XTLO, BFOT
768fs (fs = 44.1kHz) is assumed for the master clock system, and the connection is as shown below. (Please
inquire with regard to use at other than fs = 44.1kHz.)
(1) Master
O 384fs
BFOT
Frequency divider
I
XTLI
768fs
O
768fs
XTLO
(2) Slave
I
768fs
XTLI
768fs
O OPEN
XTLO
– 12 –
CXD2720Q
3. Input/Output Synchronization Circuit
[Relevant pins] LRCK, XWO
During normal operation, synchronization is performed automatically to input LRCK (in slave mode), and phase
is matched with serial input data, but if there is a lot of jitter on LRCK, or during power input, synchronization
may be impossible. In this case, forced synchronization can be done by making the XWO pin Low for 2/Fs or
more. Forced synchronization operation is done by the timing of the second LRCK rising edge after the XWO
pin is made Low. When synchronization is completed, return the XWO pin to High.
4. Reset Circuit
[Relevant pins] XRST, XTLI, XTLO
This LSI must be reset after power is turned ON.
Reset is done by making the XRST pin Low for 1/Fs or more after supply voltage satisfies the recommended
operating condition, and the crystal oscillator clock of the XTLI, XTLO pins or the external clock input from the
XTLI pin is correctly applied.
5. Serial Audio Interface (SIF)
[Relevant pins] SI, SO, BCK, LRCK, XS24, XMST
Serial data is used for the external communication of the digital audio data.
The CXD2720Q has one system each for input and output, and each one inputs/outputs 2 channels of data at
1 sampling cycles. Either the 32-bit clock mode or 24-bit clock mode can be selected. In master mode, the 32
bit clock mode is fixed.
(1) Pin Configuration
The pins shown in the table below are assigned to SIF.
Pin
name
I/O
SI
I
Serial input; taken synchronized to BCK.
SO
O
Serial output; output synchronized to BCK.
BCK
I/O
BCK input/output; either 32-bit clock mode (64fs) or 24-bit clock mode (48fs). BCK output
supports 32-bit clock mode only.
LRCK
I/O
LRCK input/output (1fs).
XS24
I
SI0 slot number (24/32) selection input. Low: 24-bit slot; High: 32-bit slot. Valid only in slave
mode. Set High in master mode.
XMST
I
BCK, LRCK master mode/slave mode switching input. Low: master mode; High: slave mode.
Function
Table 5-1. Pin Configuration
– 13 –
CXD2720Q
(2) Operation Modes
The LRCK/BCK mode and SI/SO system settings can be selected by the setup register settings as follows.
LRCK/BCK Mode Setting
Setup register
Function
SQ11
SQ10
SQ09
LRCK format
LRCK polarity selection
BCK polarity selection relative to LRCK edge
Contents
“0” : normal,
“0” : Lch “H”,
“0” : edge↓,
“1” : IIS
“1” : Lch “L”
“1” : edge↑
Table 5-2. LRCK/BCK Mode Setting
SI/O System Register Setting
SI system
Setup register
Function
SQ08
SQ07
SI data list
SI frontward/rearward truncation
SQ06
SQ05
SI data word length
SI data word length
Contents
“0” : MSB first,
“1” : LSB first
“0” : Forward truncation,
“1” : Rearward truncation
SQ06 SQ05
0
0
: 16 bit
1
1
: 24 bit
Table 5-3. SI System Register Setting
SO system
Setup register
Function
SQ04
SQ03
SO data list
SO forward/rearward truncation
SQ02
SQ01
SO data word length
Contents
“0” : MSB first,
“1” : LSB first
“0” : Forward truncation,
“1” : Rearward truncation
SQ02 SQ01
0
0
: 16 bit
0
1
: 18 bit
1
0
: 20 bit
1
1
: 24 bit
Table 5-4. SO System Register Setting
– 14 –
CXD2720Q
(3) SIF Format
Serial I/F have one input/output system each, and except for slot number, the following formats can be set for
input and output, independently, by setting the setup register. It can also be made to support IIS format, to
enable connection to Philips and other devices. The timing charts for each data format are given on the
following pages.
32-bit slot (XS24 = High)
Setup register SQ05 SQ06 SQ07 SQ08
SI format
MSB first
MSB first
LSB first
24 bit Forward truncation
16 bit Forward truncation
24 bit Rearward truncation
1
0
1
1
0
1
0
1
1
0
0
1
Supplement
Supports 20, 16 bits
Supports 20, 16 bits
Table 5-5. 32-bit Slot Serial IN
Setup register SQ01 SQ02 SQ03 SQ04
SI format
MSB first
MSB first
MSB first
MSB first
MSB first
LSB first
16 bit
18 bit
20 bit
24 bit
24 bit
24 bit
Rearward truncation
Rearward truncation
Rearward truncation
Rearward truncation
Forward truncation
Rearward truncation
0
1
0
1
1
1
0
0
1
1
1
1
1
1
1
1
0
1
0
0
0
0
0
1
Table 5-6. 32-bit Slot Serial OUT
24-bit slot (XS24 = Low)
Setup register SQ05 SQ06 SQ07 SQ08
SI format
MSB first
MSB first
16 bit Rearward truncation
24 bit
0
1
0
1
∗
0
0
LSB first
24 bit
1
1
∗
1
1
Supplement
Supports 20, 16 bits for forward
truncation
Supports 20, 16 bits for rearward
truncation
Table 5-7. 24-bit Slot Serial IN
Setup register SQ01 SQ02 SQ03 SQ04
SI format
MSB first
MSB first
MSB first
MSB first
LSB first
16 bit Rearward truncation
18 bit Rearward truncation
20 bit Rearward truncation
24 bit
24 bit
0
1
0
1
1
0
0
1
1
1
1
1
1
∗
∗
0
0
0
0
1
Table 5-8. 24-bit Slot Serial OUT
Note 1) When performing 20-bit and 16-bit data input in serial IN 24-bit data format, fill the lower 4 and 8 bits
with “0”, respectively.
Note 2) ∗ means “don't care”.
– 15 –
– 16 –
SI
23
22
21
20
LSB
00
01
02
03
MSB
• LSB first 24 bits
04
19
Invalid
• MSB first 24 bits
05
18
Invalid
MSB
LSB
06
17
07
16
15
14
08
15
09
14
MSB
10
13
13
11
12
12
Lch
12
11
11
13
10
10
14
09
09
15
08
08
16
07
07
17
06
06
18
05
05
19
04
04
20
03
03
00
00
LSB
23
22
23
00
01
MSB LSB
22
LSB MSB
01
01
Figure 5-1.
21
02
02
MSB
Rch
02
21
03
20
04
19
Invalid
Invalid
05
18
MSB
LSB
15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
Invalid
06
17
LSB
07
16
15
14
08
15
09
14
MSB
10
13
13
11
12
12
12
11
11
Rch
13
10
10
14
09
09
15
08
08
16
07
07
17
06
06
18
05
05
19
04
04
20
03
03
21
02
02
00
23
LSB
00
LSB
MSB
22
01
01
MSB
00 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 19 20 21 22 23
Invalid
LSB
23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
MSB
LSB
15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
LSB
00 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 19 20 21 22 23
• MSB first 16 bits rearward truncation
BCK
LRCK
Invalid
• LSB first 24 bits rearward truncation
Invalid
MSB
• MSB first 16 bits rearward truncation
24 bit slot
SI
Lch
23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
• MSB first 24 bits forward truncation
BCK
LRCK
32 bit slot
Digital Audio Data Input Timing (with polarities: SQ11 = 0, SQ10 = 0, SQ09 = 0)
CXD2720Q
– 17 –
SO
14
16
15
14
22
21
20
LSB
00
01
02
03
MSB
• LSB first 24 bits
23
04
19
MSB
• MSB first 24 bits
19
05
18
18
06
17
17
07
16
16
08
15
15
09
14
14
MSB
• MSB first 20 bits rearward truncation
17
MSB
• MSB first 18 bits rearward truncation
15
LSB
LSB
" 0 " truncation
10
13
13
13
13
11
12
12
12
12
12
11
11
11
11
Lch
13
10
10
10
10
14
09
09
09
09
15
08
08
08
08
16
07
07
07
07
17
06
06
06
06
18
05
05
05
05
19
04
04
04
04
20
03
03
03
03
00
00
LSB
00
LSB
00
LSB
23
22
23
00
01
MSB LSB
22
02
21
19
MSB
03
20
04
19
05
18
LSB
LSB
" 0 " truncation
LSB
06
17
17
07
16
16
16
08
15
15
15
MSB
09
14
14
14
14
10
13
13
13
13
11
12
12
12
12
12
11
11
11
11
13
10
10
10
10
Rch
14
09
09
09
09
15
08
08
08
08
16
07
07
07
07
17
06
06
06
06
18
05
05
05
05
19
04
04
04
04
20
03
03
03
03
21
02
02
02
02
00
23
LSB
00
LSB
00
LSB
00
LSB
MSB
22
01
01
01
01
MSB
00 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 19 20 21 22 23
MSB
18
LSB
16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
LSB
14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
MSB
MSB
22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
MSB
LSB
MSB
17
15
" 0 " truncation
LSB MSB
01
01
01
01
MSB
Figure 5-2.
21
02
02
02
02
MSB
23
19
17
15
Rch
23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
LSB
00 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 19 20 21 22 23
LSB
• MSB first 16 bits rearward truncation
BCK
24 bit slot
LRCK
LSB
18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
MSB
• LSB first 24 bits rearward truncation
" 0 " truncation
LSB
14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
MSB
Lch
22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
MSB
• MSB first 24 bits forward truncation
23
MSB
SO • MSB first 24 bits rearward truncation
19
• MSB first 20 bits rearward truncationMSB
17
• MSB first 18 bits rearward truncation
15
• MSB first 16 bits rearward truncation
BCK
LRCK
32 bit slot
Digital Audio Data Output Timing (with polarities: SQ11 = 0, SQ10 = 0, SQ09 = 0)
CXD2720Q
CXD2720Q
6. Microcomputer Interface
[Relevant pins] RVDT, TRDT, SCK, XLAT, REDY
The CXD2720Q performs serial audio interface format setting, volume, coefficient settings of microphone echo
delay amount and others by serial data from the microcomputer.
Further, bidirectional communication such as internal data read from the CXD2720Q to the microcomputer can
be done at the rate of once in 1 LRCK.
(1) Pin Structure
The five external pins indicated in the table below are allocated for microcomputer interface.
Microcomputer interface begins operation when XLAT is received, so RVDT, TRDT, SCK and REDY are
connected in common, and by controlling (wiring) only XLAT separately, multiple CXD2720Qs can be used.
Pin
name
I/O
RVDT
I
Serial data input from microcomputer.
TRDT
O
Serial data output to microcomputer. High impedance state unless this pin is set to internal
data read state by the microcomputer. Therefore, it is preferable to perform pull-up or pulldown so that potential is not unstable when this pin is not active.
SCK
I
Shift clock for serial data. Input data from RVDT is taken according to SCK rise, and output
data from TRDT is sent out according to SCK fall.
XLAT
I
Interprets the 8 bits of RVDT before this signal rises as transmission mode data, and the
bits before that as address data.
REDY
O
Transmission prohibited while at Low level. Transmission enabled at High. This pin is an
open drain, and must be pulled up externally.
Function
Table 6-1. Microcomputer Interface External Pins
– 18 –
CXD2720Q
(2) Description of Communication Formats
The data transmission timing between the microcomputer interface and coefficient RAM and setup register is
called the SV cycle, and is generated once in 1LRCK.
The SV cycle is generated immediately preceding the signal processing program, so it has absolutely no effect
on signal processing, and there is no risk of the sound being cut.
In read/write modes,
Address section + Mode section + Data section
act as one package of data to perform data transmission between the microcomputer and the CXD2720Q.
[Write] • For coefficient RAM
Address section (8 bits)
RVDT
A0
A7
Mode section (8 bits)
M0
M7
Data section (16 bits)
D0
D15
SCK
XLAT
REDY
TRDT
[Read] • For coefficient RAM
Address section (8 bits) Mode section (8 bits)
RVDT
A0
A7
M0
M7
SCK
XLAT
REDY
Data section (16 bits)
TRDT
D0
Note) For both read and write, the data section is 24 bits for the setup register.
Figure 6-1. Examples of Communication
– 19 –
D15
CXD2720Q
(3) Data Structure
Data structure is classified in three types, as shown in the table below. All data communication is done with
LSB first.
Name
Bit length
Contents
Remarks
A0 to A7
8
Address section
M0 to M7
8
Transmission
mode section
D0 to D15/SQ00 to SQ23
16/24
Data section
Coefficient RAM is 16 bits; setup register is
24 bits
Table 6-2. Data Structure
(3)-1. Transmission Mode Section
The transmission mode section is 8 bits and has the following functions.
Bit
Name
M7
XVMT
Function
M6
Reserve
M5
M4
0: ON (No sound)
1: OFF
SO Mute
VS1
Data type
M3
VS0
M2
VS0
0
0
Setup register
Coefficient RAM (K-RAM)
Reserve
M1
M0
VS1
0
1
VRD
Send/Receive
0: Receive
1: Send
Note) Polarity as seen from the CXD2720Q
Table 6-3. Transmission Mode Section
(3)-2. Address Section
The coefficient RAM has a 192-word structure, so the address section is 8 bits. The setup register has a 1word structure, so the address section data may be optional.
(3)-3. Data Section
Sixteen SCK are required, as the coefficient RAM has a 16-bit structure (D0 to D15). The setup register has a
24-bit structure (SQ00 to SQ23), so twenty-four SCK are required.
– 20 –
CXD2720Q
(4) Details of Communication Methods
The definitions of signal timing required for control from the microcomputer are given below.
(4)-1. Write
First, address section data and mode section data are sent from the microcomputer, synchronized to SCK, to
the RVDT pin.
The address section data is 8 bits both for the coefficient RAM and setup register, and the setup register
transmits optional data for 1 word length. Address section data is sent with LSB first.
Mode section data is fixed at 8 bits regardless of content.
The phase relationship between SCK and RV data (data applied to the RVDT pin) has the following restrictions:
• RV data must be verified before SCK rise (tDS ≥ 20ns).
• RV data must be held for 1t + 20ns or more after SCK rise (tDH).
SCK itself has the following restrictions:
• SCK Low level must be 1t+ 20ns or more (tSWL).
• SCK High level must also be 1t + 20ns or more (tSWH).
After raising SCK which corresponds to mode section final data, XLAT is raised (tSLP ≥ 20ns). XLAT Low level
width must be maintained at 1t + 20ns or more (tLWL). Further, fall timing restrictions are:
• for the preceding transmission, if REDY falls due to SCK, as for write, 3t + 20ns or more is required. (tSLD)
• for the preceding transmission, if REDY falls due to XLAT, as for read, 20ns or more is required. (tLDR)
Further, if preceding transmissions have been performed and REDY = Low, it is necessary to wait for REDY =
High to raise XLAT.
The procedure until this point is the same for write and read.
RVDT
A0
A7
M0
tDS
tDH
tSWL
tSWH
M7
D0/SQ00
D15/SQ23
SQ00
SQ23
A0
M7
tSS
SCK
tSLP
tLSD
tBSP
tSLP
XLAT
tSLD or tLWH
tLWL
tSLD
tLDR
tRLP
tSBD
REDY
TRDT
High-Z
Figure 6-2. Write Timing
– 21 –
tLDR
tRLP
CXD2720Q
Data section write begins after XLAT rise, and here also transmission must be with LSB first, with tDS and tDH
restrictions. In addition, after raising XLAT at the starting point for sending to the data section, wait for 3t +
20ns or more for the first SCK rise. (tLSD)
When 16 bits (coefficient RAM) or 24 bits (setup register) of this write is repeated, REDY = Low within 4t + 50ns,
and the microcomputer is informed of waiting status for the SV cycle, which is the dedicated data rewrite cycle
by microcomputer interface. (tSBD)
When REDY goes High again, the corresponding data is written.
The next communication restarts by using the REDY signal as follows.
• When REDY = Low, the SCK for the next transmission can rise (tBSP ≥ 20ns ).
• In the same way, when REDY = Low, the XLAT for the next transmission can fall (tLDR ≥ 20ns).
REDY will fall due to this transmission, but it is prohibited for XLAT to rise for the next transmission before the
REDY rises. Be sure to raise the next XLAT after REDY falls (tRLP ≥ 20ns ).
In order to restart the next transmission without using the REDY signal, the following conditions must be observed:
• There should be 2t + 40ns or more left between the SCK rise for the final data section and the SCK rise for
the next transmission (tSS).
• In the same way, the XLAT for the next transmission can fall after waiting 3t + 20ns or more after the final
data section SCK rise (tSLD).
The tss and tSLD here are shorter times than tSBD ≤ 4t + 50ns, so the restriction conditions are not much strict.
However, even in this case the rise of XLAT for the next transmission must come after REDY rise (tRLP ≥
20ns).
Further, the restriction for XLAT fall at the starting point of this write from tSLD can be:
• tSLD ≥ 3t + 20ns if the preceding transmission was “write”.
– 22 –
CXD2720Q
(4)-2. Read
First, address section and mode section data are transmitted synchronized to SCK, and XLAT is raised
matched with this; the procedure until this point is the same as for write, so the description is omitted here.
Read differs from write in that after XLAT rise, REDY falls within 3t + 50ns (tLBD), and the microcomputer is
informed of SV cycle waiting.
At this time, the TRDT pin changes from high-impedance state to active state (tLDN ≤ 3t + 80ns) simultaneously
with REDY fall. When the read data is ready, the REDY pin changes from Low to High. When the data read out
from the TRDT pin is made TR, and SCK falls (tRSDP ≥ 20ns) when the REDY pin goes High, the first TR data
is defined within 2t + 70ns (tSDD). The microcomputer reads this data at SCK rise. The TR data is read in order
from the LSB with 16 bits for the coefficient RAM and 24 bits for the setup register by adding SCK, the
corresponding data is all read, and then read is completed.
Next, the method for restarting transmission after read is completed is described.
As in Case 1, there is a method for sending address section and mode section data consecutively after reading
all of the 16- or 24-bit data. There should be 2t + 40ns or more left between the SCK rise for the final data read
and the next SCK rise (tss), and this is established by the conditions tSWL ≥ 1t + 20ns and tSWH ≥ 1t + 20ns.
Further, at this read REDY changes from High to Low, but it is prohibited for the XLAT for the next
transmission to fall before this. If REDY = Low has been verified, XLAT can fall (tLDR ≥ 20 ns).
Also, while 16- or 24-bit data is being read from the TRDT pin, address and mode section data writing to the
RVDT pin for the next transmission can be started.
In Case 3, the final section of read data and the final data in the mode section overlap, and this allows shifting
to the next transmission processing in the shortest possible time after data read.
It is also possible to have data read and address and mode section write overlap partially, as shown by Case 2.
– 23 –
CXD2720Q
RVDT
A0
tDS
A7
M0
M7
A0
A1
M7
tDH
SCK
tSWL
tSWH
XLAT
tSLP
tLWL
tRSDP
tSLP
tLBD
tSLD or tLWH
REDY
tLDR
tLDN
tLDR
tRLP
tSDD
TRDT
A0
tDS
A7
M0
tSDD
SQ00
D0/SQ00
case1
RVDT
tSS
tSDD
SQ22
tSDF
SQ23
D14/SQ22 D15/SQ23
M7
A5
A6
M7
tDH
SCK
tSWL
tSWH
XLAT
tSLP
tLWL
tRSDP
tLBD
tSLD or tLWH
REDY
tSLP
tLDR
tLDN
tLDR
tRLP
tSDD
TRDT
A0
tDS
A7
M0
tSDD
SQ00
D0/SQ00
case2
RVDT
tSS
tSDD
SQ22
tSDF
SQ23
D14/SQ22 D15/SQ23
M7
M7
tDH
SCK
tSWL
XLAT
tSWH
tSLP
tLWL
tRSDP
tLBD
tSLD or tLWH
REDY
tSLP
tLDR
tLDN
tLDR
tRLP
tSDD
TRDT
tSDD
SQ00
D0/SQ00
case3
Figure 6-3. Read Timing
– 24 –
tSDD
SQ22
SQ23
D14/SQ22 D15/SQ23
CXD2720Q
7. Setup Register
When the setup register is selected for microcomputer interface transmission mode, the following settings are
possible for serial audio interface and DAC.
Data
section bit
Control
SQ23 to 12 Reserve bit
When system reset is Low
Must be Low for setup register setting
change
All Low
SQ11
LRCK format
0: normal
1: IIS
Normal
SQ10
LRCK polarity selection
0: Lch High
1: Lch Low
Lch High
SQ09
BCK polarity selection
relative to LRCK edge
0: Falling edge
1: Rising edge
Falling edge
SQ08
SI data list
0: MSB first
1: LSB first
(24-bit rearward truncation)
MSB first
SQ07
SI frontward/rearward
truncation
0: Frontward truncation
(valid only for MSB first/24 bits/32 slots) Frontward truncation
1: Rearward truncation
SQ06, 05
SI data word length
SQ06
0
1
SQ04
SO data list
0: MSB first
1: LSB first
LSB first
SQ03
SO frontward/rearward
truncation
0: Frontward truncation
1: Rearward truncation
Frontward truncation
SQ02, 01
SO data word length
SQ02
0
0
1
1
16 bits
SQ00
DAC forced mute
0: ON
1: OFF
SQ05
0
1
SQ01
0
1
0
1
: 16 bits
: 24 bits
: 16 bits
: 18 bits
: 20 bits
: 24 bits
16 bits
ON
Table 7-1.
– 25 –
CXD2720Q
8. Coefficient RAM Setting
When the coefficient RAM is selected in microcomputer interface transmission mode, the coefficient parameters
such as each section's volumes and microphone echo delay amount can be set. Data settings other than those
given following in Tables 8-1 and 8-2 are “don't care”.
(1) Fixed Values for System Initialization
When the system is initialized, the coefficient RAM must be set at the fixed values, shown below, due to
internal operation.
Address
Fixed value
01H
68A9H
02H
5121H
03H
0000H
0DH
0000H
12H
8B2AH
13H
3BF7H
14H
38DFH
15H
4E77H
16H
2E90H
17H
0000H
19H
0000H
1AH
2000H
1BH
4000H
1DH
4000H
20H
0010H
21H
4000H
23H
4000H
24H
1600H
25H
2A00H
26H
3FF0H
27H
8000H
28H
0000H
2DH
0008H
30H
0000H
32H
0000H
41H
8000H
46H
0000H
50H
0008H
58H
0008H
Table 8-1.
∗ For Fs = 44.1kHz. Please inquire with regard to use at other than Fs = 44.1kHz, as the fixed values change.
– 26 –
CXD2720Q
(2) Setting Data
The relationships between the coefficient RAM and each function during DSP operation are as follows.
Address
Name
Function
Setting value
00H
Ki
SI data input level control
Refer to Table 12-1 for setting value
04H
Ke
De-emphasis ON/OFF
ON/AC19H; OFF/0000H
05H
KisLm
SI CH1 data → Lch mix
Refer to Table 12-1 for setting value
06H
KisRc
SI CH2 data → Lch mix
Refer to Table 12-1 for setting value
07H
KiaLm
ADC CH1 data → Lch mix
Refer to Table 12-1 for setting value
08H
KiaRc
ADC CH2 data → Lch mix
Refer to Table 12-1 for setting value
09H
KisRm
SI CH2 data → Rch mix
Refer to Table 12-1 for setting value
0AH
KisLc
SI CH1 data → Rch mix
Refer to Table 12-1 for setting value
0BH
KiaRm
ADC CH2 data → Rch mix
Refer to Table 12-1 for setting value
0CH
KiaLc
ADC CH1 data → Rch mix
Refer to Table 12-1 for setting value
0EH
DC1sw
DC cut1 ON/OFF for accompaniment
ON/4000H; OFF/0000H
0FH
DC1f0
DC cut1 cut-off frequency for accompaniment
Refer to Table 14-1 for setting value
10H
PL
Panpot volume for voice cancellation
Refer to Table 9-1 for setting value
11H
PR
Panpot volume for voice cancellation
Refer to Table 9-1 for setting value
18H
Kvc
Voice cancelling ON/OFF
ON/8000H; OFF/0000H
22H
nRpR
Pitch ratio for accompaniment
Refer to Table 10-1 for setting value
2EH
Ks
Key control ON/OFF for accompaniment
ON/8000H; OFF/0000H
31H
Kimc
Microphone input level control
Refer to Table 12-1 for setting value
33H
DC2f0
DC cut2 cut-off frequency for voice
Refer to Table 14-1 for setting value
34H
DC2sw
DC cut2 ON/OFF for voice
ON/4000H; OFF/0000H
35H
PEQa
PEQ coefficient for voice
Refer to Table 14-4 for setting value
36H
PEQb1
PEQ coefficient for voice
Refer to Table 14-4 for setting value
37H
PEQb2
PEQ coefficient for voice
Refer to Table 14-4 for setting value
38H
PEQg
PEQ coefficient for voice
Refer to Table 14-5 for setting value
39H
HC1a1
High cut1 for voice
Refer to Table 14-2 for setting value
3AH
HC1a0
High cut1 for voice
Refer to Table 14-2 for setting value
3BH
HC1b
High cut1 for voice
Refer to Table 14-2 for setting value
3CH
Kdry
Microphone input direct sound mix
Refer to Table 12-1 for setting value
3DH
Keff
Microphone input echo mix
Refer to Table 12-1 for setting value
3EH
KLm
Key control output Lch mix for accompaniment
Refer to Table 12-1 for setting value
3FH
KRm
Key control output Rch mix for accompaniment
Refer to Table 12-1 for setting value
40H
KLo
System volume Lch
Refer to Table 12-1 for setting value
42H
KRo
System volume Rch
Refer to Table 12-1 for setting value
44H
Tdo
Microphone echo delay amount
Refer to Table 11-1 for setting value
45H
Kre
Microphone echo read tap volume
Refer to Table 12-2 for setting value
Table 8-2 (1). Coefficient RAM Setting Data (1/2)
– 27 –
CXD2720Q
Address
Name
Function
Setting value
47H
Tre
Microphone echo read tap address
Refer to Table 11-1 for setting value
49H
Krd
Microphone echo input sound mix
Refer to Table 12-1 for setting value
4AH
Kfb
Microphone echo reverberation sound mix
Refer to Table 12-1 for setting value
4BH
HC2a1
Microphone echo high cut2
Refer to Table 14-3 for setting value
4CH
HC2a0
Microphone echo high cut2
Refer to Table 14-3 for setting value
4DH
HC2b
Microphone echo high cut2
Refer to Table 14-3 for setting value
53H
VnRpR
Voice pitch ratio
Refer to Table 10-1 for setting value
5AH
Krmc
Microphone input mix
Refer to Table 12-1 for setting value
5BH
Krmp
Voice pitch control output mix
Refer to Table 12-1 for setting value
Table 8-2. Coefficient RAM Setting Data (2/2)
∗ Refer to 13. DSP Signal Flow regarding the names.
9. Voice Canceller Settings
[Relevant pins] PL (address = 10H), PR (address = 11H), Kvc (address = 18H)
The vocal sound set at the center can be cancelled by setting Kvc = 8000H and PL, PR = 7000H.
Voice canceling at other than center setting can be done by the panpot volume.
Panpot volume value is PL for CH1, and PR for CH2, and at the center position they are both 0.857. When
voice cancellation is OFF, set Kvc = 0000H and PL, PR = 0000H.
PL and PR setting values are hexadecimal notation with D15 as MSB and D0 as LSB.
PL
PR
Setting position
PL
PR
Setting position
7000H
7000H
center
7000H
7000H
center
7000H
6000H
6000H
7000H
7000H
5000H
5000H
7000H
7000H
4000H
4000H
7000H
7000H
3000H
3000H
7000H
7000H
2000H
2000H
7000H
7000H
1000H
1000H
7000H
7000H
0000H
0000H
7000H
CH2
Table 9-1. Settings for Voice Canceller Panpot Volume
– 28 –
CH1
CXD2720Q
10. Key Controller Setting
[Relevant coefficients] nRpR (address = 22H), Ks (address = 2EH), VnRpR (address = 53H),
Krmp (address = 5BH)
(1) Key Controller Pitch Ratio
nRpR (D15,.....,D2) is a 2’s complement format with a decimal point between D14 and D13, and sets the
desired pitch ratio directly. (VnRpR has the same type of setting as nRpR.)
15
nRpR = ∑Dn × 2n–14
n=2
The expression range for the pitch ratio is: –2.0 ≤ nRpR ≤ 2.0 – 2–12
but for practical use it is: –0.5 ≤ nRpR ≤ 1.0
or ±1 octave.
Use within a range of ± half an octave is recommended for quality of sound, although it depends on the aim
and the source.
Also, the algorithm is such that allophones will not be generated even when nRpR setting value is changed.
(2) Notes on Key Controller OFF
The pitch does not change when nRpR and VnRpR are set to 0000H (OFF) when the key controller is OFF,
but depending on the internal state during OFF, there is no guarantee that the input value will be output as is.
During OFF, after setting nRpR and VnRpR to 0000H (OFF), set the pitch control section to through state with
the following settings.
Accompaniment controller OFF: Ks = 0000H (OFF)
Voice key controller OFF:
sKrmp = 0000H (OFF)
– 29 –
CXD2720Q
(3) Examples of Key Controller Setting
Examples of pitch ratio setting are illustrated below.
nRpR setting values are hexadecimal notation with D15 as MSB and D2 as LSB for a total of 14 bits.
(D1 and D0 can be optional data.)
CENT
nPpR
CENT
nPpR
0
0000H
0
0000H
+50
01E0H
–50
FE2EH
+100
03CEH
–100
FC69H
+150
05CAH
–150
FAB1H
+200
07D6H
–200
F905H
+250
09F1H
–250
F765H
+300
0C1BH
–300
F5D2H
+350
0E56H
–350
F44AH
+400
10A2H
–400
F2CCH
+450
12FFH
–450
F15AH
+500
156EH
–500
EFF3H
+550
17EEH
–550
EE95H
+600
1A82H
–600
ED42H
+650
1D29H
–650
EBF8H
+700
1FE4H
–700
EAB8H
+750
22B3H
–750
E980H
+800
2597H
–800
E852H
+850
2892H
–850
E72CH
+900
2BA2H
–900
E60EH
+950
2EC9H
–950
E4F9H
+1000
3208H
–1000
E3ECH
+1050
3560H
–1050
E2E6H
+1100
38D0H
–1100
E1E8H
+1150
3C5BH
–1150
E0F1H
+1200
4000H
–1200
E000H
Table 10-1. Pitch Ratio Setting Examples
The numeric representation format for pitch ratio here is:
15
nRpR = ∑Dn × 2n–14
n=2
The numeric representation range is: –2.0 ≤ nRpR ≤ 2.0 – 2–12
Also, the relationship formula with music word cent value C is:
C
nRpR = 2 1200 – 1, C = 1200 log2 [nRpR + 1] [cent]
The semitone at average ratio is 100 [cent].
– 30 –
CXD2720Q
11. Microphone Echo Delay Amount Setting
[Relevant coefficients] Tdo (address = 44H), Tre (address = 47H)
Microphone echo delay amount can be varied by setting coefficient Tdo (12 bits from D14 to D3) values. The
relationships between the coefficient and the delay amount are shown in Table 11-1.
Coefficient Tre (12 bits from D14 to D3) is microphone input echo initial delay time.
Set in the range of 0008H to Tdo.
Setting value Tdo
0008H
0010H
0018H
·
·
·
·
7ff0H
7ff8H
0000H
4096step
Delay (fs = 44.1kHz)
0.045ms
·
·
·
·
·
·
·
·
185.76ms
0.045 ms/step
setting possible
Table 11-1. Microphone Echo Delay Amount Setting
∗ When Fs = 44.1kHz. Please inquire with regard to use at other than Fs = 44.1kHz, as the delay amount changes.
– 31 –
CXD2720Q
12. Input/Output Level Settings
[Relevant coefficients] Ki (address = 00H), KisLm (address = 05H), KisRc (address = 06H),
KiaLm (address = 07H), KiaRc (address = 08H), KisRm (address = 09H),
KisLc (address = 0AH), KiaRm (address = 0BH), KiaLc (address = 0CH),
Kimc (address = 31H), Kdry (address = 3CH), Keff (address = 3DH),
KLm (address = 3EH), KRm (address = 3FH), KLo (address = 40H),
KRo (address = 42H), Kre (address = 45H), Krd (address = 49H),
Kfb (address = 4AH), Krmc (address = 5AH), Krmp (address = 5BH)
The input/output levels and volumes are 2’s complement format with a decimal point between D15 and D14,
and hexadecimal notation with D15 as MSB and D0 as LSB.
The coefficient and level relationships are as follows.
D15 to D0
Level
D15 to D0
Level
8000H
↓
FFFFH
0000H
0dB
↓
–90.31dB
–∞
8000H
↓
FFFFH
0000H
+12.04dB
↓
–78.27dB
–∞
Table 12-1. Input/Output Level Settings
(other than Kre)
Table 12-2. Input/Output Level Settings
(Kre)
The input/output levels for 8001H to FFFEH are determined by the following formulas.
14
(Coefficient value) = [ (–1) × D15 + ∑Dn × 2n–15] × (–1)
for other than Kre
n=0
14
(Coefficient value) = [ (–1) × D15 + ∑Dn × 2n–15] × (–4)
for Kre
n=0
Input/output level = 20 log [coefficient value] dB
∗ D15 to D0 are negative values, but the calculation is (–1) × (D15 to D0).
– 32 –
– 33 –
Decimation
ADC
AD2
31H
–Kimc
DC Cut1
0EH 0FH
DC Cut1
–Krd
Down
Sampling
49H
DC Cut2
33H 34H
–Kfb 4AH
5BH
5AH
–Krmp
–Krmc
0BH –KiaRm
0CH –KiaLc
09H –KisRm
0AH –KisLc
08H –KiaRc
07H –KiaLm
06H –KisRc
05H –KisLm
High Cut2
4BH 4CH 4DH
53H
Pitch
Control
∗ Refer to the coefficient RAM setting for information on each coefficient.
Decimation
DeEmphasis
04H
DeEmphasis
Decimation
ADC
–Ki 00H
–Ki
ADC
AD1
SI2
SI1
MIC
13. DSP Signal Flow
45H
11H 18H
Tdo
44H
Pitch
Control
22H 2EH
Pitch
Control
Over
Sampling
–Kre
Tre
47H
Delay Line
39H
High Cut1
3AH 3BH
10H
Voice
Cancel
Tdi
35H 36H
PEQ
37H 38H
3FH
–KRm
3EH
–KLm
3CH
–Kdry
3DH
–Keff
42H
–KRo
40H
–KLo
Over
Sampling
Over
Sampling
DAC
DAC
DA2
SO2
DA1
SO1
CXD2720Q
CXD2720Q
14. Filter Coefficient Table
[Relevant coefficient] DC1f0 (address = 0FH), DC2f0 (address = 33H), HC1b (address = 3BH),
HC1a1 (address = 39H), HC1a0 (address = 3AH), HC2b (address = 4DH),
HC2a1 (address = 4BH), HC2a0 (address = 4CH), PEQa (address = 35H),
PEQb1 (address = 36H), PEQb2 (address = 37H), PEQg (address = 38H)
The cut-off frequencies and PEQ gain, Q, and center frequency settings for each signal flow filter are shown in
Tables 13-1 to 13-5.
Note that if the above setting values are changed during DSP operation, the output level becomes unstable for
several 1/fs.
Tables 14-1 to 14-5 and digital de-emphasis are given for fs = 44.1kHz. Please inquire with regard to using an
fs other than this value.
(1) DC Cut1 for Accompaniment/ DC Cut2 for Voice
Cut-off
frequency (Hz)
DC1f0
DC2f0
Cut-off
frequency (Hz)
DC1f0
DC2f0
Cut-off
frequency (Hz)
DC1f0
DC2f0
Cut-off
frequency (Hz)
DC1f0
DC2f0
20
30
40
50
60
70
80
90
100
110
120
130
140
150
160
170
180
190
200
210
220
230
240
250
260
7FA2
7F74
7F45
7F17
7EE9
7EBA
7E8C
7E5E
7E30
7E02
7DD4
7DA6
7D78
7D4B
7D1D
7CEF
7CC2
7C94
7C67
7C39
7C0C
7BDF
7BB2
7B85
7B58
270
280
290
300
310
320
330
340
350
360
370
380
390
400
410
420
430
440
450
460
470
480
490
500
510
7B2B
7AFE
7AD1
7AA4
7A77
7A4B
7A1E
79F1
79C5
7998
796C
7940
7914
78E7
78BB
788F
7863
7837
780B
77DF
77B4
7788
775C
7731
7705
520
530
540
550
560
570
580
590
600
610
620
630
640
650
660
670
680
690
700
710
720
730
740
750
760
76D9
76AE
7683
7657
762C
7601
75D6
75AB
7580
7555
752A
74FF
74D4
74A9
747E
7454
7429
73FF
73D4
73AA
737F
7355
732B
7301
72D6
770
780
790
800
810
820
830
840
850
860
870
880
890
900
910
920
930
940
950
960
970
980
990
1000
72AC
7282
7258
722E
7204
71DB
71B1
7187
715D
7134
710A
70E1
70B7
708E
7064
703B
7012
6FE9
6FBF
6F96
6F6D
6F44
6F1B
6EF2
Table 14-1.
– 34 –
CXD2720Q
(2) High Cut1 for Voice
Cut-off
frequency (Hz)
HC1b
HC1a1
HC1a0
Cut-off
frequency (Hz)
HC1b
HC1a1
HC1a0
1000
1100
1200
1300
1400
1500
1600
1700
1800
1900
2000
2100
2200
2300
2400
2500
2600
2700
2800
2900
3000
3100
3200
3300
3400
3500
3600
3700
3800
3900
4000
4100
4200
4300
4400
4500
4600
4700
4800
4900
5000
5100
5200
5300
5400
5500
6EF2
6D5C
6BCB
6A3E
68B6
6733
65B4
6439
62C3
6150
5FE2
5E77
5D11
5BAE
5A4E
58F2
579A
5645
54F3
53A4
5259
5110
4FCB
4E88
4D48
4C0B
4AD0
4998
4863
4730
4600
44D2
43A6
427C
4155
4030
3F0D
3DEC
3CCD
3BAF
3A94
397B
3863
374D
3639
3527
0886
0951
0A1A
0AE0
0BA4
0C66
0D25
0DE3
0E9E
0F57
100E
10C4
1177
1228
12D8
1386
1432
14DD
1586
162D
16D3
1777
181A
18BB
195B
19FA
1A97
1B33
IBCE
1C67
1CFF
1D96
1E2C
1EC1
1F55
1FE7
2079
2109
2199
2228
22B5
2342
23CE
2459
24E3
256C
F77A
F6AF
F5E6
F520
F45C
F39A
F2DB
F21D
F162
F0A9
EFF2
EF3C
EE89
EDD8
ED28
EC7A
EBCE
EB23
EA7A
E9D3
E92D
E889
E7E6
E745
E6A5
E606
E569
E4CD
E432
E399
E301
E26A
E1D4
E13F
E0AB
E019
DF87
DEF7
DE67
DDD8
DD4B
DCBE
DC32
DBA7
DB1D
DA94
5600
5700
5800
5900
6000
6100
6200
6300
6400
6500
6600
6700
6800
6900
7000
7100
7200
7300
7400
7500
7600
7700
7800
7900
8000
8100
8200
8300
8400
8500
8600
8700
8800
8900
9000
9100
9200
9300
9400
9500
9600
9700
9800
9900
10000
OFF
3416
3306
31F9
30EC
2FE2
2ED8
2DD0
2CCA
2BC4
2AC0
29BD
28BC
27BB
26BC
25BD
24C0
23C4
22C9
21CF
20D5
1FDD
1EE6
1DEF
1CF9
1C04
1B10
1A1C
192A
1838
1746
1655
1565
1475
1386
1298
11A9
10BC
0FCF
0EE2
0DF5
0D09
0C1E
0B32
0A47
095C
0000
25F4
267C
2703
2789
280E
2893
2917
299A
2A1D
2A9F
2B21
2BA1
2C22
2CA1
2D21
2D9F
2E1D
2E9B
2F18
2F95
3011
308C
3108
3183
31FD
3277
32F1
336A
33E3
345C
34D5
354D
35C5
363C
36B3
372B
37A1
3818
388E
3905
397B
39F0
3A66
3ADC
3B51
0000
DA0C
D984
D8FD
D877
D7F2
D76D
D6E9
D666
D5E3
D561
D4DF
D45F
D3DE
D35F
D2DF
D261
D1E3
D165
D0E8
D06B
CFEF
CF74
CEF8
CE7D
CE03
CD89
CD0F
CC96
CC1D
CBA4
CB2B
CAB3
CA3B
C9C4
C94D
C8D5
C85F
C7E8
C772
C6FB
C685
C610
C59A
C524
C4AF
8000
Table 14-2.
– 35 –
CXD2720Q
(3) High Cut2 for Microphone Echo
Cut-off
frequency (Hz)
HC2b
HC2a1
HC2a0
Cut-off
frequency (Hz)
HC2b
HC2a1
HC2a0
1000
1100
1200
1300
1400
1500
1600
1700
1800
1900
2000
2100
2200
2300
2400
2500
2600
2700
2800
2900
3000
3100
3200
3300
3400
3500
3600
3700
3800
3900
4000
4100
4200
4300
4400
4500
4600
4700
4800
4900
5000
5100
5200
5300
5400
5500
5FE2
5D11
5A4E
579A
54F3
5259
4FCB
4D48
4AD0
4863
4600
43A6
4155
3F0D
3CCD
3A94
3863
3639
3416
31F9
2FE2
2DD0
2BC4
29BD
27BB
25BD
23C4
21CF
1FDD
1DEF
1C04
1A1C
1838
1655
1475
1298
10BC
0EE2
0D09
0B32
095C
0788
05B3
03E0
020D
003A
100E
1177
12D8
1432
1586
16D3
181A
195B
1A97
1BCE
1CFF
1E2C
1F55
2079
2199
22B5
23CE
24E3
25F4
2703
280E
2917
2A1D
2B21
2C22
2D21
2E1D
2F18
3011
3108
31FD
32F1
33E3
34D5
35C5
36B3
37A1
388E
397B
3A66
3B51
3C3B
3D26
3E0F
3EF9
3FE2
EFF2
EE89
ED28
EBCE
EA7A
E92D
E7E6
E6A5
E569
E432
E301
E1D4
E0AB
DF87
DE67
DD4B
DC32
DB1D
DA0C
D8FD
D7F2
D6E9
D5E3
D4DF
D3DE
D2DF
D1E3
D0E8
CFEF
CEF8
CE03
CD0F
CC1D
CB2B
CA3B
C94D
C85F
C772
C685
C59A
C4AF
C3C5
C2DA
C1F1
C107
C01E
5600
5700
5800
5900
6000
6100
6200
6300
6400
6500
6600
6700
6800
6900
7000
7100
7200
7300
7400
7500
7600
7700
7800
7900
8000
8100
8200
8300
8400
8500
8600
8700
8800
8900
9000
9100
9200
9300
9400
9500
9600
9700
9800
9900
10000
OFF
FE68
FC95
FAC2
F8EE
F719
F543
F36C
F194
EFBB
EDE0
EC02
EA23
E841
E65D
E476
E28C
E09F
DEAE
DCBA
DAC1
D8C5
D6C4
D4BE
D2B3
D0A3
CE8E
CC72
CA50
C828
C5F9
C3C2
C184
BF3E
BCEF
BA98
B837
B5CC
B357
B0D7
AE4C
ABB5
A911
A660
A3A1
A0D4
0000
40CC
41B5
429F
4389
4473
455E
464A
4736
4822
4910
49FF
4AEE
4BDF
4CD1
4DC5
4EBA
4FB0
50A9
51A3
529F
539D
549E
55A1
56A6
57AE
58B9
59C7
5AD8
5BEC
5D03
5E1F
5F3E
6061
6188
62B4
63E4
651A
6654
6794
68DA
6A25
6B77
6CD0
6E2F
6F96
0000
BF34
BE4B
BD61
BC77
BB8D
BAA2
B9B6
B8CA
B7DE
B6F0
B601
B512
B421
B32F
B23B
B146
B050
AF57
AE5D
AD61
AC63
AB62
AA5F
A95A
A852
A747
A639
A528
A414
A2FD
A1E1
A0C2
9F9F
9E78
9D4C
9C1C
9AE6
99AC
986C
9726
95DB
9489
9330
91D1
906A
8000
Table 14-3.
– 36 –
CXD2720Q
(4) PEQ for Voice
Center
frequency (Hz)
PEQa
PEQb1
PEQb2
Gain (dB)
PEQg
250.0
280.6
315.0
353.6
396.9
445. 4
500. 0
561.2
630.0
707.1
793.7
890.9
1000. 0
1122.5
1259.9
1414.2
1587.4
1781.8
2000.0
2244.9
2519.8
2828.4
3174.8
3563.6
4000.0
4489.8
5039.7
5656.9
6349.6
7127.2
8000.0
023D
0282
02CF
0325
0385
03F0
0467
04EC
0580
0624
06DB
07A6
0886
097E
0A91
0BC0
0D0D
0E7C
100E
11C7
13A8
15B5
17F1
1A5E
1CFF
1FD8
22ED
2642
29DB
2DC1
31FD
7DAE
7D64
7D10
7CB2
7C47
7BCF
7B48
7AAE
7A01
793D
785E
7762
7643
74FD
738B
71E5
7004
6DE0
6B6D
68A1
656E
61C6
5D97
58CF
535A
4D24
4617
3E23
353B
2B5C
2097
847B
8505
859F
864B
870B
87E1
88CF
89D9
8B01
8C4A
8DB7
8F4D
910E
92FE
9524
9781
9A1C
9CFA
A01E
A38F
A752
AB6C
AFE4
B4BE
BA00
BFB2
C5DC
CC85
D3B8
DB84
E3FC
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
6.5
7.0
7.5
8.0
8.5
9.0
9.5
10.0
10.5
11.0
11.5
12.0
0000
01E5
03E7
0608
0849
0AAC
0D33
0FE1
12B7
15B8
18E7
1C46
1FD9
23A1
27A3
2BE2
3061
3524
3A30
3F88
4531
4B30
518A
5844
5F64
Table 14-5.
Table 14-4.
– 37 –
CXD2720Q
Filter Characteristics
ADC Filter Characteristics (43rd + 15th FIR)
Stop band
Pass band
500.00
0.00
400.00
–10.00
300.00
–20.00
–30.00
100.00
Response [dB]
Response [dB × 10–3]
200.00
0.00
–100.00
–200.00
–300.00
–400.00
–40.00
–50.00
–60.00
–70.00
–500.00
–80.00
–600.00
–90.00
–700.00
–800.00
–100.00
0
5
10
15
1fs
20
Frequency [kHz]
2fs
Frequency [kHz]
DAC Filter Characteristics (43rd + 7th FIR)
Stop band
Pass band
0.00
500.00
400.00
–10.00
300.00
–20.00
–30.00
100.00
Response [dB]
Response [dB × 10–3]
200.00
0.00
–100.00
–200.00
–300.00
–40.00
–50.00
–60.00
–70.00
–400.00
–500.00
–80.00
–600.00
–90.00
–700.00
–800.00
–100.00
0
5
10
15
1fs
20
Frequency [kHz]
Frequency [kHz]
– 38 –
2fs
SIN
DA16
BCK
DA15
LRCK
LRCK
DGND
DGND
CXD2500Q
XTAI
DGND
0.01
DGND
84 85
DGND
83
81 82
80 VSS6
79 NC
78 NC
77 NC
76 NC
75 NC
74 NC
73 NC
72 NC
71 NC
70 VDD2
69 VSS5
68 NC
67 NC
66 NC
65 NC
64 NC
63 NC
62 NC
61 NC
CXD2720Q
86 87
88
91 92
0.01
DGND
90
DGND
89
93 94
97
95 96
E
AGND
D
AGND
3
2
RVDT
VSS0
DGND DGND
0.01
AVS0
1
5
Microcomputer
6
REDY
4
7
TRDT
SCK
XWO
8
XLAT
XRST
9
DGND
DGND
0.01
DGND
DGND
DGND
0.01
AGND
0.01
XWO
98 99 100
0.01
B
AGND
AGND
0.01
XRST
VSS1 10
VDD0 11
SO 12
XS24 13
TST0 14
TST1 15
TST2 16
TST3 17
TST4 18
TST5 19
VSS2 20
AIN3 22
AVS3 21
59 NC
60 NC
AVD4 24
AVD3 23
AO1P 25
56 NC
57 NC
AO1N 26
55 NC
58 NC
AVS4 27
54 NC
X768
DGND
AIN1 29
AVS1 28
52 NC
AVD1 30
31
34 33 32
36 35
38 37
39
40
41
42
43
44
46 45
53 VSS4
51 NC
C
0.01 0.01
F
47
DGND AGND
20p AGND
768fs
A
0.01
AGND AGND
20p
AGND
49 48
0.01
AGND AGND
50
NC
INVI
BFOT
5532 operational amplifier used
NC
NC
: Digital power supply + 5V
NC
: AO2 +5V power supply
DGND
BCK
F
SI
: AO1 +5V power supply
VSS7
: AIN3 +5V power supply
NC
E
AVD5
NC
D
NC
: AIN2 +5V power supply
AIN2
NC
: AIN1 +5V power supply
NC
XTLI
NC
B
NC
XVSS
NC
– 39 –
AVD0
C
NC
: Crystal oscillator circuit +5V power supply
NC
NC
: DA operational amplifier –12V power supply
: AD operational amplifier –12V power supply
3
VSS3
VDD1
4
: DA operational amplifier +12V power supply
2
AVS5
A
: AD operational amplifier +12V power supply
1
AO2P
LRCK
AO2N
XMST
AVD2
NC
AVS2
NC
XVDD
XTLO
VDD3
Application Circuit
22k
22k
22k
22k
12k
100p
6 39k
AGND
5
100k
6
5
100p
AGND
5
100k
6
7
7
7
7
7
1.8k
10k
1.8k
1.8k
10k
3
2
3
2
3
2
3
2
3
2
AGND
1200p
2200p
1.8k
AGND
220p
1000p
10k
AGND
1200p
2200p
1.8k
AGND
1200p
2200p
1.8k
AGND
220p
1000p
10k
3
1
4
2
3
1
3
1
4
2
4
8
4
8
4
8
4
8
4
8
0.01
AGND
AGND
1
10µ
1M
CH1 OUT
AGND
1M
AGND
330k
AGND
1M
AGND
AGND
10µ 4.7k
0.01
0.01
AGND
AGND
1
10µ 4.7k
0.01
0.01
AGND
AGND
1
CH2 OUT
AGND
330k
AGND
10µ 4.7k
0.01
0.01
AGND
AGND
1
10µ
0.01
0.01
AGND
AGND
1
0.01
Application circuits shown are typical examples illustrating the operation of
the devices. Sony cannot assume responsibility for any problems arising out
of the use of these circuits or for any infringement of third party patent and
other right due to same.
AGND
CH3 IN
6
5
100k
AGND
AGND AGND
39k
AGND
CH1 IN
AGND
CH2 IN
6 39k
5
100p
AGND AGND
39k
220p
12k
12k
220p
12k
100p
CXD2720Q
CXD2720Q
Unit: mm
100PIN QFP (PLASTIC)
+ 0.4
14.0 – 0.01
17.9 ± 0.4
15.8 ± 0.4
+ 0.1
0.15 – 0.05
23.9 ± 0.4
+ 0.4
20.0 – 0.1
A
0.65
+ 0.35
2.75 – 0.15
±0.12 M
(16.3)
0.15
0° to 15°
DETAIL A
0.8 ± 0.2
Package Outline
PACKAGE STRUCTURE
SONY CODE
QFP-100P-L01
EIAJ CODE
∗QFP100-P-1420-A
JEDEC CODE
– 40 –
PACKAGE MATERIAL
EPOXY RESIN
LEAD TREATMENT
SOLDER PLATING
LEAD MATERIAL
COPPER / 42 ALLOY
PACKAGE WEIGHT
1.4g