SONY CXD2728Q

CXD2728Q
Single-Chip Dolby Pro Logic Surround Decoder
Description
The CXD2728Q is a CMOS LSI developed for
Dolby Pro Logic Surround. A SRAM for short delay
and AD/DA converters are built in, and all functions
necessary for Dolby Pro Logic Surround such as an
adaptive matrix, a passive decoder including
Modified Dolby B-type NR, auto input balance, a
noise sequencer and center channel mode control
are contained on a single chip. Further, this LSI also
supports Dolby 3 Stereo and Virtual Dolby Surround.
Features
• Dolby Pro Logic Surround decoding with a single
chip
• 2-channel 1-bit AD converter and decimation filter
• 4-channel 1-bit DA converter and oversampling filter
• 32K-bit SRAM for short delay
• No separation or other variance for digital
processing
• External parts reduced due to the built-in AD/DA
converters
80 pin QFP (Plastic)
Recommended Operating Conditions
• Supply voltage VDD
3.0 to 3.6 (3.3 typ.)
V
AVDD
3.1 to 3.5 (3.3 typ.)
V
Note) Use this IC under the following condition
during the normal operation except for the
power on.
• Supply voltage difference VDD ≤ AVDD + 0.3
V
VSS ≤ AVSS – 0.3
V
• Operating temperature
Ta
–20 to +75
°C
Functions
• Adaptive matrix
• Center channel mode control
(Normal/Phantom/Wide)
• Dolby 3 Stereo
• Auto input balance control (ON/OFF)
• Noise sequencer
• Variable delay time (0 to 46.4ms)
• 7kHz low-pass filter (12dB/Oct)
• Modified Dolby B-type NR
• Simple SFC function
• Virtual Dolby Surround
• SFC mode
Input/Output Capacitance (VDD = VI = 0V, f = 1MHz)
• Input capacitance CIN
9 (max.)
pF
• Output capacitance COUT
11 (max.)
pF
• Input/output capacitance
CI/O
11 (max.)
pF
Maximum Current Consumption
(Ta = 25°C, VDD = 3.6V)
• Digital/analog block total: 75.8mA
Absolute Maximum Ratings (Ta = 25°C, VSS = 0V)
• Supply voltage VDD
VSS – 0.5 to +4.6
V
AVDD ∗1 AVss – 0.5 to + 4.6
V
• Input voltage VID
VSS – 0.5 to VDD + 0.5
V
∗2 Vss – 0.5 to 5 to Min (VDD + 4.6, 7.0) V
VIA ∗3 AVss – 0.5 to AVD + 0.5 V
• Output voltage VOD
VSS – 0.5 to VDD + 0.5
V
∗4 Vss – 0.5 to Min (VDD + 4.6, 7.0) V
VOA ∗3 AVss – 0.5 to AVDD + 0.5 V
• Storage temperature
Tstg
–55 to +150
°C
∗1 Analog power supply including AVDX
∗2 Pins 28, 31, 32 and 76
∗3 Analog input/output pin
∗4 Pin 29
Dolby level
• During analog input: 200 to 300mVrms
• During digital input: –20dBFS
Analog Characteristics
Conditions: Pro Logic ON
Measurement at Dolby level = 300mVrms
• S/N: L, Rch = 72dB, C, Sch = 70dB
• THD + N: L, Rch = 0.03%, C, Sch = 0.03%
∗ All values typ.
Structure
Silicon gate CMOS
Applications
Equipment having Dolby Pro Logic Surround
function such as AV amplifiers, receivers and
compact music systems
This device is available only to parties obtaining the license from Dolby Laboratories Licensing Corporation.
"Dolby", the double-D symbol
and "Pro Logic" are trademarks of Dolby Laboratories Licensing Corporation.
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E98Z02-PS
CXD2728Q
Block Diagram
32K bit DELAY RAM
RVDT 32
ADC1
25 LIN
ADC2
80 RIN
MICROCOMPUTER
I/F
SCK 28
XLAT 31
REDY 29
20 AO1N
DSP
DAC1
21 AO1P
LRCK 41
BCK 39
DAC2
SERIAL
DATA
I/F
SI 37
4
AO2N
5
AO2P
16 AO3N
DAC3
17 AO3P
XMST 42
CLOCK GENERATOR
/TIMING CIRCUIT
13
12
8
AO4N
9
AO4P
35
BFOT
XTLO
XTLI
DAC4
LRCK
T.P
XMST
T.P
T.P
VSS2
T.P
T.P
T.P
T.P
VDD2
T.P
T.P
T.P
T.P
T.P
VSS3
T.P
T.P
T.P
T.P
T.P
T.P
T.P
Pin Configuration
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
VSS4 65
40 VSS1
T.P 66
39 BCK
T.P 67
38 T.P
T.P 68
37 SI
T.P 69
36 T.P
T.P 70
35 BFOT
VDD0 71
34 XS24
T.P 72
33 VDD1
T.P 73
32 RVDT
T.P 74
31 XLAT
T.P 75
30 T.P
29 REDY
XRST 76
T.P 77
28 SCK
VSS5 78
27 VSS0
AVS2 79
26 AVS1
RIN 80
LREF
AVD1
AVD3
AO1P
AVS3
AO1N
AO4P
AVS5
AO4N
AO3P
AVS6
AO3N
AVS4
–2–
AVD5
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
AVSX
8
XTLI
7
XTLO
6
AVDX
5
AVD6
4
AO2P
AVD2
3
AVD4
2
AO2N
1
RREF
25 LIN
CXD2728Q
Pin Description
Pin No.
Symbol
Notations in parentheses indicate the fixed pin connection status.
Description
I/O
1
RREF
O
R-ch AD converter reference.
2
AVD2
—
R-ch AD converter power supply.
(AVDD)
3
AVD4
—
R-ch DA converter power supply.
(AVDD)
4
AO2N
O
R-ch DA converter opposite phase PWM output.
5
AO2P
O
R-ch DA converter forward phase PWM output.
6
AVS4
—
R-ch DA converter GND.
(AVSS)
7
AVS6
—
S-ch DA converter GND.
(AVSS)
8
AO4N
O
S-ch DA converter opposite phase PWM output.
9
AO4P
O
S-ch DA converter forward phase PWM output.
10
AVD6
—
S-ch DA converter power supply.
(AVDD)
11
AVDX
—
Oscillator analog power supply.
(AVDD)
12
XTLO
O
Oscillator output.
13
XTLI
I
Oscillator input.
14
AVSX
—
Oscillator analog GND.
(AVSS)
15
AVD5
—
C-ch DA converter power supply.
(AVDD)
16
AO3N
O
C-ch DA converter opposite phase PWM output.
17
AO3P
O
C-ch DA converter forward phase PWM output.
18
AVS5
—
C-ch DA converter GND.
(AVSS)
19
AVS3
—
L-ch DA converter GND.
(AVSS)
20
AO1N
O
L-ch DA converter opposite phase PWM output.
21
AO1P
O
L-ch DA converter forward phase PWM output.
22
AVD3
—
L-ch DA converter power supply.
(AVDD)
23
AVD1
—
L-ch AD converter power supply.
(AVDD)
24
LREF
O
L-ch AD converter reference.
25
LIN
I
L-ch AD converter analog input
26
AVS1
—
L-ch AD converter GND.
27
VSS0
—
Digital GND.
28
SCK
I
Shift clock input for microcomputer interface.
29
REDY
O
Transfer enabling signal output for microcomputer interface. Transfer prohibited
when Low.
30
T.P
O
Test monitor. Normally outputs Hi-Z.
31
XLAT
I
Latch input for microcomputer interface.
32
RVDT
I
Data input for microcomputer interface.
33
VDD1
—
(AVSS)
(VSS)
Digital power supply.
(OPEN)
(VDD)
(OPEN): Open, (VDD): +3.3V digital power supply, (AVDD): +3.3V analog power supply
(Vss): Digital GND, (AVss): Analog GND
–3–
CXD2728Q
Notations in parentheses indicate the fixed pin connection status.
Pin No.
Symbol
I/O
Description
34
XS24
I
Serial data 24-/32-bit slot selection. 24-bit slot when Low. [valid for slave mode]
35
BFOT
O
Clock frequency-division output. (384/768/256/512fs)
36
T.P
O
Test output. Normally outputs Low.
37
SI
I
1-sampling 2-channel serial data input.
38
T.P
I
Test input. Normally inputs Low.
39
BCK
I/O
Serial bit transfer clock for serial input data SI.
40
VSS1
—
Digital GND.
41
LRCK
I/O
Sampling frequency clock for serial input data SI.
42
XMST
I
BCK and LRCK master/slave mode switching input. Master mode when Low.
I
Test input. Normally inputs Low.
(VSS)
Digital GND.
(VSS)
Test input. Normally inputs Low.
(VSS)
Digital power supply.
(VDD)
Test input. Normally inputs Low.
(VSS)
Digital GND.
(VSS)
Test input. Normally inputs Low.
(VSS)
Digital GND.
(VSS)
Test input. Normally inputs Low.
(VSS)
Digital power supply.
(VDD)
I
Test input. Normally inputs Low.
(VSS)
43 to 45 T.P
46
VSS2
47 to 50 T.P
51
VDD2
52 to 56 T.P
57
VSS3
58 to 64 T.P
65
VSS4
66 to 70 T.P
71
VDD0
72 to 75 T.P
—
I
—
I
—
I
—
I
—
(OPEN)
(VSS)
(VSS)
76
XRST
I
System reset input. Reset when Low.
77
T.P
I
Test input. Normally inputs High.
(VDD)
78
VSS5
—
Digital GND.
(VSS)
79
AVS2
—
R-ch AD converter GND.
80
RIN
I
(AVSS)
R-ch AD converter analog input.
(OPEN): Open, (VDD): +3.3V digital power supply, (AVDD): +3.3V analog power supply
(Vss): Digital GND, (AVss): Analog GND
∗ The CXD2728Q has 3 digital and 7 analog power supplies and the order of turning them on is not specified.
–4–
CXD2728Q
DC Characteristics
(VDD0 to 2 = 3.0 to 3.6V, AVD1 to 6 = AVDX = 3.1 to 3.5V, AVS1 to 6 = AVSX = VSS0 to 5 = 0V, Ta = –20 to +75°C)
Item
Symbol
Input voltage
(1)
High level VIH
Input voltage
(2)
High level VIH
Input voltage
(3)
High level VIH
Low level
Low level
Low level
Input voltage (4)
VIL
VIL
VIL
CMOS input
Schmitt input
LVTTL input
Min.
Typ.
Max.
Unit
Applicable pins
V
∗1, ∗2, ∗6, ∗7
V
∗1, ∗2, ∗6, ∗7
V
∗5
V
∗5
V
∗3
0.8
V
∗3
VDD
V
∗4
V
∗8, ∗9, ∗13
V
∗8, ∗9, ∗13
V
∗11
0.7VDD
0.3VDD
0.8VDD
0.2VDD
2.0
Analog input
VSS
Output voltage High level VOH
(1)
Low level VOL
IOH = –4.0mA
VDD – 0.4
Output voltage High level VOH
(2)
Low level VOL
IOH = –12.0mA
IOL = 12.0mA
VDD/2
V
∗11
Output voltage (3) Low level
VOL
IOL = 4.0mA
0.4
V
∗10
Input leak current (1)
II
VIH = VDD, VSS
–10
10
µA
∗1, ∗7
Input leak current (2)
II
VIH = VDD, VSS
–40
40
µA
∗2, ∗3, ∗5, ∗6
Output leak current
IOZ
VIH = VDD, VSS
–40
40
µA
∗9, ∗10
Feedback resistance
RFB
2.5M
Ω
Resistance between ∗7 and ∗11
∗1
∗2
∗3
∗4
∗5
∗6
∗7
∗8
∗9
∗10
∗11
∗12
∗13
VIN
Conditions
IOL = 4.0mA
0.4
VDD/2
250k
TST0 to TST4, XMST
XS24, SI
SCK, XLAT, RVDT
LIN, RIN
XRST
During input to bidirectional pins BCK, LRCK
XTLI
During output from bidirectional pins BCK, LRCK
BFOT
REDY
XTLO
LREF, RREF
AO1P, AO1N, AO2P, AO2N, AO3P, AO3N, AO4P, AO4N
–5–
1M
CXD2728Q
AC Characteristics
(VDD0 to 2 = 3.0 to 3.6V, AVD1 to 6 = AVDX = 3.1 to 3.5V, AVS1 to 6 = AVDX = VSS0 to 5 = 0V, Ta = –20 to +75°C)
Input Timing from Power-on to Input Pin
VDD
0.95VDD
Determined by the crystal and other external circuit conditions
Stable (clock applied correctly)
·····
XTLI
1/fs or more
2.0V
0.8V
XRST
1/fs or more
Input pins
0.7VDD
0.2VDD
First input
Serial Audio Interface Timing
[Slave mode]
0.7VDD
0.2VDD
BCK
tSSI
tHSI
0.7VDD
0.2VDD
SI
tSLR
tHLR
0.7VDD
0.2VDD
LRCK
[Master mode]
BCK
tDLR
LRCK
Item
SI setup time
SI hold time
LRCK setup time
LRCK hold time
LRCK delay time
Symbol
tSSI
tHSI
tSLR
tHLR
tDLR
Conditions
Min.
Max.
Unit
Slave mode
20
ns
Slave mode
40
ns
Slave mode
20
ns
Slave mode
40
ns
Master mode, CL = 120pF
–6–
50
ns
CXD2728Q
Microcomputer Interface Timing
Transfer timing for address section, transfer mode section and data section LSB
RVDT
Address LSB
Mode MSB
tSWL
tDS
tSWH
2.0V
0.8V
Data LSB
Data MSB
tDH
SCK
tSLP
2.0V
0.8V
XLAT
tLWL
tLSD
2.0V
0.8V
REDY
Transfer timing from data section MSB to address section and transfer mode section
RVDT Data MSB
Address LSB
Mode MSB
2.0V
0.8V
tSS
2.0V
0.8V
SCK
tSLD
XLAT
2.0V
0.8V
tLDR
tSBD
tRLP
tBSP
REDY
Item
RVDT data setup time relative to SCK rise
RVDT data hold time from SCK rise
SCK Low level width
SCK High level width
XLAT Low level width
XLAT High level width
SCK rise preceding time relative to XLAT rise
SCK rise wait time relative to XLAT rise
Delay time to REDY fall relative to SCK rise
REDY fall preceding time relative to SCK rise
REDY rise preceding time relative to XLAT rise
REDY rise preceding time relative to SCK fall
XLAT fall wait time relative to SCK rise
XLAT fall delay time relative to REDY fall
SCK rise wait time for next transfer
Symbol
Min.
tDS
tDH
tSWL
tSWH
tLWL
tLWH
tSLP
tLSD
tSBD
tBSP
tRLP
tRSDP
tSLD
tLDR
tSS
20
ns
1t + 20
ns
1t + 20
ns
1t + 20
ns
1t + 20
ns
1t + 20
ns
20
ns
3t + 20
ns
Notes) 1. t is the cycle of 2/3 the clock frequency applied to the XTLI pin. (512fs)
2. The REDY pin is the value for CL = 60pF.
–7–
Max.
4t + 50
Unit
ns
20
ns
20
ns
20
ns
3t + 20
ns
20
ns
2t + 40
ns
CXD2728Q
Analog Characteristics
(AVD0 to 6 = VDD0 to 2 = AVDX = 3.3V, AVS0 to 6 = VSS0 to 5 = AVSX = 0V, fs = 44.1kHz, Ta = 25°C)
When Pro Logic mode is on, the input signal level while measuring the center (C) and surround (S) channels
should be –3dB smaller than the input level while measuring the left (L) and right (R) channels. At this time, for
the C channel, the signal is input in-phase, and for the S channel, the signal is input at reversed phase to each
L and R channel.
The input level is the same for all measurement items when Pro Logic mode is off.
1. ADC + DAC Connection Total Characteristics
These are the total characteristics for the ADC and DAC. Use the analog I/O circuits in the Application Circuit
for the measurement circuit.
1-1. When Pro Logic Mode is on
Unless otherwise specified, the measurement conditions are as given below.
• VIN (L, R measurement) = 300mVrms (0dB), VIN (C, S measurement) = 212mVrms (–3dB)
• FIN = 1kHz
• Sampling frequency = 44.1kHz
• Measured bands = 10Hz to 20kHz
Item
Measurement conditions
CCIR/ARM filter
S/N ratio∗1
Measured bands:
70Hz to 300kHz
16.5dB∗2
0dB∗3
(THD + N)/S
–3.52dB∗4
Measured bands:
70Hz to 300kHz
Head room
Channels
Min.
Typ.
L, R
65.5
72
C, S
65.5
70
57
C, S
52
L, R
0.006
1.00
C, S
0.006
1.00
L, R
0.03
C, S
0.03
L, R
0.045
C, S
0.045
L, R
0.23
C, S
0.32
16.5
L, R
25
53
C, S
25
45
Unit
dB
L, R
(THD + N)/S = 1%
Matrix rejection∗5
Max.
%
dB
dB
Output level
(all)
300
mV
Level difference between channels
(all)
±0.2
dB
Current consumption
Power supply fluctuation
elimination ratio∗6
Analog system
(including oscillator circuit)
17.2
Digital system
43.1
100mVrms,
100Hz sine wave
L, R
24
C
–9
S
30
mA
dB
∗1 When VIN = 200mVrms (= –3.52dB = –20dBFS), the S/N ratio is 3.52dB smaller than the values noted in
the table above.
∗2 VIN (L, R) = 2.0Vrms, VIN (C, S) = 1.414Vrms
∗3 VIN (L, R) = 300mVrms, VIN (C, S) = 212mVrms
∗4 VIN (L, R) = 200mVrms, VIN (C, S) = 141mVrms
∗5 When the L and R channel gain deviation is 0.1dB or less in the prefilter output.
∗6 Including amplification by the external amplifier (L/Rch: 11.35dB, C/Sch: 14.42dB)
–8–
CXD2728Q
1-1. When Pro Logic Mode is off
Unless otherwise specified, the measurement conditions are as given below.
• VIN (L, R, C, S) = 2Vrms (0dB), 1kHz
• Sampling frequency = 44.1kHz
• Measured bands = 10Hz to 20kHz
Item
Measurement conditions
Channels
Min.
Typ.
Max.
Unit
S/N ratio
"A" weighting filter
(all)
90
dB
(THD + N)/S∗1
0dB
(all)
0.006
%
Dynamic range∗2
"A" weighting filter
(all)
90
dB
506
mVrms
(all)
2.00
Vrms
(all)
–6
dB
ADC maximum input level∗3
Output level∗4
Power supply fluctuation
elimination ratio∗5
100mVrms, 100Hz sine wave
∗1 See Graph 1: ADC Characteristics.
∗2 S/(THD + N) during –60dB input
∗3 The ADC maximum input level depends on the supply voltage (AVDn), so when the supply voltage (AVDn)
contains deviation, calculate the maximum input level from the formula below and adjust the level so that
the waveform is not clipped at the minimum voltage.
Maximum input level [Vrms] = 0.506 [Vrms] ×
Minimum supply voltage [V]
3.3 [V]
∗4 Like the ADC, the DAC conversion gain also varies according to the supply voltage (AVDn). However, the
DAC has the reverse characteristics of the ADC, so the total gain between the ADC and DAC is constant.
∗5 Including amplification by the external amplifier (L/Rch: 11.35dB, C/Sch: 14.42dB)
5
2
1
THD + N CH1 [%]
0.500
0.200
0.100
0.050
0.020
0.010
0.005
0.002
0.001
2m 3m 5m
10m
20m
50m 0.1
0.2
GEN VOLT [Vrms]
Graph 1. ADC Characteristics
–9–
0.5
1
2
CXD2728Q
2. DAC Characteristics
Use the digital input and analog output circuits in the Application Circuit for the measurement circuit.
2-1. When Pro Logic mode is on
Unless otherwise specified, the measurement conditions are as given below.
• Input data = 16.5dBFS (= 0dB), 1kHz, 16 bits
• Sampling frequency = 44.1kHz
• Measured bands = 10Hz to 20kHz
Item
Measurement conditions
CCIR/ARM filter
S/N ratio
Measured bands:
70Hz to 300kHz
(THD + N)/S
Measured bands:
70Hz to 300kHz
Channels
Matrix rejection
Level difference between
channels
Typ.
L, R
76
C
74
S
73
L, R
57
C, S
52
L, R
0.017
C
0.022
S
0.024
L, R
0.23
C
0.32
S
0.33
AVDn [V]
3.3 [V]
– 10 –
Unit
dB
%
dBFS
(all)
300
mVrms
L, R
51
C
70
S
56
(all)
±0.2
∗1 The output level depends on the supply voltage (AVDn) as shown in the formula below.
Output level [Vrms] = 300 [mVrms] ×
Max.
–16.5
Dolby level
Output level∗1
Min.
dB
dB
CXD2728Q
2-2. When Pro Logic mode is off
Unless otherwise specified, the measurement conditions are as given below.
• Input data = 0dBFS (= 0dB), 1kHz, 16 bits
• Sampling frequency = 44.1kHz
• Measured bands = 10Hz to 20kHz
Item
Measurement conditions
S/N ratio
Channels
"A" weighting filter
(THD + N)/S∗1
Dynamic range∗2
"A" weighting filter
Output level∗3
Min.
Typ.
L, R
98
C
97
S
95
L, R
0.005
C, S
0.003
L, R
97
C
96
S
94
(all)
2.01
Max.
Unit
dB
%
dB
Vrms
∗1 See Graphs 2 and 3.
∗2 S/(THD + N) during –60dB input
∗3 The output level depends on the supply voltage (AVDn) as shown in the formula below.
AVDn [V]
3.3 [V]
5
5
2
1
0.500
2
1
0.500
THD + N CH1 [%]
THD + N CH1 [%]
Output level [Vrms] = 2.01 [Vrms] ×
0.200
0.100
0.050
0.020
0.010
0.005
0.002
0.001
–60
0.200
0.100
0.050
0.020
0.010
0.005
0.002
–50
–40
–30
–20
–10
0.001
–60
0
GEN VOLT [dBFS]
–50
–40
–30
–20
–10
GEN VOLT [dBFS]
Graph 2. DAC Characteristics (L, Rch)
Graph 3. DAC Characteristics (C, Sch)
– 11 –
0
CXD2728Q
Description of Functions
1. Master/Slave Modes
[Relevant pins] XMST, LRCK, BCK
When using the CXD2728Q alone without digital input, set the CXD2728Q to master mode.
When using digital input, the CXD2728Q may be set to either master mode or slave mode.
The clock applied to LRCK and BCK in slave mode must be synchronized to either the crystal oscillator clock
of the XTLI and XTLO pins or the external clock input from the XTLI pin.
XMST
Mode
LRCK, BCK I/O
H
Slave mode
Input
L
Master mode
Output
Table 1-1. LRCK, BCK Mode Setting
2. Master Clock System
[Relevant pins] XTLI, XTLO, BFOT
768fs (fs = 32 to 48kHz) is assumed for the master clock system, and the connection is as shown below.
BFOT outputs the clock obtained by frequency dividing the master clock. The frequency division ratio can be
changed by the setup register (SQC04, SQC05). (See "6. Setup Register".)
SQC05 SQC04
BFOT
0
0
384fs
0
1
256fs
1
0
512fs
1
1
768fs
(1) Master
(2) Slave
O
512fs
BFOT
256fs/384fs/512fs/768fs
I
768fs
XTLI
Frequency
divider
512fs
Frequency
divider
O OPEN
XTLO
768fs
I
XTLI
Setup
Register
O
XTLO
Note) Oscillation circuits may differ according to peripheral circuit and substrate. Consult with crystal oscillator
manufacturers about the selecting oscillation circuits.
Fig. 2-1.
– 12 –
CXD2728Q
3. Reset Circuit
[Relevant pins] XRST, XTLI, XTLO
This LSI must be reset after the power is turned on.
Reset is done by setting the XRST pin Low for 1/fs or more after the supply voltage satisfies the recommended
operating condition, and the crystal oscillator clock of the XTLI and XTLO pins or the external clock input from
the XTLI pin is correctly applied. (See "AC Characteristics".)
4. Serial Audio Interface (SIF)
[Relevant pins] SI, BCK, LRCK, XS24, XMST
Serial data is used for the external communication of the digital audio data. The CXD2728Q has only one input
system, and 2 channels of data are input for each sampling cycle. Either the 32-bit clock mode or the 24-bit
clock mode can be selected. In master mode, the mode is fixed to the 32-bit clock mode.
(1) Pin Configuration (The pins shown in the table below are assigned to the SIF.)
Symbol
I
SI
Function
I/O
Serial input; taken with synchronized to BCK.
BCK
I/O
BCK I/O; either 32-bit clock mode (64fs) or 24-bit clock mode (48fs). BCK output supports
32-bit clock mode only.
LRCK
I/O
LRCK I/O (1fs).
XS24
I
SIO slot number (24/32) selection input. Low: 24-bit slot; High: 32-bit slot.
Valid only in slave mode. Set High in master mode.
Do not switch between High and Low during DSP operation.
XMST
I
BCK, LRCK master mode/slave mode switching input.
Low: master mode; High: slave mode.
Table 4-1. Pin Configuration
(2) Operation Modes
The LRCK/BCK mode can be selected by the setup register settings as follows. (See "6. Setup Register".)
LRCK/BCK Mode Setting
Contents
Function
Setup register
SQC15
LRCK format
"0": normal,
SQC14
LRCK polarity selection
"0": Lch "H", "1": Lch "L"
SQC13
BCK polarity selection relative to LRCK edge.
Valid only in slave mode. Fix to "0" in master
mode.
"0": edge ↓,
Table 4-2. LRCK/BCK Mode Setting
– 13 –
"1": IIS
"1" : edge ↑
CXD2728Q
(3) SIF Format
The serial audio interface has only one input system, and except for the slot number, the following formats can
be set by setting the setup register. The serial audio interface can also support IIS format to enable connection
to Philips and other company's devices.
The timing charts for each data format are given on the following page.
SQC12 SQC11 Data arrangement/Frontward or rearward truncation/Data word length
0
0
MSB first/Frontward truncation/24 bits
0
1
MSB first/Rearward truncation/16 bits
1
0
MSB first/Rearward truncation/18 bits
1
1
MSB first/Rearward truncation/20 bits
∗ All formats support either the 24- or 32-bit slot in slave mode.
Table 4-3. Setup Register Settings
– 14 –
– 15 –
SI
BCK
LRCK
24-bit slot
SI
BCK
LRCK
32-bit slot
MSB
21
20
19
18
17
16
15
14
13
12
Lch
11
10
09
08
07
14
13
12
11
10
09
08
07
16
15
14
13
12
11
10
09
08
07
Invalid
MSB
19
18
17
16
15
14
13
12
11
10
09
08
07
Invalid
MSB
• MSB first 20 bits rearward truncation (SQC12, 11 = 1, 1)
17
Invalid
MSB
• MSB first 18 bits rearward truncation (SQC12, 11 = 1, 0)
15
MSB
• MSB first 16 bits rearward truncation (SQC12, 11 = 0, 1)
22
• MSB first 24 bits (SQC12, 11 = 0, 0)
23
LSB
LSB
06
06
06
06
05
05
05
05
04
04
04
04
03
03
03
03
02
02
02
02
00
23
22
01
01
01
LSB
00
LSB
00
LSB
00
19
MSB
19
Invalid
20
18
18
17
17
16
16
17
16
MSB
Invalid
Invalid
Invalid
Invalid
21
Invalid
LSB MSB
01
LSB
19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
Invalid
MSB
• MSB first 20 bits rearward truncation (SQC12, 11 = 1, 1)
Rch
15
15
MSB
15
LSB
MSB
LSB
17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
MSB
14
14
14
14
13
13
13
13
12
12
12
12
11
11
11
11
Rch
10
10
10
10
09
09
09
09
08
08
08
08
07
07
07
07
06
06
06
06
05
05
05
05
04
04
04
04
03
03
03
03
02
02
02
02
01
01
01
01
LSB
00
LSB
00
LSB
00
LSB
00
LSB
19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
MSB
15
Invalid
15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
LSB
23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
MSB
17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
Invalid
MSB
• MSB first 18 bits rearward truncation (SQC12, 11 = 1, 0)
Invalid
Invalid
15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
MSB
LSB
• MSB first 16 bits rearward truncation (SQC12, 11 = 0, 1)
23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
• MSB first 24 bits frontward truncation (SQC12, 11 = 0, 0)
Lch
Digital Audio Data Input Timing (with polarities: SQC15 = 0, SQC14 = 0, SQC13 = 0)
CXD2728Q
CXD2728Q
5. Microcomputer Interface
[Relevant pins] RVDT, SCK, XLAT, REDY
The CXD2728Q performs the serial audio interface format setting and the coefficient settings such as volume
and filter by serial data from the microcomputer.
(1) Pin Configuration
The four external pins indicated in the table below are assigned to the microcomputer interface.
Symbol
Function
I/O
RVDT
I
Serial data input from microcomputer.
SCK
I
Shift clock for serial data. Input data from RVDT is taken according to the SCK rise.
XLAT
I
Interprets the 8 bits of RVDT before this signal rises as transfer mode data, and the
bits before that as address data.
REDY
O
Transfer prohibited while at Low level. Transfer enabled at High. This pin is an open
drain, and must be pulled up externally.
Table 5-1. Microcomputer Interface External Pins
(2) Description of Communication Formats
The internal data transfer timing from the microcomputer interface to the coefficient RAM and setup register is
called the SV cycle, and is generated once per 1 LRCK.
The SV cycle is generated immediately preceding the signal processing program, so it has absolutely no effect
on signal processing, and there is no risk of the sound being cut.
Address section + Mode section + Data section
act as one package of data to transfer data from the microcomputer to the CXD2728Q.
Address section (8 bits) Mode section (8 bits)
RVDT
A0
A7
M0
M7
Data section (16 bits)
D0
SCK
XLAT
REDY
Fig. 5-1. Example of Communication
– 16 –
D15
CXD2728Q
(3) Data Structure
The data structure is classified into three types, as shown in the table below. All data communication is done
with LSB first.
Symbol
Bit length
Contents
A0 to A7
8
Address section
M0 to M7
8
Transfer mode section
D0 to D15/SQ00 to SQ15
16
Data section
Remarks
Coefficient RAM and setup register are both 16 bits
Table 5-2. Data Structure
(3)-1. Transfer Mode Section
The transfer mode section is 8 bits and has the following functions.
Bit
Function
Symbol
Reserve
M7
M6
SU1
M5
SU0
M4
VS1
M3
VS0
Setup Reg.
type
Data type
Normally fixed to "0"
SU1
0
0
1
1
VS1
0
1
SU0
0
1
0
1
VS0
0
0
Field A
Field B (Not used)
Field C
Field D
Setup register
Coefficient RAM
M2
M1
Reserve
Normally fixed to "0"
M0
Table 5-3. Transfer Mode Section
(3)-2. Address Section
The coefficient RAM has a 256-word structure, so the address section is 8 bits. The setup register has a 4word structure and the field (address) is specified by the mode section, so the address section data may be
optional.
(3)-3. Data Section
The coefficient RAM and setup register both have a 16-bit structure, so 16 SCK are required.
– 17 –
CXD2728Q
(4) Details of Communication Methods
The definitions of signal timing required for control from the microcomputer are given below.
(4)-1. Signal Timing
First, address section data and mode section data are sent from the microcomputer, synchronized to SCK, to
the RVDT pin.
The address section data is 8 bits for both the coefficient RAM and setup register, and the setup register has a
length of one word, so optional data can be transferred. Address section data is sent with LSB first.
Mode section data is fixed at 8 bits regardless of the transfer contents.
The phase relationship between SCK and RV data (data applied to the RVDT pin) has the following
restrictions:
• RV data must be established before SCK rises (tDS ≥ 20ns).
• RV data must be held for 1t + 20ns or more after SCK rises (tDH).
SCK itself has the following restrictions:
• SCK Low level must be 1t + 20ns or more (tSWL).
• SCK High level must be 1t + 20ns or more (tSWH).
After the SCK rise which corresponds to the mode section final data, XLAT rises (tSLP ≥ 20ns).
The XLAT Low level width must be maintained at 1t + 20ns or more (tLWL). The fall timing is restricted in that
even if REDY falls due to SCK during the preceding transfer, 3t + 20ns or more (tSLD) is required from the SCK
rise which corresponds to the data section final data.
Further, if preceding transfers have been performed and REDY = Low, XLAT must rise after REDY = High.
RVDT
A0
tDS
A7
M0
D0/SQ00
SQ00
M7
D15/SQ15
SQ15
tDH
A0
M7
tSS
SCK
tSWL
tSWH
tSLP
tLSD
tBSP
tSLP
XLAT
tSLD or tLWH
tLWL
tSLD
tRLP
tSBD
REDY
tLDR
Fig. 5-2. Write Timing
∗ t is the cycle of 2/3 the clock frequency applied to the XTLI pin. (512fs)
– 18 –
tLDR
tRLP
CXD2728Q
Data section write begins after XLAT rises, and here also transfer must be performed with LSB first, with tDS
and tDH restrictions. In addition, after XLAT rises at the starting point for sending the data section, wait for 3t +
20ns or more for the first SCK rise (tLSD).
When 16 bits of this write is repeated, REDY goes Low within 4t + 50ns, and the microcomputer is informed of
waiting status for the SV cycle, which is the dedicated data rewrite cycle, by the microcomputer interface (tSBD).
When REDY goes High again, the corresponding data is written.
The next communication can be restarted by using the REDY signal as follows.
• When REDY = Low, the SCK for the next transfer can rise (tBSP ≥ 20ns).
• In the same way, when REDY = Low, the XLAT for the next transfer can fall (tLDR ≥ 20ns).
REDY will fall due to this communication, but it is prohibited for XLAT to rise for the next transfer before REDY
rises. Make sure that the next XLAT rises after REDY rises (tRLP ≥ 20ns).
In order to restart the next transfer without using the REDY signal, the following conditions must be observed:
• There should be 2t + 40ns or more left between the SCK rise for the final data section and the SCK rise for
the next transfer (tSS).
• In the same way, the XLAT for the next transfer can fall after waiting for 3t + 20ns or more after the final
data section SCK rise (tSLD).
The tSS and tSLD here are shorter times than tSBD ≤ 4t + 50ns, so these are rather loose restrictions. However,
even in this case the XLAT rise for the next transfer must come after REDY rises (tRLP ≥ 20ns).
Further, the restriction for the XLAT fall at the starting point of this transfer from tSLD can be:
tSLD ≥ 3t + 20ns
– 19 –
CXD2728Q
6. Setup Register
When the setup register is selected in microcomputer interface transfer mode, the following settings are
possible for hardware such as the serial audio interface and DAC, and for software such as the Dolby Pro
Logic Surround decoder.
The setup register has a total of four fields, and 16 bits of setup information can be stored per field. However,
when this LSI is reset, the setup register contents are also reset to the settings shown in the "When reset"
column in Tables 6-1 to 6-3 below.
(1) Field A
Data
section bit
SQA15
SQA14
SQA13
SQA12
SQA11,
SQA10
SQA09,
SQA08
SQA07,
SQA06
SQA05,
SQA04
SQA03 to
SQA00
Control contents
When reset
Reserve bit
Be sure to set this bit Low when changing the setup
register Field A settings.
"L"
Noise sequencer
0: OFF
1: ON
OFF
Virtualizer
0: OFF
1: ON
OFF
Compensation filter
0: OFF
1: ON
OFF
Decimation ratio setting SQA11 SQA10
(SFC mode only)
0
0
: 1/1 (No decimation)
Be sure to also set
0
1
: 1/2 decimation
SQC07 and SQC06.
1
0
: 1/3 decimation
Dolby 3 Stereo
1/1
(No decimation)
SQA09 SQA08
0
0
: OFF
0
1
: ON
OFF
Reserve bit
Be sure to set both bits Low when changing the
setup register Field A settings.
all "L"
SFC mode
SQA05 SQA04
0
0
: OFF
0
1
: ON
OFF
Be sure to set all of these bits Low when changing
the setup register Field A settings.
all "L"
Reserve bit
Table 6-1. Setup Register Field A
∗ Bit names are indicated by the field name and the bit number. The bit names for Field A are SQA00 to
SQA15, and the first three letters of the bit names for Fields B, C and D are SQB, SQC and SQD,
respectively.
(2) Field B
Field B is not used. The Field B data is not necessary to be transferred after reset.
– 20 –
CXD2728Q
(3) Field C
Data
section bit
Control contents
0: normal
1: IIS
normal
SQC14
LRCK polarity selection 0: Lch "H"
1: Lch "L"
Lch "H"
SQC13
BCK polarity selection
relative to LRCK edge Note)
Falling edge
SQC15
SQC12,
SQC11
SQC10
SQC09,
SQC08
SQC07,
SQC06
SQC05,
SQC04
LRCK format
When reset
Serial audio
interface setting
0: Falling edge
1: Rising edge
SQC12 SQC11
0
0
: MSB first/Frontward truncation/24 bits
0
1
: MSB first/Rearward truncation/16 bits
1
0
: MSB first/Rearward truncation/18 bits
1
1
: MSB first/Rearward truncation/20 bits
MSB
first/Frontward
truncation/24 bits
DAC forced mute
0: ON
1: OFF
ON
Reserve bit
Be sure to set both bits Low when changing
the setup register Field C settings.
all "L"
Decimation ratio setting SQC07 SQC06
(SFC mode only)
0
0
: 1/1 (No decimation)
Be sure to also set
0
1
: 1/2 decimation
∗
SQA11 and SQA10.
1
: 1/3 decimation
BFOT output clock
frequency division
ratio setting
SQC03 to Reserve bit
SQC00
1/1
(No decimation)
SQC05 SQC04
0
0
: 384Fs
0
1
: 256Fs
1
0
: 512Fs
1
1
: 768Fs
384Fs
Be sure to set all of these bits Low when changing
the setup register Field C settings.
all "L"
Table 6-2. Setup Register Field C
Note) BCK polarity selection (SQC13) is valid only in slave mode. Fix to "0" in master mode.
– 21 –
CXD2728Q
(4) Field D
Data
section bit
SQD15 to
SQD03
Control contents
Reserve bit
Be sure to set all of these bits Low when changing the
setup register Field D settings.
Coefficient memory SQD02
type setting
0
0
SQD02 to
SQD00
01
0
0
00
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
ROM only (ROM = 00 to ffH)
ROM/RAM mixed
(ROM = 00 to dfH/RAM = E0 to ffH)
ROM/RAM mixed
(ROM = 00 to bfH/RAM = C0 to ffH)
ROM/RAM mixed
(ROM = 00 to 9fH/RAM = A0 to ffH)
ROM/RAM mixed
(ROM = 00 to 7fH/RAM = 80 to ffH)
ROM/RAM mixed
(ROM = 00 to 3fH/RAM = 40 to ffH)
ROM/RAM mixed
(ROM = 00 to 1fH/RAM = 20 to ffH)
RAM only (RAM = 00 to ffH)
Table 6-3. Setup Register Field D
– 22 –
When reset
all "L"
ROM only
CXD2728Q
7. Coefficient RAM/ROM
When the coefficient RAM is selected in microcomputer interface transfer mode, the various application
functions can be turned on and off, and the coefficient parameters such as each section's volume and delay
time can be set.
Coefficient RAM addresses other than those given in these specifications are "don't care". However, the RAM
is not cleared entirely when this LSI is reset, so there are no initial values as for the setup register. Be sure to
set all of the necessary data; otherwise misoperation may result.
(1) Configuration
The coefficient RAM and ROM have a capacity of 256 words × 16 bits each. However, the address space for
the coefficient data is from 00H to ffH (256 words), so it is not possible to access all of the coefficient RAM and
ROM data at the same time. That is to say, of the total 512 words in both the coefficient RAM and ROM, only
the specified 256 words can be handled.
The coefficient RAM and ROM areas are allocated by setting SQD02 to SQD00 of setup register Field D.
Coefficient data transferred via the microcomputer interface is stored only in the coefficient RAM area specified
by these bits.
(Even if a ROM area address is specified and transfer is performed, the transfer is ignored.)
AAA
AAA
AAA
+ AAA
AAA
00H
bfH
c0H
ffH
00H
ROM
=
bfH
c0H
RAM
ffH
ROM
RAM
Coefficient address space
Fig. 7-1. Coefficient Data ROM/RAM Allocation when SQD02 to SQD00 are Set to "010" (Setting Example)
The contents of the data transferred to the coefficient RAM area differ for each mode. (See "8. Applications" for
the detailed contents.) The RAM area may also differ, so SQD02 to SQD00 must be sent when switching the
mode.
Mode
Setting item SQD02 to SQD00
Remarks
Pro Logic + simple SFC mode
111
00 to ff = Coefficient RAM area
Virtual Dolby Surround mode
100
80 to ff = Coefficient RAM area
SFC mode
111
00 to ff = Coefficient RAM area
Table 7-1. Coefficient RAM Area
– 23 –
CXD2728Q
8. Applications
The CXD2728Q is equipped with various applications such as Dolby Pro Logic Surround mode (Pro Logic
mode), Virtual Dolby Surround mode (Virtual mode), Dolby 3 Stereo mode, noise sequencer mode and SFC
mode.
The methods of setting each mode and of changing the mode are described below.
Note) The filter and other parameter values for each application assume a sampling frequency (fs) of 44.1 [kHz].
Consult your Sony representative with regard to use at other fs.
8-1. Dolby Pro Logic Surround Mode (Pro Logic Mode)
Pro Logic mode is realized using the adaptive matrix, passive decoder including BNR, auto input balance,
center channel mode control, simple SFC and other functions.
(1) Setting Pro Logic Mode
Pro Logic mode must be set by the following procedures in order to achieve stable adaptive matrix operation.
Setting Pro Logic mode by procedures other than those given below may aggravate the decoder
characteristics.
• Immediately after power-on reset
i) Transfer the following setup data.
SQA = 0030H (Field A)
SQD = 7ee7H (Field D)
∗ Field C is "All 0", so the DAC forced mute is applied.
ii) Transfer the Pro Logic mode coefficient data.
iii) Transfer the setup data set in Pro Logic mode.
• Changing to Pro Logic mode from Virtual mode
Note) The coefficients for the Pro Logic mode soft mute∗1 status must be set in coefficient RAM addresses
00H to 7fH before shifting to Virtual mode.
i) Apply the soft mute in Virtual mode.
ii) Transfer the setup data set in Pro Logic mode.
iii) Cancel the Pro Logic mode soft mute.
• Changing to Pro Logic mode from a different mode (other than Virtual mode)
i) Apply the soft mute in the current mode.
ii) Set the coefficients at the following addresses to "0000H".
Addresses: 6eH to 7fH
iii) Transfer the following setup data.
SQA = 0030H (Field A)
SQD = 7ee7H (Field D)
∗ The DAC forced mute is not applied by Field C.
iv) Transfer the Pro Logic mode coefficients for the soft mute status.
v) Transfer the setup data set in Pro Logic mode.
vi) Cancel the Pro Logic mode soft mute.
∗1 Soft mute: See "Appendix 1. Soft Mute".
– 24 –
CXD2728Q
(2) Setting Data
(2)-1. Setup Data
Table 8-1-1 lists the registers most closely related to Pro Logic mode.
Setup data not listed in Table 8-1-1 may be set as desired, with due consideration given to the contents of
Fields A to D noted in "6. Setup Register".
Register name Setting value
Remarks
SQA14
"0"
1: Noise sequencer mode
SQA13
"0"
1: Virtual mode
SQA09, 08
"00"
01: Dolby 3 Stereo mode
SQA05, 04
"00"
01: SFC mode
SQD02 to 00
"111"
Coefficient RAM area setting (111: Other than Virtual mode, 100: Virtual mode)
Table 8-1-1. Pro Logic Mode Setup Register Settings
– 25 –
CXD2728Q
(2)-2. Coefficient Data
The coefficient RAM area for Pro Logic mode is from addresses 00H to ffH (all areas). The coefficient data
consists of "fixed values" shown in Table 8-1-2 and "setting values" shown in Table 8-1-3 which can be set by
the user. All coefficient values must be sent to the coefficient RAM via the microcomputer interface.
Note that once data has been transferred to the coefficient RAM, the coefficient RAM data (00H to 7fH) is
saved unless the power is turned off, even if the RAM area is changed by setting SQD02 to SQD00 (even if
the mode is changed to Virtual mode).
• Fixed values during Pro Logic mode initialization
The following fixed values must be set in the coefficient RAM to ensure proper internal operation.
Address
Fixed value
Address
Fixed value
Address
Fixed value
Address
Fixed value
27H
6dH
6eH
6fH
70H
71H
72H
73H
74H
75H
76H
77H
78H
79H
7aH
7bH
7cH
7dH
7eH
7fH
80H
81H
82H
83H
84H
85H
86H
87H
88H
89H
8aH
8bH
8cH
8dH
8eH
8fH
0000H
051eH
ff86H
02a0H
f6c0H
2715H
4000H
5149H
e571H
0f4eH
f5b8H
075cH
fa97H
0402H
fd0bH
0225H
fe7cH
01d3H
f312H
4b85H
850fH
7d6bH
7d72H
22b6H
3a94H
0074H
7f18H
a000H
8000H
febfH
04f9H
eb83H
7b01H
cae0H
0400H
0074H
90H
91H
92H
93H
94H
95H
96H
97H
98H
99H
9aH
9bH
9cH
9dH
9eH
9fH
a0H
a1H
a2H
a3H
a4H
a5H
a6H
a7H
a8H
a9H
aaH
abH
acH
adH
aeH
b3H
b4H
b6H
b8H
b9H
7f18H
0400H
001eH
7fc5H
0002H
7ffdH
8000H
dd1eH
da82H
109cH
2641H
3441H
dd1eH
109cH
da82H
2641H
3441H
0bbfH
e755H
4000H
f619H
e57eH
36dcH
5a82H
10c9H
2641H
7f18H
7e30H
4cbaH
c216H
0aa4H
27b4H
7e14H
7ff9H
0063H
0000H
baH
bbH
bcH
bdH
beH
bfH
c0H
c1H
c2H
c3H
c4H
c5H
c6H
c7H
c8H
c9H
caH
cbH
ccH
cdH
ceH
cfH
d0H
d1H
d2H
d3H
d5H
d7H
d8H
daH
dbH
deH
dfH
e3H
e4H
e5H
43b9H
0400H
401eH
ec00H
8000H
a000H
0024H
ff92H
010aH
fce2H
097bH
e38dH
1555H
0400H
1400H
2000H
c000H
ffe4H
febcH
f520H
c144H
a57eH
0757H
0012H
7f00H
7fffH
fc00H
68a9H
5121H
7ff4H
7fe8H
8000H
c400H
0000H
0000H
0000H
e6H
e7H
e8H
e9H
eaH
ebH
ecH
edH
eeH
efH
f0H
f9H
feH
ffH
0000H
0000H
0000H
0000H
0000H
0000H
0000H
0000H
0000H
0000H
7fffH
8000H
b800H
0001H
Table 8-1-2. Pro Logic Mode Fixed Value Coefficients
– 26 –
CXD2728Q
• Pro Logic mode user setting coefficients
The relationships between the coefficient RAM and each function during Pro Logic mode operation are as
follows.
Address
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0aH
0bH
0cH
0dH
0eH
0fH
10H
11H
12H
13H
14H
15H
16H
17H
18H
19H
1aH
1bH
1cH
1dH
1eH
1fH
20H
21H
22H
23H
24H
Symbol
KLV
KRV
KCV
KSV
KLm1
KRm1
a0
a1
b
KLm2
KRm2
a0
a1
b
KLd
KRd
KCd
KSd
Kfb
a0
a1
b
a0
a1
b
KDin
TP1
TP2
TP3
TP4
TP5
TP6
KDout
KDV1
KDV2
KDV3
KLRm1
Function
Simple SFC: L-ch dry → L-ch mix volume
Simple SFC: R-ch dry → R-ch mix volume
Simple SFC: C-ch → C-ch volume
Simple SFC: S + L/R (HPF1) → S-ch mix volume
Simple SFC: L-ch → LPF1 mix volume
Simple SFC: R-ch → LPF1 mix volume
Simple SFC: LPF1 coefficient
Simple SFC: LPF1 coefficient
Simple SFC: LPF1 coefficient
Simple SFC: L-ch → HPF1 mix volume
Simple SFC: R-ch → HPF1 mix volume
Simple SFC: HPF1 coefficient
Simple SFC: HPF1 coefficient
Simple SFC: HPF1 coefficient
Simple SFC: L-ch → Delay RAM mix volume
Simple SFC: R-ch → Delay RAM mix volume
Simple SFC: C-ch → Delay RAM mix volume
Simple SFC: S-ch → Delay RAM mix volume
Simple SFC: Delay RAM feedback volume
Simple SFC: HPF2 coefficient
Simple SFC: HPF2 coefficient
Simple SFC: HPF2 coefficient
Simple SFC: LPF2 coefficient
Simple SFC: LPF2 coefficient
Simple SFC: LPF2 coefficient
Simple SFC: Delay RAM write address
Simple SFC: Delay RAM read Tap1 address
Simple SFC: Delay RAM read Tap2 address
Simple SFC: Delay RAM read Tap3 address
Simple SFC: Delay RAM read Tap4 address
Simple SFC: Delay RAM read Tap5 address
Simple SFC: Delay RAM read Tap6 address
Simple SFC: Delay RAM feedback Tap address
Simple SFC: Delay RAM → S-ch mix volume
Simple SFC: Delay RAM → R-ch mix volume
Simple SFC: Delay RAM → L-ch mix volume
Simple SFC: LPF1 → L-ch mix volume
Table 8-1-3 (1). Pro Logic Mode Setting Value Coefficients
– 27 –
Setting value
See Table 8-1-13.
See Table 8-1-13.
See Table 8-1-13.
See Table 8-1-13.
See Table 8-1-13.
See Table 8-1-13.
See Table 8-1-16.
See Table 8-1-16.
See Table 8-1-16.
See Table 8-1-13.
See Table 8-1-13.
See Table 8-1-16.
See Table 8-1-16.
See Table 8-1-16.
See Table 8-1-13.
See Table 8-1-13.
See Table 8-1-13.
See Table 8-1-13.
See Table 8-1-13.
See Table 8-1-16.
See Table 8-1-16.
See Table 8-1-16.
See Table 8-1-16.
See Table 8-1-16.
See Table 8-1-16.
See Table 8-1-15.
See Table 8-1-15.
See Table 8-1-15.
See Table 8-1-15.
See Table 8-1-15.
See Table 8-1-15.
See Table 8-1-15.
See Table 8-1-15.
See Table 8-1-13.
See Table 8-1-13.
See Table 8-1-13.
See Table 8-1-13.
CXD2728Q
Address
25H
26H
28H
29H
2aH
2bH
2cH
2dH
afH
b0H
b1H
b2H
b5H
b7H
d4H
d6H
d9H
dcH
ddH
f2H
f3H
f4H
f5H
f6H
f7H
f8H
faH
fbH
Symbol
KLRm2
KLRm3
KTP1
KTP2
KTP3
KTP4
KTP5
KTP6
b2
b1
a
–a
aslw
2D
Kx
KiA
Ke
Kia
Kis
KL
KR
KH
KP
KCH
KCP
KS
Kdlb
Dly
Function
Simple SFC: LPF1 → R-ch mix volume
Simple SFC: HPF1 → S-ch mix volume
Simple SFC: Tap1 volume
Simple SFC: Tap2 volume
Simple SFC: Tap3 volume
Simple SFC: Tap4 volume
Simple SFC: Tap5 volume
Simple SFC: Tap6 volume
7K LPF parameter
7K LPF parameter
7K LPF parameter
7K LPF parameter
Passive decoder M-BNR
Passive decoder M-BNR
Auto input balance ON/OFF
Serial audio interface input volume
De-emphasis ON/OFF
Analog input mix volume
Digital input mix volume
Center mode control volume
Center mode control volume
Center mode control volume
Center mode control volume
Center mode control volume
Center mode control volume
Passive decoder volume
Passive decoder M-BNR ON/OFF
Passive decoder delay time adjustment
Table 8-1-3 (2). Pro Logic Mode Setting Value Coefficients
– 28 –
Setting value
See Table 8-1-13.
See Table 8-1-13.
See Table 8-1-13.
See Table 8-1-13.
See Table 8-1-13.
See Table 8-1-13.
See Table 8-1-13.
See Table 8-1-13.
0000 = OFF, df66 = ON
0000 = OFF, 5723 = ON
0000 = OFF, 125e = ON
8000 = OFF, eda2 = ON
See Table 8-1-12.
See Table 8-1-12.
0000 = OFF, 00ff = ON
See Table 8-1-5.
0000 = OFF, ac19 = ON
See Table 8-1-4.
See Table 8-1-5.
See Tables 8-1-7, 8.
See Tables 8-1-7, 8.
See Tables 8-1-7, 8.
See Tables 8-1-7, 8.
See Tables 8-1-7, 8.
See Tables 8-1-7, 8.
See Table 8-1-8.
0000 = OFF, 2000 = ON
See Table 8-1-9.
SIA2
SIA1
RIN
LIN
–KiA (d6H)
–KiA (d6H)
ADC
ADC
DeEmphasis
DeEmphasis
Decimation
Decimation
DC Cut
DC Cut
(2)-3. Signal Flow for Dolby Pro Logic Mode
– 29 –
–Kis (ddH)
–Kia (dcH)
–Kis (ddH)
–Kia (dcH)
Fig. 8-1-1
Rt
Pro
Logic
Decoder
Lt
S
C
R
L
R
L
S
C
S
C
Simple SFC
R
L
Over
Sampling
Over
Sampling
Over
Sampling
Over
Sampling
DAC
DAC
DAC
DAC
XSOUT
XCOUT
ROUT
LOUT
CXD2728Q
CXD2728Q
(3) Volume Coefficient Settings
[Relevant data] Coefficients: KiA (d6H), Kia (dcH), Kis (ddH)
The I/O levels and volumes are 2's complement format with a decimal point between D15 and D14, and
hexadecimal notation with D15 as MSB and D0 as LSB.
The coefficient and level relationships are as follows.
∗ D15 to D0 are negative values, but the DSP calculation is (–1) × (D15 to D0).
(3)-1. Kia (dcH): 0dB = c000H
The I/O levels for 8000H to ffffH are obtained by the following formulas.
D15 to D0
Level [dB]
8000H
a599H
c000H
d2b2H
e000H
eff6H
ffffH
0000H
+6.02
+3.00
0.00
–3.00
–6.02
–12.00
–84.29
–∞
14
(Coefficient value) = [(–1) × D15 + ∑ (Dn × 2n – 15)] × (–2)
n=0
I/O level = 20 log [coefficient value] dB
Table 8-1-4. Kia (dcH) Setting Value Examples
(3)-2. KiA (d6H), Kis (ddH): 0dB = 8000H
The I/O levels for 8000H to ffffH are obtained by the following formulas.
14
(Coefficient value) = [(–1) × D15 + ∑ (Dn × 2n – 15)] × (–1)
n=0
I/O level = 20 log [coefficient value] dB
D15 to D0
Level [dB]
8000H
a563H
c000H
e000H
ffffH
0000H
0.00
–3.00
–6.02
–12.04
–90.31
–∞
Table 8-1-5. KiA (d6H), Kis (ddH) Setting Value Examples
∗ Unless otherwise specified, subsequent setting examples (Pro Logic mode) in these specifications assume
either:
Kia = d2b2H, KiA = 0000H, Kis = 0000H
or:
Kia = 0000H, KiA = 8000H, Kis = a563H
(4) Auto Input Balance Control
[Relevant data] Coefficient: Kx (d4H)
The auto input balance function is turned on and off by coefficient Kx (d4H).
Coefficient
Kx (d4H)
ON = 00ffH
OFF = 0000H
Table 8-1-6. Auto Input Balance ON/OFF
– 30 –
CXD2728Q
(5) Center Mode Control
[Relevant data] Coefficients: KP (f5H), KH (f4h), KL (f2H), KR (f3H), KCP (f7H), KCH (f6H)
The center channel output mode can be set to Normal, Wide or Phantom mode as shown in Table 8-1-7 below.
Mode
KP (f5H)
KH (f4H)
KL (f2H)
KR (f3H)
KCP (f7H)
KCH (f6H)
e000H
e000H
d2cdH
d2cdH
0000H
e000H
Wide
0000H
0000H
d2cdH
d2cdH
e000H
0000H
Phantom
e000H
0000H
d2cdH
d2cdH
0000H
0000H
Coefficient
Normal
Table 8-1-7. Center Mode Control Setting Value Examples
–KL (f2H)
LP
LO
–KR (f3H)
RP
RO
–KH (f4H), –KP (f5H)
LPF
CP
–KCH (f6H)
HPF
–KCP (f7H)
CO
Note) If KH is set to 0000H in Phantom center channel mode, the LPF is set to
data through status and the data added to the L and R channels is CP × KP.
Fig. 8-1-2. Signal Flow for Center Mode Control (L, R, C-ch)
Note) In Phantom center channel mode, the center channel information is divided equally between the left and
right speakers.
The level of each channel can be adjusted by changing
the KP, KH, KL, KR, KCP and KCH setting values. In
these cases, be sure to change only the shaded portions
for each mode in Table 8-1-7.
However, make sure that KP = KH in Normal mode. In
Phantom mode, set KH to 0000H and adjust the mix level
to the left and right channels using KP.
The I/O levels for 8000H to ffffH are obtained by the
following formulas.
14
(Coefficient value) = [(–1) × D15 + ∑ (Dn × 2n – 15)] × (–4)
n=0
I/O level = 20 log [coefficient value] dB
D15 to D0
Level [dB]
8000H
c000H
d2cdH
e000H
e959H
eff6H
f7f6H
ffffH
0000H
+12.04
+6.02
+3.00
0
–3.00
–6.00
–12.00
–78.27
–∞
Table 8-1-8. KP, KH, KL, KR, KCP, KCH and KS
Setting Value Examples
∗ In Table 8-1-7, lowering the input level by 3dB using Kia (dcH) or Kis (ddH) raises the output level of the L
and R channels by 3dB. In this case, attaching external parts as shown in the Application Circuit is
recommended to increase the C and S channel gains.
– 31 –
CXD2728Q
(6) Passive Decoder (Surround Channel)
The surround channel is processed according to the flow shown in Fig. 8-1-3.
The setting method for each section is described below.
–KS (f8H)
7kHz
LPF
SP
M-BNR
Delay
SO
Fig. 8-1-3. Passive Decoder Signal Flow (S-ch)
(6)-1. Delay Time Setting
Setting value Dly (fbH)
Delay (fs = 44.1kHz)
0020H
0040H
·
·
52b0H
·
6e40H
·
89d0H
·
a560H
·
·
ff80H
ffa0H
0.022ms
0.045ms
·
·
15.000ms
·
20.000ms
·
25.000ms
·
30.000ms
·
·
46.349ms
46.372ms
[Relevant data] Coefficient: Dly (fbH)
The surround channel delay time can be varied
by setting the coefficient Dly value. (Dly is the
delay line read address.)
Only the upper 11 of the 16 coefficient bits are
used. The lower 5 bits are not used, and are
ignored even if set.
That is to say, Dly can be set in 0020H
increments, and the delay time can be set in
approximately 0.022 ms increments.
The following condition also applies.
• 0020H ≤ Dly ≤ ffa0H
Table 8-1-9. Surround Channel (S-ch) Delay Time Setting
Value Examples
The coefficient value is calculated as follows.
(Dly) Decimal = (Delay [s]) × fs [Hz] × 32
Example) For 20ms (fs = 44100 [Hz])
0.02 × 44100 × 32 = 28224
Hexadecimal conversion
6e40H
(6)-2. 7kHz Low-Pass Filter
[Relevant data] Coefficients: b2 (afH), b1 (b0H), a (b1H), –a (b2H)
The 7kHz LPF of the passive decoder can be turned on and off by setting the coefficients in Table 8-1-10.
ON
OFF
b2
b1
a
–a
df66
0000
5723
0000
125e
0000
eda2
8000
Table 8-1-10. Passive Decoder 7kHz LPF ON/OFF Setting
– 32 –
CXD2728Q
(6)-3. Modified Dolby B-type NR
[Relevant data] Coefficients: aslw (b5H), 2D (b7H), KiA (d6H), Kia (dcH), Kis (ddH), Kdlb (faH)
The aslw and 2D coefficients and the ON/OFF coefficient Kdlb must be set for Modified Dolby B-type NR.
This function is turned on and off by setting Kdlb as shown in Table 8-1-11. The aslw and 2D coefficient values
differ according to the Dolby level, prefilter and coefficient Kia/Kis (KiA) conditions. Table 8-1-12 shows typical
setting value examples based on these three conditions. The prefilter gain is the value when using the
Application Circuit given in these specifications.
Consult your Sony representative with regard to use under conditions other than those noted in Table 8-1-12.
Coefficient
Kdlb (faH)
ON = 2000H
OFF = 0000H
Table 8-1-11. Modified Dolby B-type NR ON/OFF Setting
Prefilter
Dolby level
Kia (dcH)
Kis (ddH)
aslw (b5H)
2D (b7H)
–3.52dB
300mVrms
c53cH
0000H
00caH
0033H
–3.52dB
200mVrms
c53cH
0000H
00caH
0023H
(Digital input)
–20dBFS
0000H
a563H
00caH
0023H
Table 8-1-12. Modified Dolby B-type NR Coefficient Value Examples for Different Input Level Conditions
(during digital input: KiA (d6H) = 8000H)
(6)-4. Volume
[Relevant data] Coefficient: KS (f8H)
The KS (f8H) volume values are as shown in Table 8-1-8. See "5. Center Mode Control" for the calculation
method.
– 33 –
CXD2728Q
(7) Simple SFC
Simple SFC effects can be added after Dolby Pro Logic Surround decoder processing. (See Fig. 8-1-1.)
Fig. 8-1-4 shows the signal flow for the simple SFC block.
When not using simple SFC, set the coefficients as follows to set the simple SFC block to through status.
KLV (00H), KRV (01H), KCV (02H), KSV (03H) = 8000H
KDV1 (21H), KDV2 (22H), KDV3 (23H), KLRm1 (24H), KLRm2 (25H), KLRm3 (26H) = 0000H
–KCV (02H)
C
C
–KLV (00H)
L
L
–KRV (01H)
R
R
–KCd (10H)
–Kfb (12H)
–KRd (0fH)
Delay
KDin
KDout
TP1 TP2 TP3 TP4 TP5 TP6
HPF2 + LPF2
13H to 18H
–KDV3
(23H)
–KLd (0eH)
1
–KSd (11H)
2
3
4
5
–KTP1 to –KTP6
(28H to 2dH)
–KRm1 (05H)
6
–KDV2
(22H)
–KLRm1
(24H)
–KLRm2
(25H)
–KDV1 (21H)
LPF1
06H to 08H
–KLm1 (04H)
–KRm2 (0aH)
HPF1
0bH to 0dH
–KLm2 (09H)
–KLRm3 (26H)
–KSV (03H)
S
S
Fig. 8-1-4. Simple SFC Signal Flow
– 34 –
CXD2728Q
(7)-1. Volume Settings for Each Section
[Relevant data] Coefficients: KLV (00H), KRV (01H), KCV (02H), KSV (03H), KLm1 (04H), KRm1 (05H),
KLm2 (09H), KRm2 (0aH), KLd (0eH), KRd (0fH), KCd (10H), KSd (11H),
Kfb (12H), KDV1 (21H), KDV2 (22H), KDV3 (23H), KLRm1 (24H),
KLRm2 (25H), KLRm3 (26H), KTP1 (28H), KTP2 (29H), KTP3 (2aH),
KTP4 (2bH), KTP5 (2cH), KTP6 (2dH)
The format is the same as that described in "(3) Volume Coefficient Settings". The levels are as follows when
0dB = 8000H.
The I/O levels for 8000H to ffffH are obtained by the following formulas.
14
(Coefficient value) = [(–1) × D15 + ∑ (Dn × 2n – 15)] × (–1)
n=0
I/O level = 20 log [coefficient value] dB
D15 to D0
Level [dB]
8000H
a563H
c000H
d2b2H
e000H
f000H
ffffH
0000H
0.00
–3.00
–6.02
–9.02
–12.04
–18.06
–90.31
–∞
Table 8-1-13. Setting Value Examples for Each Volume
(Negative Values)
The above coefficients are normally applied as negative values, but positive values should be applied when
intentionally inverting the phase with TP1 to TP6, etc. In this case, the levels are as follows when 0dB = 7fffH.
The I/O levels for 7fffH to 0001H are obtained by the following formulas.
14
(Coefficient value) = [D15 + ∑ (Dn × 2n – 15)]
n=0
I/O level = 20 log [coefficient value] dB
D15 to D0
Level [dB]
7fffH
5a9dH
4000H
2d4eH
2000H
1000H
0001H
0000H
0.00
–3.00
–6.02
–9.02
–12.04
–18.06
–90.31
–∞
Table 8-1-14. Setting Value Examples for Each Volume
(Positive Values)
– 35 –
CXD2728Q
(7)-2. Delay Line Settings
[Relevant data] Coefficients: KDin (19H), TP1 (1aH), TP2 (1bH), TP3 (1cH), TP4 (1dH), TP5 (1eH),
TP6 (1fH), KDout (20H)
The Pro Logic mode delay lines are used for both the passive decoder short delay and the simple SFC
reverberation, and are thus subject to the following restrictions:
• Dly + 0020H ≤ KDin (0020H ≤ Dly ≤ KDin – 0020H)
• 0020H ≤ TP∗ ≤ KDout
• KDin + KDout ≤ bfe0H
Dly (fbH): Pro Logic delay line read address
KDin (19H): Simple SFC delay line write address
TP1 to TP6 (1aH to 1fH): Simple SFC tap read addresses (determine the delay time for each tap)
KDout (20H): Simple SFC feedback loop read address (determines the maximum delay time)
Note) The minimum unit for all the above coefficients is "0020H". Values smaller than this are ignored.
The TP1 to TP6 and KDout addresses are specified in a different
manner than Dly and KDin. These addresses are specified by the
address value assuming KDin as the reference (= 0000H).
That is to say, the actual address is KDin + KDout, etc.
The coefficient values are calculated as follows.
Delay
Setting value
KDout, TP1 to TP6 (fs = 44.1kHz)
0020H
0040H
·
·
1a60H
·
35f0H
·
5180H
·
6d10H
·
·
ff80H
ffa0H
(Dly) Decimal = (Delay [s]) × fs [Hz] × 32
Example) When using 20ms for the passive decoder, and all
remaining delay lines as reverberation
20ms → Dly = 6e40H
KDin = 6e40H + 0020H = 6e60H
KDout = ffe0H – 6e60H = 9180H
0020H ≤ TP1 to 6 ≤ 9180H
0.022ms
0.045ms
·
·
4.784ms
·
9.784ms
·
14.784ms
·
19.784ms
·
·
46.349ms
46.372ms
Table 8-1-15. Simple SFC Delay Time Setting
Value Examples
Passive decoder
0000H
20.0ms
Dly
6e40H
KDin
6e60H
Simple SFC
KDout
26.4ms
9180H
46.4ms (0000H to ffe0H)
Fig. 8-1-5. Pro Logic Mode Delay Line Setting Example
– 36 –
CXD2728Q
(7)-3. Filters
[Relevant data] Coefficients: a0 (06H, 0bH, 13H, 16H), a1 (07H, 0cH, 14H, 17H), b (08H, 0dH, 15H, 18H)
LPF1, HPF1, LPF2 and HPF2 are comprised of primary IIR filters, and the coefficient setting and cut-off
frequency relationship are as shown in Table 8-1-16.
LPF1, 2
HPF1, 2
Cut-off
frequency [Hz]
a0
a1
b
a0
a1
b
100
200
300
400
500
600
700
800
900
1000
1200
1400
1600
1800
2000
2200
2400
2600
2800
3000
3200
3400
3600
3800
4000
4200
4400
4600
4800
5000
FF19
FE34
FD53
FC74
FB99
FAC1
F9EB
F918
F848
F77A
F5E6
F45C
F2DB
F162
EFF2
EE89
ED28
EBCE
EA7A
E92D
E7E6
E6A5
E569
E432
E301
E1D4
E0AB
DF87
DE67
DD4B
00E7
01CC
02AD
038C
0467
053F
0615
06E8
07B8
0886
0A1A
0BA4
0D25
0E9E
100E
1177
12D8
1432
1586
16D3
181A
195B
1A97
1BCE
1CFF
1E2C
1F55
2079
2199
22B5
7E30
7C67
7AA4
78E7
7731
7580
73D4
722E
708E
6EF2
6BCB
68B6
65B4
62C3
5FE2
5D11
5A4E
579A
54F3
5259
4FCB
4D48
4AD0
4863
4600
43A6
4155
3F0D
3CCD
3A94
80E8
81CD
82AE
838D
8468
8540
8616
86E9
87B9
8887
8A1B
8BA5
8D26
8E9F
900F
9178
92D9
9433
9587
96D4
981B
995C
9A98
9BCF
9D00
9E2D
9F56
A07A
A19A
A2B6
7F18
7E33
7D52
7C73
7B98
7AC0
79EA
7917
7847
7779
75E5
745B
72DA
7161
6FF1
6E88
6D27
6BCD
6A79
692C
67E5
66A4
6568
6431
6300
61D3
60AA
5F86
5E66
5D4A
7E30
7C67
7AA4
78E7
7731
7580
73D4
722E
708E
6EF2
6BCB
68B6
65B4
62C3
5FE2
5D11
5A4E
579A
54F3
5259
4FCB
4D48
4AD0
4863
4600
43A6
4155
3F0D
3CCD
3A94
LPF1, 2
HPF1, 2
Cut-off
frequency [Hz]
a0
a1
b
a0
a1
b
5200
5400
5600
5800
6000
6200
6400
6600
6800
7000
7200
7400
7600
7800
8000
8200
8400
8600
8800
9000
9200
9400
9600
9800
10000
10200
10400
10600
10800
11000
OFF
DC32
DB1D
DA0C
D8FD
D7F2
D6E9
D5E3
D4DF
D3DE
D2DF
D1E3
D0E8
CFEF
CEF8
CE03
CD0F
CC1D
CB2B
CA3B
C94D
C85F
C772
C685
C59A
C4AF
C3C5
C2DA
C1F1
C107
C01E
8000
23CE
24E3
25F4
2703
280E
2917
2A1D
2B21
2C22
2D21
2E1D
2F18
3011
3108
31FD
32F1
33E3
34D5
35C5
36B3
37A1
388E
397B
3A66
3B51
3C3B
3D26
3E0F
3EF9
3FE2
0000
3863
3639
3416
31F9
2FE2
2DD0
2BC4
29BD
27BB
25BD
23C4
21CF
1FDD
1DEF
1C04
1A1C
1838
1655
1475
1298
10BC
0EE2
0D09
0B32
095C
0788
05B3
03E0
020D
003A
0000
A3CF
A4E4
A5F5
A704
A80F
A918
AA1E
AB22
AC23
AD22
AE1E
AF19
B012
B109
B1FE
B2F2
B3E4
B4D6
B5C6
B6B4
B7A2
B88F
B97C
BA67
BB52
BC3C
BD27
BE10
BEFA
BFE3
8000
5C31
5B1C
5A0B
58FC
57F1
56E8
55E2
54DE
53DD
52DE
51E2
50E7
4FEE
4EF7
4E02
4D0E
4C1C
4B2A
4A3A
494C
485E
4771
4684
4599
44AE
43C4
42D9
41F0
4106
401D
0000
3863
3639
3416
31F9
2FE2
2DD0
2BC4
29BD
27BB
25BD
23C4
21CF
1FDD
1DEF
1C04
1A1C
1838
1655
1475
1298
10BC
0EE2
0D09
0B32
095C
0788
05B3
03E0
020D
003A
0000
Table 8-1-16. Simple SFC HPF and LPF Setting Coefficients
– 37 –
CXD2728Q
8-2. Virtual Dolby Surround Mode (Virtual Mode)
Virtual mode is comprised of the Dolby Pro Logic Surround decoder and the Virtualizer as shown in Fig. 8-2-1.
Virtual Dolby Surround is realized by the Virtualizer block.
(1) Setting Virtual Mode
Virtual mode must be set by the following procedures in order to achieve stable adaptive matrix operation.
Setting Virtual mode by procedures other than those given below may aggravate the decoder characteristics.
• Immediately after power-on reset
i) Transfer the following setup data.
SQA = 0030H (Field A)
SQD = 7ee7H (Field D)
∗ Field C is "All 0", so the DAC forced mute is applied.
ii) Transfer the Virtual mode coefficient data.
iii) Transfer the setup data set in Virtual mode.
• Changing to Virtual mode from a different mode
i) Apply the soft mute in the current mode.
ii) Set the coefficients at the following addresses to "0000H".
Addresses: 6eH to 7fH
iii) Transfer the following setup data.
SQA = 0030H (Field A)
SQD = 7ee7H (Field D)
∗ The DAC forced mute is not applied by Field C.
iv) Transfer the Virtual mode coefficients for the soft mute status.
v) Transfer the setup data set in Virtual mode.
vi) Cancel the Virtual mode soft mute.
(2) Setting Data
(2)-1. Setup Data
Table 8-2-1 lists the registers most closely related to Virtual mode.
Setup data not listed in Table 8-2-1 may be set as desired, with due consideration given to the contents of
Fields A to D noted in "6. Setup Register".
Register name Setting value
Remarks
SQA14
"0"
1: Noise sequencer mode
SQA13
"1"
1: Virtual mode
SQA09, 08
"00"
01: Dolby 3 Stereo mode
SQA05, 04
"00"
01: SFC mode
SQD02 to 00
"100"
Coefficient RAM area setting (111: Other than Virtual mode, 100: Virtual mode)
Table 8-2-1. Virtual Mode Setup Register Settings
– 38 –
CXD2728Q
(2)-2. Coefficient Data
The coefficient RAM area for Virtual mode is from addresses 80H to ffH. Addresses 00 to 7fH use the ROM
data. (The ROM contents are mainly the coefficients used by the Virtualizer.)
Like Pro Logic mode, the coefficient data consists of fixed values and setting values, with all fixed values
exactly the same as for Pro Logic mode.
Use the area from address 80H in Table 8-1-2. The setting values are as shown in Table 8-2-2, and consist of
adding the Virtualizer attenuation coefficient attV (f1H) setting to the Wide center mode settings of Pro Logic
mode.
Address
afH
b0H
b1H
b2H
b5H
b7H
d4H
d6H
d9H
dcH
ddH
f1H
f2H
f3H
f4H
f5H
f6H
f7H
f8H
faH
fbH
Symbol
b2
b1
a
–a
aslw
2D
Kx
KiA
Ke
Kia
Kis
attV
KL
KR
KH
KP
KCH
KCP
KS
Kdlb
Dly
Function
7K LPF parameter
7K LPF parameter
7K LPF parameter
7K LPF parameter
Passive decoder M-BNR
Passive decoder M-BNR
Auto input balance ON/OFF
Serial audio interface input volume
De-emphasis ON/OFF
Analog input mix switch
Digital input mix switch
Virtual Dolby Surround attenuator
Center mode control volume
Center mode control volume
Center mode control volume
Center mode control volume
Center mode control volume
Center mode control volume
Passive decoder volume
Passive decoder M-BNR ON/OFF
Passive decoder delay time setting
Table 8-2-2. Virtual Mode Setting Value Coefficients
– 39 –
Setting value
0000 = OFF, df66 = ON
0000 = OFF, 5723 = ON
0000 = OFF, 125e = ON
8000 = OFF, eda2 = ON
See Table 8-1-12.
See Table 8-1-12
0000 = OFF, 00ff = ON
See Table 8-1-5.
0000 = OFF, ac19 = ON
See Table 8-1-4.
See Table 8-1-5.
See Table 8-2-3.
See Tables 8-1-7, 8.
See Tables 8-1-7, 8.
See Tables 8-1-7, 8.
See Tables 8-1-7, 8.
See Tables 8-1-7, 8.
See Tables 8-1-7, 8.
See Table 8-1-8.
0000 = OFF, 2000 = ON
See Table 8-1-9.
– 40 –
SIA2
SIA1
RIN
LIN
–KiA (d6H)
–KiA (d6H)
ADC
ADC
DeEmphasis
DeEmphasis
Decimation
Decimation
DC Cut
DC Cut
–Kis (ddH)
–Kia (dcH)
–Kis (ddH)
–Kia (dcH)
(2)-3. Signal Flow for Dolby Virtual Surround Mode
Rt
S
C
R
L
Fig. 8-2-1
Pro
Logic
Decoder
Lt
Virtual
Surround
Process
VR
VL
C
R
L
Virtualizer
Mixing
Over
Sampling
Over
Sampling
DAC
DAC
ROUT
LOUT
CXD2728Q
CXD2728Q
(3) Volume Coefficient Settings
[Relevant data] Coefficients: attV (f1H), KL (f2H), KR (f3H), KCP (f7H), KS (f8H)
Adjust the levels of the two Virtual mode channels by the amount of the four Pro Logic decoder output
channels using KL (f2H), KR (f3H), KCP (f7H) and KS (f8H). (See Table 8-1-7.)
The mixing level of the surround channel can be adjusted
with coefficient attV (f1H).
attV can be set in the range of 7fffH to 0000H as shown in
Table 8-2-3.
Coefficient value Level [dB]
7fffH
5a67H
3fffH
2d4eH
2000H
1000H
0001H
0000H
The I/O levels for 7fffH to 0001H are obtained by the
following formulas.
+6.02
+3.00
0.00
–3.00
–6.02
–12.04
–84.29
–∞
∗ Sony recommended value: 5333H (+2.28dB)
14
(Coefficient value) = [D15 + ∑ (Dn × 2n – 15)] × 2
Table 8-2-3. attV (f1H) Setting Value Examples
n=0
I/O level = 20 log [coefficient value] dB
Also, the most effective listening area is shown in Fig. 8-2-3.
Lch
L
Lt
Lt
L
L
L
R
–KR (f3H)
R
Rout
Mixing
C
1.2 to 2.0m
44°
C
attV (f1H)
–KCP (f7H)
Rt
R
Phantom
center
R
Rt
C
Lout
–KL (f2H)
Pro
Logic
Decoder
Rch
S
–KS (f8H)
VL
Virtual
Surround
Process
VR
Virtual
surround
Virtual
surround
S
S
attV (f1H)
Listening center
Fig. 8-2-2. Volume Setting Coefficients
Fig. 8-2-3. Listening Area
– 41 –
CXD2728Q
8-3. Dolby 3 Stereo Mode
This mode is a part of the Pro Logic adaptive matrix functions.
Specifically, surround output is muted and surround signal directionality is not harmonized.
(1) Setting Dolby 3 Stereo Mode
Dolby 3 Stereo mode must be set by the following procedures in order to achieve stable adaptive matrix
operation. Setting Dolby 3 Stereo mode by procedures other than those given below may aggravate the
decoder characteristics.
• Immediately after power-on reset
i) Transfer the following setup data.
SQA = 0030H (Field A)
SQD = 7ee7H (Field D)
∗ Field C is "All 0", so the DAC forced mute is applied.
ii) Transfer the Dolby 3 Stereo mode coefficient data.
iii) Transfer the setup data set in Dolby 3 Stereo mode.
• Changing to Dolby 3 Stereo mode from Virtual mode
Note) The coefficients for the Dolby 3 Stereo mode or Pro Logic mode soft mute status must be set in
coefficient RAM addresses 00H to 7fH when shifting to Virtual mode.
i) Apply the soft mute in Virtual mode.
ii) Transfer the setup data set in Dolby 3 Stereo mode.
iii) Cancel the Dolby 3 Stereo mode soft mute.
• Changing to Dolby 3 Stereo mode from a different mode
i) Apply the soft mute in the current mode.
ii) Set the coefficients at the following addresses to "0000H".
Addresses: 6eH to 7fH
iii) Transfer the following setup data.
SQA = 0030H (Field A)
SQD = 7ee7H (Field D)
∗ The DAC forced mute is not applied by Field C.
iv) Transfer the Dolby 3 Stereo mode coefficients for the soft mute status.
v) Transfer the setup data set in Dolby 3 Stereo mode.
vi) Cancel the Dolby 3 Stereo mode soft mute.
– 42 –
CXD2728Q
(2) Setting Data
(2)-1. Setup Data
Table 8-3-1 lists the registers most closely related to Dolby 3 Stereo mode.
Setup data not listed in Table 8-3-1 may be set as desired, with due consideration given to the contents of
Fields A to D noted in "6. Setup Register".
Register name Setting value
Remarks
SQA14
"0"
1: Noise sequencer mode
SQA13
"0"
1: Virtual mode
SQA09, 08
"01"
01: Dolby 3 Stereo mode
SQA05, 04
"00"
01: SFC mode
SQD02 to 00
"111"
Coefficient RAM area setting (111: Other than Virtual mode, 100: Virtual mode)
Table 8-3-1. Dolby 3 Stereo Mode Setup Register Settings
(2)-2. Coefficient Data
The coefficient data used in Dolby 3 Stereo mode is entirely the same as that for Pro Logic mode. See "8-1.
Dolby Pro Logic Surround Mode".
– 43 –
CXD2728Q
8-4. Noise Sequencer Mode
(1) Setting Noise Sequencer Mode
Set noise sequencer mode by the following procedures.
• Immediately after power-on reset
i) Transfer the setup data set in noise sequencer mode.
ii) Transfer the noise sequencer mode coefficient data.
• Changing to noise sequencer mode from a different mode
i) Apply the soft mute in the current mode.
ii) Transfer the setup data set in noise sequencer mode.
iii) Transfer the noise sequencer mode coefficient data.
(2) Setting Data
(2)-1. Setup Data
Table 8-4-1 lists the registers most closely related to noise sequencer mode.
Setup data not listed in Table 8-4-1 may be set as desired, with due consideration given to the contents of
Fields A to D noted in "6. Setup Register".
Register name Setting value
Remarks
SQA14
"1"
1: Noise sequencer mode
SQA13
"0"
1: Virtual mode
SQA09, 08
"00"
01: Dolby 3 Stereo mode
SQA05, 04
"00"
01: SFC mode
SQD02 to 00
"111"
Coefficient RAM area setting (111: Other than Virtual mode, 100: Virtual mode)
Table 8-4-1. Noise Sequencer Mode Setup Register Settings
– 44 –
CXD2728Q
(2)-2. Coefficient Data
Noise sequencer mode allows both Pro Logic and Virtual processing. Of the coefficients for these two types of
processing, change the coefficients from addresses d0H to e2H as shown in the tables below.
The other coefficients may be left as the Pro Logic mode or Virtual mode coefficient settings.
Then, set the 7kHz low-pass filter (page 32) of the surround (S) channel to off.
L-ch
C-ch
R-ch
S-ch
L→C→R→S
L→C→R
T1 (d0H)
T2 (d1H)
T3 (d2H)
T4 (d3H)
Address
Fixed value
2000
0000
0000
0000
2000
2000
2000
3000
0000
0000
3000
3000
2000
3000
4000
0000
4000
4000
2000
3000
4000
5000
5000
4000
d4H
d5H
d6H
d7H
d8H
d9H
daH
dbH
dcH
ddH
deH
dfH
e0H
e1H
e2H
1000H
0040H
c000H
d2b1H
0000H
2d4fH
0000H
d2b1H
c000H
d2b1H
8000H
7789H
6f12H
0876H
6f14H
Table 8-4-2. Noise Sequencer Mode Coefficient Setting Values
Table 8-4-3. Noise Sequencer Mode
Coefficient Fixed Values
(3) Output Level Adjustment
[Relevant data] Coefficients: KL (f2H), KR (f3H), KH (f4H), KP (f5H), KCH (f6H), KCP (f7H), KS (f8H)
The noise output level in noise sequencer mode is adjusted by the center mode control coefficients (f2H to
f7H) and the passive decoder volume coefficient (f8H)
See (5) and (6)-4 of "8-1. Pro Logic Mode".
8-5. SFC Mode
SFC mode is used for 2-channel stereo input, and realizes reverberation effects using the delay lines, and
dynamics processing using 1/2 and 1/3 decimation and the compressor.
∗ This is a separate application from the simple SFC of Pro Logic mode.
(1) Setting SFC Mode
Set SFC mode by the following procedures.
• Immediately after power-on reset
i) Transfer the setup data set in SFC mode.
ii) Transfer the SFC mode coefficient data.
• Changing to SFC mode from a different mode
i) Apply the soft mute in the current mode.
ii) Transfer the setup data set in SFC mode.
iii) Transfer the SFC mode coefficient data.
– 45 –
CXD2728Q
(2) Setting Data
(2)-1. Setup Data
Table 8-5-1 lists the registers most closely related to SFC mode.
Setup data not listed in Table 8-5-1 may be set as desired, with due consideration given to the contents of
Fields A to D noted in "6. Setup Register".
Register name
Setting value
SQA11, 10
Don't care
SQA05, 04
"01"
SQC07, 06
Don't care
SQD02 to 00
Remarks
00: No decimation, 01: 1/2, 10: 1/3
01: SFC mode
00: No decimation, 01: 1/2, 1∗: 1/3
"111"
Coefficient RAM area setting (111: SFC mode)
Table 8-5-1. SFC Mode Setup Register Settings
(2)-2. Coefficient Data
The SFC mode coefficient data uses the RAM for the entire area. Also, like other modes, the coefficient data
consists of fixed values and setting values.
• Fixed values during SFC mode initialization
The following fixed values must be set in the coefficient RAM to ensure proper DSP internal operation.
Address
Fixed value
Address
Fixed value
Address
Fixed value
Address
Fixed value
00H
01H
38H
39H
3aH
3bH
3cH
3dH
3eH
3fH
40H
41H
42H
43H
44H
45H
7fe8H
7fd1H
0000H
0092H
0209H
02cdH
0109H
fda9H
fd19H
0189H
058aH
016dH
f7beH
f72aH
0a4eH
2706H
46H
47H
48H
49H
4aH
4bH
4cH
4dH
4eH
4fH
50H
51H
52H
53H
54H
55H
34eeH
0000H
6000H
ff80H
00a1H
016eH
01f8H
0193H
0024H
fe70H
fdbaH
fed8H
015aH
037fH
0344H
ffffH
56H
57H
58H
59H
5aH
5bH
5cH
6dH
6eH
6fH
70H
71H
72H
73H
74H
75H
fb5cH
f8e3H
fbf6H
0575H
129cH
1e0dH
2294H
051eH
ff86H
02a0H
f6c0H
2715H
4000H
5149H
e571H
0f4eH
76H
77H
78H
79H
7aH
7bH
7cH
7dH
7eH
7fH
80H
94H
d7H
d8H
daH
dbH
f5b8H
075cH
fa97H
0402H
fd0bH
0225H
fe7cH
01d3H
f312H
4b85H
0000H
7fffH
68a9H
5121H
7ff4H
7fe8H
Table 8-5-2. SFC Mode Fixed Value Coefficients
– 46 –
CXD2728Q
• SFC mode user setting coefficients
The relationships between the coefficient RAM and each function during SFC mode operation are as follows.
Address
02H
03H
04H
05H
06H
07H
08H
09H
0aH
0bH
0cH
0dH
0eH
0fH
10H
11H
12H
13H
14H
15H
16H
17H
18H
19H
1aH
1bH
1cH
1dH
1eH
1fH
20H
21H
22H
23H
24H
25H
26H
Symbol
k
XthP
XthM
Ksd
Ap
Am
Bp
Bm
Cp
Cm
KLsri
KRsri
Kfb
ahd
a00
a01
a02
b01
b02
KLtp0
KLtp1
KLtp2
KLtp3
KLtp4
KRtp0
KRtp1
KRtp2
KRtp3
KRtp4
KStp0
KStp1
KStp2
KStp3
b0
b1
KLdry
KRdry
Function
Compressor gain coefficient
Compressor threshold value (+)
Compressor threshold value (–)
Compressor ON/OFF
Compressor parameter
Compressor parameter
Compressor parameter
Compressor parameter
Compressor parameter
Compressor parameter
Delay line L-ch input volume
Delay line R-ch input volume
Delay line feedback coefficient
Feedback loop internal Hi-dump filter coefficient
Feedback loop internal LPF0 parameter
Feedback loop internal LPF0 parameter
Feedback loop internal LPF0 parameter
Feedback loop internal LPF0 parameter
Feedback loop internal LPF0 parameter
Delay line L-ch Tap0 volume
Delay line L-ch Tap1 volume
Delay line L-ch Tap2 volume
Delay line L-ch Tap3 volume
Delay line L-ch Tap4 volume
Delay line R-ch Tap0 volume
Delay line R-ch Tap1 volume
Delay line R-ch Tap2 volume
Delay line R-ch Tap3 volume
Delay line R-ch Tap4 volume
Delay line S-ch Tap0 volume
Delay line S-ch Tap1 volume
Delay line S-ch Tap2 volume
Delay line S-ch Tap3 volume
All pass filter 0 coefficient
All pass filter 1 coefficient
L-ch direct sound mix volume
R-ch direct sound mix volume
Table 8-5-3 (1). SFC Mode Setting Value Coefficients
– 47 –
Setting value
See Table 8-5-7.
See Table 8-5-7.
See Table 8-5-7.
0000 = OFF, 8000 = ON
See Table 8-5-7.
See Table 8-5-7.
See Table 8-5-7.
See Table 8-5-7.
See Table 8-5-7.
See Table 8-5-7.
See Table 8-5-5.
See Table 8-5-5.
See Tables 8-5-5, 6.
See Table 8-2-8.
See Tables 8-5-9, 10, 11.
See Tables 8-5-9, 10, 11.
See Tables 8-5-9, 10, 11.
See Tables 8-5-9, 10, 11.
See Tables 8-5-9, 10, 11.
See Tables 8-5-5, 6.
See Tables 8-5-5, 6.
See Tables 8-5-5, 6.
See Tables 8-5-5, 6.
See Tables 8-5-5, 6.
See Tables 8-5-5, 6.
See Tables 8-5-5, 6.
See Tables 8-5-5, 6.
See Tables 8-5-5, 6.
See Tables 8-5-5, 6.
See Tables 8-5-5, 6.
See Tables 8-5-5, 6.
See Tables 8-5-5, 6.
See Tables 8-5-5, 6.
See Tables 8-5-5, 6.
See Tables 8-5-5, 6.
See Table 8-5-5.
See Table 8-5-5.
CXD2728Q
Address
27H
28H
29H
2aH
2bH
2cH
2dH
2eH
2fH
30H
31H
32H
33H
34H
35H
36H
37H
5dH
81H
82H
83H
84H
85H
86H
87H
88H
89H
8aH
8bH
8cH
8dH
8eH
8fH
90H
91H
92H
93H
d6H
d9H
dcH
ddH
Symbol
KLeff
KReff
KLlpi
KRlpi
a10
a11
a12
b11
b12
KLlpo
KRlpo
KLod
KRod
KSod
KLd
KRd
KCod
Kd
Ltp0
Ltp1
Ltp2
Ltp3
Ltp4
Rtp0
Rtp1
Rtp2
Rtp3
Rtp4
Stp0
Stp1
Stp2
Stp3
tp_fb
ap0_in
ap0_out
ap1_in
ap1_out
KiA
Ke
Kia
Kis
Function
L-ch reflected sound mix volume
R-ch reflected sound mix volume
LPF1 L-ch input volume
LPF1 R-ch input volume
LPF1 parameter
LPF1 parameter
LPF1 parameter
LPF1 parameter
LPF1 parameter
LPF1 L-ch mix volume
LPF1 R-ch mix volume
L-ch output total volume
R-ch output total volume
S-ch output total volume
L-ch → C-ch mix volume
R-ch → C-ch mix volume
C-ch output total volume
Compressor input volume (both L and R)
Delay line L-ch Tap0 read address
Delay line L-ch Tap1 read address
Delay line L-ch Tap2 read address
Delay line L-ch Tap3 read address
Delay line L-ch Tap4 read address
Delay line R-ch Tap0 read address
Delay line R-ch Tap1 read address
Delay line R-ch Tap2 read address
Delay line R-ch Tap3 read address
Delay line R-ch Tap4 read address
Delay line S-ch Tap0 read address
Delay line S-ch Tap1 read address
Delay line S-ch Tap2 read address
Delay line S-ch Tap3 read address
Delay line feedback read address
All pass filter 0 delay RAM write address
All pass filter 0 delay RAM read address
All pass filter 1 delay RAM write address
All pass filter 1 delay RAM read address
Serial audio interface input volume
De-emphasis ON/OFF
Analog input mix switch
Digital input mix switch
Table 8-5-3 (2). Coefficient RAM Setting Data in SFC Mode
– 48 –
Setting value
See Table 8-5-5.
See Table 8-5-5.
See Table 8-5-5.
See Table 8-5-5.
See Table 8-5-9.
See Table 8-5-9.
See Table 8-5-9.
See Table 8-5-9.
See Table 8-5-9.
See Table 8-5-5.
See Table 8-5-5.
See Table 8-5-5.
See Table 8-5-5.
See Table 8-5-5.
See Table 8-5-5.
See Table 8-5-5.
See Table 8-5-5.
See Table 8-5-5.
See Table 8-5-12.
See Table 8-5-12.
See Table 8-5-12.
See Table 8-5-12.
See Table 8-5-12.
See Table 8-5-12.
See Table 8-5-12.
See Table 8-5-12.
See Table 8-5-12.
See Table 8-5-12.
See Table 8-5-12.
See Table 8-5-12.
See Table 8-5-12.
See Table 8-5-12.
See Table 8-5-12.
See Table 8-5-12.
See Table 8-5-12.
See Table 8-5-12.
See Table 8-5-12.
See Table 8-5-5.
0000 = OFF, ac19 = ON
See Table 8-5-4.
See Table 8-5-5.
RIN
LIN
SIA2
SIA1
Decimation
Decimation
DeEmphasis
DeEmphasis
DC_Cut1
DC_Cut1
– 49 –
0
0
1
1
Delay
0
3
b1 (24H)
Delay
Hi-Sampling
–KSod (34H)
Over
Sampling
Over
Sampling
–KRlpo (31H)
–KRod (33H)
–KRlpi (2aH)
(2bH to 2fH)
Secondary
LPF
LPF1
Over
Sampling
Over
Sampling
–KLlpo (30H)
–KLod (32H)
–KCod (37H)
–KLlpi (29H)
–KRdry (26H)
b1 (24H)
–KReff (28H)
2
–KLeff (27H)
1
–KRd (36H)
–KLd (35H)
–KLdry (25H)
(02H to 0bH)
Compressor
(02H to 0bH)
Compressor
–KStp
(1fH to 22H)
4
Delay
4
Hi-Sampling
3
3
Hi-Sampling
–Kd (5dH)
–Kd (5dH)
Fig. 8-5-1. Signal Flow for SFC Mode
b0 (23H)
2
2
b0 (23H)
–KRtp
(1aH to 1eH)
(10H to 14H)
Secondary
LPF
LPF0
–Kia (dcH)
–Kis (ddH)
–Kia (dcH)
–Kis (ddH)
–KLtp
(15H to 19H)
–Kfb (0eH)
ALL PASS FILTER
(REVERVE)
–ahd (0fH)
1, 1/2, 1/3
–KRsri (0dH)
Hi Dump
Down Sampling
–KLsri (0cH)
The settings for this section are the same as
for DPL mode. (Same coefficients and addresses)
ADC
ADC
–KiA (d6H)
–KiA (d6H)
(2)-3. Signal Flow
DAC
DAC
DAC
DAC
S-ch
R-ch
L-ch
C-ch
CXD2728Q
CXD2728Q
(3) Volume Settings
[Relevant data] Coefficients: KLsri (0cH), KRsri (0dH), Kfb (0eH), KLtp0 (15H), KLtp1 (16H),
KLtp2 (17H), KLtp3 (18H), KLtp4 (19H), KRtp0 (1aH), KRtp1 (1bH),
KRtp2 (1cH), KRtp3 (1dH), KRtp4 (1eH), KStp0 (1fH), KStp1 (20H),
KStp2 (21H), KStp3 (22H), b0 (23H), b1 (24H), KLdry (25H), KRdry (26H),
KLeff (27H), KReff (28H), KLlpi (29H), KRlpi (2aH), KLlpo (30H),
KRlpo (31H), KLod (32H), KRod (33H), KSod (34H), KLd (35H), KRd (36H),
KCod (37H), Kd (5dH), KiA (d6H), Kia (dcH), Kis (ddH)
The I/O levels and volumes are 2's complement format with a decimal point between D15 and D14, and
hexadecimal notation with D15 as MSB and D0 as LSB.
The coefficient and level relationships are as follows.
(3)-1. Kia (dcH): 0dB = c000H
The I/O levels for 8000H to ffffH are obtained by the following
formulas.
14
(Coefficient value) = [(–1) × D15 + ∑ (Dn × 2n – 15)] × (–2)
n=0
I/O level = 20 log [coefficient value] dB
D15 to D0
Level [dB]
8000H
c000H
e000H
eff6H
ffffH
0000H
+6.02
0.00
–6.02
–12.00
–84.29
–∞
Table 8-5-4. Kia (dcH) Setting Value Examples
(3)-2. Other Coefficients
Except for Kia, the coefficients listed in the [Relevant data] above
are basically specified by negative values (D15 to D0) with "0dB =
8000H". When intentionally inverting the phase, however, specify
positive values with "0dB = 7fffH".
∗ The DSP calculation for coefficient values other than Kfb is
(–1) × (D15 to D0).
The I/O levels for 8000H to ffffH are obtained by the following
formulas.
14
(Coefficient value) = [(–1) × D15 + ∑ (Dn × 2n – 15)] × (–1)
n=0
I/O level = 20 log [coefficient value] dB
14
n=0
I/O level = 20 log [coefficient value] dB
Level [dB]
8000H
a563H
c000H
d2b2H
e000H
f000H
ffffH
0000H
0.00
–3.00
–6.02
–9.02
–12.04
–18.06
–90.31
–∞
Table 8-5-5. Setting Value Examples
for Each Volume
(Other than Kia, Negative Values)
The I/O levels for 7fffH to 0001H are obtained by the following
formulas.
(Coefficient value) = [D15 + ∑ (Dn × 2n – 15)]
D15 to D0
D15 to D0
Level [dB]
7fffH
5a9dH
4000H
2d4eH
2000H
1000H
0001H
0000H
0.00
–3.00
–6.02
–9.02
–12.04
–18.06
–90.31
–∞
Table 8-5-6. Setting Value Examples for Each Volume
(Other than Kia, Positive Values)
– 50 –
CXD2728Q
(4) Compressor
[Relevant data] Coefficients: k (02H), XthP (03H), XthM (04H), Ksd (05H), Ap (06H), Am (07H), Bp (08H),
Bm (09H), Cp (0aH), Cm (0bH)
The parameter table is shown in Table 8-5-7, and the I/O characteristics in Fig. 8-5-2.
Compressor ON: Ksd (05H) = 8000H
Compressor OFF: Ksd (05H) = 0000H
Threshold
XthM
XthP
–∞ [dB]
Comp_5
0
0000
0
0000
–20 [dB]
Comp_4
–1/10
F334
1/10
0CCC
–17 [dB]
Comp_3
–1/7
EDB7
1/7
1249
–14 [dB]
Comp_2
–1/5
E667
1/5
1999
–9.5 [dB]
Comp_1
–1/3
D556
1/3
2AAA
Gain
k
6.0 [dB]
2.0
4000
5.2 [dB]
20/11
3A2E
4.4 [dB]
5/3
3555
2.9 [dB]
7/5
2CCC
1.6 [dB]
6/5
2666
Coefficient
Ap
Am
Bp
Bm
Cp
Cm
–1.0
E000
1.0
2000
2.0
4000
2.0
4000
0
0000
0
0000
–100/99
DFAE
100/99
2052
200/99
40A5
200/99
40A5
–1/99
FEB6
1/99
014A
–49/54
E2F7
49/54
1D09
52/27
3DA1
52/27
3DA1
–1/54
FDA2
1/54
025E
–5/8
EC00
5/8
1400
33/20
34CC
33/20
34CC
–1/40
FCCD
1/40
0333
–9/20
F19A
9/20
0E66
3/2
3000
3/2
3000
–1/20
F99A
1/99
0666
Table 8-5-7. Compressor Parameter Table
– 51 –
CXD2728Q
Input Level [dB]
0
–30
–20
–10
Comp5
–10
Comp4
Output Level [dB]
Comp3
Linear
Comp2
Comp1
6.0 [dB]
–20
–30
–20
Comp4
–17
Comp3
–14
Comp2
–9.5
Comp1
Threshold Level [dB]
Fig. 8-5-2. Compressor I/O Characteristics
– 52 –
CXD2728Q
(5) Hi-Dump Filter Setting
[Relevant data] Coefficient: ahd (0fH)
This filter is used to attenuate the high frequencies. It is mainly used in the delay line feedback loop to prevent
or alleviate noise generated when high frequency components are multiplied. Table 8-5-8 shows the
parameter table.
To turn off this filter, set "ahd = 8000H".
fc [Hz]
40
60
80
100
200
400
600
800
–ahd
1/1
1/2
1/3
EF46
FEEA
FE8D
FE31
FC68
F8EA
F585
F23A
FE8D
FDD5
FD1E
FC68
F8EA
F23A
EBEE
E603
FDD5
FCC3
FBB3
FAA6
F585
EBEE
E32F
DB3B
fc [Hz]
1k
2k
4k
6k
8k
10k
12k
14k
–ahd
1/1
1/2
1/3
EF08
E073
C97A
B91E
AD94
A578
9FC6
9BCC
E073
C97A
AD94
9FC6
9912
D404
B91E
9FC6
974D
Table 8-5-8. Hi-Dump Filter Parameter Table
(6) Secondary LPF Settings
[Relevant data] Coefficients: a00 (10H), a01 (11H), a02 (12H), b01 (13H), b02 (14H), a10 (2bH),
a11 (2cH), a12 (2dH), b11 (2eH), b12 (2fH)
These two LPF are comprised from the same secondary IIR filters. The parameter tables are shown in Tables
8-5-9 to 8-5-11. These tables show the parameters for no decimation, 1/2 decimation and 1/3 decimation,
respectively.
Use Table 8-5-9 (No decimation) for LPF1.
The coefficients used for the LPF0 and LPF1 parameters are as follows.
LPF0: a00 (10H), a01 (11H), a02 (12H), b01 (13H), b02 (14H)
LPF1: a10 (2bH), a11 (2cH), a12 (2dH), b11 (2eH), b12 (2fH)
To turn off the filters, set only a00 and a10 to "8000H" and the other four coefficient values to "0000H".
– 53 –
CXD2728Q
a00
Cut-off
frequency [Hz] a10
5200
5300
5400
5500
5600
5700
5800
5900
6000
6100
6200
6300
6400
6500
6600
6700
6800
6900
7000
7100
7200
7300
7400
7500
7600
7700
7800
7900
8000
8100
F4A5
F448
F3EB
F38D
F32D
F2CD
F26D
F20B
F1A8
F145
F0E0
F07B
F016
EFAF
EF47
EEDF
EE76
EE0D
EDA2
ED37
ECCB
EC5E
EBF0
EB82
EB13
EAA4
EA33
E9C2
E950
E8DD
a01
a11
a02
a12
b01
b11
b02
b12
16B6
176F
182A
18E7
19A5
1A65
1B27
1BEA
1CB0
1D77
1E3F
1F09
1FD5
20A2
2171
2241
2313
23E7
24BC
2593
266B
2744
281F
28FC
29DA
2AB9
2B9A
2C7C
2D60
2E45
0B5B
0BB8
0C15
0C73
0CD3
0D33
0D93
0DF5
0E58
0EBB
0F20
0F85
0FEA
1051
10B9
1121
118A
11F3
125E
12C9
1335
13A2
1410
147E
14ED
155C
15CD
163E
16B0
1723
7FDF
7D90
7B43
78F7
76AD
7464
721C
6FD6
6D91
6B4D
690B
66CA
648A
624B
600D
5DD1
5B96
595C
5723
54EA
52B3
507D
4E48
4C14
49E1
47AF
457E
434D
411E
3EEF
D2B4
D391
D469
D53B
D609
D6D2
D796
D855
D910
D9C6
DA77
DB24
DBCD
DC71
DD10
DDAC
DE43
DED6
DF66
DFF0
E077
E0FA
E179
E1F4
E26C
E2DF
E34F
E3BA
E422
E487
a00
Cut-off
frequency [Hz] a10
8200
8300
8400
8500
8600
8700
8800
8900
9000
9100
9200
9300
9400
9500
9600
9700
9800
9900
10000
10100
10200
10300
10400
10500
10600
10700
10800
10900
11000
OFF
E86A
E7F6
E781
E70C
E696
E61F
E5A7
E52F
E4B6
E43C
E3C1
E346
E2CA
E24D
E1D0
E152
E0D3
E053
DFD3
DF52
DED0
DE4D
DDCA
DD45
DCC0
DC3B
DBB4
DB2D
DAA5
8000
a01
a11
a02
a12
b01
b11
b02
b12
2F2C
3014
30FD
31E8
32D5
33C3
34B2
35A3
3695
3788
387D
3974
3A6C
3B65
3C60
3D5C
3E5A
3F5A
405A
415D
4261
4366
446D
4575
467F
478B
4898
49A6
4AB7
0000
1796
180A
187F
18F4
196A
19E1
1A59
1AD1
1B4A
1BC4
1C3F
1CBA
1D36
1DB3
1E30
1EAE
1F2D
1FAD
202D
20AE
2130
21B3
2236
22BB
2340
23C5
244C
24D3
255B
0000
3CC1
3A93
3867
363B
3410
31E5
2FBB
2D92
2B69
2941
2719
24F2
22CB
20A5
1E7F
1C5A
1A35
1810
15EB
13C7
11A3
0F7F
0D5C
0B38
0915
06F2
04CF
02AC
0089
0000
E4E8
E545
E59E
E5F4
E647
E695
E6E1
E729
E76D
E7AE
E7EC
E826
E85D
E890
E8C0
E8ED
E917
E93D
E960
E980
E99C
E9B5
E9CB
E9DD
E9ED
E9F9
EA02
EA07
EA0A
0000
Table 8-5-9. Secondary LPF Parameter Table (No Decimation, Q = 0.707107)
– 54 –
CXD2728Q
Cut-off
a00
frequency [Hz]
2600
2700
2800
2900
3000
3100
3200
3300
3400
3500
3600
3700
3800
3900
4000
F4A5
F3EB
F32D
F26D
F1A8
F0E0
F016
EF47
EE76
EDA2
ECCB
EBF0
EB13
EA33
E950
a01
a02
b01
b02
16B6
182A
19A5
1B27
1CB0
1E3F
1FD5
2171
2313
24BC
266B
281F
29DA
2B9A
2D60
0B5B
0C15
0CD3
0D93
0E58
0F20
0FEA
10B9
118A
125E
1335
1410
14ED
15CD
16B0
7FDF
7B43
76AD
721C
6D91
690B
648A
600D
5B96
5723
52B3
4E48
49E1
457E
411E
D2B4
D469
D609
D796
D910
DA77
DBCD
DD10
DE43
DF66
E077
E179
E26C
E34F
E422
Cut-off
a00
frequency [Hz]
4100
4200
4300
4400
4500
4600
4700
4800
4900
5000
5100
5200
5300
5400
5500
OFF
E86A
E781
E696
E5A7
E4B6
E3C1
E2CA
E1D0
E0D3
DFD3
DED0
DDCA
DCC0
DBB4
DAA5
8000
a01
a02
b01
b02
2F2C
30FD
32D5
34B2
3695
387D
3A6C
3C60
3E5A
405A
4261
446D
467F
4898
4AB7
0000
1796
187F
196A
1A59
1B4A
1C3F
1D36
1E30
1F2D
202D
2130
2236
2340
244C
255B
0000
3CC1
3867
3410
2FBB
2B69
2719
22CB
1E7F
1A35
15EB
11A3
0D5C
0915
04CF
0089
0000
E4E8
E59E
E647
E6E1
E76D
E7EC
E85D
E8C0
E917
E960
E99C
E9CB
E9ED
EA02
EA0A
0000
Table 8-5-10. Secondary LPF Parameter Table (1/2 Decimation, Q = 0.707107)
Cut-off
a00
frequency [Hz]
1800
1900
2000
2100
2200
2300
2400
2500
2600
2700
2800
2900
3000
3100
3200
3300
3400
3500
3600
OFF
F3EB
F2CD
F1A8
F07B
EF47
EE0D
ECCB
EB82
EA33
E8DD
E781
E61F
E4B6
E346
E1D0
E053
DED0
DD45
DBB4
8000
a01
a02
b01
b02
182A
1A65
1CB0
1F09
2171
23E7
266B
28FC
2B9A
2E45
30FD
33C3
3695
3974
3C60
3F5A
4261
4575
4898
0000
0C15
0D33
0E58
0F85
10B9
11F3
1335
147E
15CD
1723
187F
19E1
1B4A
1CBA
1E30
1FAD
2130
22BB
244C
0000
7B43
7464
6D91
66CA
600D
595C
52B3
4C14
457E
3EEF
3867
31E5
2B69
24F2
1E7F
1810
11A3
0B38
04CF
0000
D469
D6D2
D910
DB24
DD10
DED6
E077
E1F4
E34F
E487
E59E
E695
E76D
E826
E8C0
E93D
E99C
E9DD
EA02
0000
Table 8-5-11. Secondary LPF Parameter Table (1/3 Decimation, Q = 0.707107)
– 55 –
CXD2728Q
(7) Delay Time Settings
[Relevant data] Coefficients: Ltp0 (81H), Ltp1 (82H), Ltp2 (83H), Ltp3 (84H), Ltp4 (85H), Rtp0 (86H),
Rtp1 (87H), Rtp2 (88H), Rtp3 (89H), Rtp4 (8aH), Stp0 (8bH), Stp1 (8cH),
Stp2 (8dH), Stp3 (8eH), tp_fb (8fH), ap0_in (90H), ap0_out (91H),
ap1_in (92H), ap1_out (93H)
Setup: SQA05, SQA04, SQC07, SQC06
First, select No decimation, 1/2 decimation or 1/3 decimation.
1/1 (No decimation): SQA11, 10 = "00", SQC07, 06 = "00"
1/2 decimation:
SQA11, 10 = "01", SQC07, 06 = "01"
1/3 decimation:
SQA11, 10 = "10", SQC07, 06 = "1∗" (∗ = Don't care)
Next, set tp_fb (8fH) which determines the comb filter delay time, and ap0_in (90H), ap0_out (91H), ap1_in
(92H) and ap1_out (93H) which determine the all pass filter delay times.
The following conditions apply.
• 0 ≤ tp_fb, tp_fb + 0020H ≤ ap0_in ≤ ap0_out, ap0_out + 0020H ≤ ap1_in ≤ ap1_out ≤ ffe0H
• 0 ≤ Comb filter tap (Ltp0 to Stp3) ≤ tp_fb
Note) The minimum unit for all the above coefficients is "0020H". Values smaller than this are ignored.
(7)-1. Comb Filter
First, set the comb filter maximum delay time tp_fb (8fH). The coefficient value is calculated as follows.
(Dly) Decimal = (Delay [s]) × fs [Hz] × 32
(The delay value is multiplied by 1/2 and 1/3 during 1/2 and 1/3 decimation, respectively.)
Next set the delay times for the comb filter taps, and calculate the coefficient values in the same manner as for
tp_fb. (0 ≤ Tap ≤ tp_fb)
Example) For a maximum delay time of 58ms (1/2 decimation, fs = 44100Hz)
0.058 × (1/2) × 44100 × 32 = 40924.8
Rounding up to 40925 and converting to hexadecimal notation:
9fddH
However, the address is specified in 0020H increments, so this becomes:
9fe0H
Therefore, set all (14) of the L, R and S channel taps to 9fe0H (58ms) or less. For example, the L
channel settings could be:
Ltp0 = 1ba0H (10ms)
Ltp1 = 3720H (20ms)
Ltp2 = 52c0H (30ms)
Ltp3 = 6e40H (40ms)
Ltp4 = 89e0H (50ms)
Set the R and S channels in the same manner.
– 56 –
CXD2728Q
Delay (fs = 44.1kHz)
Setting
value
1/1 (No decimation)
1/2 decimation
1/3 decimation
0020H
0040H
·
·
3720H
·
6e40H
·
a560H
·
dc80H
·
ff80H
·
ffa0H
0.022ms
0.045ms
·
·
10.000ms
·
20.000ms
·
30.000ms
·
40.000ms
·
46.349ms
·
46.372ms
0.045ms
0.090ms
·
·
20.000ms
·
40.000ms
·
60.000ms
·
80.000ms
·
92.698ms
·
92.744ms
0.068ms
0.136ms
·
·
30.000ms
·
60.000ms
·
90.000ms
·
120.000ms
·
139.048ms
·
139.116ms
Table 8-5-12. SFC Mode Delay Time Setting Value Examples
(7)-2. All Pass Filters (APF0, APF1)
The all pass filter delay times are determined by (read address) – (write address - 0020H). Set ap∗_in and
ap∗_out so that this subtraction results in the target delay time setting value. The calculation method is the
same as that for tp_fb.
Example) When setting a maximum comb filter delay time of 58ms and splitting the remainder evenly
between APF0 and APF1.
(1/2 decimation)
(ffe0h – 9fe0H)/2 = 3000H
3000H is used for each.
tp_fb = 9fe0H, so:
ap0_in = a000H, ap0_out = 9fe0H + 3000H = cfe0H
ap1_in = d000H, ap1_out = cfe0H + 3000H = ffe0H
tp_fb
0000H
9fe0H
58.0ms
ap0_in
ap0_out
a000H
cfe0H
17.4ms
ap1_in
ap1_out
d000H
ffe0H
17.4ms
92.8ms (0000H to ffe0H)
Fig. 8-5-3. Delay Time Setting Example (1/2 Decimation)
Note) Assuming the tap read address to be 0000H, the comb filter has a delay time of "0". However, the all
pass filters are delayed by one sample after reading from the delay RAM.
Therefore, perfect through operation is not possible even if (write address) = (read address).
– 57 –
CXD2728Q
Appendix 1. Soft Mute
The condition where the final volume coefficient data connected to the CXD2728Q output of each mode is off
(= 0000H) is called "soft mute".
Table 9 shows the coefficients that should be set to 0000H in each mode during soft mute. Table 9 also
includes the loop input volume coefficients and feedback volume coefficients for modes which contain a
feedback loop.
Mode name
Coefficient name (Address [H])
Pro Logic mode
KLV (00), KRV (01), KCV (02), KSV (03), KLd (0e), KRd (0f), KCd (10), KSd (11),
Kfb (12), KDV1 (21), KDV2 (22), KDV3 (23), KLRm1 (24), KLRm2 (25), KLRm3 (26),
KL (f2), KR (f3), KH (f4), KP (f5), KCH (f6), KCP (f7), KS (f8)
Virtual mode
attV (f1), KL (f2), KR (f3), KCP (f7), KS (f8)
Dolby 3 Stereo mode
Same as Pro Logic mode
Noise sequencer mode
Same as Pro Logic or Virtual mode
SFC mode
KLsri (0c), KRsri (0d), Kfb (0e), KLod (32), KRod (33), KSod (34), KCod (37)
Table 9. Recommended Mute Coefficients
RAM Initialization
Although this LSI contains a number of RAM, there is no clear function and the like. Therefore, it is impossible
to predict the type of data existing in the RAM after power-on. Also, the previous mode's data remains even
after the mode is changed, possibly causing momentary noise. If these problems cannot be handled by the
system mute, apply soft mute for a time equal to the maximum delay time of the delay RAM (varies according
to the mode and coefficient settings) during power-on and when changing the mode. This clears all the RAM.
Example 1) When using 20.0ms for the passive decoder and 26.4ms for the simple SFC delay line
The maximum delay time is 26.4ms, so soft mute must be applied continuously for 26.4ms.
Example 2) When using the delay RAM in SFC mode with 1/2 decimation
Comb filter delay time = 58.0ms
All pass filter delay time = 17.4ms
The maximum delay time is 58.0ms, so soft mute must be applied for 58.0ms.
– 58 –
CXD2728Q
Appendix 2. Compensation Filter
This filter compensates the shoulder characteristics of the digital filters. Fig. 9 shows the frequency response
measured under the following conditions.
• Vin = 300mVrms (sine wave)
• Output level at 1kHz = 0dB
• DC cut filter cut-off = 5kHz
+2
+1
0
–1
Level [dB]
–2
–3
–4
–5
–6
Compensation filter [L-ch]
0dB = 300mVrms (1kHz sin)
–7
–8
–9
–10
10
20
50
100 200
500 1k
Frequency [Hz]
2k
5k
10k
20k
Fig. 9. Compensation Filter Frequency Response (Dotted line: Without the compensation filter)
Operation
Turn the filter on and off in each mode except bypass mode using SQA12 of setup register Field A. See "6.
Setup Register".
– 59 –
A
G
CXD2728Q
AVD6 10
DGND
0.1µF
DGND
AGND
0.1µF
65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80
AVD2 2
RREF 1
AVD4 3
AO2N 4
: Digital +3.3V power supply
G
F
E
D
C
B
A
–12V
IC3
–12V
IC1
220p
47k
AGND
47k
47k
47k
AGND
220p
15k
4.3k
IC3
Sch output
AGND
Rch input
AGND AGND
Rch output
AGND AGND
22p 10µF
220p
AGND
3.9k
AGND
22p
Cch output
AGND AGND
15p 10µF
IC2
Lch output
AGND AGND
15p 10µF
15p IC2
AGND
120k
220p
AGND
3.3k
18k
150k
120k 15k
120p
AGND
47k
100p
15p
AGND
150k 18k
100p
AGND
47k
150p
18k
150k
AGND
Lch input
22p 10µF
22p IC1
AGND
150k 18k
100p
AGND
47k
150p
15k
120k 15k
120p
120k
4.3k
220p
AGND
3.9k
220p
AGND
AGND
47k
100p
3.9k
AGND
18k
18k
10k
10k
10k
10k
18k
18k
AGND
3.9k
3.3k
Application circuits shown are typical examples illustrating the operation of the devices.
Sony cannot assume responsibility for any problems arising out of the use of these circuits
or for any infringement of third party patent and other right due to same.
10µF
1.5M
AGND
AGND
AGND
AGND
AGND
AGND
AGND
0.1µF
0.1µF
AGND
AO2P 5
AVS4 6
0.1µF
0.1µF
AGND
0.1µF
AGND
AGND
0.1µF
0.1µF
AGND
0.1µF
0.1µF
2.2M 10µF
AGND
AVS6 7
AO4N 8
AO4P 9
: +3.3V power supplies for each analog I/O and the crystal oscillator circuit
64 T.P
63 T.P
62 T.P
61 T.P
60 T.P
59 T.P
58 T.P
57 VSS3
56 T.P
55 T.P
XTLO 12
AVDX 11
53 T.P
54 T.P
52 T.P
XTLI 13
AVSX 14
T.P
51 VDD2
T.P
AVD5 15
T.P
AO3N 16
T.P
50 T.P
T.P
49 T.P
VDD0
AO3P 17
T.P
48 T.P
T.P
47
T.P
AVS5 18
T.P
T.P
VSS5
• Two NE5522 operational amplifiers are used in combination as shown in the figure.
• Use ±12V power supplies for the operational amplifiers and connect 0.1µF by-pass capacitors.
• A crystal oscillator (DAISHINKU CORP., AT-49, 33.8688MHz) is used.
• Wiring specified by bold lines should be thick, short, and shielded around its periphery by GND.
• Resistor deviation: ±1%, capacitor deviation: ±5%
(In particular, large ADC front-end resistor deviation will adversely affect Pro Logic mode separation.)
to
DGND
BCK
AVS3 19
SI
46 VSS2
T.P
AO1N 20
T.P
45 T.P
BFOT
AO1P 21
VDD1
44 T.P
XS24
AVD3 22
RVDT
43 T.P
T.P
LREF 24
XLAT
AVD1 23
VSS0
42 XMST
SCK
T.P
LIN
41 LRCK
AVS2
VSS1
VSS4
DGND
DGND AGND
AVS1
40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
DGND
Microcomputer
REDY
XRST
XRST
– 60 –
RIN
0.1µF
0.1µF
DGND DGND DGND
Application circuit
CXD2728Q
CXD2728Q
Package Outline
Unit: mm
80PIN QFP (PLASTIC)
23.9 ± 0.4
+ 0.1
0.15 – 0.05
+ 0.4
20.0 – 0.1
64
0.15
41
65
16.3
17.9 ± 0.4
+ 0.4
14.0 – 0.1
40
A
+ 0.2
0.1 – 0.05
25
1
24
0.8
0.2
M
+ 0.15
0.35 – 0.1
+ 0.35
2.75 – 0.15
0° to 10°
DETAIL A
PACKAGE STRUCTURE
PACKAGE MATERIAL
EPOXY RESIN
SONY CODE
QFP-80P-L01
LEAD TREATMENT
SOLDER PLATING
EIAJ CODE
QFP080-P-1420
LEAD MATERIAL
42/COPPER ALLOY
PACKAGE MASS
1.6g
JEDEC CODE
– 61 –
0.8 ± 0.2
80