SONY CXD3412

CXD3412GA
Timing Generator and Signal Processor for Frame Readout CCD Image Sensor
Description
The CXD3412GA is a timing generator and CCD
signal processor IC for the ICX412 CCD image sensor.
Features
• Timing generator functions
• Horizontal drive frequency 22.5MHz
(base oscillation frequency 45MHz)
• Supports frame readout/draft (sextuple speed)/
AF (auto focus)
• High-speed/low-speed shutter function
• Horizontal and vertical drivers for CCD image
sensor
• CCD signal processor functions
• Correlated double sampling
• Programmable gain amplifier (PGA) allows gain
adjustment over a wide range (–6 to +42dB)
• 10-bit A/D converter
• Chip Scale Package (CSP):
CSP allows vast reduction in the CCD camera
block footprint
96 pin LFLGA (Plastic)
Absolute Maximum Ratings
• Supply voltage
VDDa, VDDb, VDDc, VDDd VSS – 0.3 to +7.0
V
VDDe, VDDf, VDDg
VSS – 0.3 to +4.0
V
VL
–10.0 to VSS
V
VH
VL – 0.3 to +26.0
V
• Input voltage (analog)
VIN
VSS – 0.3 to VDD + 0.3 V
• Input voltage (digital)
VI
VSS – 0.3 to VDD + 0.3 V
• Output voltage
VO1
VSS – 0.3 to VDD + 0.3 V
VO2
VL – 0.3 to VSS + 0.3 V
VO3
VL – 0.3 to VH + 0.3
V
• Operating temperature
Topr
–20 to +75
°C
• Storage temperature
Tstg
–55 to +125
°C
Applications
Digital still cameras
Structure
Silicon gate CMOS IC
Applicable CCD Image Sensors
ICX412 (Type 1/1.8, 3240K pixels)
Recommended Operating Conditions
• Supply voltage
VDDd
3.0 to 5.5
VDDa, VDDb, VDDc, VDDd,
VDDe, VDDf, VDDg
3.0 to 3.6
VM
0.0
VH
14.5 to 15.5
VL
–7.0 to –8.0
• Operating temperature
Topr
–20 to +75
V
V
V
V
V
°C
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E02217-PS
CXD3412GA
DVSS2
E2 F2 F3
DVSS1
B5
DVDD2
DVDD1
A3 A4 B4
DVSS3
TEST5
TEST3
A5 C4
SEN2
SSI2
SCK2
AVSS5
AVSS4
AVSS3
B8 B6 B9 A6 C5
TEST4
A1 A2 C7 D8 D7
AVDD4
AVDD3
C1
C2
C3
NC
NC
Block Diagram
E3 F1
C4 C8
AVDD5 A9
Serial Port
Register
DAC
AVSS6 A8
C7 B7
C8 A7
B3
D0 (LSB)
B2
D1
B1
D2
C3 D3
C9 C6
C2 D4
CDS
CCDIN C9
PGA
ADC
Latch
C1 D5
AVDD1 E9
D3 D6
AVDD2 E8
D2 D7
AVSS1 D9
D1 D8
AVSS2 E7
XSHPI
F9
XSHDI
F8
PBLKI
F7
XSHP
G9
XSHD
G8
PBLK
G7
E1
Dummy Pixel
Auto Zero
Preblanking
Black Level
Auto Zero
G1
G2
G3
L3
H1
XRS H7
H2
VDD4 H8
H3
VDD2 K7
J3
RG K8
VSS2 K9
L1
VDD3 H9
K1
Pulse Generator
H1 J8
J1
H2 J9
1/2
VSS3 J7
ID/EXP N9
Latch
D9 (MSB)
ADCLKI
CLPOBI
CLPDMI
VSS4
ADCLK
CLPOB
CLPDM
VSS5
OSCI
OSCO
CKI
J2
CKO
K2
MCKO
N8 SNCSL
Selector
WEN M9
L2
Serial Port
Register
VH M5
SSI1
M1 SCK1
V Driver
N1 SEN1
Selector
VM L4
–2–
L8
L9
K3 L7
N3
VD
VDD1
VDD5
VSS1
VSS6
SSG
N2 M2
HD
SUB
V4
V3B
V3A
N6 N4 N7
V2
L5 N5 M4 L6
V1B
TEST2
TEST1
RST
M8 M3 M7
V1A
VL M6
SSGSL
CXD3412GA
Pin Configuration (Top View)
A
NC
NC
SCK2
SSI2
TEST3
AVSS4
C8
AVSS6
AVDD5
B
D2
D1
D0
SEN2
TEST5
AVDD4
C7
AVDD3
AVSS3
C
D5
D4
D3
TEST4
AVSS5
C9
C3
C4
CCDIN
D
D8
D7
D6
C1
C2
AVSS1
E
D9
DVDD1
DVSS1
AVSS2
AVDD2
AVDD1
F
DVSS2
DVSS3
DVDD2
PBLKI
XSHDI
XSHPI
G
ADCLKI
CLPOBI
CLPDMI
PBLK
XSHD
XSHP
H
ADCLK
CLPOB
CLPDM
XRS
VDD4
VDD3
J
CKI
CKO
VSS5
VSS3
H1
H2
K
OSCO
MCKO
VDD5
VDD2
RG
VSS2
L
OSCI
SSI1
VSS4
VM
V1A
V3A
VSS1
SSGSL
VDD1
M
SCK1
VD
TEST1
V2
VH
VL
TEST2
RST
WEN
N
SEN1
HD
VSS6
V4
V1B
V3B
SUB
SNCSL
ID/EXP
1
2
3
4
5
6
7
8
9
–3–
CXD3412GA
Pin Description
Pin
No.
Symbol
I/O
Description
A1
NC
—
No connected. (Open)
A2
NC
—
No connected. (Open)
A3
SCK2
I
CCD signal processor block serial interface clock input. (Schmitt trigger)
A4
SSI2
I
CCD signal processor block serial interface data input. (Schmitt trigger)
A5
TEST3
I
CCD signal processor block test input 3. Connect to DVSS.
A6
AVSS4
—
CCD signal processor block analog GND.
A7
C8
—
Capacitor connection.
A8
AVSS6
—
CCD signal processor block analog GND.
A9
AVDD5
—
CCD signal processor block analog power supply.
B1
D2
O
ADC output.
B2
D1
O
ADC output.
B3
D0
O
ADC output (LSB).
B4
SEN2
I
CCD signal processor block serial interface enable input. (Schmitt trigger)
B5
TEST5
I
CCD signal processor block test input 5. Connect to DVDD.
B6
AVDD4
—
CCD signal processor block analog power supply.
B7
C7
—
Capacitor connection.
B8
AVDD3
—
CCD signal processor block analog power supply.
B9
AVSS3
—
CCD signal processor block analog GND.
C1
D5
O
ADC output.
C2
D4
O
ADC output.
C3
D3
O
ADC output.
C4
TEST4
I
CCD signal processor block test input 4. Connect to DVSS.
C5
AVSS5
—
CCD signal processor block analog GND.
C6
C9
—
Capacitor connection.
C7
C3
—
Capacitor connection.
C8
C4
—
Capacitor connection.
C9
CCDIN
I
CCD output signal input.
D1
D8
O
ADC output.
D2
D7
O
ADC output.
D3
D6
O
ADC output.
D7
C1
—
Capacitor connection.
D8
C2
—
Capacitor connection.
D9
AVSS1
—
CCD signal processor block analog GND.
E1
D9
O
ADC output (MSB).
E2
DVDD1
—
CCD signal processor block digital power supply. (Power supply for ADC)
E3
DVSS1
—
CCD signal processor block digital GND. (GND for ADC)
E7
AVSS2
—
CCD signal processor block analog GND.
–4–
CXD3412GA
Pin
No.
Symbol
I/O
Description
E8
AVDD2
—
CCD signal processor block analog power supply.
E9
AVDD1
—
CCD signal processor block analog power supply.
F1
DVSS2
—
CCD signal processor block digital GND.
F2
DVSS3
—
CCD signal processor block digital GND.
F3
DVDD2
—
CCD signal processor block digital power supply.
F7
PBLKI
I
Pulse input for horizontal and vertical blanking period pulse cleaning.
(Schmitt trigger)
F8
XSHDI
I
CCD data level sample-and-hold pulse input. (Schmitt trigger)
F9
XSHPI
I
CCD precharge level sample-and-hold pulse input. (Schmitt trigger)
G1
ADCLKI
I
Clock input for analog/digital conversion. (Schmitt trigger)
G2
CLPOBI
I
CCD optical black signal clamp pulse input. (Schmitt trigger)
G3
CLPDMI
I
CCD dummy signal clamp pulse input. (Schmitt trigger)
G7
PBLK
O
Pulse output for horizontal and vertical blanking period pulse cleaning.
G8
XSHD
O
CCD data level sample-and-hold pulse output.
G9
XSHP
O
CCD precharge level sample-and-hold pulse output.
H1
ADCLK
O
Clock output for analog/digital conversion.
Logical phase can be adjusted by serial interface data.
H2
CLPOB
O
CCD optical black signal clamp pulse output.
Horizontal/vertical OB pattern can be changed by serial interface data.
H3
CLPDM
O
CCD dummy signal clamp pulse output.
H7
XRS
O
Sample-and-hold pulse output for analog/digital conversion phase alignment.
H8
VDD4
—
Timing generator block digital power supply. (Power supply for CDS block)
H9
VDD3
—
Timing generator block 3.0 to 5.0V power supply. (Power supply for H1/H2)
J1
CKI
I
Inverter input.
J2
CKO
O
Inverter output.
J3
VSS5
—
Timing generator block digital GND.
J7
VSS3
—
Timing generator block digital GND.
J8
H1
O
CCD horizontal register clock output.
J9
H2
O
CCD horizontal register clock output.
K1
OSCO
O
Inverter output for oscillation. When not used, leave open or connect a capacitor.
K2
MCKO
O
System clock output for signal processor IC.
K3
VDD5
—
Timing generator block digital power supply. (Power supply for common logic block)
K7
VDD2
—
Timing generator block digital power supply. (Power supply for RG)
K8
RG
O
CCD reset gate pulse output.
K9
VSS2
—
Timing generator block digital GND.
L1
OSCI
I
Inverter input for oscillation. When not used, fix to low.
L2
SSI1
I
Timing generator block serial interface data input. Schmitt trigger input.
–5–
CXD3412GA
Pin
No.
Symbol
I/O
Description
L3
VSS4
—
Timing generator block digital GND.
L4
VM
—
Timing generator block digital GND. (GND for vertical driver)
L5
V1A
O
CCD vertical register clock output.
L6
V3A
O
CCD vertical register clock output.
L7
VSS1
—
Timing generator block digital GND.
L8
SSGSL
L9
VDD1
—
M1
SCK1
I
M2
VD
M3
TEST1
I
Timing generator block test input 1.
Normally fix to GND.
M4
V2
O
CCD vertical register clock output.
M5
VH
—
Timing generator block 15.0V power supply. (Power supply for vertical driver)
M6
VL
—
Timing generator block –7.5V power supply. (Power supply for vertical driver)
M7
TEST2
I
I/O
Internal SSG enable.
High: Internal SSG valid, Low: External sync valid
(With pull-down resistor)
Timing generator block digital power supply. (Power supply for common logic block)
Timing generator block serial interface clock input.
Schmitt trigger input.
Vertical sync signal input/output.
I
Timing generator block test input 2.
Normally fix to GND.
(With pull-down resistor)
(With pull-down resistor)
M8
RST
I
Timing generator block reset input.
High: Normal operation, Low: Reset control
Normally apply reset during power-on.
Schmitt trigger input/No protective diode on power supply side.
M9
WEN
O
Memory write timing pulse output.
N1
SEN1
I
Timing generator block serial interface strobe input.
Schmitt trigger input.
N2
HD
I/O
Horizontal sync signal input/output.
N3
VSS6
—
Timing generator block digital GND.
N4
V4
O
CCD vertical register clock output.
N5
V1B
O
CCD vertical register clock output.
N6
V3B
O
CCD vertical register clock output.
N7
SUB
O
CCD electronic shutter pulse output.
N8
SNCSL
I
Control input used to switch sync system.
High: CKI sync, Low: MCKO sync
N9
ID/EXP
O
Vertical direction line identification pulse output/exposure time identification pulse
output.
Switching possible using the serial interface data. (Default: ID)
–6–
(With pull-down resistor)
CXD3412GA
Electrical Characteristics
Timing Generator Block Electrical Characteristics
DC Characteristics
Item
(Within the recommended operating conditions)
Pins
Symbol
Conditions
Min.
Typ.
Max.
Unit
Supply voltage 1
VDD2
VDDa
3.0
3.3
3.6
V
Supply voltage 2
VDD3
VDDb
3.0
3.3
5.25
V
Supply voltage 3
VDD4
VDDc
3.0
3.3
3.6
V
Supply voltage 4
VDD1, VDD5
VDDd
3.0
3.3
3.6
V
Input
voltage 1∗1
RST, SSI1,
SCK1, SEN1
VI+
Input
voltage 2∗2
TEST1, TEST2, VIH1
SNCSL, SSGSL VIL1
0.7VDDd
VIH2
0.8VDDd
Input/output
voltage
VD, HD
VI–
VOL1
Pull-in current where IOL = 2.4mA
VOH2
Feed current where IOH = –22.0mA VDDb – 0.8
VOL2
Pull-in current where IOL = 14.4mA
VOH3
Feed current where IOH = –3.3mA
VOL3
Pull-in current where IOL = 2.4mA
Output
voltage 2
RG
Output
voltage 3
XSHP, XSHD,
XRS, PBLK, VOH4
CLPOB,
CLPDM,
VOL4
ADCLK
Output
voltage 4
CKO
Output
voltage 5
MCKO
Output
voltage 6
ID/EXP,
WEN
Output
current 1
V1A, V1B,
V3A, V3B,
V2, V4
SUB
Feed current where IOH = –3.3mA
VDDd – 0.8
VOH5
Feed current where IOH = –6.9mA
VOL5
Pull-in current where IOL = 4.8mA
VOH6
Feed current where IOH = –3.3mA
VOL6
Pull-in current where IOL = 2.4mA
VOH7
Feed current where IOH = –2.4mA
VOL7
Pull-in current where IOL = 4.8mA
IOL
V1A/B, V2, V3A/B, V4 = –8.25V
IOM1
V1A/B, V2, V3A/B, V4 = –0.25V
IOM2
V1A/B, V3A/B = 0.25V
IOH
V1A/B, V3A/B = 14.75V
IOSL
SUB = –8.25V
IOSH
SUB = 14.75V
V
V
0.4
VDDa – 0.8
V
V
0.4
VDDc – 0.8
V
V
0.4
VDDd – 0.8
V
V
0.4
VDDd – 0.8
V
V
0.4
VDDd – 0.8
V
V
0.4
10.0
V
mA
–5.0
5.0
mA
mA
–7.2
5.4
mA
mA
–4.0
∗1 This input pin is a schmitt trigger input and it has protective diode of the power supply side in the IC.
It is not supported to 5V input.
∗2 These input pins are with pull-down resistor in the IC.
Note) This table indicates the conditions for 3.3V drive.
–7–
V
V
0.4
Pull-in current where IOL = 2.4mA
V
V
0.2VDDd
Feed current where IOH = –1.2mA
V
V
0.3VDDd
VOH1
H1, H2
V
0.2VDDd
VIL2
Output
voltage 1
Output
current 2
0.8VDDd
mA
CXD3412GA
Inverter I/O Characteristics for Oscillation
Item
Pins
Logical Vth
OSCI
Input
voltage
OSCI
Output
voltage
OSCO
Feedback
resistor
Oscillation
frequency
Symbol
(Within the recommended operating conditions)
Conditions
Min.
LVth
Typ.
Max.
VDDd/2
VIH
V
0.7VDDd
V
VIL
0.3VDDd
VOH
Feed current where IOH = –3.6mA
VOL
Pull-in current where IOL = 2.4mA
OSCI,
OSCO
RFB
VIN = VDDd or VSS
OSCI,
OSCO
f
VDDd – 0.8
500k
Unit
V
V
2M
20
0.4
V
5M
Ω
50
MHz
Inverter Input Characteristics for Base Oscillation Clock Duty Adjustment
(Within the recommended operating conditions)
Item
Pins
Symbol
Logical Vth
LVth
Input
voltage
VIH
CKI
Input
amplitude
Conditions
Min.
Typ.
VDDd/2
V
0.3VDDd
fmax 50MHz sine wave
Unit
V
0.7VDDd
VIL
VIN
Max.
0.3
V
Vp-p
Note) Input voltage is the input voltage characteristics for direct input from an external source.
Input amplitude is the input amplitude characteristics in the case of input through a capacitor.
Switching Characteristics
Item
Rise time
Fall time
Output noise voltage
(VH = 15.0V, VM = GND, VL = –7.5V)
Symbol
Conditions
Min.
Typ.
Max.
Unit
TTLM
VL to VM
200
350
500
ns
TTMH
VM to VH
200
350
500
ns
TTLH
VL to VH
30
60
90
ns
TTML
VM to VL
200
350
500
ns
TTHM
VH to VM
200
350
500
ns
TTHL
VH to VL
30
60
90
ns
VCLH
1.0
V
VCLL
1.0
V
VCMH
1.0
V
VCML
1.0
V
Notes)
1. The MOS structure of this IC has a low tolerance for static electricity, so full care should be given for
measures to prevent electrostatic discharge.
2. For noise and latch-up countermeasures, be sure to connect a by-pass capacitor (0.1µF or more) between
each power supply pin (VH, VL) and GND.
3. To protect the CCD image sensor, clamp the SUB pin output at VH before input to the CCD image sensor.
–8–
CXD3412GA
Switching Waveforms
TTMH
TTHM
VH
V1A (V1B, V3A, V3B)
TTLM
90%
90%
10%
10%
TTML
VM
90%
90%
10%
10%
TTML
TTLM
VL
VM
90%
90%
V2 (V4)
10%
10%
TTLH
TTHL
90%
VL
VH
90%
SUB
10%
10%
VL
Waveform Noise
VM
VCMH
VCML
VCLH
VCLL
VL
–9–
Measurement Circuit
Serial interface data
CKI
VD
HD
+3.3V
C6
+15.0V
C4
C5 C5
C6
C6
–7.5V
PBLK
XSHD
VSS4
XSHP
CLPOB
XRS
CLPDM
VDD4
CKI
VDD3
VSS5
CKO
H1
VSS3
H2
VDD5
OSCI
OSCO
RG
VDD2
VSS2
MCKO
VSS6
R1
SSI1
N3 L2 K2 K9 K8 K7 K1 L1 K3 J9 J8 J7 J3 J2 J1 H9 H8 H7 H3 H2 L3 G9 G8 G7
M4 V2
CLPDMI G3
M5 VH
CLPOBI G2
M6 VL
ADCLK
H1
E1 D9
XSHPI
F9
L8
SSGSL
XSHDI
F8
L9
VDD1
PBLKI
F7
DVDD2
F3
DVSS3
F2
M1 SCK1
M2 VD
C2
M3 TEST1
R1
C1 C2
E7
E3
M9 WEN
DVDD1
E2
N1 SEN1
AVDD2
E8
N2 HD
C2
D8
L4
VM
C1
D7
L5
V1A
D6
D3
L6
V3A
D7
D2
N7 SUB
D8
D1
CCDIN
C9
N8 SNCSL
C4
C8
N9 ID/EXP
C3
C7
C9
AVSS5
TEST4
D3
D4
D5
AVDD3
AVSS3
C7
AVDD4
TEST5
SEN2
D0
C3
VSS1
D1
L7
D2
R1
DVSS1
AVDD5
C2
R2
F1
M8 RST
AVSS6
R1
DVSS2
C8
C1
C1
C2
AVSS2
CXD3412GA
M7 TEST2
AVSS4
C2
D9
TEST3
C1
C2
E9
AVSS1
N6 V3B
C2
C2
AVDD1
N5 V1B
SSI2
R1
C2 C2
C2
N4 V4
SCK2
C2
C1
C2
NC
– 10 –
C1
C2
ADCLKI G1
NC
C2
R1
A2 A1 A3 A4 A5 A6 A7 A8 A9 B1 B2 B3 B4 B5 B6 B7 B9 B8 C1 C2 C3 C4 C5 C6
C2: 560pF
R2: 10Ω
C3: 820pF
C4: 8pF
C5: 215pF
C6: 10pF
CXD3412GA
C1: 3300pF
R1: 30Ω
CXD3412GA
AC Characteristics
AC characteristics between the serial interface clocks
0.8VDDd
SSI1
0.2VDDd
0.8VDDd
0.2VDDd
ts1
SCK1
SEN1
th1
0.2VDDd
ts3
0.8VDDd
SEN1
ts2
(Within the recommended operating conditions)
Symbol
Definition
Min.
Typ.
Max.
Unit
ts1
SSI1 setup time, activated by the rising edge of SCK1
20
ns
th1
SSI1 hold time, activated by the rising edge of SCK1
20
ns
ts2
SCK1 setup time, activated by the rising edge of SEN1
20
ns
ts3
SEN1 setup time, activated by the rising edge of SCK1
20
ns
Serial interface clock internal loading characteristics (1)
Example: During frame mode
VD
HD
V1A
Enlarged view
HD
0.2VDDd
V1A
th1
ts1
SEN1
0.8VDDd
0.2VDDd
∗ Be sure to maintain a constantly high SEN1 logic level near the falling edge of the HD in the horizontal
period during which V1A/B and V3A/B values take the ternary value and during that horizontal period.
(Within the recommended operating conditions)
Symbol
Definition
Min.
Typ.
Max.
Unit
ts1
SEN1 setup time, activated by the falling edge of HD
0
ns
th1
SEN1 hold time, activated by the falling edge of HD
113
µs
– 11 –
CXD3412GA
Serial interface clock internal loading characteristics (2)
Example: During frame mode
VD
HD
Enlarged view
VD
0.2VDDd
HD
ts1
SEN1
th1
0.8VDDd
0.2VDDd
∗ Be sure to maintain a constantly high SEN1 logic level near the falling edge of VD.
(Within the recommended operating conditions)
Symbol
Definition
Min.
Typ.
Max.
Unit
ts1
SEN1 setup time, activated by the falling edge of VD
0
ns
th1
SEN1 hold time, activated by the falling edge of VD
200
ns
Serial interface clock output variation characteristics
Normally, the serial interface data is loaded to the CXD3412GA at the timing shown in "Serial interface clock
internal loading characteristics (1)" above. However, one exception to this is when the data such as STB is
loaded to the CXD3412GA and controlled at the rising edge of SEN1. See "Description of Operation".
SEN1
0.8VDDd
Output signal
tpdPULSE
(Within the recommended operating conditions)
Symbol
Definition
Min.
tpdPULSE Output signal delay, activated by the rising edge of SEN1
– 12 –
15
Typ.
Max.
Unit
100
ns
CXD3412GA
RST loading characteristics
RST
0.2VDDd
0.2VDDd
tw1
(Within the recommended operating conditions)
Symbol
tw1
Definition
Min.
RST pulse width
Typ.
Max.
28
Unit
ns
VD and HD phase characteristics
VD
0.2VDDd
0.2VDDd
ts1
th1
HD
0.2VDDd
(Within the recommended operating conditions)
Symbol
Definition
Min.
Typ.
Max.
Unit
ts1
VD setup time, activated by the falling edge of HD
0
ns
th1
VD hold time, activated by the falling edge of HD
0
ns
HD loading characteristics
HD
0.2VDDd
0.2VDDd
ts1
th1
0.8VDDd
MCKO
MCKO load capacitance = 10pF
(Within the recommended operating conditions)
Symbol
Definition
Min.
Typ.
Max.
Unit
ts1
HD setup time, activated by the rising edge of MCKO
20
ns
th1
HD hold time, activated by the rising edge of MCKO
0
ns
– 13 –
CXD3412GA
Output variation characteristics
0.8VDDd
MCKO
WEN, ID/EXP
tpd1
WEN and ID/EXP load capacitance = 10pF
(Within the recommended operating conditions)
Symbol
tpd1
Definition
Min.
Time until the above outputs change after the rise of MCKO
25
– 14 –
Typ.
Max.
Unit
70
ns
CXD3412GA
CCD Signal Processor Block Electrical Characteristics
DC Characteristics
Item
(Fc = 22.5MSPS, DVDD1, 2 = AVDD1, 2, 3, 4, 5 = 3.3V, Ta = 25°C)
Pins
Symbol
Conditions
Min.
Typ. Max. Unit
Supply voltage 1 DVDD1
VDDe
3.0
3.3
3.6
V
Supply voltage 2 DVDD2
VDDf
3.0
3.3
3.6
V
AVDD1,
AVDD2,
Supply voltage 3 AVDD3,
AVDD4,
AVDD5
VDDg
3.0
3.3
3.6
V
Analog input
capacitance
CCDIN
CIN
15
pF
1.8
V
Input voltage
SCK2, SSI2,
VI+
SEN2, TEST3,
TEST4, XSHDI,
XSHPI, ADCLKI, VI–
CLPOBI,
CLPDMI, PBLKI
1.1
V
A/D clock duty
ADCLKI
50
%
Output voltage
D0 to D9
VOH
Feed current where IOH = –2.0mA VDDe – 0.9
VOL
Pull-in current where IOL = 2.0mA
0.4
V
(Fc = 22.5MSPS, DVDD1, 2 = AVDD1, 2, 3, 4, 5 = 3.3V, Ta = 25°C)
Analog Characteristics
Item
V
Symbol
Conditions
Min.
900
Typ.
Max. Unit
CCDIN input voltage amplitude
VIN
PGA gain = 0dB, output full scale
PGA maximum gain
Gmax
PGA gain setting data = "3FFh"
42
dB
PGA minimum gain
Gmin
PGA gain setting data = "000h"
–6
dB
10
bit
ADC resolution
1100 mV
ADC maximum conversion rate
Fc max
22.5
ADC integral non-linearity error
EL
PGA gain = 0dB
±1.0
LSB
ADC differential non-linearity error
ED
PGA gain = 0dB
±0.5
LSB
Signal-to-noise ratio
SNR
CCDIN input connected to GND
via a coupling capacitor
PGA gain = 0dB
77
dB
CCDIN input voltage clamp level
CLP
1.5
V
CCD optical black signal clamp
level
OB
32
LSB
OBLVL = "8h"
PGA gain = 0dB
– 15 –
MHz
CXD3412GA
AC Characteristics
AC characteristics between the serial interface clocks
0.8VDD
SSI2
0.2VDD
0.8VDD
SCK2
ts1
SEN2
th1
0.2VDD
ts3
0.8VDD
SEN2
ts2
∗ The setting values are reflected to the operation 6 ADCLKI clocks after the serial data is loaded at the rise
of SEN2.
(Fc = 22.5MSPS, DVDD1, 2 = AVDD1, 2, 3, 4, 5 = 3.3V, Ta = 25°C)
Symbol
Definition
Min.
Typ.
Max.
Unit
tp1
SCK2 clock period
100
ns
ts1
SSI2 setup time, activated by the rise of SCK2
30
ns
th1
SSI2 hold time, activated by the rise of SCK2
30
ns
ts2
SCK2 setup time, activated by the rise of SEN2
30
ns
ts3
SEN2 setup time, activated by the rise of SCK2
30
ns
– 16 –
CXD3412GA
CDS/ADC Timing Chart
N
N+1
N+2
N+3
CCDIN
XSHPI
XSHDI
tw1
ADCLKI
DL
D0 to D9
N – 10
N–9
N–8
N–7
∗ Set the input pulse polarity setting data D13, D14 and D15 of the serial interface data to "0".
(Fc = 22.5MSPS, DVDD1, 2 = AVDD1, 2, 3, 4, 5 = 3.3V, Ta = 25°C)
Symbol
tw1
DL
Definition
Min.
ADCLKI clock period
Typ.
44
Max.
Unit
ns
ADCLKI clock duty
50
%
Data latency
9
clocks
Preblanking Timing Chart
PBLKI
11 Clocks
ADCLKI
11 Clocks
All "0"
D0 to D9
– 17 –
CXD3412GA
Description of Operation
Pulses output from the CXD3412GA's timing generator block are controlled mainly by the RST pin and by the
serial interface data. The Pin Status Table is shown below, and the details of serial interface control are
described on page 20 and thereafter.
Pin Status Table
Pin
No.
Symbol
CAM
SLP
STB
RST
Pin
No.
Symbol
CAM
SLP
STB
RST
A1
NC
—
D8
C2
—
A2
NC
—
D9
AVSS1
—
A3
SCK2
—
E1
D9
—
A4
SSI2
—
E2
DVDD1
—
A5
TEST3
—
E3
DVSS1
—
A6
AVSS4
—
E7
AVSS2
—
A7
C8
—
E8
AVDD2
—
A8
AVSS6
—
E9
AVDD1
—
A9
AVDD5
—
F1
DVSS2
—
B1
D2
—
F2
DVSS3
—
B2
D1
—
F3
DVDD2
—
B3
D0
—
F7
PBLKI
—
B4
SEN2
—
F8
XSHDI
—
B5
TEST5
—
F9
XSHPI
—
B6
AVDD4
—
G1
ADCLKI
—
B7
C7
—
G2
CLPOBI
—
B8
AVDD3
—
G3
CLPDMI
—
B9
AVSS3
—
G7
PBLK
ACT
L
L
H
C1
D5
—
G8
XSHD
ACT
L
L
ACT
C2
D4
—
G9
XSHP
ACT
L
L
ACT
C3
D3
—
H1
ADCLK
ACT
L
L
ACT
C4
TEST4
—
H2
CLPOB
ACT
L
L
H
C5
AVSS5
—
H3
CLPDM
ACT
L
L
H
C6
C9
—
H7
XRS
ACT
L
L
ACT
C7
C3
—
H8
VDD4
—
C8
C4
—
H9
VDD3
—
C9
CCDIN
—
J1
CKI
ACT
ACT
ACT
ACT
D1
D8
—
J2
CKO
ACT
ACT
L
ACT
D2
D7
—
J3
VSS5
—
D3
D6
—
J7
VSS3
—
D7
C1
—
J8
H1
L
ACT
– 18 –
ACT
L
CXD3412GA
Pin
No.
Symbol
CAM
SLP
STB
RST
Pin
No.
Symbol
CAM
SLP
STB
RST
ACT
L
L
H
VM
VM
J9
H2
ACT
L
L
ACT
M2
VD∗1
K1
OSCO
ACT
ACT
ACT
ACT
M3
TEST1
K2
MCKO
ACT
ACT
L
ACT
M4
V2
K3
VDD5
—
M5
VH
—
K7
VDD2
—
M6
VL
—
K8
RG
M7
TEST2
—
K9
VSS2
M8
RST
ACT
ACT
ACT
L
L1
OSCI
ACT
ACT
ACT
ACT
M9
WEN
ACT
L
L
L
L2
SSI1
ACT
ACT
ACT
DIS
N1
ACT
ACT
ACT
DIS
L3
VSS4
—
N2
SEN1
HD∗1
ACT
L
L
H
L4
VM
—
N3
VSS6
L5
V1A
ACT
VH
VH
VM
N4
V4
ACT
VM
VM
VL
L6
V3A
ACT
VH
VH
VL
N5
V1B
ACT
VH
VH
VM
L7
VSS1
N6
V3B
ACT
VH
VH
VL
L8
SSGSL
N7
SUB
ACT
VH
VH
VL
L9
VDD1
N8
SNCSL
ACT
ACT
ACT
ACT
M1
SCK1
N9
ID/EXP
ACT
L
L
L
ACT
L
L
ACT
—
—
ACT
ACT
ACT
ACT
—
ACT
ACT
ACT
DIS
—
ACT
VM
—
∗1 It is for output. For input, all items are "ACT".
Note) ACT means that the circuit is operating, and DIS means that loading is stopped.
L indicates a low output level, and H a high output level in the controlled status.
Also, VH, VM and VL indicate the voltage levels applied to VH (Pin M5), VM (Pin L3) and VL (Pin M6),
respectively, in the controlled status.
– 19 –
CXD3412GA
Timing Generator Block Serial Interface Control
The CXD3412GA's timing generator block basically loads and reflects the timing generator block serial
interface data sent in the following format in the readout portion at the falling edge of HD. Here, readout portion
specifies the horizontal period during which V1A/B and V3A/B, etc. take the ternary value.
Note that some items reflect the timing generator block serial interface data at the falling edge of VD or the
rising edge of SEN1.
SSI1
00
01
02
03
04
05
06
07
41
42
43
44
45
46
47
SCK1
SEN1
There are two categories of timing generator block serial interface data: CXD3412GA timing generator block
drive control data (hereafter "control data") and electronic shutter data (hereafter "shutter data").
The details of each data are described below.
– 20 –
CXD3412GA
Control Data
Data
D00
to
D07
Symbol
Data = 0
Sunction
Data = 1
RST
Chip enable
10000001 → Enabled
Other values → Disabled
All
0
D08,
CTG
D09
Category switching
See D08 to D09 CTG.
All
0
D10
to
D12
MODE
Drive mode switching
See D10 to D12 MODE.
All
0
D13
SMD
D14
HTSG
Electronic shutter mode switching∗1
HTSG control switching∗1
D15
PTSG
Internal SSG function switching
D16
to
D31
—
D32
FGOB
Wide CLPOB generation switching∗2
D33
EXP
ID/EXP output switching
CHIP
—
OFF
ON
0
OFF
ON
0
NTSC equivalent
PAL equivalent
0
—
—
All
0
OFF
ON
0
ID
EXP
0
All
0
D34,
PTOB
D35
CLPOB waveform pattern switching
See D34 to D35 PTOB.
D36,
LDAD
D37
ADCLK logic phase switching
See D36 to D37 LDAD.
D38,
STB
D39
Standby control
D40
to
D47
—
See D38 to D39 STB.
—
—
∗1 See D13 SMD.
∗2 See D32 FGOB.
– 21 –
—
1
0
All
0
All
0
CXD3412GA
Shutter Data
Data Symbol
D00
to
D07
Function
Data = 0
Data = 1
RST
Chip enable
10000001 → Enabled
Other values → Disabled
All
0
D08,
CTG
D09
Category switching
See D08 to D09 CTG.
All
0
D10
to
D19
SVD
Electronic shutter vertical period
specification
See D10 to D19 SVD.
All
0
D20
to
D31
SHD
Electronic shutter horizontal period
specification
See D20 to D31 SHD.
All
0
D32
to
D41
SPL
High-speed shutter position specification
See D32 to D41 SPL.
All
0
—
—
All
0
D42
to
D47
CHIP
—
– 22 –
CXD3412GA
Detailed Description of Each Data
Shared data: D08 , D09 CTG [Category]
Of the data provided to the CXD3412GA by the serial interface, the CXD3412GA loads D10 and subsequent
data to each data register as shown in the table below according to the conbination of D08 and D09 .
D09
D08
Description of operation
0
0
Loading to control data register
0
1
Loading to shutter data register
1
X
Test mode
Note that the CXD3412GA can apply these categories consecutively within the same vertical period. However,
care should be taken as the data is overwritten if the same category is applied.
Control data: D10 to D12 MODE [Drive mode]
The CXD3412GA timing generator block drive mode can be switched as follows. However, the drive mode bits
are loaded to the CXD3412GA and reflected at the falling edge of VD.
D12
D11
D10
Description of operation
0
0
0
Draft mode (sextuple speed: default)
0
0
1
Frame mode (A field read out)
0
1
0
Frame mode (B field read out)
0
1
1
Frame mode
1
0
X
AF1 mode
1
1
X
AF2 mode
Control data: D15 PTSG [Internal SSG output pattern]
The CXD3412GA internal SSG output pattern can be switched as follows. However, the internal SSG output
pattern bits are loaded to the CXD3412GA and reflected at the falling edge of VD.
D15
Description of operation
0
NTSC equivalent pattern output
1
PAL equivalent pattern output
VD period in each pattern is defined as follows. However, care should be taken that HD period is changing by
the mode.
Frame mode
NTSC equivalent pattern
885H + 810ck
PAL equivalent pattern
884H + 1104ck
Draft mode
AF1 mode
AF2 mode
285H + 1455ck × 2 142H + 1384ck + 1383ck 71H + 1384ck
342H + 2592ck
See the Timing Charts for the actual operation.
– 23 –
171H + 1296ck
85H + 1960ck
CXD3412GA
Control data: D32 FGOB [Wide CLPOB generation]
This controls wide CLPOB generation during the vertical OPB period. See the Timing Charts for the actual
operation. The default is "OFF".
D32
Description of operation
0
Wide CLPOB generation OFF
1
Wide CLPOB generation ON
Control data: D34 , D35 PTOB [CLPOB waveform pattern]
This indicates the CLPOB waveform pattern. The default is "Normal".
D35
D34
Waveform pattern
0
0
(Normal)
0
1
(Shifted rearward)
1
0
(Shifted forward)
1
1
(Wide)
Control data: D36 , D37 LDAD [ADCLK logic phase]
This indicates the ADCLK logic phase adjustment data. The default is 90° relative to MCKO.
D37
D36
Degree of adjustment (°)
0
0
0
0
1
90
1
0
180
1
1
270
Control data: D38 , D39 STB [Standby]
The operating mode is switched as follows. However, the standby bits are loaded to the CXD3412GA and
control is applied immediately at the rising edge of SEN1.
D39
D38
Symbol
Operating mode
X
0
CAM
Normal operating mode
0
1
SLP
Sleep mode
1
1
STB
Standby mode
See the Pin Status Table for the pin status in each mode.
– 24 –
CXD3412GA
Control data/shutter data: [Electronic shutter]
The CXD3412GA realizes various electronic shutter functions by using control data D13 SMD and D14
HTSG and shutter data D10 to D19 SVD, D20 to D31 SHD and D32 to D41 SPL.
These functions are described in detail below.
First, the various modes are shown below. These modes are switched using control data D13 SMD.
D13
Description of operation
0
Electronic shutter stopped mode
1
Electronic shutter mode
The electronic shutter data is expressed as shown in the table below using D20 to D31 SHD as an example.
However, MSB (D31) is a reserve bit for the future specification, and it is handled as a dummy on this IC.
MSB
D31
LSB
D30 D29 D28 D27
X
0
↓
1
0
1
1
D26 D25 D24 D23
1
↓
C
0
0
0
D22 D21 D20
0
↓
3
1
1
SHD is expressed as 1C3h .
[Electronic shutter stopped mode]
During this mode, all shutter data items are invalid.
SUB is not output in this mode, so the shutter speed is the accumulation time for one field.
[Electronic shutter mode]
During this mode, the shutter data items have the following meanings.
Symbol
Data
Description
SVD
D10 to D19
Number of vertical periods specification (000h ≤ SVD ≤ 3FFh)
SHD
D20 to D31
Number of horizontal periods specification (000h ≤ SHD ≤ 7FFh)
SPL
D32 to D41
Vertical period specification for high-speed shutter operation (000h ≤ SPL ≤ 3FFh)
Note) The bit data definition area is assured in terms of the CXD3412GA functions, and does not assure the
CCD characteristics.
The period during which SVD and SHD are specified together is the shutter speed. An image of the exposure
time calculation formula is shown below. In actual operation, the precise exposure time is calculated from the
operating frequency, VD and HD periods, decoding value during the horizontal period, and other factors.
(Exposure time) = SVD + {(number of HD per 1V) – (SHD + 1)}
Concretely, when specifying high-speed shutter, SVD is set to "000h". (See the figure.) During low-speed
shutter, or in other words when SVD is set to "001h" or higher, the serial interface data is not loaded until this
period is finished.
The vertical period indicated here corresponds to one field in each drive mode. In addition, the number of
horizontal periods applied to SHD can be considered as (number of SUB pulses – 1).
– 25 –
CXD3412GA
VD
SHD
SVD
V1A
SUB
WEN
EXP
SMD
1
1
SVD
002h
000h
SHD
10Fh
050h
Exposure time
Further, SPL can be used during this mode to specify the SUB output at the desired vertical period during the
low-speed shutter period.
In the case below, SUB is output based on SHD at the SPL vertical period out of (SVD + 1) vertical periods.
SPL
000
001
VD
002
SVD
SHD
V1A
SUB
WEN
EXP
1
SMD
1
SPL
001h
000h
SVD
002h
000h
SHD
10Fh
0A3h
Exposure time
Incidentally, SPL is counted as "000h", "001h", "002h" and so on in conformance with SVD. At this time,
performing SPL > SVD setting applies to the state of SPL = SVD correspondingly.
Using this function it is possible to achieve smooth exposure time transitions when changing from low-speed
shutter to high-speed shutter or vice-versa.
– 26 –
CXD3412GA
[HTSG control mode]
This mode controls the V1A/B and V3A/B ternary level outputs (readout pulse block) using D14 HTSG.
When control starts, V pulse modulation during readout period is not generated and the normal V transfer is
performed.
D14
Description of operation
0
Readout pulse (SG) normal operation
1
HTSG control mode
VD
V1A
SUB
VCK
WEN
EXP
HTSG
0
1
0
SMD
1
0
1
Exposure time
[EXP pulse]
The ID/EXP (Pin 9) output can be switched between the ID pulse or the EXP pulse using D33 EXP. The
default is the "ID" pulse. See the Timing Charts for the ID pulse. The EXP pulse indicates the exposure time
when it is high. In the draft mode, the transition point is the last SUB pulse falling edge, and midpoint value
(1443ck) of each V1A/B and V3A/B ternary output falling edge. When there is no SUB pulse, the later ternary
output falling edge (1538ck) is used. In the frame mode, the transition point is the last SUB pulse falling edge,
and each V1A/B and V3A/B ternary output falling edge (1348ck). When there is no SUB pulse, the V pulse
modulation falling edge just after ternary output (1386ck) is used. In addition, switching from ID to EXP is
performed at the timing (ID transition point of the horizontal period where V1A/B and V3A/B ternary output)
and reset to low.
See the EXP pulse indicated in the explanatory diagrams under Electronic Shutter for an image of operation.
– 27 –
Chart-1
Vertical Direction Timing Chart
MODE
Applicable CCD image sensor
Frame mode
• ICX412
A Field
B Field
VD
877
886 1
96
877
101
886 1
95
101
HD
SUB
C
High-speed sweep block
A
C
High-speed sweep block
B
V1A
V1B
V2
V3A
1549
1547
1545
1 3 5 7 1 3 5 7 9 11
1543
1550
1548
1546
CCD OUT
1544
V4
1542
– 28 –
V3B
2 4 6 8 2 4 6 8 10
PBLK
CLPOB
Wide CLPOB
CLPDM
ID/EXP
WEN
CXD3412GA
∗ The number of SUB pulses is determined by the serial interface data. This chart shows the case where SUB pulses are output in each horizontal period.
∗ ID/EXP of this chart shows ID. ID is low for lines where CCD OUT contains the R component, and high for lines where CCD OUT contains the B component.
∗ 1560 stages are fixed for high-speed sweep block.
∗ VD of this chart is NTSC equivalent pattern (885H + 810ck units). For PAL equivalent pattern, it is 884H + 1104ck units.
Chart-2
Vertical Direction Timing Chart
MODE
Applicable CCD image sensor
Draft mode
• ICX412
VD
260
287 1 2
287 1 2
260
HD
SUB
D
D
V1A
V1B
V2
V3A
1549
1537 1539
1544 1546
1532 1534
6 3 10 15 22 27 30
4 1 8 13 20 25 28
1525 1527
1549
1537 1539
1544 1546
CCD OUT
1532 1534
V4
1525 1527
– 29 –
V3B
6 3 10 15 22 27 30
4 1 8 13 20 25 28
PBLK
CLPOB
Wide CLPOB
CLPDM
ID/EXP
WEN
CXD3412GA
∗ The number of SUB pulses is determined by the serial interface data. This chart shows the case where SUB pulses are output in each horizontal period.
∗ ID/EXP of this chart shows ID. ID is low for lines where CCD OUT contains the R component, and high for lines where CCD OUT contains the B component.
∗ VD of this chart is NTSC equivalent pattern (285H + 1455ck + 1455ck units). For PAL equivalent pattern, it is 342H + 2592ck units.
Chart-3
Vertical Direction Timing Chart
MODE
Applicable CCD image sensor
AF1 mode
• ICX412
VD
131
144
2
131
14
144
2
14
HD
SUB
E
High-speed
sweep block
D
E
E
Frame shift block
High-speed
sweep block
D
E
Frame shift block
V1A
V1B
V2
V3A
440 442
433 435
428 430
6
4
421 423
1117 1119
1112 1114
440 442
433 435
428 430
6
4
421 423
CCD OUT
1117 1119
V4
1112 1114
– 30 –
V3B
PBLK
CLPOB
Wide CLPOB
CLPDM
ID/EXP
WEN
High-speed sweep block starts from 159H.
CXD3412GA
∗ The number of SUB pulses is determined by the serial interface data. This chart shows the case where SUB pulses are output in each horizontal period.
∗ ID/EXP of this chart shows ID. ID is low for lines where CCD OUT contains the R component, and high for lines where CCD OUT contains the B component.
∗ 75 stages are fixed for high-speed sweep block; 68 stages are fixed for frame shift block.
∗ VD of this chart is NTSC equivalent pattern (142H + 1384ck + 1383ck units). For PAL equivalent pattern, it is 171H + 1296ck units.
Chart-4
Vertical Direction Timing Chart
MODE
Applicable CCD image sensor
AF2 mode
• ICX412
VD
54
72
2
54
21
72
2
21
HD
SUB
E
High-speed
sweep block
D
E
E
Frame shift block
High-speed
sweep block
D
E
Frame shift block
V1A
V1B
V2
V3A
692 694
685 687
680 682
6
4
673 675
865 867
860 862
692 694
685 687
680 682
867
6
4
673 675
862
CCD OUT
865
V4
860
– 31 –
V3B
PBLK
CLPOB
Wide CLPOB
CLPDM
ID/EXP
WEN
High-speed sweep block starts from 68H. However, in this case, NTSC equivalent pattern frame rate is 0.5ck longer than 1/120s.
CXD3412GA
∗ The number of SUB pulses is determined by the serial interface data. This chart shows the case where SUB pulses are output in each horizontal period.
∗ ID/EXP of this chart shows ID. ID is low for lines where CCD OUT contains the R component, and high for lines where CCD OUT contains the B component.
∗ 116 stages are fixed for high-speed sweep block; 110 stages are fixed for frame shift block.
∗ VD of this chart is NTSC equivalent pattern (71H + 1384ck units). For PAL equivalent pattern, it is 85H + 1960ck units.
Chart-5
Horizontal Direction Timing Chart
(2544)
0
50
100
150
MODE
Applicable CCD image sensor
Frame mode
• ICX412
200
250
300
350
400
450
500
550
HD
MCKO
4
52
428
456/460/464
H1
H2
162
276
V1A/B
238
352
V2
124
314
V3A/B
200
390
V4
52
120
SUB
– 32 –
52
454
PBLK
16
42
CLPOB (1)
8
34
CLPOB (2)
24
50
CLPOB (3)
8
50
CLPOB (4)
50
458
CLPOB (wide)
430
454
CLPDM
124
ID/EXP
124
WEN
CXD3412GA
∗ The HD of this chart indicates the actual CXD3412GA load timing.
∗ The numbers at the output pulse transition points indicate the count at the MCKO rise from the fall of HD.
∗ The HD fall period should be between approximately 2.3 to 19.0µs (when the drive frequency is 22.5MHz).
This chart shows a period of 124ck (5.5µs). Internal SSG is at this timing.
∗ SUB is output at the timing shown above when output is controlled by the serial interface data.
∗ ID/EXP of this chart shows ID. ID/EXP and WEN are output at the timing shown above at the position shown in Chart-1.
∗ CLPOB (wide) is output at the timing shown above at the position shown in Chart-1.
Chart-6
Horizontal Direction Timing Chart
(2624)
0
50
100
150
MODE
Applicable CCD image sensor
Draft mode, AF1 mode, AF2 mode
• ICX412
200
250
300
350
400
450
500
550
HD
MCKO
4
52
508
536/540/544
H1
H2
140
188
268
316
396
444
V1A/B
172
220
300
348
428
476
V2
124
204
252
332
380
460
V3A/B
156
236
284
364
412
492
V4
52
120
SUB
– 33 –
52
534
PBLK
16
42
CLPOB (1)
8
34
CLPOB (2)
24
50
CLPOB (3)
8
50
CLPOB (4)
50
538
CLPOB (wide)
510
534
CLPDM
124
ID/EXP
124
WEN
CXD3412GA
∗ The HD of this chart indicates the actual CXD3412GA load timing.
∗ The numbers at the output pulse transition points indicate the count at the MCKO rise from the fall of HD.
∗ The HD fall period should be between approximately 2.3 to 19.0µs (when the drive frequency is 22.5MHz).
This chart shows a period of 124ck (5.5µs). Internal SSG is at this timing.
∗ SUB is output at the timing shown above when output is controlled by the serial interface data.
∗ ID/EXP of this chart shows ID. ID/EXP and WEN are output at the timing shown above at the position shown in Chart-2, 3 and 4.
∗ CLPOB (wide) is output at the timing shown above at the position shown in Chart-2, 3 and 4.
Chart-7
Horizontal Direction Timing Chart
(High-speed sweep: C)
(2544)
0
50
100
150
200
MODE
Applicable CCD image sensor
Frame mode
• ICX412
250
300
350
400
450
500
550
HD
MCKO
4
52
428
456/460/464
H1
H2
52
128
204
280
356
432
508
V1A/B
90
166
242
318
394
470
546
V2
52
128
204
280
356
432
508
V3A/B
– 34 –
90
166
242
318
394
470
546
V4
#1
52
#2
#3
#4
120
SUB
PBLK
CLPOB
CLPDM
ID/EXP
WEN
CXD3412GA
∗ The HD of this chart indicates the actual CXD3412GA load timing.
∗ The numbers at the output pulse transition points indicate the count at the MCKO rise from the fall of HD.
∗ The HD fall period should be between approximately 2.3 to 19.0µs (when the drive frequency is 22.5MHz).
This chart shows a period of 124ck (5.5µs). Internal SSG is at this timing.
∗ SUB is output at the timing shown above when output is controlled by the serial interface data.
∗ ID/EXP of this chart shows ID.
∗ High-speed sweep of V1A/B, V2, V3A/B and V4 is performed up to 93H 580ck (#1560).
Chart-8
Horizontal Direction Timing Chart
(Frame shift, High-speed sweep: E)
(2624)
0
50
100
150
200
MODE
Applicable CCD image sensor
AF1 mode, AF2 mode
• ICX412
250
300
350
400
450
500
550
HD
MCKO
4
52
508
536/540/544
H1
H2
68
116
196
244
324
372
452
500
V1A/B
100
148
228
276
356
404
484
532
V2
52
132
180
260
308
388
436
516
V3A/B
84
164
242
292
340
420
468
548
– 35 –
V4
#1
52
#2
120
SUB
52
PBLK
16
42
CLPOB
CLPDM
ID/EXP
124
WEN
CXD3412GA
∗ The HD of this chart indicates the actual CXD3412GA load timing.
∗ The numbers at the output pulse transition points indicate the count at the MCKO rise from the fall of HD.
∗ The HD fall period should be between approximately 2.3 to 19.0µs (when the drive frequency is 22.5MHz).
This chart shows a period of 124ck (5.5µs). Internal SSG is at this timing.
∗ SUB is output at the timing shown above when output is controlled by the serial interface data.
∗ ID/EXP of this chart shows ID. PBLK, CLPOB, ID/EXP and WEN are output at the timing shown above at the position shown in Chart-3 and 4.
∗ Frame shift of V1A/B, V2, V3A/B and V4 is performed up to 11H 2548ck (#68) in AF1 mode and 18H 308ck (#110) in AF2 mode.
In addition, high-speed sweep is performed up to 141H 2612ck (#75) in AF1 mode and 70H 2612ck (#116) in AF2 mode.
390
352
314
276
238
200
162
(2544)
0
124
(2544)
0
1386
• ICX412
1348
Frame mode
1310
Applicable CCD image sensor
1272
MODE
1234
Horizontal Direction Timing Chart
1196
Chart-9
HD
[A Field]
[A]
V1A
V1B
V2
V3A
V3B
– 36 –
V4
[B Field]
[B]
V1A
V1B
V2
V3A
V3B
V4
CXD3412GA
∗ The HD of this chart indicates the actual CXD3412GA load timing.
∗ The numbers at the output pulse transition points indicate the count at the MCKO rise from the fall of HD.
∗ The HD fall period should be between approximately 2.3 to 19.0µs (when the drive frequency is 22.5MHz).
This chart shows a period of 124ck (5.5µs). Internal SSG is at this timing.
(2544)
0
124
140
156
172
188
204
220
236
252
268
284
300
316
332
348
364
380
396
412
428
444
460
476
492
1576
1592
1608
1624
1640
1656
1672
1688
1538
1500
1462
• ICX412
1424
Draft mode, AF1 mode, AF2 mode
1386
Applicable CCD image sensor
1348
MODE
1310
1272
1234
(2624)
0
1196
1158
Chart-10 Horizontal Direction Timing Chart
HD
[D]
V1A
V1B
V2
V3A
– 37 –
V3B
V4
∗ The HD of this chart indicates the actual CXD3412GA load timing.
∗ The numbers at the output pulse transition points indicate the count at the MCKO rise from the fall of HD.
∗ The HD fall period should be between approximately 2.3 to 19.0µs (when the drive frequency is 22.5MHz).
This chart shows a period of 124ck (5.5µs). Internal SSG is at this timing.
CXD3412GA
Chart-11 High-Speed Phase Timing Chart
MODE
Applicable CCD image sensor
• ICX412
HD
HD'
CKI
CKO
ADCLK
1
52
428/508
MCKO
H1
– 38 –
H2
RG
XSHP
XSHD
XRS
∗ HD' indicates the HD which is the actual CXD3412GA load timing.
∗ The phase relationship of each pulse shows the logical position relationship. For the actual output waveform, a delay is added to each pulse.
∗ The logical phase of ADCLK can be specified by the serial interface data.
CXD3412GA
Chart-12 Vertical Direction Sequence Chart
MODE
Applicable CCD image sensor
Draft → Frame → Draft
• ICX412
VD
V1A
V1B
V2
V3A
V3B
– 39 –
V4
SUB
Mechanical
shutter
Close
Exposure
time
A
CCD OUT
B
C
D
A
B
C
Open
E
F
E
E
F
MODE
0
0
0
0
0
3
3
0
0
SMD
1
1
1
1
1
0
0
1
1
SHD
050h
050h
050h
050h
050h
000h
000h
050h
050h
CXD3412GA
∗ This chart is a drive timing chart example of electronic shutter normal operation.
∗ Data exposed at D includes a blooming component. For details, see the CCD image sensor data sheet.
∗ The CXD3412GA does not generate the pulse to control mechanical shutter operation.
∗ The switching timing of drive mode and electronic shutter data is not the same.
CXD3412GA
CCD Signal Processor Block Serial Interface Control
The CXD3412GA's CCD signal processor block basically loads the CCD signal processor block serial interface
data sent in the following format at the rising edge of SEN2, and the setting values are then reflected to the
operation 6 ADCLKI clocks after that.
CCD signal processor block serial interface control requires clock input to ADCLKI in order to load and reflect
the serial interface data to operation, so this should normally be performed when the timing generator block is
in the normal operation mode.
00
SSI2
01
02
03
04
05
06
07
08
09
10
11
12
13
14
15
SCK2
SEN2
There are four categories of CCD signal processor block serial interface data: standby control data, PGA gain
setting data, OB clamp level setting data, and input pulse polarity setting data.
Note that when data from multiple categories is loaded consecutively, the data for the category loaded last is
valid and data from other categories is lost. When transferring data from multiple categories, raise SEN2 for
each category and wait until the setting value 6 ADCKLI clocks after that has been reflected to operation, then
transmit the next category.
The detail of each data are described below.
Standby Control Data
Data
Symbol
Function
D00
TEST
Test code
D01
to
D03
CTG
Category switching
D04
to
D14
FIXED
D15
STB
Data = 0
Data = 1
Set to 0.
D01 to D03 CTG
—
Set to All 0.
Standby control
Normal operation mode
Standby mode
Data = 0
Data = 1
PGA Gain Setting Data
Data
Symbol
Function
D00
TEST
Test code
D01
to
D03
CTG
Category switching
D04,
FIXED
D05
D06
to
D15
GAIN
Set to 0.
D01 to D03 CTG
—
Set to All 0.
PGA gain setting data
See D06 to D15 GAIN.
– 40 –
CXD3412GA
OB Clamp Level Setting Data
Data
Symbol
Function
D00
TEST
Test code
D01
to
D03
CTG
Category switching
D04
to
D11
FIXED
D12
to
D15
OBLVL
Data = 0
Data = 1
Set to 0.
D01 to D03 CTG
—
Set to All 0.
OB clamp level setting data
See D12 to D15 OBLVL.
Input Pulse Polarity Setting Data
Data
Symbol
Function
D00
TEST
Test code
D01
to
D03
CTG
Category switching
D04
to
D12
FIXED
D13
to
D15
POL
Data = 0
Data = 1
Set to 0.
D01 to D03 CTG
—
Set to All 0.
Input pulse polarity setting data
– 41 –
Set to All 0.
CXD3412GA
Detailed Description of Each Data
Shared data: D01 to D03 CTG [Category]
Of the data provided to the CXD3412GA by the CCD signal processor block serial interface, the CXD3412GA
loads D04 and subsequent data to each data register as shown in the table below according to the
combination of D01 to D03 .
Description of operation
D01
D02
D03
0
0
0
Loading to standby control data register
0
0
1
Loading to PGA gain setting data register
0
1
0
Loading to OB clamp level setting data register
0
1
1
Loading to input pulse polarity setting data register
1
X
X
Access prohibited
Standby control data: D15 STB [Standby]
The operating mode of the CCD signal processor block is switched as follows. When the CCD signal processor
block is in standby mode, only the serial interface is valid.
D00
Description of operation
0
Normal operating mode
1
Standby mode
PGA gain setting data: D06 to D15 GAIN [PGA gain]
The CXD3412GA can set the programmable gain amplifier (PGA) gain from –6dB to +42dB in 1024 steps by
using PGA gain setting data D06 to D15 GAIN.
The PGA gain setting data is expressed as shown in the table below using D06 to D15 GAIN.
MSB
LSB
D06 D07 D08 D09
0
↓
1
1
1
1
D10 D11 D12 D13
↓
C
0
0
0
0
↓
3
D14
D15
1
1
GAIN is expressed as 1C3h .
For example, when GAIN is set to "000h", "080h", "220h", "348h" and "3FFh", the respective PGA gain setting
values are –6dB, 0dB, +20dB, +34dB and +42dB.
– 42 –
CXD3412GA
OB clamp level setting data: D12 to D15 OBLVL [OB clamp output]
The CXD3412GA can set the OPB clamp output value from 0 to 60LSB in 4LSB steps by using CCD signal
processor block control data D12 to D15 OBLVL.
The OPB clamp output setting data is expressed as shown in the table below using D12 to D15 OBLVL.
MSB
LSB
D12 D13 D14
D15
0
1
↓
6
1
0
OBLVL is expressed as 6h .
For example, when OBLVL is set to "0h", "1h", "8h" and "Fh", the respective OPB clamp output setting values
are 0LSB, 4LSB, 32LSB and 60LSB.
– 43 –
F9 F8 F7 G3 G2
CCD
ICX412
CCDOUT
CCDIN
1µF
1µF
390pF
390pF
G9 G8 G7 H3 H2 H1
G1
B7
C9 0.1µF
C8 0.1µF
C7 0.1µF
ADCLKI
ADCLK
CLPOB
CLPDM
PBLK
XSHD
XSHP
CLPOBI
CLPDMI
PBLKI
XSHDI
XSHPI
Application Circuit Block Diagram
A7
C6
C9
A2
C1
C2
C3
C4
A1
D7
B3
D8
B2
B1
C7
C3
C8
C2
240pF
C1
D3
D2
N2
M4
N9
L5
M9
N6
NC
D0 (LSB)
D1
D2
D3
D4
D5
D6
D7
D8
D9 (MSB)
CKO
VD
HD
ID/EXP
WEN
M8
RST
N7
N8
SNCSL
L8
SSGSL
SCK2
SSI2
L2 N1 M1 A4 B4 A3
SEN2
M3 M7 A5 C4 B5
SCK1
L1
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for
any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
Controller
CXD3412GA
This block diagram illustrates connections with each circuit
block, and is not an actual circuit diagram. See the CCD
image sensor data sheet for an example of specific circuit
connections with the CCD image sensor.
K1
OSCO
J1
Signal
Processor
Block
MCKO
N4
SEN1
SUB
M2
SSI1
V4
L5
N5
TEST5
V3B
K2
TEST4
V3A
K8
TEST3
V2
J2
TEST2
V1B
E1
J9
TEST1
V1A
TG/CDS/PGA/ADC
CXD3412GA
J8
OSCI
H2
RG
D1
CKI
– 44 –
H1
NC
CXD3412GA
Notes on Operation
1. Be sure to start up the timing generator block VL and VH pin power supplies at the timing shown in the
figure below in order to prevent the SUB pin of the CCD image sensor from going to negative potential. In
addition, start up the timing generator block VDD1, VDD2, VDD3, VDD4 and VDD5 pin and CCD signal processor
block DVDD1, DVDD2, AVDD1, AVDD2, AVDD3, AVDD4 and AVDD5 pin power supplies at the same time either
before or at the same time as the VH pin power supply is started up.
15.0V
t1
20%
0V
20%
t2
t2 ≥ t1
–7.5V
2. Reset the timing generator block and CCD signal processor block during power-on. The timing generator
block is reset by inputting the reset signal to the RST pin. The CCD signal processor block is reset by
initializing the serial data.
3. Separate the timing generator block VDD1, VDD2, VDD3, VDD4 and VDD5 pins from the CCD signal processor
block DVDD1, DVDD2, AVDD1, AVDD2, AVDD3, AVDD4, and AVDD5 pins.
Also, the ADC output driver stage is connected to the dedicated power supply pin DVDD1. Separating this pin
from other power supplies is recommended to avoid affecting the internal analog circuits.
4. The difference in potential between the timing generator block VDD4 pin supply voltage 3 VDDc and the CCD
signal processor block DVDD1, DVDD2, AVDD1, AVDD2, AVDD3, AVDD4 and AVDD5 pin supply voltages 1 VDDe, 2
VDDf and 3 VDDg should be 0.1V or less.
5. The timing generator block and CCD signal processor block ground pins should use a shared ground which
is connected outside the IC. When the set ground is divided into digital and analog blocks, connect the
timing generator block ground pins to the digital ground and the CCD signal processor block ground pins to
the analog ground. The difference in potential between the timing generator block VSS1, VSS2, VSS3, VSS4,
VSS5, VSS6 and VM and the CCD signal processor block DVSS1, DVSS2, DVSS3, AVSS1, AVSS2, AVSS3, AVSS4,
AVSS5 and AVSS6 should be 0.1V or less.
6. Do not perform serial communication with the CCD signal processor block during the effective image
period, as this may cause the picture quality to deteriorate. In addition, using SCK2, SSI2 and SEN2, which
are used by the CCD signal processor block, use of the dedicated ports is recommended. When using
these pins as shared ports with the timing generator block or other ICs, be sure to thoroughly confirm the
effects on picture quality before use.
– 45 –
CXD3412GA
Package Outline
Unit: mm
0.2
96PIN LFLGA
S A
8.0
PIN 1 INDEX
1.3 MAX
0.2
0.2
S
S B
12.0
0.10MAX
0.10 S
X
x4
S
0.15
0.5
A
N
M
L
K
J
H
G
F
E
D
φ0.08 M S A B
B
C
B
0.9
96 -φ0.45 ± 0.05
0.8
0.8
0.9
(0.3)
DETAIL X
(0.3)
3 – φ0.50
0.5
(0.3)
1 2 3 4 5 6 7 8 9
0.8
0.5
1.2
(0.3)
0.5
A
PACKAGE STRUCTURE
PACKAGE MATERIAL
ORGANIC SUBSTRATE
SONY CODE
LFLGA-96P-02
TERMINAL TREATMENT NICKEL & GOLD PLATING
EIAJ CODE
P-LFLGA96-12X8-0.8
TERMINAL MATERIAL
JEDEC CODE
PACKAGE MASS
– 46 –
COPPER
0.3g
Sony Corporation