SONY ICX412

CXD3606R
Timing Generator for Frame Readout CCD Image Sensor
Description
The CXD3606R is a timing generator IC which
generates the timing pulses for performing frame
readout using the ICX412 CCD image sensor.
Features
• Base oscillation frequency 45MHz
• Electronic shutter function
• Supports draft (sextuple speed) / AF (auto focus)
drive
• Horizontal driver for CCD image sensor
• Vertical driver for CCD image sensor
Absolute Maximum Ratings
• Supply voltage VDD
VSS – 0.3 to +7.0
V
VL
–10.0 to VSS
V
VH
VL – 0.3 to +26.0
V
• Input voltage
VI
VSS – 0.3 to VDD + 0.3 V
• Output voltage VO1 VSS – 0.3 to VDD + 0.3 V
VO2
VL – 0.3 to VSS + 0.3
V
VO3
VL – 0.3 to VH + 0.3
V
• Operating temperature
Topr
–20 to +75
°C
• Storage temperature
Tstg
–55 to +150
°C
Applications
Digital still cameras
Structure
Silicon gate CMOS IC
Applicable CCD Image Sensors
ICX412 (Type 1/1.8, 3240K pixels)
VSS6
HD
VD
SEN
SCK
SSI
MCKO
VDD5
OSCI
OSCO
CKI
CKO
Pin Configuration
36
35
34
33
32
31
30
29
28
27
26
25
TEST1
37
24 VSS5
VM
38
23 ADCLK
V2
39
22 OBCLP
V4
40
21 VSS4
V1A
41
20 CLPDM
VH
42
19 PBLK
V1B
43
18 XRS
V3A
44
17 XSHD
VL
45
16 XSHP
6
7
8
VDD2
9
10
11
12
H1
5
VSS3
4
RG
3
VSS2
2
VDD1
13 H2
WEN
48
SSGSL
TEST2
ID/EXP
14 VDD3
SNCSL
15 VDD4
47
RST
46
VSS1
V3B
SUB
1
48 pin LQFP (Plastic)
Recommended Operating Conditions
• Supply voltage VDDb
3.0 to 5.25
VDDa, VDDc, VDDd
3.0 to 3.6
VM
0.0
VH
14.5 to 15.5
VL
–7.0 to –8.0
• Operating temperature
Topr
–20 to +75
V
V
V
V
V
°C
∗ Groups of pins enclosed in the figure indicate
sections for which power supply separation is
possible.
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E01216-PS
CXD3606R
OSCI
OSCO
ADCLK
VDD4
10
15 16 17 18 21 23
VSS4
VSS2
9
XRS
RG
XSHD
VDD2
XSHP
VSS3
8
H2
14 12 13 11
H1
VDD3
Block Diagram
28
27
19 PBLK
CKI
20 CLPDM
26
22 OBCLP
Pulse Generator
24 VSS5
CKO 25
MCKO 30
SNCSL
3
1/2
Selector
Latch
4
ID/EXP
5
WEN
41 V1A
43 V1B
SSI 31
39 V2
SCK 32
Register
44 V3A
SEN 33
6
RST
2
46 V3B
V Driver
Selector
SSGSL
SSG
40 V4
47 SUB
42 VH
TEST1 37
38 VM
TEST2 48
1
36
–2–
VDD5
VSS1
VSS6
35
34
VD
29
HD
7
VDD1
45 VL
CXD3606R
Pin Description
Pin
No.
Symbol
I/O
Description
1
VSS1
—
GND
2
RST
I
Internal system reset input. High: Normal operation, Low: Reset control
Normally apply reset during power-on.
Schmitt trigger input/protective diode on power supply side
3
SNCSL
I
Control input used to switch sync system. High: CKI sync, Low: MCKO sync
With pull-down resistor
4
ID/EXP
O
Vertical direction line identification pulse output/exposure time identification pulse output.
Switching possible using the serial interface data. (Default: ID)
5
WEN
O
Memory write timing pulse output
6
SSGSL
I
Internal SSG enable. High: Internal SSG valid, Low: External sync valid.
With pull-down resistor
7
VDD1
—
3.3V power supply. (Power supply for common logic block)
8
VDD2
—
3.3V power supply. (Power supply for RG)
9
RG
O
CCD reset gate pulse output
10
VSS2
—
GND
11
VSS3
—
GND
12
H1
O
CCD horizontal register clock output
13
H2
O
CCD horizontal register clock output
14
VDD3
—
3.3 to 5.0V power supply. (Power supply for H1/H2)
15
VDD4
—
3.3V power supply. (Power supply for CDS)
16
XSHP
O
CCD precharge level sample-and-hold pulse output
17
XSHD
O
CCD data level sample-and-hold pulse output
18
XRS
O
Sample-and-hold pulse output for analog/digital conversion phase alignment
19
PBLK
O
Pulse output for horizontal and vertical blanking period pulse cleaning
20
CLPDM
O
CCD dummy signal clamp pulse output
21
VSS4
—
GND
22
OBCLP
O
CCD optical black signal clamp pulse output
The horizontal/vertical OB pattern can be changed using the serial interface data.
23
ADCLK
O
Clock output for analog/digital conversion IC
Logical phase adjustment possible using the serial interface data
24
VSS5
—
GND
25
CKO
O
Inverter output
26
CKI
I
Inverter input
27
OSCO
O
Inverter output for oscillation. When not used, leave open or connect a capacitor.
28
OSCI
I
Inverter input for oscillation. When not used, fix low.
29
VDD5
—
3.3V power supply. (Power supply for common logic block)
–3–
CXD3606R
Pin
No.
Symbol
I/O
Description
30
MCKO
O
System clock output for signal processing IC
31
SSI
I
Serial interface data input for internal mode settings.
Schmitt trigger input/protective diode on power supply side
32
SCK
I
Serial interface clock input for internal mode settings.
Schmitt trigger input/protective diode on power supply side
33
SEN
I
Serial interface strobe input for internal mode settings.
Schmitt trigger input/protective diode on power supply side
34
VD
I/O
Vertical sync signal input/output
35
HD
I/O
Horizontal sync signal input/output
36
VSS6
—
GND
37
TEST1
38
VM
—
GND (GND for vertical driver)
39
V2
O
CCD vertical register clock output
40
V4
O
CCD vertical register clock output
41
V1A
O
CCD vertical register clock output
42
VH
—
15.0V power supply. (Power supply for vertical driver)
43
V1B
O
CCD vertical register clock output
44
V3A
O
CCD vertical register clock output
45
VL
—
–7.5V power supply. (Power supply for vertical driver)
46
V3B
O
CCD vertical register clock output
47
SUB
O
CCD electronic shutter pulse output
48
TEST2
I
IC test pin 2; normally fixed GND.
I
IC test pin 1; normally fixed to GND.
–4–
With pull-down resistor
With pull-down registor
CXD3606R
Electrical Characteristics
DC Characteristics
Item
(Within the recommended operating conditions)
Pins
Symbol
Conditions
Min.
Typ.
Max.
Unit
Supply voltage 1
VDD2
VDDa
3.0
3.3
3.6
V
Supply voltage 2
VDD3
VDDb
3.0
3.3
5.25
V
Supply voltage 3
VDD4
VDDc
3.0
3.3
3.6
V
Supply voltage 4
VDD1, VDD5
VDDd
3.0
3.3
3.6
V
Input voltage 1∗1
RST, SSI, SCK,
SEN
Vt+
Input voltage 2∗2
TEST1, TEST2,
SNCSL, SSGSL
VIH1
0.2VDDd
Vt–
0.2VDDd
VIL1
VD, HD
Feed current where IOH = –1.2 mA
VOL1
Pull-in current where IOL = 2.4mA
VOH2
Feed current where IOH = –22.0mA
VOL2
Pull-in current where IOL = 14.4mA
VOH3
Feed current where IOH = –3.3mA
VOL3
Pull-in current where IOL = 2.4mA
Output voltage 1
H1, H2
Output voltage 2
RG
Output voltage 3
XSHP, XSHD,
VOH4
XRS, PBLK,
OBCLP, CLPDM,
VOL4
ADCLK
Output voltage 4
CKO
Output voltage 5
MCKO
Output voltage 6
ID/EXP,
WEN
Output current 1
V1A, V1B,
V3A, V3B,
V2, V4
Output current 2
SUB
0.2VDDd
VOH1
Feed current where IOH = –3.3mA
VOH5
Feed current where IOH = –6.9mA
VOL5
Pull-in current where IOL = 4.8mA
VOH6
Feed current where IOH = –3.3mA
VOL6
Pull-in current where IOL = 2.4mA
VOH7
Feed current where IOH = –2.4mA
VOL7
Pull-in current where IOL = 4.8mA
IOL
V1A/B, V2, V3A/B, V4 = –8.25V
IOM1
V1A/B, V2, V3A/B, V4 = –0.25V
IOM2
V1A/B, V3A/B = 0.25V
IOH
V1A/B, V3A/B = 14.75V
IOSL
SUB = –8.25V
IOSH
SUB = 14.75V
V
V
VDDd – 0.8
0.4
V
V
VDDb – 0.8
0.4
V
V
VDDa – 0.8
0.4
V
V
VDDc – 0.8
Pull-in current where IOL = 2.4mA
V
V
0.8VDDd
VIL2
V
V
0.7VDDd
VIH2
Input/output
voltage
V
0.8VDDd
0.4
V
V
VDDd – 0.8
0.4
V
V
VDDd – 0.8
0.4
V
V
VDDd – 0.8
0.4
V
mA
10.0
–5.0
mA
mA
5.0
–7.2
mA
mA
5.4
–4.0
mA
∗1 These input pins are Schmitt trigger inputs, and have a protective diode on the power supply side in the IC.
Therefore, they do not support 5V input.
∗2 This input pin is with pull-down registor in the IC.
Note) The above table indicates the condition for 3.3V drive.
–5–
CXD3606R
Inverter I/O Characteristics for Oscillation
Item
Pins
Logical Vth
OSCI
Input voltage
OSCI
Output voltage
OSCO
Feedback
resistor
Oscillation
frequency
Symbol
(Within the recommended operating conditions)
Conditions
Min.
Typ.
LVth
Max.
VDDd/2
VIH
V
0.7VDDd
V
VIL
0.3VDDd
VOH
Feed current where IOH = –3.6mA VDDd – 0.8
VOL
Pull-in current where IOL = 2.4mA
OSCI, OSCO
RFB
VIN = VDDd or VSS
OSCI, OSCO
f
500k
Unit
V
V
2M
20
0.4
V
5M
Ω
50
MHz
Inverter Input Characteristics for Base Oscillation Clock Duty Adjustment
(Within the recommended operating conditions)
Item
Pins
Logical Vth
Symbol
Conditions
Min.
LVth
Input voltage
CKI
Input amplitude
Typ.
VDDd/2
VIH
V
0.3VDDd
fmax 50MHz sine wave
Unit
V
0.7VDDd
VIL
VIN
Max.
0.3
V
Vp-p
Note) Input voltage is the input voltage characteristics for direct input from an external source. Input amplitude
is the input amplitude characteristics in the case of input through a capacitor.
Switching Characteristics
Item
Rise time
Fall time
Output noise voltage
(VH = 15.0V, VM = GND, VL = –7.5V)
Symbol
Conditions
Min.
Typ.
Max.
Unit
TTLM
VL to VM
200
350
500
ns
TTMH
VM to VH
200
350
500
ns
TTLH
VL to VH
30
60
90
ns
TTML
VM to VL
200
350
500
ns
TTHM
VH to VM
200
350
500
ns
TTHL
VH to VL
30
60
90
ns
VCLH
1.0
V
VCLL
1.0
V
VCMH
1.0
V
VCML
1.0
V
Notes)
1) The MOS structure of this IC has a low tolerance for static electricity, so full care should be given for
measures to prevent electrostatic discharge.
2) For noise and latch-up countermeasures, be sure to connect a by-pass capacitor (0.1µF or more) between
each power supply pin (VH, VL) and GND.
3) To protect the CCD image sensor, clamp the SUB pin output at VH before input to the CCD image sensor.
–6–
CXD3606R
Switching Waveforms
TTMH
TTHM
VH
V1A (V1B, V3A, V3B)
TTLM
90%
90%
10%
10%
TTML
VM
90%
90%
10%
10%
TTML
TTLM
VL
VM
90%
90%
V2 (V4)
10%
10%
TTLH
TTHL
90%
VL
VH
90%
SUB
10%
10%
VL
Waveform Noise
VM
VCMH
VCML
VCLH
VCLL
VL
–7–
CXD3606R
Measurement Circuit
Serial interface data
CKI
VD
HD
C6
+3.3V
–7.5V
C6
+15.0V
36 35 34 33 32 31 30 29 28 27 26 25
R1
C2
C2
R1
R1
C1 C2
C1
C2
C2
R1
C2 C2
C2
C2
C1
C2
C1
C2
C2
C1
R1
C2
R2
C3
R1
24
38
23
39
22
40
21
41
20
42
19
CXD3606R
43
C2
C1
C2
37
18
44
17
45
16
46
15
47
14
48
13
1
2
3
4
5
6
7
8
9
10 11 12
C4
C1 3300pF
R1 30Ω
C2 560pF
R2 10Ω
C3 820pF
C4 8pF
–8–
C5 215pF
C6 10pF
C5
C6
C6
C6
C6
C6
C6
C6
C5
CXD3606R
AC Characteristics
AC characteristics between the serial interface clocks
0.8VDDd
SSI
0.2VDDd
0.8VDDd
0.2VDDd
ts1
SCK
SEN
th1
0.2VDDd
ts3
0.8VDDd
SEN
ts2
(Within the recommended operating conditions)
Symbol
ts1
th1
ts2
ts3
Definition
Min.
Typ.
Max.
Unit
SSI setup time, activated by the rising edge of SCK
20
ns
SSI hold time, activated by the rising edge of SCK
20
ns
SCK setup time, activated by the rising edge of SEN
20
ns
SEN setup time, activated by the rising edge of SCK
20
ns
Serial interface clock internal loading characteristics (1)
Example: During frame mode
VD
HD
V1A
Enlarged view
HD
0.2VDDd
V1A
ts1
SEN
th1
0.8VDDd
0.2VDDd
∗ Be sure to maintain a constantly high SEN logic level near the falling edge of the HD in the horizontal period
during which V1A/B and V3A/B values take the ternary value and during that horizontal period.
(Within the recommended operating conditions)
Symbol
ts1
th1
Definition
Min.
Typ.
Max.
Unit
SEN setup time, activated by the falling edge of HD
0
ns
SEN hold time, activated by the falling edge of HD
113
µs
–9–
CXD3606R
Serial interface clock internal loading characteristics (2)
Example: During frame mode
VD
HD
Enlarged view
VD
0.2VDDd
HD
ts1
th1
0.8VDDd
SEN
0.2VDDd
∗ Be sure to maintain a constantly high SEN logic level near the falling edge of VD.
(Within the recommended operating conditions)
Definition
Symbol
ts1
th1
Min.
Typ.
Max.
Unit
SEN setup time, activated by the falling edge of VD
0
ns
SEN hold time, activated by the falling edge of VD
200
ns
Serial interface clock output variation characteristics
Normally, the serial interface data is loaded to the CXD3606R at the timing shown in "Serial interface clock
internal loading characteristics (1)" above. However, one exception to this is when the data such as STB is
loaded to the CXD3606R and controlled at the rising edge of SEN. See "Description of Operation".
SEN
0.8VDDd
Output signal
tpdPULSE
(Within the recommended operating conditions)
Symbol
Definition
Min.
tpdPULSE Output signal delay, activated by the rising edge of SEN
– 10 –
15
Typ.
Max.
Unit
100
ns
CXD3606R
RST loading characteristics
RST
0.2VDDd
0.2VDDd
tw1
(Within the recommended operating conditions)
Symbol
tw1
Definition
Min.
RST pulse width
Typ.
Max.
Unit
ns
28
VD and HD phase characteristics
VD
0.2VDDd
0.2VDDd
ts1
th1
HD
0.2VDDd
(Within the recommended operating conditions)
Symbol
ts1
th1
Definition
Min.
Typ.
Max.
Unit
VD setup time, activated by the falling edge of HD
0
ns
VD hold time, activated by the falling edge of HD
0
ns
HD loading characteristics
HD
0.2VDDd
0.2VDDd
ts1
th1
0.8VDDd
MCKO
MCKO load capacitance = 10pF
(Within the recommended operating conditions)
Symbol
ts1
th1
Definition
Min.
Typ.
Max.
Unit
HD setup time, activated by the rising edge of MCKO
20
ns
HD hold time, activated by the rising edge of MCKO
0
ns
– 11 –
CXD3606R
Output variation characteristics
0.8VDDd
MCKO
WEN, ID/EXP
tpd1
WEN and ID/EXP load capacitance = 10pF
(Within the recommended operating conditions)
Symbol
tpd1
Definition
Min.
Time until the above outputs change after the rise of MCKO
25
– 12 –
Typ.
Max.
Unit
70
ns
CXD3606R
Description of Operation
Pulses output from the CXD3606R are controlled mainly by the RST pin and by the serial interface data. The
Pin Status Table is shown below, and the details of serial interface control are described on the following
pages.
Pin Status Table
Pin
No.
Symbol
CAM
SLP
STB
RST
—
1
VSS1
2
RST
ACT
ACT
ACT
3
SNCSL
ACT
ACT
4
ID/EXP
ACT
5
WEN
6
SSGSL
7
VDD1
8
VDD2
9
RG
10
VSS2
—
11
VSS3
—
12
H1
ACT
L
L
13
H2
ACT
L
L
14
VDD3
15
VDD4
16
XSHP
ACT
L
L
17
XSHD
ACT
L
18
XRS
ACT
19
PBLK
20
CLPDM
21
VSS4
22
OBCLP
ACT
L
L
23
ADCLK
ACT
L
L
24
VSS5
Pin
No.
Symbol
CAM
SLP
STB
RST
25
CKO
ACT
ACT
L
ACT
L
26
CKI
ACT
ACT
ACT
ACT
ACT
ACT
27
OSCO
ACT
ACT
ACT
ACT
L
L
L
28
OSCI
ACT
ACT
ACT
ACT
ACT
L
L
L
29
VDD5
ACT
ACT
ACT
ACT
30
MCKO
ACT
ACT
L
ACT
—
31
SSI
ACT
ACT
ACT
DIS
—
32
SCK
ACT
ACT
ACT
DIS
33
ACT
ACT
ACT
DIS
34
SEN
VD∗1
ACT
L
L
H
35
HD∗1
ACT
L
L
H
ACT
36
VSS6
—
ACT
37
TEST1
—
—
38
VM
—
—
39
V2
ACT
VM
VM
VM
ACT
40
V4
ACT
VM
VM
VL
L
ACT
41
V1A
ACT
VH
VH
VM
L
L
ACT
42
VH
ACT
L
L
H
43
V1B
ACT
VH
VH
VM
ACT
L
L
H
44
V3A
ACT
VH
VH
VL
45
VL
H
46
V3B
ACT
VH
VH
VL
ACT
47
SUB
ACT
VH
VH
VL
48
TEST2
ACT
L
L
ACT
—
—
—
—
—
—
∗1 It is for output. For input, all items are “ACT”.
Note) ACT means that the circuit is operating, and DIS means that loading is stopped. L indicates a low output
level, and H a high output level in the controlled status.
Also, VH, VM and VL indicate the voltage levels applied to VH (Pin 42), VM (Pin 38) and VL (Pin 45),
respectively, in the controlled status.
– 13 –
CXD3606R
Serial Interface Control
The CXD3606R basically loads and reflects the serial interface data sent in the following format in the readout
portion at the falling edge of HD. Here, readout portion specifies the horizontal period during which V1A/B and
V3A/B, etc. take the ternary value.
Note that some items reflect the serial interface data at the falling edge of VD or the rising edge of SEN.
SSI
00
01
02
03
04
05
06
07
41
42
43
44
45
46
47
SCK
SEN
These are two categories of serial interface data : the CXD3606R drive control data (hereafter “control data”)
and electronic shutter data (hereafter “shutter data”).
The details of each data are described below.
– 14 –
CXD3606R
Control Data
Data
Symbol
Data = 0
Function
Data = 1
RST
D00
to
D07
CHIP
Chip enable
10000001 → Enabled
Other values → Disabled
All
0
D08
D09
CTG
Category switching
See D08 to D09 CTG.
All
0
D10
to
D12
MODE
Drive mode switching
See D10 to D12 MODE.
All
0
D13
SMD
D14
HTSG
Electronic shutter mode switching∗1
HTSG control switching∗1
D15
PTSG
Internal SSG function switching
D16
to
D31
—
OFF
ON
0
OFF
ON
0
NTSC
PAL
0
—
—
—
All
0
OFF
ON
0
ID
EXP
0
D32
FGOB
Wide OBCLP generation switching∗2
D33
EXP
ID/EXP output switching
D34
D35
PTOB
OBCLP waveform pattern switching
See D34 to D35 PTOB.
D36
D37
LDAD
ADCLK logic phase adjustment
See D36 to D37 LDAD.
D38
D39
STB
Standby control
D40
to
D47
—
See D38 to D39 STB.
—
—
∗1 See D13 SMD.
∗2 See D32 FGOB.
– 15 –
—
All
0
1
0
All
0
All
0
CXD3606R
Shutter Data
Data
Function
Symbol
Data = 0
Data = 1
RST
D00
to
D07
CHIP
Chip enable
10000001 → Enabled
Other values → Disabled
All
0
D08
D09
CTG
Category switching
See D08 to D09 CTG.
All
0
D10
to
D19
SVD
Electronic shutter vertical period
specification
See D10 to D19 SVD.
All
0
D20
to
D31
SHD
Electronic shutter horizontal period
specification
See D20 to D31 SHD.
All
0
D32
to
D41
SPL
High-speed shutter position
specification
See D32 to D41 SPL.
All
0
D42
to
D47
—
—
—
– 16 –
—
All
0
CXD3606R
Detailed Description of Each Data
Shared data: D08 to D09 CTG [Category]
Of the data provided to the CXD3606R by the serial interface, the CXD3606R loads D10 and subsequent data
to each data register as shown in the table below according to the combination of D08 and D09 .
D09
D08
Description of operation
0
0
Loading to control data register
0
1
Loading to shutter data register
1
X
Test mode
Note that the CXD3606R can apply these categories consecutively within the same vertical period. However,
care should be taken as the data is overwritten if the same category is applied.
Control data: D10 to D12 MODE [Drive mode]
The CXD3606R drive mode can be switched as follows. However, the drive mode bits are located to the
CXD3606R and reflected at the falling edge of VD.
D12
D11
D10
Description of operation
0
0
0
Draft mode (sextuple speed: default)
0
0
1
Frame mode (A field readout)
0
1
0
Frame mode (B field readout)
0
1
1
Frame mode
1
0
X
AF1 mode
1
1
X
AF2 mode
Control data: D15 PTSG [Internal SSG output pattern]
The CXD3606R internal SSG output pattern can be switched as follows. However, the internal SSG output
pattern bits are loaded to the CXD3606R and reflected at the falling edge of VD.
D15
Description of Operation
0
NTSC equivalent pattern output
1
PAL equivalent pattern output
VD period in each pattern is defined as follows. However, note that the HD period also changes according to
the mode.
Frame mode
NTSC equivalent pattern
885H + 810ck
PAL equivalent pattern
884H + 1104ck
Draft mode
AF1 mode
285H + 1455ck × 2 142H + 1384ck + 1383ck
342H + 2592ck
See the Timing Charts for the actual operation.
– 17 –
171H + 1296ck
AF2 mode
71H + 1384ck
85H + 1960ck
CXD3606R
Control data: D32 FGOB [Wide OBCLP generation]
This controls wide OBCLP generation during the vertical OPB period. See the Timing Charts for the actual
operation. The default is "OFF".
D32
Description of operation
0
Wide OBCLP generation OFF
1
Wide OBCLP generation ON
Control data: D34 to D35 PTOB [OBCLP waveform pattern]
This indicates the OBCLP waveform pattern. The default is "Normal".
D35
D34
Waveform pattern
0
0
(Normal)
0
1
(Shifted rearward)
1
0
(Shifted forward)
1
1
(Wide)
Control data: D36 to D37 LDAD [ADCLK logic phase]
This indicates the ADCLK logic phase adjustment data. The default is "90°" relative to MCKO.
D37
D36
Degree of adjustment (°)
0
0
0
0
1
90
1
0
180
1
1
270
Control data : D38 to D39 STB [Standby]
The operating mode is switched as follows. However, the standby bits are loaded to the CXD3606R and control
is applied immediately at the rising edge of SEN.
D39
D38
Symbol
Operating mode
X
0
CAM
Normal operating mode
0
1
SLP
Sleep mode
1
1
STB
Standby mode
See the Pin Status Table for the pin status in each mode.
– 18 –
CXD3606R
Control data/shutter data: [Electronic shutter]
The CXD3606R realizes various electronic shutter functions by using control data D13 SMD and D14 HTSG
and shutter data D10 to D19 SVD, D20 to D31 SHD and D32 to D41 SPL.
These functions are described in detail below.
First, the various modes are shown below. These modes are switched using control data D13 SMD.
D13
Description of operation
0
Electronic shutter stopped mode
1
Electronic shutter mode
The electronic shutter data is expressed as shown in the table below using D20 to D31 SHD as an example.
However, MSB (D31) is a reserve bit for the future specification, and it is handled as a dummy on this IC.
MSB
LSB
D31
D30
X
0
↓
1
D29
D28
D27
D26
0
1
1
1
↓
C
D25
D24
D23
D22
0
0
0
0
↓
3
D21
D20
1
1
→ SHD is expressed as 1C3h .
[Electronic shutter stopped mode]
During this mode, all shutter data items are invalid.
SUB is not output in this mode, so the shutter speed is the accumulation time for one field.
[High-speed/low-speed shutter mode]
During this mode, the shutter data items have the following meanings.
Symbol
Data
Description
SVD
D10 to D19
Number of vertical periods specification (000h ≤ SVD ≤ 3FFh)
SHD
D20 to D31
Number of horizontal periods specification (000h ≤ SHD ≤ 7FFh)
SPL
D32 to D41
Vertical period specification for high-speed shutter operation (000h ≤ SPL ≤ 3FFh)
Note)
The bit data definition area is assured in terms of the CXD3606R functions, and does not assure the CCD
characteristics.
The period during which SVD and SHD are specified together is the shutter speed. An image of the exposure
time calculation formula is shown below. In actual operation, the precise exposure time is calculated from the
operating frequency, VD and HD periods, decoding value during the horizontal period, and other factors.
(Exposure time) = SVD + {(number of HD per 1V) – (SHD + 1)}
Concretely, when specifying high-speed shutter, SVD is set to "000h". (See the figure.) During low-speed
shutter, or in other words when SVD is set to "001h" or higher, the serial interface data is not loaded until this
period is finished.
The vertical period indicated here corresponds to one field in each drive mode. In addition, the number of
horizontal periods applied to SHD can be considered as (number of SUB pulses – 1).
– 19 –
CXD3606R
VD
SVD
SHD
V1A
SUB
WEN
EXP
SMD
1
1
SVD
002h
000h
SHD
10Fh
050h
Exposure time
Further, SPL can be used during this mode to specify the SUB output at the desired vertical period during the
low-speed shutter period.
In the case below, SUB is output based on SHD at the SPL vertical period out of (SVD + 1) vertical periods.
SPL
000
001
VD
002
SVD
SHD
V1A
SUB
WEN
EXP
SMD
1
SPL
001h
000h
SVD
002h
000h
SHD
10Fh
0A3h
1
Exposure time
Incidentally, SPL is counted as "000h", "001h", "002h" and so on in conformance with SVD. At this time, even if
SPL > SVD is set, operation conforms to the state when SPL = SVD.
Using this function it is possible to achieve smooth exposure time transitions when changing from low-speed
shutter to high-speed shutter or vice versa.
– 20 –
CXD3606R
[HTSG control mode]
This mode controls the V1A/B and V3A/B ternary level outputs (readout pulse block) using D14 HTSG. When
control is applied, V pulse modulation does not occur during the readout period, and only normal V transfer is
performed.
D14
Description of operation
0
Readout pulse (SG) normal operation
1
HTSG control mode
VD
V1A
SUB
Vck
WEN
EXP
HTSG
0
1
0
SMD
1
0
1
Exposure time
[EXP pulse]
The ID/EXP pin (Pin 4) output can be switched between the ID pulse or the EXP pulse using D33 EXP. The
default is the "ID" pulse. See the Timing Charts for the ID pulse. The EXP pulse indicates the exposure time
when it is high. In draft mode, the transition point is midpoint value (1443ck) of the last SUB pulse falling edge
and each V1A/B and V3A/B ternary output falling edge. When there is no SUB pulse, the later ternary output
falling edge (1538ck) is used. In frame mode, the transition point is the last SUB pulse falling edge, and each
V1A/B and V3A/B ternary level output falling edge (1348ck). When there is no SUB pulse, the V pulse
modulation falling edge (1386ck) immediately after the ternary output is used. In addition, switching from the ID
pulse to the EXP pulse is performed at the ID reset timing (the ID transition point during the horizontal period of
each V1A/B and V3A/B ternary level output), and the EXP pulse is reset low at this point. See the EXP pulse
indicated in the explanatory diagrams under [Electronic shutter] for an image of operation.
– 21 –
– 22 –
V4
V3B
V3A
V2
V1B
V1A
SUB
HD
VD
WEN
ID/EXP
CLPDM
Wide OBCLP
OBCLP
PBLK
1548
1546
1544
1542
877
C
High-speed sweep block
886 1
A
96
1 3 5 7 1 3 5 7 9 11
101
877
C High-speed sweep block
886 1
B
95
B Field
• ICX412
Frame mode
A Field
Applicable CCD image sensor
MODE
1549
1547
1545
1543
101
2 4 6 8 2 4 6 8 10
∗ The number of SUB pulses is determined by the serial interface data. This chart shows the case where SUB pulses are output in each horizontal period.
∗ ID/EXP of this chart shows ID. ID is low for lines where CCD OUT contains the R component, and high for lines where CCD OUT contains the B component.
∗ The high-speed sweep block is fixed to 1560 stages.
∗ VD of this chart is NTSC equivalent pattern (885H + 810ck units). For PAL equivalent pattern, it is 884H + 1104ck units.
1550
Vertical Direction Timing Chart
CCD OUT
Chart-1
CXD3606R
– 23 –
V4
V3B
V3A
V2
V1B
V1A
SUB
HD
WEN
ID/EXP
CLPDM
Wide OBCLP
OBCLP
PBLK
260
1544 1546
1532 1534
1525 1527
D
6 3 10 15 22 27 30
4 1 8 13 20 25 28
287 1 2
260
D
6 3 10 15 22 27 30
4 1 8 13 20 25 28
287 1 2
• ICX412
Draft mode
1537 1539
1532 1534
1525 1527
∗ The number of SUB pulses is determined by the serial interface data. This chart shows the case where SUB pulses are output in each horizontal period.
∗ ID/EXP of this chart shows ID. ID is low for lines where CCD OUT contains the R component, and high for lines where CCD OUT contains the B component.
∗ VD of this chart is NTSC equivalent pattern (285H + 1455ck + 1455ck units). For PAL equivalent pattern, it is 342H + 2592ck units.
1537 1539
Applicable CCD image sensor
1544 1546
VD
1549
MODE
1549
Vertical Direction Timing Chart
CCD OUT
Chart-2
CXD3606R
– 24 –
WEN
ID/EXP
CLPDM
Wide OBCLP
OBCLP
PBLK
CCD OUT
V4
V3B
V3A
V2
V1B
V1A
∗
∗
∗
∗
E
High-speed
sweep block
D
144
6
4
E
2
Frame shift block
14
E
131
High-speed
sweep block
D
144
6
4
E
2
Frame shift block
14
440 442
433 435
421 423
The number of SUB pulses is determined by the serial interface data. This chart shows the case where SUB pulses are output in each horizontal period.
ID/EXP of this chart shows ID. ID is low for lines where CCD OUT contains the R component, and high for lines where CCD OUT contains the B component.
75 stages are fixed for high-speed sweep block; 68 stages are fixed for frame shift block.
VD of this chart is NTSC equivalent pattern (142H + 1384ck + 1383ck units). For PAL equivalent pattern it is 171H + 1296ck units, and the high-speed sweep block starts from 159H.
1112 1114
SUB
131
1117 1119
HD
1112 1114
VD
421 423
• ICX412
428 430
AF1 mode
433 435
Applicable CCD image sensor
440 442
MODE
1117 1119
Vertical Direction Timing Chart
428 430
Chart-3
CXD3606R
WEN
ID/EXP
CLPDM
Wide OBCLP
OBCLP
PBLK
CCD OUT
V4
V3B
V3A
V2
V1B
V1A
SUB
∗
∗
∗
∗
E
High-speed
sweep block
D
72
6
4
E
2
Frame shift block
21
E
54
High-speed
sweep block
D
72
6
4
E Frame shift block
2
21
692 694
685 687
673 675
The number of SUB pulses is determined by the serial interface data. This chart shows the case where SUB pulses are output in each horizontal period.
ID/EXP of this chart shows ID. ID is low for lines where CCD OUT contains the R component, and high for lines where CCD OUT contains the B component.
116 stages are fixed for high-speed sweep block; 110 stages are fixed for frame shift block.
VD of this chart is NTSC equivalent pattern (71H + 1384ck units). For PAL equivalent pattern, it is 85H + 1960ck units, and the high-speed sweep block starts from 68H.
However, in this case the frame rate for NTSC equivalent pattern is 0.5ck longer than for 1/120s.
862
54
860 862
HD
865 867
VD
867
860
– 25 –
865
• ICX412
680 682
AF2 mode
685 687
Applicable CCD image sensor
692 694
MODE
673 675
Vertical Direction Timing Chart
680 682
Chart-4
CXD3606R
HD
– 26 –
∗
∗
∗
∗
∗
∗
WEN
ID/EXP
CLPDM
OBCLP (wide)
OBCLP (4)
OBCLP (3)
OBCLP (2)
OBCLP (1)
PBLK
SUB
V4
V3A/B
V2
V1A/B
H2
H1
8
8
16
24
34
42
50
50
50
52
52
52
50
100
124
124
120
124
150
162
200
238
250
276
300
314
352
350
390
400
430
428
454
458
454
456/460/464
450
500
• ICX412
Frame mode
200
Applicable CCD image sensor
MODE
550
The HD of this chart indicates the actual CXD3606R load timing.
The numbers at the output pulse transition points indicate the count at the MCKO rise from the fall of HD.
The HD fall period should be between approximately 2.3 to 19.0µs (when the drive frequency is 22.5MHz). This chart shows a period of 124ck (5.5µs). Internal SSG is at this timing.
SUB is output at the timing shown above when output is controlled by the serial interface data.
ID/EXP of this chart shows ID. ID/EXP and WEN are output at the timing shown above at the position shown in Chart-1.
OBCLP (wide) is output at the above timing at the position indicated in Chart-1.
4
(2544)
0
Horizontal Direction Timing Chart
MCKO
Chart-5
CXD3606R
HD
– 27 –
WEN
ID/EXP
CLPDM
OBCLP (wide)
OBCLP (4)
OBCLP (3)
OBCLP (2)
OBCLP (1)
PBLK
SUB
V4
V3A/B
V2
V1A/B
H2
H1
∗
∗
∗
∗
∗
∗
8
8
16
24
34
42
50
50
50
52
52
52
50
100
124
124
120
124
140
156
150
172
188
204
220
236
252
250
268
284
300
300
316
332
348
350
364
380
396
400
412
428
444
450
460
476
492
510
508
500
• ICX412
Draft mode, AF1 mode, AF2 mode
200
Applicable CCD image sensor
MODE
534
538
534
536/540/544
550
The HD of this chart indicates the actual CXD3606R load timing.
The numbers at the output pulse transition points indicate the count at the MCKO rise from the fall of HD.
The HD fall period should be between approximately 2.3 to 19.0µs (when the drive frequency is 22.5MHz). This chart shows a period of 124ck (5.5µs). Internal SSG is at this timing.
SUB is output at the timing shown above when output is controlled by the serial interface data.
ID/EXP of this chart shows ID. ID/EXP and WEN are output at the timing shown above at the position shown in Chart-2,3 and 4.
OBCLP (wide) is output at the above timing at the position indicated in Chart-2,3 and 4.
4
(2624)
0
Horizontal Direction Timing Chart
MCKO
Chart-6
CXD3606R
– 28 –
WEN
ID/EXP
CLPDM
OBCLP
PBLK
SUB
V4
V3A/B
V2
V1A/B
H2
H1
MCKO
HD
∗
∗
∗
∗
∗
∗
Chart-7
52
52
52
52
50
90
90
100
120
#1
128
128
150
166
166
204
204
242
242
250
#2
280
280
300
318
318
356
356
350
394
394
400
#3
432
432
428
450
470
470
456/460/464
• ICX412
Frame mode
200
Applicable CCD image sensor
MODE
508
508
500
#4
546
546
550
The HD of this chart indicates the actual CXD3606R load timing.
The numbers at the output pulse transition points indicate the count at the MCKO rise from the fall of HD.
The HD fall period should be between approximately 2.3 to 19.0µs (when the drive frequency is 22.5MHz). This chart shows a period of 124ck (5.5µs). Internal SSG is at this timing.
SUB is output at the timing shown above when output is controlled by the serial interface data.
ID/EXP of this chart shows ID.
High-speed sweep of V1A/B, V2, V3A/B, V4 is performed up to 98H 580ck (#1560).
4
(2544)
0
Horizontal Direction Timing Chart
(High-speed sweep: C)
CXD3606R
– 29 –
WEN
ID/EXP
CLPDM
OBCLP
PBLK
SUB
V4
V3A/B
V2
V1A/B
H2
H1
MCKO
HD
Chart-8
∗
∗
∗
∗
∗
∗
16
42
52
52
52
52
50
68
84
100
100
124
120
116
132
148
150
164
180
196
228
242
#1
244
250
260
276
292
308
300
324
340
356
350
372
388
404
400
420
436
452
450
468
484
• ICX412
AF1 mode, AF2 mode
200
Applicable CCD image sensor
MODE
#2
500
516
508
500
532
548
536/540/544
550
The HD of this chart indicates the actual CXD3606R load timing.
The numbers at the output pulse transition points indicate the count at the MCKO rise from the fall of HD.
The HD fall period should be between approximately 2.3 to 19.0µs (when the drive frequency is 22.5MHz). This chart shows a period of 124ck (5.5µs). Internal SSG is at this timing.
SUB is output at the timing shown above when output is controlled by the serial interface data.
ID/EXP of this chart shows ID. PBLK, OBCLP, ID/EXP and WEN are output at the timing shown above at the position shown in Chart-3 and 4.
Frame shift of V1A/B, V2, V3A/B and V4 is performed up to 11H 2548ck (#68) in AF1 mode and 18H 308ck (#110) in AF2 mode.
In addition, high-speed sweep is performed up to 141H 2612ck (#75) in AF1 mode and 70H 2612ck (#116) in AF2 mode.
4
(2624)
0
Horizontal Direction Timing Chart
(Frame shift, high-speed sweep: E)
CXD3606R
[B Field]
[A Field]
– 30 –
B
A
(2544)
0
• ICX412
390
352
162
124
1386
1348
1310
1272
1234
∗ The HD of this chart indicates the actual CXD3606R load timing.
∗ The numbers at the output pulse transition points indicate the count at the MCKO rise from the fall of HD.
∗ The HD fall period should be between approximately 2.3 to 19.0µs (when the drive frequency is 22.5MHz). This chart shows a period of 124ck (5.5µs). Internal SSG is at this timing.
V4
V3B
V3A
V2
V1B
V1A
V4
V3B
V3A
V2
V1B
V1A
HD
(2544)
0
1196
Frame mode
200
Applicable CCD image sensor
238
MODE
276
Horizontal Direction Timing Chart
314
Chart-9
CXD3606R
– 31 –
V4
V3B
V3A
V2
V1B
V1A
HD
D
1500
1462
1424
1386
1348
1310
1272
1234
1196
1158
(2544)
0
• ICX412
Applicable CCD image sensor
∗ The HD of this chart indicates the actual CXD3606R load timing.
∗ The numbers at the output pulse transition points indicate the count at the MCKO rise from the fall of HD.
∗ The HD fall period should be between approximately 2.3 to 19.0µs (when the drive frequency is 22.5MHz). This chart shows a period of 124ck (5.5µs). Internal SSG is at this timing.
(2624)
0
1538
Draft mode, AF1 mode, AF2 mode
MODE
1576
1592
1608
1624
1640
1656
1672
1688
Horizontal Direction Timing Chart
124
140
156
172
188
204
220
236
252
268
284
300
316
332
348
364
380
396
412
428
444
460
476
492
Chart-10
CXD3606R
– 32 –
XRS
XSHD
XSHP
RG
H2
H1
MCKO
ADCLK
CKO
CKI
HD'
HD
Chart-11
MODE
52
• ICX412
428/508
Applicable CCD image sensor
∗ HD' of this chart indicates the HD which is the actual CXD3606R load timing.
∗ The phase relationship of each pulse shows the logical position relationship. For the actual output waveform, a delay is added to each pulse.
∗ The logical phase of ADCLK can be specified by the serial interface data.
1
High-Speed Phase Timing Chart
CXD3606R
– 33 –
SUB
V4
V3B
V3A
V2
V1B
V1A
VD
1
050h
SMD
SHD
∗
∗
∗
∗
0
0
MODE
B
050h
1
0
B
C
050h
1
0
C
D
050h
1
0
E
000h
0
3
E
000h
0
3
E
050h
1
0
Open
• ICX412
Draft → Frame → Draft
Close
Applicable CCD image sensor
MODE
This chart is a drive timing chart example of electronic shutter normal operation.
Data exposed at D includes the blooming component. For details, see the CCD image sensor data sheet.
The CXD3606R does not generate the pulse to control mechanical shutter operation.
The switching timing of drive mode and electronic shutter data is not the same.
050h
1
A
CCD OUT
Exposure time
A
Vertical Direction Sequence Chart
Mechanical shutter
Chart-12
F
050h
1
0
F
CXD3606R
CXD3606R
Application Circuit Block diagram
CCD OUT
V2
V3A
V3B
V4
SUB
ADCLK
OBCLP
CLPDM
PBLK
XRS
XSHD
9
25
41
30
43
TG
CXD3606R
39
44
34
SSG
V-Dr
35
ID/EXP
WEN
CKO
MCKO
HD
2
RST
40
3
SNCSL
47
6
SSGSL
37 48
OSCI
CKI
OSCO
26 27 28
Signal
Processor
Block
VD
46
31 32 33
SEN
V1B
5
SCK
V1A
13
SSI
RG
4
TEST2
H2
16 17 18 19 20 22 23
12
TEST1
H1
Digital OUT
CDS/ADC Block
XSHP
CCD
ICX412
Controller
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for
any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
Notes for Power-on
Of the three –7.5V, +15.0V, +3.3V power supplies, be sure to start up the –7.5V and +15.0V power supplies in
the following order to prevent the SUB pin of the CCD image sensor from going to negative potential.
15.0V
t1
20%
0V
20%
t2
–7.5V
t2 ≥ t1
– 34 –
CXD3606R
Package Outline
Unit: mm
48PIN LQFP (PLASTIC)
9.0 ± 0.2
∗
7.0 ± 0.1
36
S
25
13
48
B
(0.22)
0.5 ± 0.2
A
(8.0)
24
37
12
1
+ 0.05
0.127 – 0.02
0.5
+ 0.08
0.18 – 0.03
+ 0.2
1.5 – 0.1
0.13 M
0.1
S
0.5 ± 0.2
0.18 ± 0.03
0° to 10°
0.127 ± 0.04
0.1 ± 0.1
DETAIL B: PALLADIUM
DETAIL A
NOTE: Dimension “∗” does not include mold protrusion.
PACKAGE STRUCTURE
PACKAGE MATERIAL
EPOXY RESIN
SONY CODE
LQFP-48P-L01
LEAD TREATMENT
PALLADIUM PLATING
EIAJ CODE
P-LQFP48-7x7-0.5
LEAD MATERIAL
COPPER ALLOY
PACKAGE MASS
0.2g
JEDEC CODE
– 35 –
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