SONY ICX232

CXD2470R
Timing Generator for Frame Readout CCD Image Sensor
Description
The CXD2470R is a timing generator IC which
generates the timing pulses for performing frame
readout using the ICX224,ICX284,ICX202 and ICX232
CCD image sensor.
48 pin LQFP (Plastic)
Features
• Base oscillation frequency 24.00 to 36.00MHz (max.)
• High-speed/low-speed shutter function
• Supports quadruple-speed readout drive
• Horizontal driver for CCD image sensor
• Vertical driver for CCD image sensor
Absolute Maximum Ratings
• Supply voltage VDD
VSS – 0.3 to +7.0
V
–10.0 to VSS
V
VL
VH
VL – 0.3 to +26.0
V
VSS – 0.3 to VDD + 0.3 V
• Input voltage
VI
• Output voltage VO1 VSS – 0.3 to VDD + 0.3 V
VO2
VL – 0.3 to VSS + 0.3
V
VO3
VL – 0.3 to VH + 0.3
V
• Operating temperature
Topr
–20 to +75
°C
• Storage temperature
Tstg
–55 to +150
°C
Applications
Digital still cameras
Structure
Silicon gate CMOS IC
Applicable CCD Image Sensors
ICX224 (Type 1/2, 2020K pixels)
ICX284 (Type 1/2.7, 2020K pixels)
ICX202 (Type 1/3, 1250K pixels)
ICX232 (Type 1/3.6, 1250K pixels)
Recommended Operating Conditions
• Supply voltage VDDb
3.0 to 5.5
VDDa, VDDc, VDDd
3.0 to 3.6
VM
0.0
VH
14.5 to 15.5
VL
–7.0 to –8.0
• Operating temperature
Topr
–20 to +75
31
CKO
SSI
32
CKI
SCK
33
OSCO
SEN
34
OSCI
VDI
35
MCKO
HDI
36
VDD5
VSS6
Pin Configuration
30
29
28
27
26
25
TEST1
37
24 VSS5
VM
38
23 ADCLK
V2
39
22 OBCLP
V4
40
21 VSS4
V1A
41
20 CLPDM
48
13 H2
1
2
3
4
5
6
7
8
9
10
11
12
H1
14 VDD3
TEST2
VSS3
47
RG
15 VDD4
SUB
VSS2
46
VDD2
16 XSHP
V3B
VDD1
17 XSHD
45
WEN
44
VL
EBCKSM
V3A
ID
18 XRS
DSGAT
19 PBLK
43
RST
42
VSS1
VH
V1B
V
V
V
V
V
°C
∗ Groups of pins enclosed in the figure indicate
sections for which power supply separation is
possible.
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E98Y31C9Z-PS
CXD2470R
OSCI
OSCO
CKI
VDD4
10
15 16 17 18 21
28
27
19 PBLK
20 CLPDM
26
22 OBCLP
CKO 25
Pulse Generator
MCKO 30
23 ADCLK
1/2
24 VSS5
SSI 31
4
ID
5
WEN
41 V1A
SCK 32
43 V1B
Register
39 V2
SEN 33
EBCKSM
VSS4
VSS2
9
XRS
RG
XSHP
VDD2
XSHD
VSS3
8
H2
14 12 13 11
H1
VDD3
Block Diagram
44 V3A
6
46 V3B
VDD1
V Driver
7
40 V4
47 SUB
VDD5 29
42 VH
VSS1
37 48
–2–
35
34
VDI
2
TEST2
DSGAT
3
HDI
45 VL
RST
38 VM
TEST1
1
VSS6 36
CXD2470R
Pin Description
Pin
No.
Symbol
I/O
Description
1
VSS1
—
2
RST
I
Internal system reset input.
High: Normal operation, Low: Reset control
Normally apply reset during power-on.
Schmitt trigger input/No protective diode on power supply side
3
DSGAT
I
Control input used to stop pulse generation.
High: Normal operation, Low: Stop control
Schmitt trigger input/No protective diode on power supply side
4
ID
O
Vertical direction line identification pulse output.
5
WEN
O
Memory write timing pulse output.
6
EBCKSM
I
7
VDD1
—
3.3V power supply. (Power supply for common logic block)
8
VDD2
—
3.3V power supply. (Power supply for RG)
9
RG
O
CCD reset gate pulse output.
10
VSS2
—
GND
11
VSS3
—
GND
12
H1
O
CCD horizontal register clock output.
13
H2
O
CCD horizontal register clock output.
14
VDD3
—
3.3 to 5.0V power supply. (Power supply for H1/H2)
15
VDD4
—
3.3V power supply. (Power supply for CDS block)
16
XSHP
O
CCD precharge level sample-and-hold pulse output.
17
XSHD
O
CCD data level sample-and-hold pulse output.
18
XRS
O
Sample-and-hold pulse output for analog/digital conversion phase alignment.
19
PBLK
O
Pulse output for horizontal and vertical blanking period pulse cleaning.
20
CLPDM
O
CCD dummy signal clamp pulse output.
21
VSS4
—
GND
22
OBCLP
O
CCD optical black signal clamp pulse output.
23
ADCLK
O
Clock output for analog/digital conversion IC.
Logical phase adjustment possible using the serial interface data.
24
VSS5
—
GND
25
CKO
O
Inverter output.
26
CKI
I
Inverter input.
27
OSCO
O
Inverter output for oscillation.
28
OSCI
I
Inverter input for oscillation.
29
VDD5
—
3.3V power supply. (Power supply for common logic block)
30
MCKO
O
System clock output for signal processing IC.
GND
CHKSUM enable.
High: Sum check invalid, Low: Sum check valid
With pull-down resistor
–3–
When not used, leave open or connect a capacitor.
When not used, fix low.
CXD2470R
Pin
No.
Symbol
I/O
Description
31
SSI
I
Serial interface data input for internal mode settings.
Schmitt trigger input/No protective diode on power supply side
32
SCK
I
Serial interface clock input for internal mode settings.
Schmitt trigger input/No protective diode on power supply side
33
SEN
I
Serial interface strobe input for internal mode settings.
Schmitt trigger input/No protective diode on power supply side
34
VDI
I
Vertical sync signal input.
Schmitt trigger input
35
HDI
I
Horizontal sync signal input.
Schmitt trigger input
36
VSS6
—
37
TEST1
38
VM
—
GND (GND for vertical driver)
39
V2
O
CCD vertical register clock output.
40
V4
O
CCD vertical register clock output.
41
V1A
O
CCD vertical register clock output.
42
VH
—
15.0V power supply. (Power supply for vertical driver)
43
V1B
O
CCD vertical register clock output.
44
V3A
O
CCD vertical register clock output.
45
VL
—
–7.5V power supply. (Power supply for vertical driver)
46
V3B
O
CCD vertical register clock output.
47
SUB
O
CCD electronic shutter pulse output.
48
TEST2
I
IC test pin 2; normally fixed to GND.
I
GND
IC test pin 1; normally fixed to GND.
–4–
With pull-down resistor
With pull-down resistor
CXD2470R
Electrical Characteristics
DC Characteristics
(Within the recommended operating conditions)
Item
Pins
Symbol
Conditions
Min.
Typ.
Max.
Unit
Supply voltage 1 VDD2
VDDa
3.0
3.3
3.6
V
Supply voltage 2 VDD3
VDDb
3.0
3.3
5.5
V
Supply voltage 3 VDD4
VDDc
3.0
3.3
3.6
V
Supply voltage 4 VDD1, VDD5
VDDd
3.0
3.3
3.6
V
RST, DSGAT, Vt+
SSI, SCK,
∗
1
Input voltage 1
SEN,
Vt–
EBCKSM
TEST1,
Input voltage 2∗2
TEST2
H1, H2
Output voltage 2
RG
Output voltage 3
XSHP, XSHD,
VOH3
XRS, PBLK,
OBCLP,
CLPDM,
VOL3
ADCLK
Output current 1
Output current 2
V1A, V1B,
V3A, V3B,
V2, V4
SUB
V
0.3VDDd V
VIH2
Output voltage 1
CKO, MCKO
0.7VDDd
VIL1
VDI, HDI
V
0.2VDDd V
VIH1
Input voltage 3
Output voltage 4
0.8VDDd
0.7VDDd
VIL2
V
0.3VDDd V
VOH1
Feed current where IOH = –22.0mA VDDb – 0.8
VOL1
Pull-in current where IOL = 14.4mA
VOH2
Feed current where IOH = –3.3mA
VOL2
Pull-in current where IOL = 2.4mA
Feed current where IOH = –3.3mA
V
0.4
VDDb – 0.8
V
0.4
VDDc – 0.8
Pull-in current where IOL = 2.4mA
Feed current where IOH = –10.4mA VDDd – 0.8
VOL4
Pull-in current where IOL = 7.2mA
IOL
V1A/B, V2, V3A/B, V4 = –8.25V
IOM1
V1A/B, V2, V3A/B, V4 = –0.25V
IOM2
V1A/B, V3A/B = 0.25V
IOH
V1A/B, V3A/B = 14.75V
IOSL
SUB = –8.25V
IOSH
SUB = 14.75V
V
V
0.4
VOH4
V
V
V
0.4
10.0
V
mA
–5.0
5.0
mA
mA
–7.2
5.4
mA
mA
–4.0
mA
∗1 These input pins are Schmitt trigger inputs and do not have protective diodes on the internal power supply
side.
∗2 These input pins have internal pull-down resistors.
Note) The above table indicates the condition for 3.3V drive.
–5–
CXD2470R
Inverter I/O Characteristics for Oscillation
Item
Pins
Logical Vth
OSCI
Input
voltage
OSCI
Output
voltage
OSCO
Feedback
resistor
Oscillation
frequency
Symbol
(Within the recommended operating conditions)
Conditions
Min.
LVth
Typ.
Max.
VDDd/2
VIH
V
0.7VDDd
V
VIL
0.3VDDd
VOH
Feed current where IOH = –3.6mA
VOL
Pull-in current where IOL = 2.4mA
OSCI,
OSCO
RFB
VIN = VDDd or VSS
OSCI,
OSCO
f
VDDd – 0.8
500k
Unit
V
V
2M
20
0.4
V
5M
Ω
50
MHz
Inverter Input Characteristics for Base Oscillation Clock Duty Adjustment
(Within the recommended operating conditions)
Item
Pins
Symbol
Logical Vth
LVth
Input
voltage
VIH
CKI
Input
amplitude
Conditions
Min.
Typ.
VDDd/2
V
0.3VDDd
fmax 50MHz sine wave
Unit
V
0.7VDDd
VIL
VIN
Max.
0.3
V
Vp-p
Note) Input voltage is the input voltage characteristics for direct input from an external source. Input amplitude
is the input amplitude characteristics in the case of input through a capacitor.
(VH = 15.0V, VM = GND, VL = –7.5V)
Switching Characteristics
Item
Rise time
Fall time
Output noise voltage
Symbol
Conditions
Min.
Typ.
Max.
Unit
TTLM
VL to VM
200
350
500
ns
TTMH
VM to VH
200
350
500
ns
TTLH
VL to VH
30
60
90
ns
TTML
VM to VL
200
350
500
ns
TTHM
VH to VM
200
350
500
ns
TTHL
VH to VL
30
60
90
ns
VCLH
1.0
V
VCLL
1.0
V
VCMH
1.0
V
VCML
1.0
V
Notes) 1. The MOS structure of this IC has a low tolerance for static electricity, so full care should be given for
measures to prevent electrostatic discharge.
2. For noise and latch-up countermeasures, be sure to connect a by-pass capacitor (0.1µF or more)
between each power supply pin (VH, VL) and GND.
3. To protect the CCD image sensor, clamp the SUB pin output at VH before input to the CCD image
sensor.
–6–
CXD2470R
Switching Waveforms
TTMH
TTHM
VH
V1A (V1B, V3A, V3B)
TTLM
90%
90%
10%
10%
TTML
VM
90%
90%
10%
10%
TTML
TTLM
VL
VM
90%
90%
V2 (V4)
10%
10%
TTLH
TTHL
90%
VL
VH
90%
SUB
10%
10%
VL
Waveform Noise
VH
VCMH
VCML
VCLH
VCLL
VL
–7–
CXD2470R
Measurement Circuit
Serial interface data
CKI
VDI
HDI
C6
+3.3V
–7.5V
C6
+15.0V
36 35 34 33 32 31 30 29 28 27 26 25
R1
C2
C2
R1
R1
C1 C2
C1
C2
C2
R1
C2 C2
C2
C2
C1
C2
C1
C2
C2
C1
24
38
23
39
22
40
21
41
20
42
19
CXD2470R
43
C2
R1
C1
C2
R2
C2
37
18
44
17
45
16
46
15
47
14
13
48
C3
R1
1
2
3
4
5
6
7
8
9
10 11 12
C4
C1
R1
3300pF
30Ω
C2
R2
560pF
10Ω
C3
820pF
C4
30pF
–8–
C5
180pF
C6
C5
10pF
C6
C6
C6
C6
C6
C6
C6
C5
CXD2470R
AC Characteristics
AC characteristics between the serial interface clocks
0.8VDDd
SSI
0.2VDDd
0.8VDDd
SCK
ts1
SEN
th1
0.2VDDd
ts3
0.8VDDd
SEN
ts2
(Within the recommended operating conditions)
Symbol
ts1
th1
ts2
ts3
Definition
Min.
Typ.
Max.
Unit
SSI setup time, activated by the rising edge of SCK
20
ns
SSI hold time, activated by the rising edge of SCK
20
ns
SCK setup time, activated by the rising edge of SEN
80
ns
SEN setup time, activated by the rising edge of SCK
20
ns
Serial interface clock internal loading characteristics (1)
Example: During frame mode
VDI
HDI
V1A
Enlarged view
HDI
0.2VDDd
V1A
ts1
th1
0.8VDDd
SEN
0.2VDDd
∗ Be sure to maintain a constantly high SEN logic level near the falling edge of the HDI in the horizontal period
during which V1A/B and V3A/B values take the ternary value and during that horizontal period.
(Within the recommended operating conditions)
Symbol
ts1
th1
Definition
Min.
Typ.
Max.
Unit
SEN setup time, activated by the falling edge of HDI
0
ns
SEN hold time, activated by the falling edge of HDI
102
µs
–9–
CXD2470R
Serial interface clock internal loading characteristics (2)
Example: During frame mode
VDI
HDI
Enlarged view
VDI
0.2VDDd
HDI
ts1
th1
0.8VDDd
SEN
0.2VDDd
∗ Be sure to maintain a constantly high SEN logic level near the falling edge of VDI.
(Within the recommended operating conditions)
Symbol
ts1
th1
Definition
Min.
Typ.
Max.
Unit
SEN setup time, activated by the falling edge of VDI
0
ns
SEN hold time, activated by the falling edge of VDI
200
ns
Serial interface clock output variation characteristics
Normally, the serial interface data is loaded to the CXD2470R at the timing shown in "Serial interface clock
internal loading characteristics (1)" above. However, one exception to this is when the data such as STB is
loaded to the CXD2470R and controlled at the rising edge of SEN. See "Description of Operation".
SEN
0.8VDDd
Output signal
tpdPULSE
(Within the recommended operating conditions)
Symbol
Definition
Min.
tpdPULSE Output signal delay, activated by the rising edge of SEN
– 10 –
5
Typ.
Max.
Unit
100
ns
CXD2470R
RST loading characteristics
0.8VDDd
RST
0.2VDDd
tw1
(Within the recommended operating conditions)
Definition
Symbol
tw1
Min.
RST pulse width
Typ.
Max.
Unit
ns
35
VDI and HDI loading characteristics
VDI, HDI
0.2VDDd
0.2VDDd
ts1
th1
0.8VDDd
MCKO
MCKO load capacitance = 10pF∗1
(Within the recommended operating conditions)
Symbol
ts1
th1
Definition
Min.
Typ.
Max.
Unit
VDI and HDI setup time, activated by the rising edge of MCKO
20
ns
VDI and HDI hold time, activated by the rising edge of MCKO
5
ns
Output timing characteristics using DSGAT
DSGAT
0.2VDDd
H1, H2, RG, XSHP, XSHD, XRS,
ADCLK, PBLK, CLPDM, OBCLP
0.2VDDd
tpDSGAT
H1 and H2 load capacitance = 180pF, RG load capacitance = 30pF,
XSHP, XSHD, XRS, PBLK, CLPDM, OBCLP and ADCLK load capacitance = 10pF
(Within the recommended operating conditions)
Symbol
tpDSGAT
Definition
Min.
Time until the above outputs go low after the fall of DSGAT
– 11 –
Typ.
Max.
Unit
100
ns
CXD2470R
Output variation characteristics
MCKO
0.8VDDd
WEN, ID
tpd1
WEN and ID load capacitance = 10pF
(Within the recommended operating conditions)
Symbol
tpd1
Definition
Min.
Time until the above outputs change after the rise of MCKO
20
– 12 –
Typ.
Max.
Unit
60
ns
CXD2470R
Description of Operation
Pulses output from the CXD2470R are controlled mainly by the RST and DSGAT pins and by the serial
interface data. The Pin Status Table is shown below, and the details of serial interface control are described on
the following pages.
Pin Status Table
Pin
No.
Symbol
CAM
SLP
STB DSGAT RST
Symbol
CAM
SLP
STB DSGAT RST
25
CKO
ACT
ACT
L
ACT
ACT
L
26
CKI
ACT
ACT
ACT
ACT
ACT
L
ACT
27
OSCO
ACT
ACT
ACT
ACT
ACT
L
ACT
L
28
OSCI
ACT
ACT
ACT
ACT
ACT
L
L
ACT
L
29
VDD5
ACT
ACT
ACT
ACT
30
MCKO
ACT
ACT
L
ACT
ACT
—
31
SSI
ACT
ACT
ACT
ACT
DIS
—
32
SCK
ACT
ACT
ACT
ACT
DIS
33
SEN
ACT
ACT
ACT
ACT
DIS
—
34
VDI
ACT
ACT
ACT
ACT
ACT
—
35
HDI
ACT
ACT
ACT
ACT
ACT
ACT
36
VSS6
—
ACT
37
TEST1
—
—
38
VM
—
—
39
V2
ACT
VM
VM
VM
VM
ACT
40
V4
ACT
VM
VM
VM
VL
L
ACT
41
V1A
ACT
VH
VH
VH
VM
L
L
ACT
42
VH
L
L
L
H
43
V1B
ACT
VH
VH
VH
VM
L
L
L
H
44
V3A
ACT
VH
VH
VH
VL
45
VL
H
46
V3B
ACT
VH
VH
VH
VL
ACT
47
SUB
ACT
VH
VH
VH
VL
48
TEST2
1
VSS1
2
RST
ACT
ACT
ACT
ACT
3
DSGAT
ACT
ACT
ACT
4
ID
ACT
L
5
WEN
ACT
6
EBCKSM ACT
7
VDD1
8
VDD2
9
RG
10
VSS2
11
VSS3
12
H1
ACT
L
L
L
13
H2
ACT
L
L
L
14
VDD3
15
VDD4
16
XSHP
ACT
L
L
L
17
XSHD
ACT
L
L
18
XRS
ACT
L
19
PBLK
ACT
20
CLPDM
ACT
21
VSS4
22
OBCLP
ACT
L
L
L
23
ADCLK
ACT
L
L
L
24
VSS5
—
ACT
Pin
No.
L
L
L
ACT
—
—
—
—
—
—
Note) ACT means that the circuit is operating, and DIS means that loading is stopped.
L indicates a low output level, and H a high output level in the controlled status.
Also, VH, VM and VL indicate the voltage levels applied to VH (Pin 42), VM (Pin 38) and VL (Pin 45),
respectively, in the controlled status.
– 13 –
CXD2470R
Serial Interface Control
The CXD2470R basically loads and reflects the serial interface data sent in the following format in the readout
portion at the falling edge of HDI. Here, readout portion specifies the horizontal period during which V1A/B and
V3A/B, etc. take the ternary value.
Note that some items reflect the serial interface data at the falling edge of VDI or the rising edge of SEN.
SSI
00
01
02
03
04
05
06
07
41
42
43
44
45
46
47
SCK
SEN
There are two categories of serial interface data: CXD2470R drive control data (hereafter "control data") and
electronic shutter data (hereafter "shutter data").
The details of each data are described below.
– 14 –
CXD2470R
Control Data
Data
Function
Symbol
Data = 0
D00
to
D07
CHIP
Chip enable
D08
to
D09
CTG
Category switching
D10
to
D11
MODE
Drive mode switching
D12
CCD
CCD switching
D13
to
D14
SMD
Electronic shutter mode switching
D15
to
D35
D36
to
D37
LDAD
D38
to
D39
STB
Standby control
D40
to
D47
CKSM
Check sum bit
RST
10000001 → Enabled
Other values → Disabled
All
0
See D08 to D09 CTG.
All
0
See D10 to D11 MODE.
All
0
ICX224/ICX284
—
—
Data = 1
ICX202/ICX232
See D13 to D14 SMD.
—
—
0
All
0
All
0
1
ADCLK logic phase switching
See D36 to D37 LDAD.
0
– 15 –
See D38 to D39 STB.
All
0
See D40 to D47 CKSM.
All
0
CXD2470R
Shutter Data
Data
Symbol
Function
D00
to
D07
CHIP
Chip enable
D08
to
D09
CTG
D10
to
D17
Data = 0
Data = 1
RST
10000001 → Enabled
Other values → Disabled
All
0
Category switching
See D08 to D09 CTG.
All
0
SVD
Electronic shutter vertical period
specification
See D10 to D17 SVD.
All
0
D18
to
D27
SHD
Electronic shutter horizontal period
specification
See D18 to D27 SHD.
All
0
D28
to
D35
SPL
High-speed shutter position
specification
See D28 to D35 SPL.
All
0
D36
to
D39
D40
to
D47
—
CKSM
—
—
—
See D40 to D47 CKSM.
Check sum bit
– 16 –
All
0
All
0
CXD2470R
Detailed Description of Each Data
Shared data: D08 to D09 CTG [Category]
Of the data provided to the CXD2470R by the serial interface, the CXD2470R loads D10 and subsequent data
to each data register as shown in the table below according to the combination of D08 and D09 .
D09
D08
Description of operation
0
0
Loading to control data register
0
1
Loading to shutter data register
1
0
1
1
Test mode
Note that the CXD2470R can apply these categories consecutively within the same vertical period. However,
care should be taken as the data is overwritten if the same category is applied.
Shared data: D40 to D47 CKSM [Check sum]
These are the check sum bits. Apply the data shown below. This function is valid when EBCKSM (Pin 6) is low.
MSB
D07
D15
D23
D31
D39
+) D47
D06
D14
D22
D30
D38
D46
D05
D13
D21
D29
D37
D45
D04
D12
D20
D28
D36
D44
D03
D11
D19
D27
D35
D43
D02
D10
D18
D26
D34
D42
D01
D09
D17
D25
D33
D41
LSB
D00
D08
D16
D24
D32
D40
0
0
0
0
0
0
0
0
→ CKSM
→ Reflected when the total is "0".
Control data: D10 to D11 MODE [Drive mode]
The CXD2470R drive mode can be switched as follows. However, the drive mode bits are loaded to the
CXD2470R and reflected at the falling edge of VDI.
D11
D10
Description of operation
0
0
Quadruple-speed mode (default)
0
1
Frame mode (A field readout)
1
0
Frame mode (B field readout)
1
1
Frame mode
– 17 –
CXD2470R
Control data: D12 CCD [CCD switching]
Specifies CCD image sensor to be used. However, the CCD image sensor switching bit is loaded to the
CXD2470R and reflected at the falling edge of VDI. The default is "ICX224/ICX284".
D12
CCD
0
ICX224/ICX284
1
ICX202/ICX232
Control data: D36 to D37 LDAD [ADCLK logic phase adjustment]
This indicates the ADCLK logic phase adjustment data. The default is 90° relative to MCKO.
D37
D36
Degree of adjustment (°)
0
0
0
0
1
90
1
0
180
1
1
270
Control data: D38 to D39 STB [Standby]
The operating mode is switched as follows. However, the standby bits are loaded to the CXD2470R and
control is applied immediately at the rising edge of SEN.
D39
D38
Symbol
Operating mode
X
0
CAM
Normal operating mode
0
1
SLP
Sleep mode
1
1
STB
Standby mode
See the Pin Status Table for the pin status in each mode.
– 18 –
CXD2470R
Control data/shutter data: [Electronic shutter]
The CXD2470R realizes various electronic shutter functions by using control data D13 to D14 SMD and
shutter data D10 to D17 SVD, D18 to D27 SHD and D28 to D35 SPL.
These functions are described in detail below.
First, the various modes are shown below.
These modes are switched using control data D13 to D14 SMD.
D14
D13
0
0
0
1
1
0
1
1
Description of operation
Electronic shutter stopped mode
High-speed/low-speed shutter mode
HTSG control mode
The electronic shutter data is expressed as shown in the table below using D18 to D27 SHD as an example.
MSB
LSB
D27 D26
0
↓
1
1
D25
D24
1
1
↓
C
D23
D22
D21
D20
0
0
0
0
↓
3
D19
D18
1
1
→ SHD is expressed as 1C3h .
[Electronic shutter stopped mode]
During this mode, all shutter data items are invalid.
SUB is not output in this mode, so the shutter speed is the accumulation time for one field.
[High-speed/low-speed shutter mode]
During this mode, the shutter data items have the following meanings.
Symbol
Data
Description
SVD
D10 to D17
Number of vertical periods specification (00h ≤ SVD ≤ FFh)
SHD
D18 to D27
Number of horizontal periods specification (000h ≤ SHD ≤ 3FFh)
SPL
D28 to D35
Vertical period specification for high-speed shutter operation (00h ≤ SPL ≤ FFh)
The period during which SVD and SHD are specified together is the shutter speed. Concretely, when specifying
high-speed shutter, SVD is set to "00h". (See the figure.) During low-speed shutter, or in other words when
SVD is set to "01h" or higher, the serial interface data is not loaded until this period is finished.
The vertical period indicated here corresponds to one field in each drive mode. In addition, the number of
horizontal periods applied to SHD can be considered as (number of SUB pulses – 1).
Note) The bit data definition area is assured in terms of the CXD2470R functions, and does not assure the
CCD characteristics.
– 19 –
CXD2470R
VDI
SVD
SHD
V1A
SUB
WEN
SMD
01
01
SVD
02h
00h
SHD
10Fh
050h
Further, SPL can be used during this mode to specify the SUB output at the desired vertical period during the
low-speed shutter period.
In the case below, SUB is output based on SHD at the SPL vertical period out of (SVD + 1) vertical periods.
SPL
VDI
SVD
SHD
V1A
SUB
WEN
SMD
10
01
SPL
01h
00h
SVD
02h
00h
SHD
10Fh
0A3h
Incidentally, SPL is counted as "00h", "01h", "02h" and so on in conformance with SVD.
Using this function it is possible to achieve smooth exposure time transitions when changing from low-speed
shutter to high-speed shutter or vice-versa.
– 20 –
CXD2470R
[HTSG control mode]
During this mode, all shutter data items are invalid.
The V1A/B and V3A/B ternary level outputs are stopped, so the shutter speed is the value obtained by adding
the shutter speed specified in the preceding vertical period to the vertical period during which these readout
pulses are stopped as shown in the figure.
VDI
V1A
Exposure time
SUB
Vck
WEN
SMD
11
01
– 21 –
01
– 22 –
WEN
ID
CLPDM
OBCLP
PBLK
CCD OUT
V4
V3B
V3A
V2
V1B
V1A
SUB
HDI
VDI
A
25
31
1 3 5 7 9 1 3 5 7 9 11 13 15 17 19 21
A Field
MODE
Frame mode
1235
1233
1231
1229
1227
1225
1234
1232
1230
1228
C
(651)
650 1
B
24
31
2 4 6 8 10 2 4 6 8 10 12 14 16 18
B Field
• ICX224/ICX284
Applicable CCD image sensor
∗ The number of SUB pulses is determined by the serial interface. This chart shows the case where SUB pulses are output in each horizontal period.
∗ ID is low for lines where CCD OUT contains the R component, and high for lines where CCD OUT contains the B component.
C
(1300)
650 1
Vertical Direction Timing Chart
1236
Chart-1
CXD2470R
– 23 –
WEN
ID
CLPDM
OBCLP
PBLK
CCD OUT
V4
V3B
V3A
V2
V1B
V1A
SUB
HDI
325 1
D
12
4 9 2 7 10 15 18 23 26 31 34 39 42 47 50 55 58
16
MODE
Quadruple-speed mode
1231
1226
1223
1215
1218
1210
1231
1226
1223
1218
1215
325 1
D
12
16
4 9 2 7 10 15 18 23 26 31 34 39 42 47 50 55
• ICX224/ICX284
Applicable CCD image sensor
∗ The number of SUB pulses is determined by the serial interface. This chart shows the case where SUB pulses are output in each horizontal period.
∗ ID is low for lines where CCD OUT contains the R component, and high for lines where CCD OUT contains the B component.
1234
VDI
Vertical Direction Timing Chart
1234
Chart-2
CXD2470R
– 24 –
WEN
ID
CLPDM
OBCLP
PBLK
SUB
V4
V3A/B
V2
V1A/B
H2
H1
MCKO
HDI
Chart-3
(1848)
0
13
56
56
56
72
88
88
104
104
104
120
136
152
150
152
168
188
190
200
214
214
250
• ICX224/ICX284
Frame mode
100
Applicable CCD image sensor
MODE
∗ The HDI of this chart indicates the actual CXD2470R load timing.
∗ The numbers at the output pulse transition points indicate the count at the MCKO rise from the fall of HDI.
∗ The HDI fall period should be between approximately 3.1 to 10.4µs (when the drive frequency is 18MHz). This chart shows a period of 115ck (6.4µs).
∗ SUB is output at the timing shown above when output is controlled by the serial interface data.
∗ ID and WEN are output at the timing shown above at the position shown in Chart-1.
51
50
Horizontal Direction Timing Chart
CXD2470R
– 25 –
WEN
ID
CLPDM
OBCLP
PBLK
SUB
V4
V3A/B
V2
V1A/B
H2
H1
MCKO
HDI
Chart-4
(1848)
0
51
56
56
56
56
72
72
88
88
88
104
104
104
104
100
120
120
136
136
150
152
MODE
Quadruple-speed mode
152
152
168
168
188
190
200
214
214
• ICX224/ICX284
250
Applicable CCD image sensor
∗ The HDI of this chart indicates the actual CXD2470R load timing.
∗ The numbers at the output pulse transition points indicate the count at the MCKO rise from the fall of HDI.
∗ The HDI fall period should be between approximately 3.1 to 10.4µs (when the drive frequency is 18MHz). This chart shows a period of 115ck (6.4µs).
∗ SUB is output at the timing shown above when output is controlled by the serial interface data.
∗ ID and WEN are output at the timing shown above at the position shown in Chart-2.
13
50
Horizontal Direction Timing Chart
CXD2470R
– 26 –
WEN
ID
CLPDM
OBCLP
PBLK
SUB
V4
V3A/B
V2
V1A/B
H2
H1
MCKO
HDI
Chart-5
(1848)
0
51
56
56
56
56
70
70
#1
84
88
84
98
98
100
112
112
126
MODE
Frame mode
126
140
#2
140
154
152
154
150
168
168
182
182
188
196
#3
196
200
210
210
224
224
• ICX224/ICX284
238
238
252
250
Applicable CCD image sensor
252
#4
266
∗ The HDI of this chart indicates the actual CXD2470R load timing.
∗ The numbers at the output pulse transition points indicate the count at the MCKO rise from the fall of HDI.
∗ The HDI fall period should be between approximately 3.1 to 10.4µs (when the drive frequency is 18MHz). This chart shows a period of 115ck (6.4µs).
∗ SUB is output at the timing shown above when output is controlled by the serial interface data.
∗ High-speed sweep of V1A/B, V2, V3A/B and V4 is performed up to 22H of 1848ck (#758).
13
50
Horizontal Direction Timing Chart
(High-speed sweep: C)
266
280
280
CXD2470R
[B Field]
[A Field]
– 27 –
V4
V3B
V3A
V2
V1B
V1A
V4
V3B
V3A
V2
V1B
V1A
HDI
(1848)
0
[B]
[A]
MODE
Frame mode
1175
1131
1133
1091
1071
(1848)
0
• ICX224/ICX284
56 72 88 104 120 136 152 168
Applicable CCD image sensor
∗ The HDI of this chart indicates the actual CXD2470R load timing.
∗ The numbers at the output pulse transition points indicate the count at the MCKO rise from the fall of HDI.
∗ The HDI fall period should be between approximately 3.0 to 13.4µs (when the drive frequency is 18MHz). This chart shows a period of 115ck (6.4µs).
Logic alignment portion
56 72 88 104 120 136 152 168 184 200 216
Horizontal Direction Timing Chart
1027
1029
Chart-6
CXD2470R
– 28 –
V4
V3B
V3A
V2
V1B
V1A
HDI
(1848)
0
[D]
1175
1131
1133
1027
1029
(1848)
0
• ICX224/ICX284
56 72 88 104 120 136 152 168
Applicable CCD image sensor
∗ The HDI of this chart indicates the actual CXD2470R load timing.
∗ The numbers at the output pulse transition points indicate the count at the MCKO rise from the fall of HDI.
∗ The HDI fall period should be between approximately 3.1 to 10.4µs (when the drive frequency is 18MHz). This chart shows a period of 115ck (6.4µs).
56 72 88 104 120 136 152 168
1071
Quadruple-speed mode
MODE
1091
Horizontal Direction Timing Chart
1111
Chart-7
CXD2470R
– 29 –
WEN
ID
CLPDM
OBCLP
PBLK
CCD OUT
V4
V3B
V3A
V2
V1B
V1A
SUB
HDI
VDI
E
37
1 3 1 3 5 7 9 11 13 15 17 19 21 23
40
A Field
MODE
Frame mode
965
963
961
959
957
955
964
962
960
958
G
(526)
525 1
F
• ICX/202/ICX232
36
40
2 4 2 4 6 8 10 12 14 16 18 20
B Field
Applicable CCD image sensor
∗ The number of SUB pulses is determined by the serial interface data. This chart shows the case where SUB pulses are output in each horizontal period.
∗ ID is low for lines where CCD OUT contains the R component, and high for lines where CCD OUT contains the B component.
G
(1050)
525 1
Vertical Direction Timing Chart
966
Chart-8
CXD2470R
– 30 –
WEN
ID
CLPDM
OBCLP
PBLK
CCD OUT
V4
V3B
V3A
V2
V1B
V1A
SUB
HDI
VDI
1
H
17
1 4 5 8 13 16 21 24 29 32 37 40 45
20
MODE
Quadruple-speed mode
965
960
957
952
944
965
960
957
952
949
262
1
• ICX202/ICX232
H
17
1 4 5 8 13 16 21 24 29 32 37 40
20
Applicable CCD image sensor
∗ The number of SUB pulses is determined by the serial interface data. This chart shows the case where SUB pulses are output in each horizontal period.
∗ ID is low for lines where CCD OUT contains the R component, and high for lines where CCD OUT contains the B component.
262
Vertical Direction Timing Chart
949
Chart-9
CXD2470R
– 31 –
WEN
ID
CLPDM
OBCLP
PBLK
SUB
V4
V3A/B
V2
V1A/B
H2
H1
MCKO
HDI
Chart-10
(1560)
0
10
55
75
95
95
115
115
115
135
150
155
155
175
195
200
242
250
• ICX202/ICX232
Frame mode
100
Applicable CCD image sensor
MODE
244
∗ The HDI of this chart indicates the actual CXD2470R load timing.
∗ The numbers at the output pulse transition points indicate the count at the MCKO rise from the fall of HDI.
∗ The HDI fall period should be between approximately 3.0 to 13.4µs (when the drive frequency is 18MHz). This chart shows a period of 115ck (6.4µs).
∗ SUB is output at the timing shown above when output is controlled by the serial interface data.
∗ ID and WEN are output at the timing shown above at the position shown in Chart-8.
50
55
55
50
Horizontal Direction Timing Chart
270
270
CXD2470R
– 32 –
WEN
ID
CLPDM
OBCLP
PBLK
SUB
V4
V3A/B
V2
V1A/B
H2
H1
MCKO
HDI
Chart-11
(1560)
0
10
75
75
95
95
95
100
115
115
115
115
135
135
155
150
MODE
Quadruple-speed mode
155
155
175
175
195
195
200
• ICX202/ICX232
242
244
250
Applicable CCD image sensor
∗ The HDI of this chart indicates the actual CXD2470R load timing.
∗ The numbers at the output pulse transition points indicate the count at the MCKO rise from the fall of HDI.
∗ The HDI fall period should be between approximately 3.0 to 13.4µs (when the drive frequency is 18MHz). This chart shows a period of 115ck (6.4µs).
∗ SUB is output at the timing shown above when output is controlled by the serial interface data.
∗ ID and WEN are output at the timing shown above at the position shown in Chart-9.
50
55
55
55
55
50
Horizontal Direction Timing Chart
270
270
CXD2470R
– 33 –
WEN
ID
CLPDM
OBCLP
PBLK
SUB
V4
V3A/B
V2
V1A/B
H2
H1
MCKO
HDI
Chart-12
(1560)
0
10
55
55
75
75
95
95
#1
95
100
115
115
MODE
Frame mode
135
135
155
150
155
155
175
175
#2
195
195
200
215
215
• ICX202/ICX232
235
235
242
255
250
Applicable CCD image sensor
#3
255
∗ The HDI of this chart indicates the actual CXD2470R load timing.
∗ The numbers at the output pulse transition points indicate the count at the MCKO rise from the fall of HDI.
∗ The HDI fall period should be between approximately 3.0 to 13.4µs (when the drive frequency is 18MHz). This chart shows a period of 115ck (6.4µs).
∗ SUB is output at the timing shown above when output is controlled by the serial interface data.
∗ High-speed sweep of V1A/B, V2, V3A/B and V4 is performed up to 33H of 1295ck (#659).
50
55
55
50
Horizontal Direction Timing Chart
(High-speed sweep: G)
275
275
CXD2470R
[B Field]
[A Field]
– 34 –
V4
V3B
V3A
V2
V1B
V1A
V4
V3B
V3A
V2
V1B
V1A
(1560)
0
[F]
[E]
MODE
Frame mode
843
903 923
983
(1560)
0
• ICX202/ICX232
55 75 95 115 135 155 175 195
Applicable CCD image sensor
∗ The HDI of this chart indicates the actual CXD2470R load timing.
∗ The numbers at the output pulse transition points indicate the count at the MCKO rise from the fall of HDI.
∗ The HDI fall period should be between approximately 3.0 to 13.4µs (when the drive frequency is 18MHz). This chart shows a period of 115ck (6.4µs).
55 75 95 115 135 155 175 195
Horizontal Direction Timing Chart
HDI
Chart-13
CXD2470R
– 35 –
V4
V3B
V3A
V2
V1B
V1A
HDI
Chart-14
(1560)
0
[H]
843
903 923
MODE
Quadruple-speed mode
983
(1560)
0
• ICX202/ICX232
55 75 95 115 135 155 175 195
Applicable CCD image sensor
∗ The HDI of this chart indicates the actual CXD2470R load timing.
∗ The numbers at the output pulse transition points indicate the count at the MCKO rise from the fall of HDI.
∗ The HDI fall period should be between approximately 3.0 to 13.4µs (when the drive frequency is 18MHz). This chart shows a period of 115ck (6.4µs).
55 75 95 115 135 155 175 195
Horizontal Direction Timing Chart
CXD2470R
– 36 –
XRS
XSHD
XSHP
RG
H2
H1
MCKO
ADCLK
CKO
CKI
HDI'
HDI
Chart-15
MODE
55/56
188/242
• ICX224/ICX284/ICX202/ICX232
Applicable CCD image sensor
∗ HDI' indicates the HDI which is the actual CXD2470R load timing.
∗ The phase relationship of each pulse shows the logical position relationship. For the actual output waveform, a delay is added to each pulse.
∗ The logical phase of ADCLK can be specified by the serial interface.
1
High-Speed Phase Timing Chart
CXD2470R
CXD2470R
Application Circuit Block Diagram
V3A
V3B
V4
SUB
ADCLK
OBCLP
CLPDM
PBLK
30
9
34
41
35
43
TG
CXD2470R
39
44
4
5
CKO
MCKO
VDI
HDI
ID
WEN
V-Dr
46
2
RST
40
3
DSGAT
47
6
EBCKSM
37 48
OSCI
CKI
OSCO
26 27 28
31 32 33
SEN
V2
13
SCK
V1B
25
SSI
V1A
D0 to 9 10
23
16 17 18 19 20 22
TEST2
RG
A/D
CXD2311AR
12
TEST1
H2
XSHD
XSHP
H1
DRVOUT
VRT
VRB
S/H
CXA2006Q
Signal Processor Block
CCD OUT
XRS
CCD
ICX224/ICX284
ICX202/ICX232
Controller
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for
any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
Notes for Power-on
Of the three –7.5V, +15.0V and +3.3V power supplies, be sure to start up the –7.5V and +15.0V power supplies
in the following order to prevent the SUB pin of the CCD image sensor from going to negative potential.
15.0V
t1
20%
0V
20%
t2
–7.5V
t2 ≥ t1
– 37 –
CXD2470R
Package Outline
Unit: mm
48PIN LQFP (PLASTIC)
9.0 ± 0.2
∗
7.0 ± 0.1
36
S
25
13
0.5 ± 0.2
B
A
48
(8.0)
24
37
(0.22)
12
1
+ 0.05
0.127 – 0.02
0.5
+ 0.08
0.18 – 0.03
+ 0.2
1.5 – 0.1
0.13 M
0.1
S
0.5 ± 0.2
(0.18)
0° to 10°
DETAIL B:SOLDER
DETAIL A
0.18 ± 0.03
0.127 ± 0.04
+ 0.08
0.18 – 0.03
(0.127)
+0.05
0.127 – 0.02
0.1 ± 0.1
DETAIL B:PALLADIUM
NOTE: Dimension “∗” does not include mold protrusion.
PACKAGE STRUCTURE
PACKAGE MATERIAL
EPOXY RESIN
SONY CODE
LQFP-48P-L01
LEAD TREATMENT
SOLDER/PALLADIUM
PLATING
EIAJ CODE
LQFP048-P-0707
LEAD MATERIAL
42/COPPER ALLOY
PACKAGE MASS
0.2g
JEDEC CODE
– 38 –