CXG1010N Power Amplifier for PHS For the availability of this product, please contact the sales office. Description The CXG1010N is a power amplifier for PHS. This IC is designed using the Sony’s GaAs J-FET process and operates at a single power supply. Features • High output power 21.5 dBm • Positive power supply drive VDD=3.4 V • Low current consumption 200 mA • High gain 40 dB Typ. • Low distortion (ACP) –59 dBc Typ. • Small mold package 16-pin SSOP Structure GaAs J-FET MMIC 16 pin SSOP (Plastic) Absolute Maximum Ratings (Ta=25 °C) 6 • Supply voltage VDD • Voltage between gate and source Vgs0 1.5 • Drain current IDD 500 • Power dissipation PD 3 • Channel temperature • Operating temperature • Storage temperature Tch Top Tstg Electrical Characteristics VDD=3.4 V, VCTL=2.0 V, f=1.90 GHz Item ∗1 Current consumption ∗1 Gate voltage adjustment value Input VSWR Output power (for –15.5 dBm input) ∗2 Power gain ∗2 Gain control ∗3 ∗2 Average leak power level (600 kHz±100 kHz) ∗2 Average leak power level (900 kHz±100 kHz) V V mA 175 –35 to +85 –65 to +150 W °C °C °C (Ta=25 °C) Symbol IDD Min. VGG2 VSWRIN POUT GP 0 21.5 37 Typ. 200 0.5 1.5 Max. 40 43 1.0 2.0 Unit mA V — dBm dB GCTL 20 dB PLEAK600 –59 –54 dBc PLEAK900 –65 –59 dBc ∗1 This value is adjusted by VGG1 and VGG2 set with Sony’s recommended current adjustment method when 21.5 dBm is output. In this time, the voltage ratio of VGG1 and VGG2 should match to the voltage ratio generated by the resistance of the recommended gate bias circuit. ∗2 When 21.5 dBm is output. ∗3 GCTL=GP (VCTL 2.0 V)–GP (VCTL 0 V) Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. —1— E95836-TE CXG1010N Block Diagram Pin Configuration VDD1 VDD2 VDD3 RFOUT RFIN VGG1 GND VDD3 RFOUT GND GND VDD2 VGG2 GND GND VDD1 VCTL GND VGG1 RFIN GND VCTL VGG2 GND 16 1 Gate adjustment pin Gate adjustment pin VGG2 470Ω VGG1 680Ω Recommended Current Adjustment Method (1) VGG2/PIN separate adjustment (VGG2 adjustment 1) (PIN adjustment 1) (VGG2 adjustment 2) (PIN adjustment 2) When the RF input (PIN) is off, the current consumption (IDD) is adjusted to 200 mA. The output power (POUT) is adjusted to 21.5 dBm. The current consumption (IDD) is finely adjusted to 200 mA. The output power (POUT) is finely adjusted to 21.5 dBm. Variation of IDD and POUT due to adjustment IDD=200±20 mA POUT=21.5 dBm IDD=200 mA POUT=21.5±0.2 dBm IDD=200±5 mA POUT=21.5 dBm (2) Simple adjustment (IDD read) (VGG2 setting) (PIN adjustment) When the RF input (PIN) is off, the gate voltage (VGG2) is set to 0.4 V and it is read. The formula∗1 where VGG2=f (IDD: VGG2=0.4 V) is used to set VGG2. The output power (POUT) is adjusted to 21.5 dBm. Variation of IDD and POUT due to adjustment ∗1 e.g. VGG2=a-b x IDD —2— IDD=200±5 mA POUT=21.5 dBm CXG1010N Current Consumption Variation with Recommended Current Adjustment Method (For POUT=21.5 dBm output) (1) Separate adjustment (mA) 230 VGG 2/PIN separate adjustment method (Distribution of the current consumption IDD after executing the PIN adjustment 1) 5/ IDD 180 0 VGG 2 0.8 (V) VGG 2/PIN separate adjustment method (Distribution of the current consumption IDD after executing the PIN adjustment 2) (mA) 220 5/ IDD 180 0 VGG 2 0.8 (V) (2) Simple adjustment (mA) 220 Simple adjustment method (Distribution of the current consumption IDD after executing the PIN adjustment) VGG 2=a–b×IDD (Pin off/VGG 2=0.4V): a=0.804, b=2.07 5/ IDD 180 0 VGG 2 —3— 0.8 (V) CXG1010N Recommended Evaluation Circuit 50mm 3.0V 100Ω 6.8kΩ RFIN VCTL 1µ GND RV1 RV2 680 Variable resistor Rv 10kΩ (Max) 470 1µ VGG2 180Ω 18n 10n 1000p RFOUT ViaHole GND 1µ GND VDD Recommended Gate Bias Circuit and Circuit Characteristics Glass fabric-base epoxy board (0.2 mm thickness) GND for the overall back side (V) VGG2 3.0V 100Ω 6.8kΩ RV1 Variable RV2 resistor Rv 10kΩ (Max) VGG2 470Ω 0.5 180Ω VGG1 680Ω 0 5 10 RV1 (kΩ) Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party and other right due to same. —4— CXG1010N Example of Representative Characteristics (Ta=25 °C) Input/output characteristics (POUT /ACP) VDD=3.4V, Vctl=2.0V,IDD=200mA@POUT =21.5dBm –40 25 21.5dBm 21 POUT -Output power (dBm) –45 19 17 POUT 15 –50 13 11 –55 9 ACP 7 5 –40 ACP-Leak power ratio of adjacent channel (dBc) 23 –60 –35 –30 –25 –20 –15 PIN-Input power (dBm) GAIN, ACP vs. IDD POUT, ACP vs. VDD Frequency=1.9 GHz, Vctl=2.0 V, PINVGG 2 constant (IDD=200mA@VDD=3.4V) Freq=1.9GHz, VDD=3.4V, Vctl=2.0V, POUT constant 43 –50 42 –51 POUT =22dBm GAIN-Gain (dB) 41 40 POUT =21.5dBm 39 38 POUT =21.5dBm GAIN –52 –53 –54 POUT =22dBm –55 37 –56 36 –57 35 –58 34 –59 33 ACP –60 32 –61 31 –62 24 –50 –51 –52 23 POUT –53 POUT =22dBm 22 @VDD=3.4V IDD-Current consumption (mA) POUT =21.5dBm @VDD=3.4V 21 POUT =22dBm @VDD=3.4V –57 20 –58 POUT =21.5dBm @VDD=3.4V 3 4 VDD-Drain voltage (V) —5— –55 –56 ACP 19 2 30 –63 140 150 160 170 180 190 200 210 220 230 240 250 260 –54 5 –59 –60 2 ACP-Leak power ratio of adjacent channel (dBc) 44 –49 POUT -Output power (dBm) –48 ACP-Leak power ratio of adjacent channel (dBc) 45 CXG1010N Unit : mm 16PIN SSOP (PLASTIC) + 0.2 1.25 – 0.1 ∗5.0 ± 0.1 0.1 16 9 A 1 + 0.1 0.22 – 0.05 6.4 ± 0.2 ∗4.4 ± 0.1 8 + 0.05 0.15 – 0.02 0.65 ± 0.12 0.1 ± 0.1 0.5 ± 0.2 Package Outline 0° to 10° DETAIL A NOTE: Dimension “∗” does not include mold protrusion. PACKAGE STRUCTURE PACKAGE MATERIAL EPOXY RESIN SONY CODE SSOP-16P-L01 LEAD TREATMENT SOLDER / PALLADIUM PLATING EIAJ CODE SSOP016-P-0044 LEAD MATERIAL COPPER / 42 ALLOY PACKAGE WEIGHT 0.1g JEDEC CODE —6—