SONY CXG1117K

CXG1117K
Power Amplifier Module for JCDMA
Description
The CXG1117K is the power amplifier module
which operates at a single power supply. This IC is
designed using the Sony’s original p-Gate HFET
process.
8 pin LCC (Ceramic)
Features
• Single power supply operation:
VDD1 = VDD2 = 3.5V (High mode),
1.7V (Low mode),
VGG = 2.95V
• Ultrasmall package: 0.065cc (6.2mm × 6.2mm × 1.7mm)
• High efficiency: ηadd = 36.5% (@900MHz, POUT = 27.5dBm)
• Output power (high/low mode switching supported):
POUT ≤ 19dBm: Low mode (VDD1 = VDD2 = 1.7V)
POUT = 19 to 27.5dBm: High mode (VDD1 = VDD2 = 3.5V)
• Gain: Gp = 26dB (@900MHz)
Applications
Power amplifier for JCDMA system cellular phones
Structure
p-Gate HFET module
Recommended Operating Conditions
VDD = 3.3 to 4.2V (High Mode)
1.7V (Low Mode)
VGG = 2.95V±1%
Absolute Maximum Ratings
• Operating case temperature
• Storage temperature
• Bias voltage
Tcase
Tstg
VDD1, VDD2
• Bias voltage
VGG
–30 to +85
–30 to +125
(VDD1
• Input power
PIN
°C
°C
6
V
3.3
V
= VDD2 = 3.5V)
8
dBm
GaAs module is ESD sensitive devices. Special handling precautions are required.
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E01304A25-PS
CXG1117K
package Outline/Pin Configuration
Front
7
GND
PIN
1
6
VGG
VDD1
2
5
GND
VDD2
3
4
POUT
1
PIN
2
VDD1
3
VDD2
8
GND
Back
7
VGG
6
GND
5
POUT
4
GND
9
8
GND
GND
–2–
CXG1117K
Electrical Characteristics
Item
(ZS = ZL = 50Ω, IS-95 Modulation, Ta = 25°C)
Conditions
Frequency
Min.
Typ. Max. Unit
887
925 MHz
Current consumption 1
POUT = 27.5dBm, VDD = 3.5V, VGG = 2.95V
440
475
mA
Current consumption 2
POUT = 14dBm, VDD = 1.7V, VGG = 2.95V
105
125
mA
Gain
POUT = 27.5dBm, VDD = 3.5V, VGG = 2.95V
ACPR1
(High mode)
POUT = 27.5dBm, VDD = 3.5V, VGG = 2.95V,
±900kHz offset, 30kHz band width
–51
–45
dBc
ACPR2
(High mode)
POUT = 27.5dBm, VDD = 3.5V, VGG = 2.95V,
±1.98MHz offset, 30kHz band width
–59
–56
dBc
ACPR1
(Low mode)
POUT = 19dBm, VDD = 1.7V, VGG = 2.95V,
±900kHz offset, 30kHz band width
–53
–45
dBc
ACPR2
(Low mode)
POUT = 19dBm, VDD = 1.7V, VGG = 2.95V,
±1.98MHz offset, 30kHz band width
–60
–56
dBc
2nd, 3rd harmonics
POUT = 27.5dBm, VDD = 3.5V, VGG = 2.95V
–40
–30
dBc
Input VSWR
VDD = 3.5V, VGG = 2.95V
1.3
2.5
Gate current
VGG = 2.95V, POUT ≤ 27.5dBm
2.5
5
mA
Gain deviation for bias variation
VDD = 3.5V → 1.7V
VGG = 2.95V, POUT = 17dBm
3
4.5
dB
Gain deviation within band
POUT = 27.5dBm, VDD = 3.5V, VGG = 2.95V
1.2
2
dB
–3–
24
26
dB
CXG1117K
Recommended External Circuit
C1: 0.1µF
C2: 1µF
C3: 10µF
R: 5.1Ω
L: 6.8nH
R
GND
L
VGG
PIN
C1
C2
C3
VDD1
C3
C2
C1
GND
GND
VDD2
POUT
C3
C2
C1
GND
Recommended Evaluation Board
Board material:
Glass fabric-base epoxy
Size:
40mm × 50mm × 0.6mm
Relative dielectric constant: 4.6
Front
Back
VGG
GND
C3
C2
C1
R L
PIN
C1
C2
GND
POUT
C1
C2
VDD1
C3
C3
GND
GND
VDD2
–4–
CXG1117K
Example of Representative Characteristics
POUT vs. PIN
Conditions: f = 900MHz
VDD1 = VDD2 = 3.5V, VGG = 2.95V
Ta = 25°C
34
32
30
POUT [dBm]
28
26
24
22
20
18
16
14
12
10
8
6
–18 –16–14 –12 –10 –8 –6 –4 –2 0
2
4 6
8 10
PIN [dBm]
IDD vs. POUT
Gain vs. POUT
650
28.0
600
27.5
550
27.0
500
26.5
450
26.0
Gain [dB]
IDD [mA]
400
350
300
250
25.5
25.0
24.5
24.0
200
150
23.5
100
23.0
50
22.5
0
22.0
8 10 12 14 16 18 20 22 24 26 28 30 32
POUT [dBm]
POUT [dBm]
ACPR2 vs. POUT
–56
–58
–60
–62
–64
ACPR2 [dBc]
ACPR1 [dBc]
ACPR1 vs. POUT
–34
–36
–38
–40
–42
–44
–46
–48
–50
–52
–54
–56
–58
–60
–62
–64
8 10 12 14 16 18 20 22 24 26 28 30 32
–66
–68
–70
–72
–74
–76
–78
–80
8 10 12 14 16 18 20 22 24 26 28 30 32
POUT [dBm]
–5–
8 10 12 14 16 18 20 22 24 26 28 30 32
POUT [dBm]
CXG1117K
Package Outline
Unit: mm
8PIN LCC (Ceramic)
∗ 6.2 ± 0.3
1.9MAX
6.0
6.7MAX
SOLDERING POINT
PIN 1 INDEX
Y Y
0.15
COAT
TERMINAL
C0.1
R0.2
0.15
3.4 ± 0.15
5.3
1.7 ± 0.1
S
0.1
6
7
R0.2
0.1 S
DETAIL Y-Y
0.2
5.8
5
2
1
COAT
DETAIL X
X
4
3
0.6 ± 0.2
0.15
0.015MAX
3.8
1.6
0.9
1.7
8
1.1 ± 0.2
SOLDERING POINT
TERMINAL
PACKAGE STRUCTURE
Dimension " ∗"dose not inculude cutting burr.
SONY CODE
LCC-8C-601
PACKAGE MATERIAL
TERMINAL TREATMENT
EIAJ CODE
TERMINAL MATERIAL
JEDEC CODE
PACKAGE MASS
–6–
CERAMIC SUBSTRATE
GOLD PLATING
NICKEL PLATING
0.8g
Sony Corporation